/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:57 by OpenVMS SDL EV3-3 */ /* Source: 16-DEC-1998 16:25:25 $1$DGA7274:[LIB_H.SRC]TSUNAMIDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $TSUNAMIDEF ***/ #ifndef __TSUNAMIDEF_LOADED #define __TSUNAMIDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*++ */ /* */ /* FACILITY: OpenVMS AXP System Macro Libraries */ /* */ /* ABSTRACT: */ /* */ /* This file defines the control and status registers of the Tsunami Chip */ /* Set (TCS), designed for use in EV6 based platforms. */ /* */ /* Because of the disparities in the address spaces for the various chips */ /* in the Tsunami Chip Set, and because there are one C-Chip, as many as */ /* eight D-Chips and as many as two P-Chips, the Tsunami Chip Set */ /* structure is defined as three distinct data stuctures, C_CHIP, D_CHIP, */ /* and P_CHIP. This simplifies the definition, but puts an extra burden on */ /* the programmer to use the correct base addresses for the three chips. */ /* */ /* The following table shows the regions for the Tsunami Chip Set address */ /* space. */ /* */ /* -------------------------------------------------------------------- */ /* Cchip Address Space */ /* -------------------------------------------------------------------- */ /* 801 0000 0000 1 GB TIG Bus, addr<5:0> = 0, single byte valid in */ /* quadword access, 16 MB accessible */ /* 801 a000 0000 256 MB Cchip CSRs, addr<5:0> = 0, quadword access */ /* -------------------------------------------------------------------- */ /* */ /* -------------------------------------------------------------------- */ /* Dchip Address Space */ /* -------------------------------------------------------------------- */ /* 801 b000 0000 256 MB Dchip CSRs, addr<5:0> = 0, all eight bytes in */ /* quadword access must be identical. */ /* -------------------------------------------------------------------- */ /* */ /* -------------------------------------------------------------------- */ /* Pchip-0 Address Space */ /* -------------------------------------------------------------------- */ /* 800 0000 0000 4 GB PCI Memory */ /* 801 8000 0000 256 MB CSRs, addr<5:0> = 0, quadword access */ /* 801 f800 0000 64 MB PCI IACK/Special */ /* 801 fc00 0000 32 MB PCI IO */ /* 801 fe00 0000 16 MB PCI config space */ /* -------------------------------------------------------------------- */ /* */ /* -------------------------------------------------------------------- */ /* Pchip-1 Address Space */ /* -------------------------------------------------------------------- */ /* 802 0000 0000 4 GB PCI Memory */ /* 803 8000 0000 256 MB CSRs, addr<5:0> = 0, quadword access */ /* 803 f800 0000 64 MB PCI IACK/Special */ /* 803 fc00 0000 32 MB PCI IO */ /* 803 fe00 0000 16 MB PCI config space */ /* -------------------------------------------------------------------- */ /* */ /* AUTHOR: */ /* */ /* Tony Camuso 14-Jan-1997 */ /* */ /* MODIFIED BY: */ /* */ /* X-3 TLC Tony Camuso 16-Dec-1998 */ /* Add constant for maximum supported CPUs */ /* */ /* X-2 PAJ1025 Paul A. Jacobi 12-Oct-1998 */ /* Rename DIR$ to CDIR$ to avoid conflict with other symbols. */ /* */ /* X-1 TLC Tony Camuso 14-Jan-1997 */ /* Initial entry. */ /* */ /*-- */ /* The maximum number of CPUs supported by the Tsunami chipset */ /* */ #define TSUNAMI$K_MAX_CPU 4 #define TSUNAMI$C_MAX_CPU 4 /* */ /* Since SDL currently doesn't support constants greater 2**32, the high-order */ /* bits (%X80x) have their own constants defined. */ /* */ /* Tsunami Chip Set CSR base addresses <63:32> (High longword) */ /* =========================================================== */ /* */ #define TSUNAMI$L_C_CHIP_H 2049 #define TSUNAMI$L_D_CHIP_H 2049 /* */ #define TSUNAMI$L_P0_CHIP_MEM_H 2048 #define TSUNAMI$L_P0_CHIP_IO_H 2049 #define TSUNAMI$L_P0_CHIP_CSR_H 2049 /* */ #define TSUNAMI$L_P1_CHIP_MEM_H 2050 #define TSUNAMI$L_P1_CHIP_IO_H 2051 #define TSUNAMI$L_P1_CHIP_CSR_H 2051 /* */ /* */ /* Tsunami Chip Set CSR base addresses <31:0> (Low longword) */ /* ========================================================= */ /* */ #define TSUNAMI$L_C_CHIP_L -1610612736 /* Cchip */ #define TSUNAMI$L_D_CHIP_L -1342177280 /* Dchip */ /* */ /* */ /* P-Chip */ /* ------ */ #define TSUNAMI$L_P_CHIP_MEM_L 0 #define TSUNAMI$L_P_CHIP_IO_L -67108864 #define TSUNAMI$L_P_CHIP_CSR_L -2147483648 #define TSUNAMI$L_P_CHIP_IACK_L -134217728 #define TSUNAMI$L_P_CHIP_CONFIG_L -33554432 /* */ /* */ /* Tsunami Chip Set CSR offsets */ /* ================================================= */ /* */ /* ------------------------------------------------- */ /* C-Chip - base addr<63:32> = TSUNAMI$L_C_CHIP_H */ /* base addr<31:0> = TSUNAMI$L_C_CHIP_L */ /* ------------------------------------------------- */ #define TSUNAMI$L_CSC_L 0 /* Cchip System Config */ #define TSUNAMI$L_MTR_L 64 /* */ #define TSUNAMI$L_MISC_L 128 /* */ #define TSUNAMI$L_MPD_L 192 /* */ /* */ #define TSUNAMI$L_AAR0_L 256 /* */ #define TSUNAMI$L_AAR1_L 320 /* */ #define TSUNAMI$L_AAR2_L 384 /* */ #define TSUNAMI$L_AAR3_L 448 /* */ /* */ #define TSUNAMI$L_DIM0_L 512 /* */ #define TSUNAMI$L_DIM1_L 576 /* */ #define TSUNAMI$L_DIR0_L 640 /* */ #define TSUNAMI$L_DIR1_L 704 /* */ /* */ #define TSUNAMI$L_DRIR_L 768 /* */ #define TSUNAMI$L_PRBEN_L 832 /* */ #define TSUNAMI$L_IIC0_L 896 /* */ #define TSUNAMI$L_IIC1_L 960 /* */ /* */ #define TSUNAMI$L_MPR0_L 1024 /* */ #define TSUNAMI$L_MPR1_L 1088 /* */ #define TSUNAMI$L_MPR2_L 1152 /* */ #define TSUNAMI$L_MPR3_L 1216 /* */ /* */ #define TSUNAMI$L_MCTL_L 1280 /* */ #define TSUNAMI$L_TTR_L 1408 /* */ #define TSUNAMI$L_TDR_L 1472 /* */ /* */ #define TSUNAMI$L_DIM2_L 1536 /* */ #define TSUNAMI$L_DIM3_L 1600 /* */ #define TSUNAMI$L_DIR2_L 1664 /* */ #define TSUNAMI$L_DIR3_L 1728 /* */ /* */ #define TSUNAMI$L_IIC2_L 1792 /* */ #define TSUNAMI$L_IIC3_L 1856 /* */ /* */ /* */ /* ----------------------------------------------------- */ /* D-Chip - base addr <63:32> = TSUNAMI$L_D_CHIP_H */ /* base addr <31:0> = TSUNAMI$L_D_CHIP_L */ /* ----------------------------------------------------- */ #define TSUNAMI$L_DSC_L 2048 /* */ #define TSUNAMI$L_STR_L 2112 /* */ #define TSUNAMI$L_DREV_L 2176 /* */ /* */ /* */ /* ----------------------------------------------------- */ /* P-Chip - P0 base addr<63:32> = TSUNAMI$L_P0_CHIP_CSR_H */ /* P0 base addr<32:0> = TSUNAMI$L_P_CHIP_CSR_L */ /* */ /* P1 base addr<63:32> = TSUNAMI$L_P1_CHIP_CSR_H */ /* P1 base addr<32:0> = TSUNAMI$L_P_CHIP_CSR_L */ /* ----------------------------------------------------- */ #define TSUNAMI$L_WSBA0_L 0 /* */ #define TSUNAMI$L_WSBA1_L 64 /* */ #define TSUNAMI$L_WSBA2_L 128 /* */ #define TSUNAMI$L_WSBA3_L 192 /* */ /* */ #define TSUNAMI$L_WSMA0_L 256 /* */ #define TSUNAMI$L_WSMA1_L 320 /* */ #define TSUNAMI$L_WSMA2_L 384 /* */ #define TSUNAMI$L_WSMA3_L 448 /* */ /* */ #define TSUNAMI$L_TBA0_L 512 /* */ #define TSUNAMI$L_TBA1_L 576 /* */ #define TSUNAMI$L_TBA2_L 640 /* */ #define TSUNAMI$L_TBA3_L 704 /* */ /* */ #define TSUNAMI$L_PCTL_L 768 /* */ #define TSUNAMI$L_PLAT_L 832 /* */ /* */ #define TSUNAMI$L_P_RESERVED_1_L 896 /* */ /* */ #define TSUNAMI$L_PERROR_L 960 /* */ #define TSUNAMI$L_PERRMASK_L 1024 /* */ #define TSUNAMI$L_PERRSET_L 1088 /* */ /* */ #define TSUNAMI$L_TLBIV_L 1152 /* */ #define TSUNAMI$L_TLBIA_L 1216 /* */ /* */ #define TSUNAMI$L_PMONCTL_L 1280 /* */ #define TSUNAMI$L_PMONCNT_L 1344 /* */ /* */ /* */ /*************************************************************************** */ /* */ /* Tsunami Chip Set Structures */ /* */ /*************************************************************************** */ /* */ /*========================================================================== */ /* */ /* C-CHIP Structure */ /*========================================================================== */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _c_chip { /* */ /* 801.A000.000 */ /* */ /* CSC - C-Chip System Configuration Register */ /* */ #pragma __nomember_alignment __union { unsigned __int64 c_chip$iq_csc; unsigned char csc$b_pad [64]; } c_chip$r_csc_overlay; /* */ /* 801.A000.0040 */ /* */ /* MTR - C-Chip Memory Timing Register */ /* */ __union { unsigned __int64 c_chip$iq_mtr; unsigned char mtr$b_pad [64]; } c_chip$r_mtr_overlay; /* */ /* 801.A000.0080 */ /* */ /* MISC - C-Chip Miscellaneous Register */ /* */ __union { unsigned __int64 c_chip$iq_misc; unsigned char csc$b_pad [64]; } c_chip$r_misc_overlay; /* */ /* 801.A000.00C0 */ /* */ /* MPD - C-Chip Memory Presence Detect */ /* */ __union { unsigned __int64 c_chip$iq_mpd; unsigned char mpd$b_pad [64]; } c_chip$r_mpd_overlay; /* */ /* 801.A000.0100 */ /* */ /* AAR0 - C-Chip Array Address Register 0 */ /* */ __union { unsigned __int64 c_chip$iq_aar0; unsigned char aar0$b_pad [64]; } c_chip$r_aar0_overlay; /* */ /* 801.A000.0140 */ /* */ /* AAR1 - C-Chip Array Address Register 1 */ /* */ __union { unsigned __int64 c_chip$iq_aar1; unsigned char aar1$b_pad [64]; } c_chip$r_aar1_overlay; /* */ /* 801.A000.0180 */ /* */ /* AAR2 - C-Chip Array Address Register 2 */ /* */ __union { unsigned __int64 c_chip$iq_aar2; unsigned char aar2$b_pad [64]; } c_chip$r_aar2_overlay; /* */ /* 801.A000.01C0 */ /* */ /* AAR3 - C-Chip Array Address Register 3 */ /* */ __union { unsigned __int64 c_chip$iq_aar3; unsigned char aar3$b_pad [64]; } c_chip$r_aar3_overlay; /* */ /* 801.A000.0200 */ /* */ /* DIM0 - C-Chip Device Interrupt Mask Register 0 */ /* */ __union { unsigned __int64 c_chip$iq_dim0; unsigned char dim0$b_pad [64]; } c_chip$r_dim0_overlay; /* */ /* 801.A000.0240 */ /* */ /* DIM1 - C-Chip Device Interrupt Mask Register 1 */ /* */ __union { unsigned __int64 c_chip$iq_dim1; unsigned char dim1$b_pad [64]; } c_chip$r_dim1_overlay; /* */ /* 801.A000.0280 */ /* */ /* DIR0 - C-Chip Device Interrupt Request Register */ /* */ __union { unsigned __int64 c_chip$iq_dir0; unsigned char dir0$b_pad [64]; } c_chip$r_dir0_overlay; /* */ /* 801.A000.02C0 */ /* */ /* DIR1 - C-Chip Device Interrupt Request Register */ /* */ __union { unsigned __int64 c_chip$iq_dir1; unsigned char dir1$b_pad [64]; } c_chip$r_dir1_overlay; /* */ /* 801.A000.0300 */ /* */ /* DRIR - C-Chip Raw Interrupt Request Register */ /* */ __union { unsigned __int64 c_chip$iq_drir; unsigned char drir$b_pad [64]; } c_chip$r_drir_overlay; /* */ /* 801.A000.0340 */ /* */ /* PRBEN - C-Chip Probe Enable Register */ /* */ __union { unsigned __int64 c_chip$iq_prben; unsigned char prben$b_pad [64]; } c_chip$r_prben_overlay; /* */ /* 801.A000.0380 */ /* */ /* IIC0 - C-Chip Interval Ignore Count Register 0 */ /* */ __union { unsigned __int64 c_chip$iq_iic0; unsigned char iic0$b_pad [64]; } c_chip$r_iic0_overlay; /* */ /* 801.A000.03C0 */ /* */ /* IIC1 - C-Chip Interval Ignore Count Register 1 */ /* */ __union { unsigned __int64 c_chip$iq_iic1; unsigned char iic1$b_pad [64]; } c_chip$r_iic1_overlay; /* */ /* 801.A000.0400 */ /* */ /* MPR0 - C-Chip Memory Programming Register 0 */ /* */ __union { unsigned __int64 c_chip$iq_mpr0; unsigned char mpr0$b_pad [64]; } c_chip$r_mpr0_overlay; /* */ /* 801.A000.0440 */ /* */ /* MPR1 - C-Chip Memory Programming Register 1 */ /* */ __union { unsigned __int64 c_chip$iq_mpr1; unsigned char mpr1$b_pad [64]; } c_chip$r_mpr1_overlay; /* */ /* 801.A000.0480 */ /* */ /* MPR2 - C-Chip Memory Programming Register 2 */ /* */ __union { unsigned __int64 c_chip$iq_mpr2; unsigned char mpr2$b_pad [64]; } c_chip$r_mpr2_overlay; /* */ /* 801.A000.04C0 */ /* */ /* MPR3 - C-Chip Memory Programming Register 3 */ /* */ __union { unsigned __int64 c_chip$iq_mpr3; unsigned char mpr3$b_pad [64]; } c_chip$r_mpr3_overlay; /* */ /* 801.A000.0500 */ /* */ /* MCTL - C-Chip M-Port Control Register */ /* */ __union { unsigned __int64 c_chip$iq_mctl; unsigned char mctl$b_pad [128]; } c_chip$r_mctl_overlay; /* */ /* 801.A000.0580 */ /* */ /* TTR - C-Chip TIG Bus Timing Register */ /* */ __union { unsigned __int64 c_chip$iq_ttr; unsigned char ttr$b_pad [64]; } c_chip$r_ttr_overlay; /* */ /* 801.A000.05C0 */ /* */ /* TDR - C-Chip TIG Bus Device Timing Register */ /* */ __union { unsigned __int64 c_chip$iq_tdr; unsigned char tdr$b_pad [64]; } c_chip$r_tdr_overlay; /* */ /* 801.A000.0600 */ /* */ /* DIM2 - C-Chip Device Interrupt Mask Register 2 */ /* */ __union { unsigned __int64 c_chip$iq_dim2; unsigned char dim2$b_pad [64]; } c_chip$r_dim2_overlay; /* */ /* 801.A000.0640 */ /* */ /* DIM3 - C-Chip Device Interrupt Mask Register 3 */ /* */ __union { unsigned __int64 c_chip$iq_dim3; unsigned char dim3$b_pad [64]; } c_chip$r_dim3_overlay; /* */ /* 801.A000.0680 */ /* */ /* DIR2 - C-Chip Device Interrupt Request Register 2 */ /* */ __union { unsigned __int64 c_chip$iq_dir2; unsigned char dir2$b_pad [64]; } c_chip$r_dir2_overlay; /* */ /* 801.A000.06C0 */ /* */ /* DIR3 - C-Chip Device Interrupt Request Register 3 */ /* */ __union { unsigned __int64 c_chip$iq_dir3; unsigned char dir3$b_pad [64]; } c_chip$r_dir3_overlay; /* */ /* 801.A000.0700 */ /* */ /* IIC2 - C-Chip Interval Ignore Count Register 2 */ /* */ __union { unsigned __int64 c_chip$iq_iic2; unsigned char iic2$b_pad [64]; } c_chip$r_iic2_overlay; /* */ /* 801.A000.0740 */ /* */ /* IIC3 - C-Chip Interval Ignore Count Register 3 */ /* */ __union { unsigned __int64 c_chip$iq_iic3; unsigned char iic3$b_pad [192]; } c_chip$r_iic3_overlay; /* */ } C_CHIP; #if !defined(__VAXC) #define c_chip$iq_csc c_chip$r_csc_overlay.c_chip$iq_csc #define c_chip$iq_mtr c_chip$r_mtr_overlay.c_chip$iq_mtr #define c_chip$iq_misc c_chip$r_misc_overlay.c_chip$iq_misc #define c_chip$iq_mpd c_chip$r_mpd_overlay.c_chip$iq_mpd #define c_chip$iq_aar0 c_chip$r_aar0_overlay.c_chip$iq_aar0 #define c_chip$iq_aar1 c_chip$r_aar1_overlay.c_chip$iq_aar1 #define c_chip$iq_aar2 c_chip$r_aar2_overlay.c_chip$iq_aar2 #define c_chip$iq_aar3 c_chip$r_aar3_overlay.c_chip$iq_aar3 #define c_chip$iq_dim0 c_chip$r_dim0_overlay.c_chip$iq_dim0 #define c_chip$iq_dim1 c_chip$r_dim1_overlay.c_chip$iq_dim1 #define c_chip$iq_dir0 c_chip$r_dir0_overlay.c_chip$iq_dir0 #define c_chip$iq_dir1 c_chip$r_dir1_overlay.c_chip$iq_dir1 #define c_chip$iq_drir c_chip$r_drir_overlay.c_chip$iq_drir #define c_chip$iq_prben c_chip$r_prben_overlay.c_chip$iq_prben #define c_chip$iq_iic0 c_chip$r_iic0_overlay.c_chip$iq_iic0 #define c_chip$iq_iic1 c_chip$r_iic1_overlay.c_chip$iq_iic1 #define c_chip$iq_mpr0 c_chip$r_mpr0_overlay.c_chip$iq_mpr0 #define c_chip$iq_mpr1 c_chip$r_mpr1_overlay.c_chip$iq_mpr1 #define c_chip$iq_mpr2 c_chip$r_mpr2_overlay.c_chip$iq_mpr2 #define c_chip$iq_mpr3 c_chip$r_mpr3_overlay.c_chip$iq_mpr3 #define c_chip$iq_mctl c_chip$r_mctl_overlay.c_chip$iq_mctl #define c_chip$iq_ttr c_chip$r_ttr_overlay.c_chip$iq_ttr #define c_chip$iq_tdr c_chip$r_tdr_overlay.c_chip$iq_tdr #define c_chip$iq_dim2 c_chip$r_dim2_overlay.c_chip$iq_dim2 #define c_chip$iq_dim3 c_chip$r_dim3_overlay.c_chip$iq_dim3 #define c_chip$iq_dir2 c_chip$r_dir2_overlay.c_chip$iq_dir2 #define c_chip$iq_dir3 c_chip$r_dir3_overlay.c_chip$iq_dir3 #define c_chip$iq_iic2 c_chip$r_iic2_overlay.c_chip$iq_iic2 #define c_chip$iq_iic3 c_chip$r_iic3_overlay.c_chip$iq_iic3 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* */ /*========================================================================== */ /* */ /* D-CHIP Structure */ /* */ /* NOTE: All the registers in this structure are abstracted as 64-bit entities. */ /* Therefore, they MUST be accessed and manipulated as quadwords and with */ /* quadwords. */ /* */ /*========================================================================== */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _d_chip { /* */ /* 801.B000.0800 */ /* */ /* DSC - D-Chip System Configuration Register */ /* */ #pragma __nomember_alignment __union { unsigned __int64 d_chip$iq_dsc; unsigned char dsc$b_pad [64]; } d_chip$r_dsc_overlay; /* */ /* 801.B000.0840 */ /* */ /* STR - D-Chip System Timing Register */ /* */ __union { unsigned __int64 d_chip$iq_str; unsigned char str$b_pad [64]; } d_chip$r_str_overlay; /* */ /* 801.B000.0880 */ /* */ /* DREV - D-Chip System Configuration Register */ /* */ __union { unsigned __int64 d_chip$iq_drev; unsigned char drev$b_pad [64]; } d_chip$r_drev_overlay; /* */ } D_CHIP; #if !defined(__VAXC) #define d_chip$iq_dsc d_chip$r_dsc_overlay.d_chip$iq_dsc #define d_chip$iq_str d_chip$r_str_overlay.d_chip$iq_str #define d_chip$iq_drev d_chip$r_drev_overlay.d_chip$iq_drev #endif /* #if !defined(__VAXC) */ /* */ /* */ /* */ /*========================================================================== */ /* */ /* P-CHIP Structure */ /* */ /* In the addresses below, x = 1 for PChip-0 and x = 3 for PChip-1 */ /* */ /*========================================================================== */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _p_chip { /* */ /* 80x.8000.0000 */ /* */ /* WSBA0 - P-CHip Window Space Base Address Register 0 */ /* */ #pragma __nomember_alignment __union { unsigned __int64 p_chip$iq_wsba0; unsigned char wsba0$b_pad [64]; } p_chip$r_wsba0_overlay; /* */ /* 80x.8000.0040 */ /* */ /* WSBA1 - P-CHip Window Space Base Address Register 1 */ /* */ __union { unsigned __int64 p_chip$iq_wsba1; unsigned char wsba1$b_pad [64]; } p_chip$r_wsba1_overlay; /* */ /* 80x.8000.0080 */ /* */ /* WSBA2 - P-CHip Window Space Base Address Register 2 */ /* */ __union { unsigned __int64 p_chip$iq_wsba2; unsigned char wsba2$b_pad [64]; } p_chip$r_wsba2_overlay; /* */ /* 80x.8000.00C0 */ /* */ /* WSBA3 - P-CHip Window Space Base Address Register 3 */ /* */ __union { unsigned __int64 p_chip$iq_wsba3; unsigned char wsba3$b_pad [64]; } p_chip$r_wsba3_overlay; /* */ /* 80x.8000.0100 */ /* */ /* WSM0 - P-Chip Window Space Mask Register 0 */ /* */ __union { unsigned __int64 p_chip$iq_wsm0; unsigned char wsm0$b_pad [64]; } p_chip$r_wsm0_overlay; /* */ /* 80x.8000.0140 */ /* */ /* WSM1 - P-Chip Window Space Mask Register 1 */ /* */ __union { unsigned __int64 p_chip$iq_wsm1; unsigned char wsm1$b_pad [64]; } p_chip$r_wsm1_overlay; /* */ /* 80x.8000.0180 */ /* */ /* WSM2 - P-Chip Window Space Mask Register 2 */ /* */ __union { unsigned __int64 p_chip$iq_wsm2; unsigned char wsm2$b_pad [64]; } p_chip$r_wsm2_overlay; /* */ /* 80x.8000.01C0 */ /* */ /* WSM3 - P-Chip Window Space Mask Register 3 */ /* */ __union { unsigned __int64 p_chip$iq_wsm3; unsigned char wsm3$b_pad [64]; } p_chip$r_wsm3_overlay; /* */ /* 80x.8000.0200 */ /* */ /* TBA0 - P-Chip Translated Base Address Register 0 */ /* */ __union { unsigned __int64 p_chip$iq_tba0; unsigned char tba0$b_pad [64]; } p_chip$r_tba0_overlay; /* */ /* 80x.8000.0240 */ /* */ /* TBA1 - P-Chip Translated Base Address Register 1 */ /* */ __union { unsigned __int64 p_chip$iq_tba1; unsigned char tba1$b_pad [64]; } p_chip$r_tba1_overlay; /* */ /* 80x.8000.0280 */ /* */ /* TBA2 - P-Chip Translated Base Address Register 2 */ /* */ __union { unsigned __int64 p_chip$iq_tba2; unsigned char tba2$b_pad [64]; } p_chip$r_tba2_overlay; /* */ /* 80x.8000.02C0 */ /* */ /* TBA3 - P-Chip Translated Base Address Register 3 */ /* */ __union { unsigned __int64 p_chip$iq_tba3; unsigned char tba3$b_pad [64]; } p_chip$r_tba3_overlay; /* */ /* 80x.8000.0300 */ /* */ /* PCTL - P-Chip Control Register */ /* */ __union { unsigned __int64 p_chip$iq_pctl; unsigned char pctl$b_pad [64]; } p_chip$r_pctl_overlay; /* */ /* 80x.8000.0340 */ /* */ /* PLAT - P-Chip Master Latency Register */ /* */ __union { unsigned __int64 p_chip$iq_plat; unsigned char plat$b_pad [64]; } p_chip$r_plat_overlay; /* */ /* 80x.8000.0380 */ /* */ /* P_RESERVED_1 - P-Chip Reserved Register 1 */ /* */ __union { unsigned __int64 p_chip$iq_p_reserved_1; unsigned char p_reserved_1$b_pad [64]; } p_chip$r_p_reserved_1_overlay; /* */ /* 80x.8000.03C0 */ /* */ /* PERROR - P-Chip Error Register */ /* */ __union { unsigned __int64 p_chip$iq_perror; unsigned char perror$b_pad [64]; } p_chip$r_perror_overlay; /* */ /* 80x.8000.0400 */ /* */ /* PERRMASK - P-Chip Error Mask Register */ /* */ __union { unsigned __int64 p_chip$iq_perrmask; unsigned char perrmask$b_pad [64]; } p_chip$r_perrmask_overlay; /* */ /* 80x.8000.0440 */ /* */ /* PERRSET - P-Chip Error Set Register */ /* */ __union { unsigned __int64 p_chip$iq_perrset; unsigned char perrset$b_pad [64]; } p_chip$r_perrset_overlay; /* */ /* 80x.8000.0480 */ /* */ /* TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */ /* */ __union { unsigned __int64 p_chip$iq_tlbiv; unsigned char tlbiv$b_pad [64]; } p_chip$r_tlbiv_overlay; /* */ /* 80x.8000.04C0 */ /* */ /* TLBIA - P-Chip Translation Buffer Invalidate all Register */ /* */ __union { unsigned __int64 p_chip$iq_tlbia; unsigned char tlbia$b_pad [64]; } p_chip$r_tlbia_overlay; /* */ /* 80x.8000.0500 */ /* */ /* PMONCTL - P-Chip Monitor Control Register */ /* */ __union { unsigned __int64 p_chip$iq_pmonctl; unsigned char pmonctl$b_pad [64]; } p_chip$r_pmonctl_overlay; /* */ /* 80x.8000.05C0 */ /* */ /* PMONCNT - P-Chip Monitor Counters Register */ /* */ __union { unsigned __int64 p_chip$iq_pmoncnt; unsigned char pmoncnt$b_pad [64]; } p_chip$r_pmoncnt_overlay; } P_CHIP; #if !defined(__VAXC) #define p_chip$iq_wsba0 p_chip$r_wsba0_overlay.p_chip$iq_wsba0 #define p_chip$iq_wsba1 p_chip$r_wsba1_overlay.p_chip$iq_wsba1 #define p_chip$iq_wsba2 p_chip$r_wsba2_overlay.p_chip$iq_wsba2 #define p_chip$iq_wsba3 p_chip$r_wsba3_overlay.p_chip$iq_wsba3 #define p_chip$iq_wsm0 p_chip$r_wsm0_overlay.p_chip$iq_wsm0 #define p_chip$iq_wsm1 p_chip$r_wsm1_overlay.p_chip$iq_wsm1 #define p_chip$iq_wsm2 p_chip$r_wsm2_overlay.p_chip$iq_wsm2 #define p_chip$iq_wsm3 p_chip$r_wsm3_overlay.p_chip$iq_wsm3 #define p_chip$iq_tba0 p_chip$r_tba0_overlay.p_chip$iq_tba0 #define p_chip$iq_tba1 p_chip$r_tba1_overlay.p_chip$iq_tba1 #define p_chip$iq_tba2 p_chip$r_tba2_overlay.p_chip$iq_tba2 #define p_chip$iq_tba3 p_chip$r_tba3_overlay.p_chip$iq_tba3 #define p_chip$iq_pctl p_chip$r_pctl_overlay.p_chip$iq_pctl #define p_chip$iq_plat p_chip$r_plat_overlay.p_chip$iq_plat #define p_chip$iq_p_reserved_1 p_chip$r_p_reserved_1_overlay.p_chip$iq_p_reserved_1 #define p_chip$iq_perror p_chip$r_perror_overlay.p_chip$iq_perror #define p_chip$iq_perrmask p_chip$r_perrmask_overlay.p_chip$iq_perrmask #define p_chip$iq_perrset p_chip$r_perrset_overlay.p_chip$iq_perrset #define p_chip$iq_tlbiv p_chip$r_tlbiv_overlay.p_chip$iq_tlbiv #define p_chip$iq_tlbia p_chip$r_tlbia_overlay.p_chip$iq_tlbia #define p_chip$iq_pmonctl p_chip$r_pmonctl_overlay.p_chip$iq_pmonctl #define p_chip$iq_pmoncnt p_chip$r_pmoncnt_overlay.p_chip$iq_pmoncnt #endif /* #if !defined(__VAXC) */ /*************************************************************************** */ /* */ /* Bit Definitions for the Tsunami Chip Set Registers */ /* */ /*************************************************************************** */ /*========================================================================== */ /* */ /* C-Chip Registers */ /* */ /*========================================================================== */ /* */ /* */ /* CSC - C-Chip System Configuration Register */ /* */ #define CSC$M_BC 0x3 #define CSC$M_C0CFP 0x4 #define CSC$M_C1CFP 0x8 #define CSC$M_SED 0x30 #define CSC$M_SFD 0x40 #define CSC$M_FW 0x80 #define CSC$M_AW 0x100 #define CSC$M_IDDR 0xE00 #define CSC$M_IDDW 0x3000 #define CSC$M_P1P 0x4000 #define CSC$M_RSVD_0 0x8000 #define CSC$M_DWTP 0x30000 #define CSC$M_DWFP 0xC0000 #define CSC$M_DRTP 0x300000 #define CSC$M_RSVD_1 0xC00000 #define CSC$M_PME 0x1000000 #define CSC$M_QPM 0x2000000 #define CSC$M_FET 0xC000000 #define CSC$M_QDI 0x70000000 #define CSC$M_EFT 0x80000000 #define CSC$M_FTI 0x100000000 #define CSC$M_B1D 0x200000000 #define CSC$M_B2D 0x400000000 #define CSC$M_B3D 0x800000000 #define CSC$M_TPQMMAX 0x7000000000 #define CSC$M_RSVD_2 0x8000000000 #define CSC$M_FPQCMAX 0x70000000000 #define CSC$M_RSVD_3 0x80000000000 #define CSC$M_FPQPMAX 0x700000000000 #define CSC$M_RSVD_4 0x800000000000 #define CSC$M_PDTMAX 0x7000000000000 #define CSC$M_RSVD_5 0x8000000000000 #define CSC$M_PRQMAX 0x70000000000000 #define CSC$M_RSVD_6 0x80000000000000 #define CSC$M_PBQMAX 0x700000000000000 #define CSC$M_RSVD_7 0xF800000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _csc { #pragma __nomember_alignment unsigned __int64 csc$iq_data; __struct { unsigned int csc$il_l; unsigned int csc$il_h; } csc$r_longwords; __struct { unsigned csc$v_bc : 2; /* 1:0 Base Configuration */ unsigned csc$v_c0cfp : 1; /* 2 CPU 0 Clk Fwd Preset */ unsigned csc$v_c1cfp : 1; /* 3 CPU 1 Clk Fwd Preset */ unsigned csc$v_sed : 2; /* 5:4 SysDC Extract Delay */ unsigned csc$v_sfd : 1; /* 6 SysDC Fill Delay */ unsigned csc$v_fw : 1; /* 7 available for firmware */ unsigned csc$v_aw : 1; /* 8 Array Width */ unsigned csc$v_iddr : 3; /* 11:9 Issue to Data Delay on read */ unsigned csc$v_iddw : 2; /* 13:12 Issue to Data Delay for all xactions */ unsigned csc$v_p1p : 1; /* 14 P-Chip 1 present */ unsigned csc$v_rsvd_0 : 1; /* 15 reserved */ unsigned csc$v_dwtp : 2; /* 17:16 Min Dchip Delay from CPU to PAD bus */ unsigned csc$v_dwfp : 2; /* 19:18 Min Dchip Delay from PADbus to CPU or Memory */ unsigned csc$v_drtp : 2; /* 21:20 Min Dchip Delay from Memory to PAD bus */ unsigned csc$v_rsvd_1 : 2; /* 23:22 reserved */ unsigned csc$v_pme : 1; /* 24 Page Mode Enable */ unsigned csc$v_qpm : 1; /* 25 Que Priority Mode */ unsigned csc$v_fet : 2; /* 27:26 Fill to Extract Turnaround cycles */ unsigned csc$v_qdi : 3; /* 30:28 Que Drain Interval */ unsigned csc$v_eft : 1; /* 31 Extract to Fill Turnaround cycles */ /* */ unsigned csc$v_fti : 1; /* 32 Full Throttle Issue */ unsigned csc$v_b1d : 1; /* 33 Bypass 1 Issue Path Disable */ unsigned csc$v_b2d : 1; /* 34 Bypass 2 Issue Path Disable */ unsigned csc$v_b3d : 1; /* 35 Bypass 3 Issue Path Disable */ unsigned csc$v_tpqmmax : 3; /* 38:36 Max entries in TPQM on D-Chips, mod 8 */ unsigned csc$v_rsvd_2 : 1; /* 39 reserved */ unsigned csc$v_fpqcmax : 3; /* 42:40 Max entries in FQP, mod 8 */ unsigned csc$v_rsvd_3 : 1; /* 43 reserved */ unsigned csc$v_fpqpmax : 3; /* 46:44 Max entries in FPQ, mod 8 */ unsigned csc$v_rsvd_4 : 1; /* 47 reserved */ unsigned csc$v_pdtmax : 3; /* 50:48 Max data xfers to one P-Chip until ack, mod 8 */ unsigned csc$v_rsvd_5 : 1; /* 51 reserved */ unsigned csc$v_prqmax : 3; /* 54:52 max reqests to one P-Chip until ack, mod 8 */ unsigned csc$v_rsvd_6 : 1; /* 55 reserved */ unsigned csc$v_pbqmax : 3; /* 58:56 Max CPU probe queue */ unsigned csc$v_rsvd_7 : 5; /* 63:59 reserved */ } csc$r_bits; } CSC; #if !defined(__VAXC) #define csc$il_l csc$r_longwords.csc$il_l #define csc$il_h csc$r_longwords.csc$il_h #define csc$v_bc csc$r_bits.csc$v_bc #define csc$v_c0cfp csc$r_bits.csc$v_c0cfp #define csc$v_c1cfp csc$r_bits.csc$v_c1cfp #define csc$v_sed csc$r_bits.csc$v_sed #define csc$v_sfd csc$r_bits.csc$v_sfd #define csc$v_fw csc$r_bits.csc$v_fw #define csc$v_aw csc$r_bits.csc$v_aw #define csc$v_iddr csc$r_bits.csc$v_iddr #define csc$v_iddw csc$r_bits.csc$v_iddw #define csc$v_p1p csc$r_bits.csc$v_p1p #define csc$v_rsvd_0 csc$r_bits.csc$v_rsvd_0 #define csc$v_dwtp csc$r_bits.csc$v_dwtp #define csc$v_dwfp csc$r_bits.csc$v_dwfp #define csc$v_drtp csc$r_bits.csc$v_drtp #define csc$v_rsvd_1 csc$r_bits.csc$v_rsvd_1 #define csc$v_pme csc$r_bits.csc$v_pme #define csc$v_qpm csc$r_bits.csc$v_qpm #define csc$v_fet csc$r_bits.csc$v_fet #define csc$v_qdi csc$r_bits.csc$v_qdi #define csc$v_eft csc$r_bits.csc$v_eft #define csc$v_fti csc$r_bits.csc$v_fti #define csc$v_b1d csc$r_bits.csc$v_b1d #define csc$v_b2d csc$r_bits.csc$v_b2d #define csc$v_b3d csc$r_bits.csc$v_b3d #define csc$v_tpqmmax csc$r_bits.csc$v_tpqmmax #define csc$v_rsvd_2 csc$r_bits.csc$v_rsvd_2 #define csc$v_fpqcmax csc$r_bits.csc$v_fpqcmax #define csc$v_rsvd_3 csc$r_bits.csc$v_rsvd_3 #define csc$v_fpqpmax csc$r_bits.csc$v_fpqpmax #define csc$v_rsvd_4 csc$r_bits.csc$v_rsvd_4 #define csc$v_pdtmax csc$r_bits.csc$v_pdtmax #define csc$v_rsvd_5 csc$r_bits.csc$v_rsvd_5 #define csc$v_prqmax csc$r_bits.csc$v_prqmax #define csc$v_rsvd_6 csc$r_bits.csc$v_rsvd_6 #define csc$v_pbqmax csc$r_bits.csc$v_pbqmax #define csc$v_rsvd_7 csc$r_bits.csc$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* MTR - C-Chip Memory Timing Register */ /* */ #define MTR$M_RCD 0x1 #define MTR$M_RSVD_0 0x2 #define MTR$M_CAT 0x4 #define MTR$M_RSVD_1 0x8 #define MTR$M_IRD 0x70 #define MTR$M_RSVD_2 0x80 #define MTR$M_RPW 0x300 #define MTR$M_RSVD_3 0xC00 #define MTR$M_RPT 0x3000 #define MTR$M_RSVD_4 0xC000 #define MTR$M_RRD 0x10000 #define MTR$M_RSVD_5 0xE0000 #define MTR$M_MPD 0x100000 #define MTR$M_RSVD_6 0xE00000 #define MTR$M_RI 0x3F000000 #define MTR$M_RSVD_7 0xC0000000 #define MTR$M_PHCR 0xF00000000 #define MTR$M_PHCW 0xF000000000 #define MTR$M_MPH 0x3F0000000000 #define MTR$M_RSVD_8 0xFFFFC00000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _mtr { #pragma __nomember_alignment unsigned __int64 mtr$iq_data; __struct { unsigned int mtr$il_l; unsigned int mtr$il_h; } mtr$r_longwords; __struct { unsigned mtr$v_rcd : 1; /* 0 RAS to CAS Delay */ unsigned mtr$v_rsvd_0 : 1; /* 1 reserved */ unsigned mtr$v_cat : 1; /* 2 CAS Access Time */ unsigned mtr$v_rsvd_1 : 1; /* 3 reserved */ unsigned mtr$v_ird : 3; /* 6:4 Issue to RAS Delay */ unsigned mtr$v_rsvd_2 : 1; /* 7 reserved */ unsigned mtr$v_rpw : 2; /* 9:8 Minimum RAS Pulse Width */ unsigned mtr$v_rsvd_3 : 2; /* 11:10 reserved */ unsigned mtr$v_rpt : 2; /* 13:12 Min RAS Precharge Time */ unsigned mtr$v_rsvd_4 : 2; /* 15:14 reserved */ unsigned mtr$v_rrd : 1; /* 16 Min Same-Array_Diff-Bank RAS-to-RAS Delay */ unsigned mtr$v_rsvd_5 : 3; /* 19:17 reserved */ unsigned mtr$v_mpd : 1; /* 20 Mask Pipeline Delay */ unsigned mtr$v_rsvd_6 : 3; /* 23:21 reserved */ unsigned mtr$v_ri : 6; /* 29:24 Refresh Interval */ unsigned mtr$v_rsvd_7 : 2; /* 31:30 reserved */ /* */ unsigned mtr$v_phcr : 4; /* 35:32 Page Hit Cycles for Reads */ unsigned mtr$v_phcw : 4; /* 39:36 Page Hit Cycles for Writes */ unsigned mtr$v_mph : 6; /* 45:40 Max Page Hits */ unsigned mtr$v_rsvd_8 : 18; /* 63:46 reserved */ } mtr$r_bits; } MTR; #if !defined(__VAXC) #define mtr$il_l mtr$r_longwords.mtr$il_l #define mtr$il_h mtr$r_longwords.mtr$il_h #define mtr$v_rcd mtr$r_bits.mtr$v_rcd #define mtr$v_rsvd_0 mtr$r_bits.mtr$v_rsvd_0 #define mtr$v_cat mtr$r_bits.mtr$v_cat #define mtr$v_rsvd_1 mtr$r_bits.mtr$v_rsvd_1 #define mtr$v_ird mtr$r_bits.mtr$v_ird #define mtr$v_rsvd_2 mtr$r_bits.mtr$v_rsvd_2 #define mtr$v_rpw mtr$r_bits.mtr$v_rpw #define mtr$v_rsvd_3 mtr$r_bits.mtr$v_rsvd_3 #define mtr$v_rpt mtr$r_bits.mtr$v_rpt #define mtr$v_rsvd_4 mtr$r_bits.mtr$v_rsvd_4 #define mtr$v_rrd mtr$r_bits.mtr$v_rrd #define mtr$v_rsvd_5 mtr$r_bits.mtr$v_rsvd_5 #define mtr$v_mpd mtr$r_bits.mtr$v_mpd #define mtr$v_rsvd_6 mtr$r_bits.mtr$v_rsvd_6 #define mtr$v_ri mtr$r_bits.mtr$v_ri #define mtr$v_rsvd_7 mtr$r_bits.mtr$v_rsvd_7 #define mtr$v_phcr mtr$r_bits.mtr$v_phcr #define mtr$v_phcw mtr$r_bits.mtr$v_phcw #define mtr$v_mph mtr$r_bits.mtr$v_mph #define mtr$v_rsvd_8 mtr$r_bits.mtr$v_rsvd_8 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* MISC - C-Chip Miscellaneous Register */ /* */ #define MISC$M_CPUID 0x1 #define MISC$M_RSVD_0 0xE #define MISC$M_ITINTR 0x30 #define MISC$M_RSVD_1 0xC0 #define MISC$M_IPINTR 0x300 #define MISC$M_RSVD_2 0xC00 #define MISC$M_IPREQ 0x3000 #define MISC$M_RSVD_3 0xC000 #define MISC$M_ABW 0x30000 #define MISC$M_RSVD_4 0xC0000 #define MISC$M_ABT 0x300000 #define MISC$M_RSVD_5 0xC00000 #define MISC$M_ACL 0x1000000 #define MISC$M_RSVD_6 0xE000000 #define MISC$M_NXM 0x10000000 #define MISC$M_NXS 0xE0000000 #define MISC$M_REV 0xFF00000000 #define MISC$M_DEVSUP 0x30000000000 #define MISC$M_RSVD_7 0xFFFFFC0000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _misc { #pragma __nomember_alignment __struct { unsigned misc$v_cpuid : 1; /* 0 ID of CPU performing the read */ unsigned misc$v_rsvd_0 : 3; /* 3:1 reserved */ unsigned misc$v_itintr : 2; /* 5:4 Interval Timer Interrupt pending */ unsigned misc$v_rsvd_1 : 2; /* 7:6 reserved */ unsigned misc$v_ipintr : 2; /* 9:8 Interprocessor Interrupt pending */ unsigned misc$v_rsvd_2 : 2; /* 11:10 reserved */ unsigned misc$v_ipreq : 2; /* 13:12 Interprocessor Interrupt Request */ unsigned misc$v_rsvd_3 : 2; /* 15:14 reserved */ unsigned misc$v_abw : 2; /* 17:16 Arbitration Won */ unsigned misc$v_rsvd_4 : 2; /* 19:18 reserved */ unsigned misc$v_abt : 2; /* 21:20 Arbitration Try */ unsigned misc$v_rsvd_5 : 2; /* 23:22 reserved */ unsigned misc$v_acl : 1; /* 24 Arbitration Clear */ unsigned misc$v_rsvd_6 : 3; /* 27:25 reserved */ unsigned misc$v_nxm : 1; /* 28 Non eXistent Memory */ unsigned misc$v_nxs : 3; /* 31:29 NXM Source */ /* */ unsigned misc$v_rev : 8; /* 39:32 C-Chip Revision */ unsigned misc$v_devsup : 2; /* 41:40 Suppress IRQ[1] */ unsigned misc$v_rsvd_7 : 22; /* 63:42 reserved */ } misc$r_bits; } MISC; #if !defined(__VAXC) #define misc$v_cpuid misc$r_bits.misc$v_cpuid #define misc$v_rsvd_0 misc$r_bits.misc$v_rsvd_0 #define misc$v_itintr misc$r_bits.misc$v_itintr #define misc$v_rsvd_1 misc$r_bits.misc$v_rsvd_1 #define misc$v_ipintr misc$r_bits.misc$v_ipintr #define misc$v_rsvd_2 misc$r_bits.misc$v_rsvd_2 #define misc$v_ipreq misc$r_bits.misc$v_ipreq #define misc$v_rsvd_3 misc$r_bits.misc$v_rsvd_3 #define misc$v_abw misc$r_bits.misc$v_abw #define misc$v_rsvd_4 misc$r_bits.misc$v_rsvd_4 #define misc$v_abt misc$r_bits.misc$v_abt #define misc$v_rsvd_5 misc$r_bits.misc$v_rsvd_5 #define misc$v_acl misc$r_bits.misc$v_acl #define misc$v_rsvd_6 misc$r_bits.misc$v_rsvd_6 #define misc$v_nxm misc$r_bits.misc$v_nxm #define misc$v_nxs misc$r_bits.misc$v_nxs #define misc$v_rev misc$r_bits.misc$v_rev #define misc$v_devsup misc$r_bits.misc$v_devsup #define misc$v_rsvd_7 misc$r_bits.misc$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* MPD - C-Chip Memory Presence Detect */ /* */ #define MPD$M_CKS 0x1 #define MPD$M_DS 0x2 #define MPD$M_CKR 0x4 #define MPD$M_DR 0x8 #define MPD$M_RSVD_0 0xFFFFFFF0 #define MPD$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _mpd { #pragma __nomember_alignment __struct { unsigned mpd$v_cks : 1; /* 0 ClocK Send */ unsigned mpd$v_ds : 1; /* 1 Data Send */ unsigned mpd$v_ckr : 1; /* 2 ClocK Receive */ unsigned mpd$v_dr : 1; /* 3 Data Receive */ unsigned mpd$v_rsvd_0 : 28; /* 31:4 reserved */ /* */ unsigned mpd$v_rsvd_1 : 32; /* 63:32 reserved */ } mpd$r_bits; } MPD; #if !defined(__VAXC) #define mpd$v_cks mpd$r_bits.mpd$v_cks #define mpd$v_ds mpd$r_bits.mpd$v_ds #define mpd$v_ckr mpd$r_bits.mpd$v_ckr #define mpd$v_dr mpd$r_bits.mpd$v_dr #define mpd$v_rsvd_0 mpd$r_bits.mpd$v_rsvd_0 #define mpd$v_rsvd_1 mpd$r_bits.mpd$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* AAR - C-Chip Array Address Register */ /* */ #define AAR$M_BNKS 0x1 #define AAR$M_RSVD_0 0x2 #define AAR$M_ROWS 0xC #define AAR$M_RSVD_1 0xF0 #define AAR$M_SA 0x100 #define AAR$M_RSVD_2 0xE00 #define AAR$M_ASIZ 0x7000 #define AAR$M_RSVD_3 0x8000 #define AAR$M_DBG 0x10000 #define AAR$M_RSVD_4 0xFE0000 #define AAR$M_ADDR 0xFF000000 #define AAR$M_RSVD_5 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _aar { #pragma __nomember_alignment unsigned __int64 aar$iq_data; __struct { unsigned int aar$il_l; unsigned int aar$il_h; } aar$r_longwords; __struct { unsigned aar$v_bnks : 1; /* 0 Number of Bank bits in DRAMs */ unsigned aar$v_rsvd_0 : 1; /* 1 reserved */ unsigned aar$v_rows : 2; /* 2 Number of Row bits in DRAMS */ unsigned aar$v_rsvd_1 : 4; /* 7:4 reserved */ unsigned aar$v_sa : 1; /* 8 Split Array */ unsigned aar$v_rsvd_2 : 3; /* 11:9 reserved */ unsigned aar$v_asiz : 3; /* 14:12 Array Size */ unsigned aar$v_rsvd_3 : 1; /* 15 reserved */ unsigned aar$v_dbg : 1; /* 16 Enables this memory port as a debug interface */ unsigned aar$v_rsvd_4 : 7; /* 23:17 reserved */ unsigned aar$v_addr : 8; /* 31:24 Base Address */ unsigned aar$v_rsvd_5 : 32; /* 63:32 reserved */ } aar$r_bits; } AAR; #if !defined(__VAXC) #define aar$il_l aar$r_longwords.aar$il_l #define aar$il_h aar$r_longwords.aar$il_h #define aar$v_bnks aar$r_bits.aar$v_bnks #define aar$v_rsvd_0 aar$r_bits.aar$v_rsvd_0 #define aar$v_rows aar$r_bits.aar$v_rows #define aar$v_rsvd_1 aar$r_bits.aar$v_rsvd_1 #define aar$v_sa aar$r_bits.aar$v_sa #define aar$v_rsvd_2 aar$r_bits.aar$v_rsvd_2 #define aar$v_asiz aar$r_bits.aar$v_asiz #define aar$v_rsvd_3 aar$r_bits.aar$v_rsvd_3 #define aar$v_dbg aar$r_bits.aar$v_dbg #define aar$v_rsvd_4 aar$r_bits.aar$v_rsvd_4 #define aar$v_addr aar$r_bits.aar$v_addr #define aar$v_rsvd_5 aar$r_bits.aar$v_rsvd_5 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* DIM - C-Chip Device Interrupt Mask Registers */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _dim { #pragma __nomember_alignment unsigned __int64 dim$iq_data; __struct { unsigned int dim$il_l; unsigned int dim$il_h; } dim$r_longwords; } DIM; #if !defined(__VAXC) #define dim$il_l dim$r_longwords.dim$il_l #define dim$il_h dim$r_longwords.dim$il_h #endif /* #if !defined(__VAXC) */ /* */ /* */ /* DIR - C-Chip Device Interrupt Request Registers */ /* */ #define CDIR$M_DEV_L 0xFFFFFFFF #define CDIR$M_DEV_H 0xFFFFFF00000000 #define CDIR$M_RSVD_0 0x300000000000000 #define CDIR$M_ERR 0xFC00000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _dir { #pragma __nomember_alignment unsigned __int64 cdir$iq_data; __struct { unsigned int cdir$il_l; unsigned int cdir$il_h; } cdir$r_longwords; __struct { unsigned cdir$v_dev_l : 32; /* 31:0 IRQ[1] PCI Interrupts Pending */ unsigned cdir$v_dev_h : 24; /* 55:32 IRQ[1] PCI Interrupts Pending */ unsigned cdir$v_rsvd_0 : 2; /* 57:56 reserved */ unsigned cdir$v_err : 6; /* 63:58 IRQ[0] Error Interrupts */ } cdir$r_bits; } DIR; #if !defined(__VAXC) #define cdir$il_l cdir$r_longwords.cdir$il_l #define cdir$il_h cdir$r_longwords.cdir$il_h #define cdir$v_dev_l cdir$r_bits.cdir$v_dev_l #define cdir$v_dev_h cdir$r_bits.cdir$v_dev_h #define cdir$v_rsvd_0 cdir$r_bits.cdir$v_rsvd_0 #define cdir$v_err cdir$r_bits.cdir$v_err #endif /* #if !defined(__VAXC) */ /* */ /* */ /* DRIR - C-Chip Raw Interrupt Request Register */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _drir { #pragma __nomember_alignment unsigned __int64 drir$iq_data; __struct { unsigned int drir$il_l; unsigned int drir$il_h; } drir$r_longwords; } DRIR; #if !defined(__VAXC) #define drir$il_l drir$r_longwords.drir$il_l #define drir$il_h drir$r_longwords.drir$il_h #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PRBEN - C-Chip Probe Enable Register */ /* */ #define PRBEN$M_PRBEN 0x1 #define PRBEN$M_RSVD_0 0xFFFFFFFE #define PRBEN$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _prben { #pragma __nomember_alignment unsigned __int64 prben$iq_data; __struct { unsigned int prben$il_l; unsigned int prben$il_h; } prben$r_longwords; __struct { unsigned prben$v_prben : 1; /* 0 Probe Enable bit */ unsigned prben$v_rsvd_0 : 31; /* 31:1 Reserved */ unsigned prben$v_rsvd_1 : 32; /* 63:32 Reserved */ } prben$r_bits; } PRBEN; #if !defined(__VAXC) #define prben$il_l prben$r_longwords.prben$il_l #define prben$il_h prben$r_longwords.prben$il_h #define prben$v_prben prben$r_bits.prben$v_prben #define prben$v_rsvd_0 prben$r_bits.prben$v_rsvd_0 #define prben$v_rsvd_1 prben$r_bits.prben$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* IIC - C-Chip Interval Ignore Count Registers */ /* */ #define IIC$M_ICNT 0xFFFFFF #define IIC$M_OF 0x1000000 #define IIC$M_RSVD_0 0xFE000000 #define IIC$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _iic { #pragma __nomember_alignment unsigned __int64 iic$iq_data; __struct { unsigned int iic$il_l; unsigned int iic$il_h; } iic$r_longwords; __struct { unsigned iic$v_icnt : 24; /* 23:0 Count of remaining interrupts to ignore */ unsigned iic$v_of : 1; /* 24 Overflow bit */ unsigned iic$v_rsvd_0 : 7; /* 31:25 reserved */ unsigned iic$v_rsvd_1 : 32; /* 63:32 reserved */ } iic$r_bits; } IIC; #if !defined(__VAXC) #define iic$il_l iic$r_longwords.iic$il_l #define iic$il_h iic$r_longwords.iic$il_h #define iic$v_icnt iic$r_bits.iic$v_icnt #define iic$v_of iic$r_bits.iic$v_of #define iic$v_rsvd_0 iic$r_bits.iic$v_rsvd_0 #define iic$v_rsvd_1 iic$r_bits.iic$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* MPR - C-Chip Memory Programming Registers */ /* */ #define MPR$M_MPRDAT 0x1FFF #define MPR$M_RSVD_0 0xFFFFE000 #define MPR$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _mpr { #pragma __nomember_alignment unsigned __int64 mpr$iq_data; __struct { unsigned int mpr$il_l; unsigned int mpr$il_h; } mpr$r_longwords; __struct { unsigned mpr$v_mprdat : 13; /* 12:0 Data to be written on address lines 12:0 */ unsigned mpr$v_rsvd_0 : 19; /* 31:13 reserved */ unsigned mpr$v_rsvd_1 : 32; /* 63:32 reserved */ } mpr$r_bits; } MPR; #if !defined(__VAXC) #define mpr$il_l mpr$r_longwords.mpr$il_l #define mpr$il_h mpr$r_longwords.mpr$il_h #define mpr$v_mprdat mpr$r_bits.mpr$v_mprdat #define mpr$v_rsvd_0 mpr$r_bits.mpr$v_rsvd_0 #define mpr$v_rsvd_1 mpr$r_bits.mpr$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* MCTL - C-Chip M-Port Control Register */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _mctl { #pragma __nomember_alignment unsigned __int64 mctl$iq_data; __struct { unsigned int mctl$il_l; unsigned int mctl$il_h; } mctl$r_longwords; } MCTL; #if !defined(__VAXC) #define mctl$il_l mctl$r_longwords.mctl$il_l #define mctl$il_h mctl$r_longwords.mctl$il_h #endif /* #if !defined(__VAXC) */ /* */ /* */ /* TTR - C-Chip TIG Bus Timing Register */ /* */ #define TTR$M_AS 0x1 #define TTR$M_AH 0x2 #define TTR$M_RSVD_0 0xC #define TTR$M_IS 0x30 #define TTR$M_RSVD_1 0xC0 #define TTR$M_IRT 0x300 #define TTR$M_RSVD_2 0xC00 #define TTR$M_ID 0x7000 #define TTR$M_RSVD_3 0xFFFF8000 #define TTR$M_RSVD_4 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _ttr { #pragma __nomember_alignment __struct { unsigned ttr$v_as : 1; /* 0 Address Setup to the address latch before AS */ unsigned ttr$v_ah : 1; /* 1 Address Hold after AS before CS_L */ unsigned ttr$v_rsvd_0 : 2; /* 3:2 reserved */ unsigned ttr$v_is : 2; /* 5:4 Interrupt Setup time */ unsigned ttr$v_rsvd_1 : 2; /* 7:6 reserved */ unsigned ttr$v_irt : 2; /* 9:8 Interrupt Read Time */ unsigned ttr$v_rsvd_2 : 2; /* 11:10 reserved */ unsigned ttr$v_id : 3; /* 14:12 Interrupt starting Device */ unsigned ttr$v_rsvd_3 : 17; /* 31:15 reserved */ unsigned ttr$v_rsvd_4 : 32; /* 63:32 reserved */ } ttr$r_bits; } TTR; #if !defined(__VAXC) #define ttr$v_as ttr$r_bits.ttr$v_as #define ttr$v_ah ttr$r_bits.ttr$v_ah #define ttr$v_rsvd_0 ttr$r_bits.ttr$v_rsvd_0 #define ttr$v_is ttr$r_bits.ttr$v_is #define ttr$v_rsvd_1 ttr$r_bits.ttr$v_rsvd_1 #define ttr$v_irt ttr$r_bits.ttr$v_irt #define ttr$v_rsvd_2 ttr$r_bits.ttr$v_rsvd_2 #define ttr$v_id ttr$r_bits.ttr$v_id #define ttr$v_rsvd_3 ttr$r_bits.ttr$v_rsvd_3 #define ttr$v_rsvd_4 ttr$r_bits.ttr$v_rsvd_4 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* TDR - C-Chip TIG Bus Device Timing Register */ /* */ #define TDR$M_RA0 0xF #define TDR$M_RD0 0x70 #define TDR$M_RSVD_0 0x80 #define TDR$M_WS0 0x300 #define TDR$M_RSVD_1 0xC00 #define TDR$M_WP0 0x7000 #define TDR$M_WH0 0x8000 #define TDR$M_RA1 0xF0000 #define TDR$M_RD1 0x700000 #define TDR$M_RSVD_2 0x800000 #define TDR$M_WS1 0x3000000 #define TDR$M_RSVD_3 0xC000000 #define TDR$M_WP1 0x70000000 #define TDR$M_WH1 0x80000000 #define TDR$M_RA2 0xF00000000 #define TDR$M_RD2 0x7000000000 #define TDR$M_RSVD_4 0x8000000000 #define TDR$M_WS2 0x30000000000 #define TDR$M_RSVD_5 0xC0000000000 #define TDR$M_WP2 0x700000000000 #define TDR$M_WH2 0x800000000000 #define TDR$M_RA3 0xF000000000000 #define TDR$M_RD3 0x70000000000000 #define TDR$M_RSVD_6 0x80000000000000 #define TDR$M_WS3 0x300000000000000 #define TDR$M_RSVD_7 0xC00000000000000 #define TDR$M_WP3 0x7000000000000000 #define TDR$M_WH3 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _tdr { #pragma __nomember_alignment unsigned __int64 tdr$iq_data; __struct { unsigned int tdr$il_l; unsigned int tdr$il_h; } tdr$r_longwords; __struct { unsigned tdr$v_ra0 : 4; /* 3:0 Read Access time */ unsigned tdr$v_rd0 : 3; /* 6:4 Read output Disable time */ unsigned tdr$v_rsvd_0 : 1; /* 7 reserved */ unsigned tdr$v_ws0 : 2; /* 9:8 Write Setup time */ unsigned tdr$v_rsvd_1 : 2; /* 11:10 reserved */ unsigned tdr$v_wp0 : 3; /* 14:12 Write Pulse width */ unsigned tdr$v_wh0 : 1; /* 15 Write Hold time */ /* */ unsigned tdr$v_ra1 : 4; /* 19:16 Read Access time */ unsigned tdr$v_rd1 : 3; /* 22:20 Read output Disable time */ unsigned tdr$v_rsvd_2 : 1; /* 23 reserved */ unsigned tdr$v_ws1 : 2; /* 25:24 Write Setup time */ unsigned tdr$v_rsvd_3 : 2; /* 27:26 reserved */ unsigned tdr$v_wp1 : 3; /* 30:28 Write Pulse width */ unsigned tdr$v_wh1 : 1; /* 31 Write Hold time */ /* */ unsigned tdr$v_ra2 : 4; /* 35:32 Read Access time */ unsigned tdr$v_rd2 : 3; /* 38:36 Read output Disable time */ unsigned tdr$v_rsvd_4 : 1; /* 39 reserved */ unsigned tdr$v_ws2 : 2; /* 41:40 Write Setup time */ unsigned tdr$v_rsvd_5 : 2; /* 43:42 reserved */ unsigned tdr$v_wp2 : 3; /* 46:44 Write Pulse width */ unsigned tdr$v_wh2 : 1; /* 47 Write Hold time */ /* */ unsigned tdr$v_ra3 : 4; /* 51:48 Read Access time */ unsigned tdr$v_rd3 : 3; /* 54:52 Read output Disable time */ unsigned tdr$v_rsvd_6 : 1; /* 55 reserved */ unsigned tdr$v_ws3 : 2; /* 57:56 Write Setup time */ unsigned tdr$v_rsvd_7 : 2; /* 59:58 reserved */ unsigned tdr$v_wp3 : 3; /* 62:60 Write Pulse width */ unsigned tdr$v_wh3 : 1; /* 63 Write Hold time */ } tdr$r_bits; } TDR; #if !defined(__VAXC) #define tdr$il_l tdr$r_longwords.tdr$il_l #define tdr$il_h tdr$r_longwords.tdr$il_h #define tdr$v_ra0 tdr$r_bits.tdr$v_ra0 #define tdr$v_rd0 tdr$r_bits.tdr$v_rd0 #define tdr$v_rsvd_0 tdr$r_bits.tdr$v_rsvd_0 #define tdr$v_ws0 tdr$r_bits.tdr$v_ws0 #define tdr$v_rsvd_1 tdr$r_bits.tdr$v_rsvd_1 #define tdr$v_wp0 tdr$r_bits.tdr$v_wp0 #define tdr$v_wh0 tdr$r_bits.tdr$v_wh0 #define tdr$v_ra1 tdr$r_bits.tdr$v_ra1 #define tdr$v_rd1 tdr$r_bits.tdr$v_rd1 #define tdr$v_rsvd_2 tdr$r_bits.tdr$v_rsvd_2 #define tdr$v_ws1 tdr$r_bits.tdr$v_ws1 #define tdr$v_rsvd_3 tdr$r_bits.tdr$v_rsvd_3 #define tdr$v_wp1 tdr$r_bits.tdr$v_wp1 #define tdr$v_wh1 tdr$r_bits.tdr$v_wh1 #define tdr$v_ra2 tdr$r_bits.tdr$v_ra2 #define tdr$v_rd2 tdr$r_bits.tdr$v_rd2 #define tdr$v_rsvd_4 tdr$r_bits.tdr$v_rsvd_4 #define tdr$v_ws2 tdr$r_bits.tdr$v_ws2 #define tdr$v_rsvd_5 tdr$r_bits.tdr$v_rsvd_5 #define tdr$v_wp2 tdr$r_bits.tdr$v_wp2 #define tdr$v_wh2 tdr$r_bits.tdr$v_wh2 #define tdr$v_ra3 tdr$r_bits.tdr$v_ra3 #define tdr$v_rd3 tdr$r_bits.tdr$v_rd3 #define tdr$v_rsvd_6 tdr$r_bits.tdr$v_rsvd_6 #define tdr$v_ws3 tdr$r_bits.tdr$v_ws3 #define tdr$v_rsvd_7 tdr$r_bits.tdr$v_rsvd_7 #define tdr$v_wp3 tdr$r_bits.tdr$v_wp3 #define tdr$v_wh3 tdr$r_bits.tdr$v_wh3 #endif /* #if !defined(__VAXC) */ /*========================================================================== */ /* */ /* D-Chip Registers */ /* */ /*========================================================================== */ /* */ /* */ /* DSC - D-Chip System Configuration Register */ /* */ #define DSC$M_BC 0x3 #define DSC$M_C0CFP 0x4 #define DSC$M_C1CFP 0x8 #define DSC$M_C2CFP 0x10 #define DSC$M_C3CFP 0x20 #define DSC$M_P1P 0x40 #define DSC$M_RSVD_0 0x80 #define DSC$M_BC1 0x300 #define DSC$M_C0CFP1 0x400 #define DSC$M_C1CFP1 0x800 #define DSC$M_C2CFP1 0x1000 #define DSC$M_C3CFP1 0x2000 #define DSC$M_P1P1 0x4000 #define DSC$M_RSVD_1 0x8000 #define DSC$M_BC2 0x30000 #define DSC$M_C0CFP2 0x40000 #define DSC$M_C1CFP2 0x80000 #define DSC$M_C2CFP2 0x100000 #define DSC$M_C3CFP2 0x200000 #define DSC$M_P1P2 0x400000 #define DSC$M_RSVD_2 0x800000 #define DSC$M_BC3 0x3000000 #define DSC$M_C0CFP3 0x4000000 #define DSC$M_C1CFP3 0x8000000 #define DSC$M_C2CFP3 0x10000000 #define DSC$M_C3CFP3 0x20000000 #define DSC$M_P1P3 0x40000000 #define DSC$M_RSVD_3 0x80000000 #define DSC$M_BC4 0x300000000 #define DSC$M_C0CFP4 0x400000000 #define DSC$M_C1CFP4 0x800000000 #define DSC$M_C2CFP4 0x1000000000 #define DSC$M_C3CFP4 0x2000000000 #define DSC$M_P1P4 0x4000000000 #define DSC$M_RSVD_4 0x8000000000 #define DSC$M_BC15 0x30000000000 #define DSC$M_C0CFP5 0x40000000000 #define DSC$M_C1CFP5 0x80000000000 #define DSC$M_C2CFP5 0x100000000000 #define DSC$M_C3CFP5 0x200000000000 #define DSC$M_P1P5 0x400000000000 #define DSC$M_RSVD_5 0x800000000000 #define DSC$M_BC6 0x3000000000000 #define DSC$M_C0CFP6 0x4000000000000 #define DSC$M_C1CFP6 0x8000000000000 #define DSC$M_C2CFP6 0x10000000000000 #define DSC$M_C3CFP6 0x20000000000000 #define DSC$M_P1P6 0x40000000000000 #define DSC$M_RSVD_6 0x80000000000000 #define DSC$M_BC7 0x300000000000000 #define DSC$M_C0CFP7 0x400000000000000 #define DSC$M_C1CFP7 0x800000000000000 #define DSC$M_C2CFP7 0x1000000000000000 #define DSC$M_C3CFP7 0x2000000000000000 #define DSC$M_P1P7 0x4000000000000000 #define DSC$M_RSVD_7 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _dsc { #pragma __nomember_alignment unsigned __int64 dsc$iq_data; __struct { unsigned int dsc$il_l; unsigned int dsc$il_h; } dsc$r_longwords; __struct { unsigned dsc$v_bc : 2; /* 1:0 Base Configuration */ unsigned dsc$v_c0cfp : 1; /* 2 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp : 1; /* 3 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp : 1; /* 4 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp : 1; /* 5 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p : 1; /* 6 P-Chip_1 Preset */ unsigned dsc$v_rsvd_0 : 1; /* 7 reserved */ /* */ unsigned dsc$v_bc1 : 2; /* 9:8 Base Configuration */ unsigned dsc$v_c0cfp1 : 1; /* 10 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp1 : 1; /* 11 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp1 : 1; /* 12 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp1 : 1; /* 13 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p1 : 1; /* 14 P-Chip_1 Preset */ unsigned dsc$v_rsvd_1 : 1; /* 15 reserved */ /* */ unsigned dsc$v_bc2 : 2; /* 17:16 Base Configuration */ unsigned dsc$v_c0cfp2 : 1; /* 18 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp2 : 1; /* 19 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp2 : 1; /* 20 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp2 : 1; /* 21 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p2 : 1; /* 22 P-Chip_1 Preset */ unsigned dsc$v_rsvd_2 : 1; /* 23 reserved */ /* */ unsigned dsc$v_bc3 : 2; /* 25:24 Base Configuration */ unsigned dsc$v_c0cfp3 : 1; /* 26 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp3 : 1; /* 27 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp3 : 1; /* 28 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp3 : 1; /* 29 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p3 : 1; /* 30 P-Chip_1 Preset */ unsigned dsc$v_rsvd_3 : 1; /* 31 reserved */ /* */ unsigned dsc$v_bc4 : 2; /* 33:32 Base Configuration */ unsigned dsc$v_c0cfp4 : 1; /* 34 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp4 : 1; /* 35 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp4 : 1; /* 36 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp4 : 1; /* 37 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p4 : 1; /* 38 P-Chip_1 Preset */ unsigned dsc$v_rsvd_4 : 1; /* 39 reserved */ /* */ unsigned dsc$v_bc15 : 2; /* 41:40 Base Configuration */ unsigned dsc$v_c0cfp5 : 1; /* 42 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp5 : 1; /* 43 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp5 : 1; /* 44 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp5 : 1; /* 45 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p5 : 1; /* 46 P-Chip_1 Preset */ unsigned dsc$v_rsvd_5 : 1; /* 47 reserved */ /* */ unsigned dsc$v_bc6 : 2; /* 49:48 Base Configuration */ unsigned dsc$v_c0cfp6 : 1; /* 50 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp6 : 1; /* 51 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp6 : 1; /* 52 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp6 : 1; /* 53 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p6 : 1; /* 54 P-Chip_1 Preset */ unsigned dsc$v_rsvd_6 : 1; /* 55 reserved */ /* */ unsigned dsc$v_bc7 : 2; /* 57:56 Base Configuration */ unsigned dsc$v_c0cfp7 : 1; /* 58 CPU 0 Clock Forward Preset */ unsigned dsc$v_c1cfp7 : 1; /* 59 CPU 0 Clock Forward Preset */ unsigned dsc$v_c2cfp7 : 1; /* 60 CPU 0 Clock Forward Preset */ unsigned dsc$v_c3cfp7 : 1; /* 61 CPU 0 Clock Forward Preset */ unsigned dsc$v_p1p7 : 1; /* 62 P-Chip_1 Preset */ unsigned dsc$v_rsvd_7 : 1; /* 63 reserved */ } dsc$r_bits; } DSC; #if !defined(__VAXC) #define dsc$il_l dsc$r_longwords.dsc$il_l #define dsc$il_h dsc$r_longwords.dsc$il_h #define dsc$v_bc dsc$r_bits.dsc$v_bc #define dsc$v_c0cfp dsc$r_bits.dsc$v_c0cfp #define dsc$v_c1cfp dsc$r_bits.dsc$v_c1cfp #define dsc$v_c2cfp dsc$r_bits.dsc$v_c2cfp #define dsc$v_c3cfp dsc$r_bits.dsc$v_c3cfp #define dsc$v_p1p dsc$r_bits.dsc$v_p1p #define dsc$v_rsvd_0 dsc$r_bits.dsc$v_rsvd_0 #define dsc$v_bc1 dsc$r_bits.dsc$v_bc1 #define dsc$v_c0cfp1 dsc$r_bits.dsc$v_c0cfp1 #define dsc$v_c1cfp1 dsc$r_bits.dsc$v_c1cfp1 #define dsc$v_c2cfp1 dsc$r_bits.dsc$v_c2cfp1 #define dsc$v_c3cfp1 dsc$r_bits.dsc$v_c3cfp1 #define dsc$v_p1p1 dsc$r_bits.dsc$v_p1p1 #define dsc$v_rsvd_1 dsc$r_bits.dsc$v_rsvd_1 #define dsc$v_bc2 dsc$r_bits.dsc$v_bc2 #define dsc$v_c0cfp2 dsc$r_bits.dsc$v_c0cfp2 #define dsc$v_c1cfp2 dsc$r_bits.dsc$v_c1cfp2 #define dsc$v_c2cfp2 dsc$r_bits.dsc$v_c2cfp2 #define dsc$v_c3cfp2 dsc$r_bits.dsc$v_c3cfp2 #define dsc$v_p1p2 dsc$r_bits.dsc$v_p1p2 #define dsc$v_rsvd_2 dsc$r_bits.dsc$v_rsvd_2 #define dsc$v_bc3 dsc$r_bits.dsc$v_bc3 #define dsc$v_c0cfp3 dsc$r_bits.dsc$v_c0cfp3 #define dsc$v_c1cfp3 dsc$r_bits.dsc$v_c1cfp3 #define dsc$v_c2cfp3 dsc$r_bits.dsc$v_c2cfp3 #define dsc$v_c3cfp3 dsc$r_bits.dsc$v_c3cfp3 #define dsc$v_p1p3 dsc$r_bits.dsc$v_p1p3 #define dsc$v_rsvd_3 dsc$r_bits.dsc$v_rsvd_3 #define dsc$v_bc4 dsc$r_bits.dsc$v_bc4 #define dsc$v_c0cfp4 dsc$r_bits.dsc$v_c0cfp4 #define dsc$v_c1cfp4 dsc$r_bits.dsc$v_c1cfp4 #define dsc$v_c2cfp4 dsc$r_bits.dsc$v_c2cfp4 #define dsc$v_c3cfp4 dsc$r_bits.dsc$v_c3cfp4 #define dsc$v_p1p4 dsc$r_bits.dsc$v_p1p4 #define dsc$v_rsvd_4 dsc$r_bits.dsc$v_rsvd_4 #define dsc$v_bc15 dsc$r_bits.dsc$v_bc15 #define dsc$v_c0cfp5 dsc$r_bits.dsc$v_c0cfp5 #define dsc$v_c1cfp5 dsc$r_bits.dsc$v_c1cfp5 #define dsc$v_c2cfp5 dsc$r_bits.dsc$v_c2cfp5 #define dsc$v_c3cfp5 dsc$r_bits.dsc$v_c3cfp5 #define dsc$v_p1p5 dsc$r_bits.dsc$v_p1p5 #define dsc$v_rsvd_5 dsc$r_bits.dsc$v_rsvd_5 #define dsc$v_bc6 dsc$r_bits.dsc$v_bc6 #define dsc$v_c0cfp6 dsc$r_bits.dsc$v_c0cfp6 #define dsc$v_c1cfp6 dsc$r_bits.dsc$v_c1cfp6 #define dsc$v_c2cfp6 dsc$r_bits.dsc$v_c2cfp6 #define dsc$v_c3cfp6 dsc$r_bits.dsc$v_c3cfp6 #define dsc$v_p1p6 dsc$r_bits.dsc$v_p1p6 #define dsc$v_rsvd_6 dsc$r_bits.dsc$v_rsvd_6 #define dsc$v_bc7 dsc$r_bits.dsc$v_bc7 #define dsc$v_c0cfp7 dsc$r_bits.dsc$v_c0cfp7 #define dsc$v_c1cfp7 dsc$r_bits.dsc$v_c1cfp7 #define dsc$v_c2cfp7 dsc$r_bits.dsc$v_c2cfp7 #define dsc$v_c3cfp7 dsc$r_bits.dsc$v_c3cfp7 #define dsc$v_p1p7 dsc$r_bits.dsc$v_p1p7 #define dsc$v_rsvd_7 dsc$r_bits.dsc$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* STR - D-Chip System Timing Register */ /* */ #define STR$M_AW 0x1 #define STR$M_IDDR 0xE #define STR$M_IDDW 0x30 #define STR$M_RSVD_0 0xC0 #define STR$M_AW1 0x100 #define STR$M_IDDR1 0xE00 #define STR$M_IDDW1 0x3000 #define STR$M_RSVD_1 0xC000 #define STR$M_AW2 0x10000 #define STR$M_IDDR2 0xE0000 #define STR$M_IDDW2 0x300000 #define STR$M_RSVD_2 0xC00000 #define STR$M_AW3 0x1000000 #define STR$M_IDDR3 0xE000000 #define STR$M_IDDW3 0x30000000 #define STR$M_RSVD_3 0xC0000000 #define STR$M_AW4 0x100000000 #define STR$M_IDDR4 0xE00000000 #define STR$M_IDDW4 0x3000000000 #define STR$M_RSVD_4 0xC000000000 #define STR$M_AW5 0x10000000000 #define STR$M_IDDR5 0xE0000000000 #define STR$M_IDDW5 0x300000000000 #define STR$M_RSVD_5 0xC00000000000 #define STR$M_AW6 0x1000000000000 #define STR$M_IDDR6 0xE000000000000 #define STR$M_IDDW6 0x30000000000000 #define STR$M_RSVD_6 0xC0000000000000 #define STR$M_AW7 0x100000000000000 #define STR$M_IDDR7 0xE00000000000000 #define STR$M_IDDW7 0x3000000000000000 #define STR$M_RSVD_7 0xC000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _str { #pragma __nomember_alignment unsigned __int64 str$iq_data; __struct { unsigned int str$il_l; unsigned int str$il_h; } str$r_longwords; __struct { unsigned str$v_aw : 1; /* 0 Array Width */ unsigned str$v_iddr : 3; /* 3:1 Issue to Data Delay for memory reads */ unsigned str$v_iddw : 2; /* 5:4 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_0 : 2; /* 7:6 reserved */ /* */ unsigned str$v_aw1 : 1; /* 8 Array Width */ unsigned str$v_iddr1 : 3; /* 11:9 Issue to Data Delay for memory reads */ unsigned str$v_iddw1 : 2; /* 13:12 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_1 : 2; /* 15:14 reserved */ /* */ unsigned str$v_aw2 : 1; /* 16 Array Width */ unsigned str$v_iddr2 : 3; /* 19:17 Issue to Data Delay for memory reads */ unsigned str$v_iddw2 : 2; /* 21:20 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_2 : 2; /* 23:22 reserved */ /* */ unsigned str$v_aw3 : 1; /* 24 Array Width */ unsigned str$v_iddr3 : 3; /* 27:25 Issue to Data Delay for memory reads */ unsigned str$v_iddw3 : 2; /* 29:28 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_3 : 2; /* 31:30 reserved */ /* */ unsigned str$v_aw4 : 1; /* 32 Array Width */ unsigned str$v_iddr4 : 3; /* 35:33 Issue to Data Delay for memory reads */ unsigned str$v_iddw4 : 2; /* 37:36 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_4 : 2; /* 39:38 reserved */ /* */ unsigned str$v_aw5 : 1; /* 40 Array Width */ unsigned str$v_iddr5 : 3; /* 43:41 Issue to Data Delay for memory reads */ unsigned str$v_iddw5 : 2; /* 45:44 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_5 : 2; /* 47:46 reserved */ /* */ unsigned str$v_aw6 : 1; /* 48 Array Width */ unsigned str$v_iddr6 : 3; /* 51:49 Issue to Data Delay for memory reads */ unsigned str$v_iddw6 : 2; /* 53:52 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_6 : 2; /* 55:54 reserved */ /* */ unsigned str$v_aw7 : 1; /* 56 Array Width */ unsigned str$v_iddr7 : 3; /* 59:57 Issue to Data Delay for memory reads */ unsigned str$v_iddw7 : 2; /* 61:60 Issue to Data Delay for xactions other than memory reads */ unsigned str$v_rsvd_7 : 2; /* 63:62 reserved */ } str$r_bits; } STR; #if !defined(__VAXC) #define str$il_l str$r_longwords.str$il_l #define str$il_h str$r_longwords.str$il_h #define str$v_aw str$r_bits.str$v_aw #define str$v_iddr str$r_bits.str$v_iddr #define str$v_iddw str$r_bits.str$v_iddw #define str$v_rsvd_0 str$r_bits.str$v_rsvd_0 #define str$v_aw1 str$r_bits.str$v_aw1 #define str$v_iddr1 str$r_bits.str$v_iddr1 #define str$v_iddw1 str$r_bits.str$v_iddw1 #define str$v_rsvd_1 str$r_bits.str$v_rsvd_1 #define str$v_aw2 str$r_bits.str$v_aw2 #define str$v_iddr2 str$r_bits.str$v_iddr2 #define str$v_iddw2 str$r_bits.str$v_iddw2 #define str$v_rsvd_2 str$r_bits.str$v_rsvd_2 #define str$v_aw3 str$r_bits.str$v_aw3 #define str$v_iddr3 str$r_bits.str$v_iddr3 #define str$v_iddw3 str$r_bits.str$v_iddw3 #define str$v_rsvd_3 str$r_bits.str$v_rsvd_3 #define str$v_aw4 str$r_bits.str$v_aw4 #define str$v_iddr4 str$r_bits.str$v_iddr4 #define str$v_iddw4 str$r_bits.str$v_iddw4 #define str$v_rsvd_4 str$r_bits.str$v_rsvd_4 #define str$v_aw5 str$r_bits.str$v_aw5 #define str$v_iddr5 str$r_bits.str$v_iddr5 #define str$v_iddw5 str$r_bits.str$v_iddw5 #define str$v_rsvd_5 str$r_bits.str$v_rsvd_5 #define str$v_aw6 str$r_bits.str$v_aw6 #define str$v_iddr6 str$r_bits.str$v_iddr6 #define str$v_iddw6 str$r_bits.str$v_iddw6 #define str$v_rsvd_6 str$r_bits.str$v_rsvd_6 #define str$v_aw7 str$r_bits.str$v_aw7 #define str$v_iddr7 str$r_bits.str$v_iddr7 #define str$v_iddw7 str$r_bits.str$v_iddw7 #define str$v_rsvd_7 str$r_bits.str$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* DREV - D-Chip System Configuration Register */ /* */ #define DREV$M_REV0 0xF #define DREV$M_RSVD_0 0xF0 #define DREV$M_REV1 0xF00 #define DREV$M_RSVD_1 0xF000 #define DREV$M_REV2 0xF0000 #define DREV$M_RSVD_2 0xF00000 #define DREV$M_REV3 0xF000000 #define DREV$M_RSVD_3 0xF0000000 #define DREV$M_REV4 0xF00000000 #define DREV$M_RSVD_4 0xF000000000 #define DREV$M_REV5 0xF0000000000 #define DREV$M_RSVD_5 0xF00000000000 #define DREV$M_REV6 0xF000000000000 #define DREV$M_RSVD_6 0xF0000000000000 #define DREV$M_REV7 0xF00000000000000 #define DREV$M_RSVD_7 0xF000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _drev { #pragma __nomember_alignment unsigned __int64 drev$iq_data; __struct { unsigned int drev$il_l; unsigned int drev$il_h; } drev$r_longwords; __struct { unsigned drev$v_rev0 : 4; /* 3:0 D-Chip 0 Revision */ unsigned drev$v_rsvd_0 : 4; /* 7:4 CPU 0 Clk Fwd Preset */ /* */ unsigned drev$v_rev1 : 4; /* 11:8 D-Chip 1 Revision */ unsigned drev$v_rsvd_1 : 4; /* 15:12 CPU 1 Clk Fwd Preset */ /* */ unsigned drev$v_rev2 : 4; /* 19:16 D-Chip 2 Revision */ unsigned drev$v_rsvd_2 : 4; /* 23:20 CPU 2 Clk Fwd Preset */ /* */ unsigned drev$v_rev3 : 4; /* 27:24 D-Chip 3 Revision */ unsigned drev$v_rsvd_3 : 4; /* 31:28 CPU 3 Clk Fwd Preset */ /* */ unsigned drev$v_rev4 : 4; /* 35:32 D-Chip 4 Revision */ unsigned drev$v_rsvd_4 : 4; /* 39:36 CPU 4 Clk Fwd Preset */ /* */ unsigned drev$v_rev5 : 4; /* 43:40 D-Chip 5 Revision */ unsigned drev$v_rsvd_5 : 4; /* 47:44 CPU 5 Clk Fwd Preset */ /* */ unsigned drev$v_rev6 : 4; /* 51:48 D-Chip 6 Revision */ unsigned drev$v_rsvd_6 : 4; /* 55:52 CPU 6 Clk Fwd Preset */ /* */ unsigned drev$v_rev7 : 4; /* 59:56 D-Chip 7 Revision */ unsigned drev$v_rsvd_7 : 4; /* 63:60 CPU 7 Clk Fwd Preset */ } drev$r_bits; } DREV; #if !defined(__VAXC) #define drev$il_l drev$r_longwords.drev$il_l #define drev$il_h drev$r_longwords.drev$il_h #define drev$v_rev0 drev$r_bits.drev$v_rev0 #define drev$v_rsvd_0 drev$r_bits.drev$v_rsvd_0 #define drev$v_rev1 drev$r_bits.drev$v_rev1 #define drev$v_rsvd_1 drev$r_bits.drev$v_rsvd_1 #define drev$v_rev2 drev$r_bits.drev$v_rev2 #define drev$v_rsvd_2 drev$r_bits.drev$v_rsvd_2 #define drev$v_rev3 drev$r_bits.drev$v_rev3 #define drev$v_rsvd_3 drev$r_bits.drev$v_rsvd_3 #define drev$v_rev4 drev$r_bits.drev$v_rev4 #define drev$v_rsvd_4 drev$r_bits.drev$v_rsvd_4 #define drev$v_rev5 drev$r_bits.drev$v_rev5 #define drev$v_rsvd_5 drev$r_bits.drev$v_rsvd_5 #define drev$v_rev6 drev$r_bits.drev$v_rev6 #define drev$v_rsvd_6 drev$r_bits.drev$v_rsvd_6 #define drev$v_rev7 drev$r_bits.drev$v_rev7 #define drev$v_rsvd_7 drev$r_bits.drev$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /*========================================================================== */ /* */ /* P-Chip Registers */ /* */ /*========================================================================== */ /* */ /* */ /* WSBA - P-Chip Window Space Base Address Registers */ /* */ #define WSBA$M_ENA 0x1 #define WSBA$M_SG 0x2 #define WSBA$M_PTP 0x4 #define WSBA$M_RSVD_0 0xFFFF8 #define WSBA$M_ADDR 0xFFF00000 #define WSBA$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _wsba { #pragma __nomember_alignment unsigned __int64 wsba$iq_data; __struct { unsigned int wsba$il_l; unsigned int wsba$il_h; } wsba$r_longwords; __struct { unsigned wsba$v_ena : 1; /* 0 Enable */ unsigned wsba$v_sg : 1; /* 1 Scatter/Gather */ unsigned wsba$v_ptp : 1; /* 2 Peer-to-Peer */ unsigned wsba$v_rsvd_0 : 17; /* 19:3 reserved */ unsigned wsba$v_addr : 12; /* 31:20 Base Address */ unsigned wsba$v_rsvd_1 : 32; /* 63:32 Reserved */ } wsba$r_bits; } WSBA; #if !defined(__VAXC) #define wsba$il_l wsba$r_longwords.wsba$il_l #define wsba$il_h wsba$r_longwords.wsba$il_h #define wsba$v_ena wsba$r_bits.wsba$v_ena #define wsba$v_sg wsba$r_bits.wsba$v_sg #define wsba$v_ptp wsba$r_bits.wsba$v_ptp #define wsba$v_rsvd_0 wsba$r_bits.wsba$v_rsvd_0 #define wsba$v_addr wsba$r_bits.wsba$v_addr #define wsba$v_rsvd_1 wsba$r_bits.wsba$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* WSM - P-Chip Window Space Mask Registers */ /* */ #define WSM$M_RSVD_0 0xFFFFF #define WSM$M_AM 0xFFF00000 #define WSM$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _wsm { #pragma __nomember_alignment unsigned __int64 wsm$iq_data; __struct { unsigned int wsm$il_l; unsigned int wsm$il_h; } wsm$r_longwords; __struct { unsigned wsm$v_rsvd_0 : 20; /* 19:0 reserved */ unsigned wsm$v_am : 12; /* 31:20 Base Address */ unsigned wsm$v_rsvd_1 : 32; /* 63:32 Reserved */ } wsm$r_bits; } WSM; #if !defined(__VAXC) #define wsm$il_l wsm$r_longwords.wsm$il_l #define wsm$il_h wsm$r_longwords.wsm$il_h #define wsm$v_rsvd_0 wsm$r_bits.wsm$v_rsvd_0 #define wsm$v_am wsm$r_bits.wsm$v_am #define wsm$v_rsvd_1 wsm$r_bits.wsm$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* TBA - P-Chip Translated Base Address Registers */ /* */ #define TBA$M_RSVD_0 0x3FF #define TBA$M_ADDR 0x7FFFFFC00 #define TBA$M_RSVD_1 0xFFFFFFF800000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _tba { #pragma __nomember_alignment unsigned __int64 tba$iq_data; __struct { unsigned int tba$il_l; unsigned int tba$il_h; } tba$r_longwords; __struct { unsigned tba$v_rsvd_0 : 10; /* 9:0 reserved */ unsigned tba$v_addr : 25; /* 34:10 Translated Base Address */ unsigned tba$v_rsvd_1 : 29; /* 63:35 reserved */ } tba$r_bits; } TBA; #if !defined(__VAXC) #define tba$il_l tba$r_longwords.tba$il_l #define tba$il_h tba$r_longwords.tba$il_h #define tba$v_rsvd_0 tba$r_bits.tba$v_rsvd_0 #define tba$v_addr tba$r_bits.tba$v_addr #define tba$v_rsvd_1 tba$r_bits.tba$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PCTL - P-Chip Control Register */ /* */ #define PCTL$M_FDSC 0x1 #define PCTL$M_FBTB 0x2 #define PCTL$M_THDIS 0x4 #define PCTL$M_CHAINDIS 0x8 #define PCTL$M_TGTLAT 0x10 #define PCTL$M_HOLE 0x20 #define PCTL$M_MWIN 0x40 #define PCTL$M_ARBENA 0x80 #define PCTL$M_PRIGRP 0x7F00 #define PCTL$M_PPRI 0x8000 #define PCTL$M_RSVD_0 0x30000 #define PCTL$M_ECCEN 0x40000 #define PCTL$M_PADM 0x80000 #define PCTL$M_CDQMAX 0xF00000 #define PCTL$M_REV 0xFF000000 #define PCTL$M_CRQMAX 0xF00000000 #define PCTL$M_PTPMAX 0xF000000000 #define PCTL$M_PCLKX 0x30000000000 #define PCTL$M_FDSDIS 0x40000000000 #define PCTL$M_FDWDIS 0x80000000000 #define PCTL$M_PTEVRFY 0x100000000000 #define PCTL$M_RSVD_1 0xFFFFE00000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _pctl { #pragma __nomember_alignment unsigned __int64 pctl$iq_data; __struct { unsigned int pctl$il_l; unsigned int pctl$il_h; } pctl$r_longwords; __struct { unsigned pctl$v_fdsc : 1; /* 0 Fast Discard enable */ unsigned pctl$v_fbtb : 1; /* 1 Fast Back-To-Back enable */ unsigned pctl$v_thdis : 1; /* 2 Disable anti-Thrash mechanism for TLB */ unsigned pctl$v_chaindis : 1; /* 3 Disable Chaining */ unsigned pctl$v_tgtlat : 1; /* 4 Target Latency Timers timers enable */ unsigned pctl$v_hole : 1; /* 5 512K to 1M window Hole enable */ unsigned pctl$v_mwin : 1; /* 6 Monster Window enable */ unsigned pctl$v_arbena : 1; /* 7 internal Arbiter Enable */ unsigned pctl$v_prigrp : 7; /* 14:8 arbiter Priority Group */ unsigned pctl$v_ppri : 1; /* 15 arbiter Priority Group for the Pchip itself */ unsigned pctl$v_rsvd_0 : 2; /* 17:16 reserved */ unsigned pctl$v_eccen : 1; /* 18 ECC Enable for DMA & SGTE accesses */ unsigned pctl$v_padm : 1; /* 19 PAD bus Mode */ unsigned pctl$v_cdqmax : 4; /* 23:20 Max Data xfer to Dchips from both Pchips */ unsigned pctl$v_rev : 8; /* 31:24 Revision */ /* */ unsigned pctl$v_crqmax : 4; /* 35:32 Max requests to Cchip from both Pchips */ unsigned pctl$v_ptpmax : 4; /* 39:36 Max PTP requests to Cchip from both Pchips */ unsigned pctl$v_pclkx : 2; /* 41:40 PCI Clock Freq Multiplier */ unsigned pctl$v_fdsdis : 1; /* 42 Fast DMA Start & SGTE request Disable */ unsigned pctl$v_fdwdis : 1; /* 43 Fast DMA read cache blk Wrap request Disable */ unsigned pctl$v_ptevrfy : 1; /* 44 PTE Verify for DMA read */ unsigned pctl$v_rsvd_1 : 19; /* 63:45 reserved */ } pctl$r_bits; } PCTL; #if !defined(__VAXC) #define pctl$il_l pctl$r_longwords.pctl$il_l #define pctl$il_h pctl$r_longwords.pctl$il_h #define pctl$v_fdsc pctl$r_bits.pctl$v_fdsc #define pctl$v_fbtb pctl$r_bits.pctl$v_fbtb #define pctl$v_thdis pctl$r_bits.pctl$v_thdis #define pctl$v_chaindis pctl$r_bits.pctl$v_chaindis #define pctl$v_tgtlat pctl$r_bits.pctl$v_tgtlat #define pctl$v_hole pctl$r_bits.pctl$v_hole #define pctl$v_mwin pctl$r_bits.pctl$v_mwin #define pctl$v_arbena pctl$r_bits.pctl$v_arbena #define pctl$v_prigrp pctl$r_bits.pctl$v_prigrp #define pctl$v_ppri pctl$r_bits.pctl$v_ppri #define pctl$v_rsvd_0 pctl$r_bits.pctl$v_rsvd_0 #define pctl$v_eccen pctl$r_bits.pctl$v_eccen #define pctl$v_padm pctl$r_bits.pctl$v_padm #define pctl$v_cdqmax pctl$r_bits.pctl$v_cdqmax #define pctl$v_rev pctl$r_bits.pctl$v_rev #define pctl$v_crqmax pctl$r_bits.pctl$v_crqmax #define pctl$v_ptpmax pctl$r_bits.pctl$v_ptpmax #define pctl$v_pclkx pctl$r_bits.pctl$v_pclkx #define pctl$v_fdsdis pctl$r_bits.pctl$v_fdsdis #define pctl$v_fdwdis pctl$r_bits.pctl$v_fdwdis #define pctl$v_ptevrfy pctl$r_bits.pctl$v_ptevrfy #define pctl$v_rsvd_1 pctl$r_bits.pctl$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PLAT - P-Chip Master Latency Register */ /* */ #define PLAT$M_RSVD_0 0xFF #define PLAT$M_LAT 0xFF00 #define PLAT$M_RSVD_1 0xFFFF0000 #define PLAT$M_RSVD_2 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _plat { #pragma __nomember_alignment unsigned __int64 plat$iq_data; __struct { unsigned int plat$il_l; unsigned int plat$il_h; } plat$r_longwords; __struct { unsigned plat$v_rsvd_0 : 8; /* 7:0 reserved */ unsigned plat$v_lat : 8; /* 15:8 Master Latency Timer */ unsigned plat$v_rsvd_1 : 16; /* 31:16 reserved */ unsigned plat$v_rsvd_2 : 32; /* 63:32 reserved */ } plat$r_bits; } PLAT; #if !defined(__VAXC) #define plat$il_l plat$r_longwords.plat$il_l #define plat$il_h plat$r_longwords.plat$il_h #define plat$v_rsvd_0 plat$r_bits.plat$v_rsvd_0 #define plat$v_lat plat$r_bits.plat$v_lat #define plat$v_rsvd_1 plat$r_bits.plat$v_rsvd_1 #define plat$v_rsvd_2 plat$r_bits.plat$v_rsvd_2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PERROR - P-Chip Error Register */ /* */ #define PERROR$M_LOST 0x1 #define PERROR$M_SERR 0x2 #define PERROR$M_PERR 0x4 #define PERROR$M_DCRTO 0x8 #define PERROR$M_SGE 0x10 #define PERROR$M_APE 0x20 #define PERROR$M_TA 0x40 #define PERROR$M_RDPE 0x80 #define PERROR$M_NDS 0x100 #define PERROR$M_RTO 0x200 #define PERROR$M_UECC 0x400 #define PERROR$M_CRE 0x800 #define PERROR$M_RSVD_0 0xF000 #define PERROR$M_ADDR 0xFFFFFFFF0000 #define PERROR$M_ADDR_H 0x7000000000000 #define PERROR$M_RSVD_1 0x8000000000000 #define PERROR$M_CMD 0xF0000000000000 #define PERROR$M_SYN 0xFF00000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _perror { #pragma __nomember_alignment unsigned __int64 perror$iq_data; __struct { unsigned int perror$il_l; unsigned int perror$il_h; } perror$r_longwords; __struct { unsigned perror$v_lost : 1; /* 0 Lost an error */ unsigned perror$v_serr : 1; /* 1 SERR# sampled asserted */ unsigned perror$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */ unsigned perror$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */ unsigned perror$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */ unsigned perror$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */ unsigned perror$v_ta : 1; /* 6 Targed Abort as PCI master */ unsigned perror$v_rdpe : 1; /* 7 PCI Read Data Parity Error as PCI master */ unsigned perror$v_nds : 1; /* 8 No DevSel as PCI master */ unsigned perror$v_rto : 1; /* 9 Retry TimeOut as PCI master after 2^24 tries */ unsigned perror$v_uecc : 1; /* 10 Uncorrectable ECC error */ unsigned perror$v_cre : 1; /* 11 Correctable ECC error */ unsigned perror$v_rsvd_0 : 4; /* 15:12 reserved */ unsigned perror$v_addr : 32; /* 48:16 Addres of CRE or UECC */ unsigned perror$v_addr_h : 3; /* 50:48 Addres of CRE or UECC */ unsigned perror$v_rsvd_1 : 1; /* 51 reserved */ unsigned perror$v_cmd : 4; /* 55:52 PCI Command on error */ unsigned perror$v_syn : 8; /* 63:56 ECC Syndrome on CRE or UECC */ } perror$r_bits; } PERROR; #if !defined(__VAXC) #define perror$il_l perror$r_longwords.perror$il_l #define perror$il_h perror$r_longwords.perror$il_h #define perror$v_lost perror$r_bits.perror$v_lost #define perror$v_serr perror$r_bits.perror$v_serr #define perror$v_perr perror$r_bits.perror$v_perr #define perror$v_dcrto perror$r_bits.perror$v_dcrto #define perror$v_sge perror$r_bits.perror$v_sge #define perror$v_ape perror$r_bits.perror$v_ape #define perror$v_ta perror$r_bits.perror$v_ta #define perror$v_rdpe perror$r_bits.perror$v_rdpe #define perror$v_nds perror$r_bits.perror$v_nds #define perror$v_rto perror$r_bits.perror$v_rto #define perror$v_uecc perror$r_bits.perror$v_uecc #define perror$v_cre perror$r_bits.perror$v_cre #define perror$v_rsvd_0 perror$r_bits.perror$v_rsvd_0 #define perror$v_addr perror$r_bits.perror$v_addr #define perror$v_addr_h perror$r_bits.perror$v_addr_h #define perror$v_rsvd_1 perror$r_bits.perror$v_rsvd_1 #define perror$v_cmd perror$r_bits.perror$v_cmd #define perror$v_syn perror$r_bits.perror$v_syn #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PERRMASK - P-Chip Error Mask Register */ /* */ #define PERRMASK$M_LOST 0x1 #define PERRMASK$M_SERR 0x2 #define PERRMASK$M_PERR 0x4 #define PERRMASK$M_DCRTO 0x8 #define PERRMASK$M_SGE 0x10 #define PERRMASK$M_APE 0x20 #define PERRMASK$M_TA 0x40 #define PERRMASK$M_RDPE 0x80 #define PERRMASK$M_NDS 0x100 #define PERRMASK$M_RTO 0x200 #define PERRMASK$M_UECC 0x400 #define PERRMASK$M_CRE 0x800 #define PERRMASK$M_RSVD_0 0xFFFFF000 #define PERRMASK$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _perrmask { #pragma __nomember_alignment unsigned __int64 perrmask$iq_data; __struct { unsigned int perrmask$il_l; unsigned int perrmask$il_h; } perrmask$r_longwords; __struct { unsigned perrmask$v_lost : 1; /* 0 Lost an error */ unsigned perrmask$v_serr : 1; /* 1 SERR# sampled asserted */ unsigned perrmask$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */ unsigned perrmask$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */ unsigned perrmask$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */ unsigned perrmask$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */ unsigned perrmask$v_ta : 1; /* 6 Targed Abort as PCI master */ unsigned perrmask$v_rdpe : 1; /* 7 PCI Read Data Parity Error as PCI master */ unsigned perrmask$v_nds : 1; /* 8 No DevSel as PCI master */ unsigned perrmask$v_rto : 1; /* 9 Retry TimeOut as PCI master after 2^24 tries */ unsigned perrmask$v_uecc : 1; /* 10 Uncorrectable ECC error */ unsigned perrmask$v_cre : 1; /* 11 Correctable ECC error */ unsigned perrmask$v_rsvd_0 : 20; /* 31:12 reserved */ unsigned perrmask$v_rsvd_1 : 32; /* 63:32 reserved */ } perrmask$r_bits; } PERRMASK; #if !defined(__VAXC) #define perrmask$il_l perrmask$r_longwords.perrmask$il_l #define perrmask$il_h perrmask$r_longwords.perrmask$il_h #define perrmask$v_lost perrmask$r_bits.perrmask$v_lost #define perrmask$v_serr perrmask$r_bits.perrmask$v_serr #define perrmask$v_perr perrmask$r_bits.perrmask$v_perr #define perrmask$v_dcrto perrmask$r_bits.perrmask$v_dcrto #define perrmask$v_sge perrmask$r_bits.perrmask$v_sge #define perrmask$v_ape perrmask$r_bits.perrmask$v_ape #define perrmask$v_ta perrmask$r_bits.perrmask$v_ta #define perrmask$v_rdpe perrmask$r_bits.perrmask$v_rdpe #define perrmask$v_nds perrmask$r_bits.perrmask$v_nds #define perrmask$v_rto perrmask$r_bits.perrmask$v_rto #define perrmask$v_uecc perrmask$r_bits.perrmask$v_uecc #define perrmask$v_cre perrmask$r_bits.perrmask$v_cre #define perrmask$v_rsvd_0 perrmask$r_bits.perrmask$v_rsvd_0 #define perrmask$v_rsvd_1 perrmask$r_bits.perrmask$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PERRSET - P-Chip Error Set Register */ /* */ #define PERRSET$M_LOST 0x1 #define PERRSET$M_SERR 0x2 #define PERRSET$M_PERR 0x4 #define PERRSET$M_DCRTO 0x8 #define PERRSET$M_SGE 0x10 #define PERRSET$M_APE 0x20 #define PERRSET$M_TA 0x40 #define PERRSET$M_RDPE 0x80 #define PERRSET$M_NDS 0x100 #define PERRSET$M_RTO 0x200 #define PERRSET$M_UECC 0x400 #define PERRSET$M_CRE 0x800 #define PERRSET$M_RSVD_0 0xF000 #define PERRSET$M_ADDR 0xFFFFFFFF0000 #define PERRSET$M_ADDR_H 0x7000000000000 #define PERRSET$M_RSVD_1 0x8000000000000 #define PERRSET$M_CMD 0xF0000000000000 #define PERRSET$M_SYN 0xFF00000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _perrset { #pragma __nomember_alignment unsigned __int64 perrset$iq_data; __struct { unsigned int perrset$il_l; unsigned int perrset$il_h; } perrset$r_longwords; __struct { unsigned perrset$v_lost : 1; /* 0 Lost an error */ unsigned perrset$v_serr : 1; /* 1 SERR# sampled asserted */ unsigned perrset$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */ unsigned perrset$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */ unsigned perrset$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */ unsigned perrset$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */ unsigned perrset$v_ta : 1; /* 6 Targed Abort as PCI master */ unsigned perrset$v_rdpe : 1; /* 7 PCI Read Data Parity Error as PCI master */ unsigned perrset$v_nds : 1; /* 8 No DevSel as PCI master */ unsigned perrset$v_rto : 1; /* 9 Retry TimeOut as PCI master after 2^24 tries */ unsigned perrset$v_uecc : 1; /* 10 Uncorrectable ECC error */ unsigned perrset$v_cre : 1; /* 11 Correctable ECC error */ unsigned perrset$v_rsvd_0 : 4; /* 15:12 reserved */ unsigned perrset$v_addr : 32; /* 47:16 Lo 32 Address bits of CRE or UECC */ unsigned perrset$v_addr_h : 3; /* 50:48 Hi 3 Address bits of CRE or UECC */ unsigned perrset$v_rsvd_1 : 1; /* 51 reserved */ unsigned perrset$v_cmd : 4; /* 55:52 PCI Command on error */ unsigned perrset$v_syn : 8; /* 63:56 ECC Syndrome on CRE or UECC */ } perrset$r_bits; } PERRSET; #if !defined(__VAXC) #define perrset$il_l perrset$r_longwords.perrset$il_l #define perrset$il_h perrset$r_longwords.perrset$il_h #define perrset$v_lost perrset$r_bits.perrset$v_lost #define perrset$v_serr perrset$r_bits.perrset$v_serr #define perrset$v_perr perrset$r_bits.perrset$v_perr #define perrset$v_dcrto perrset$r_bits.perrset$v_dcrto #define perrset$v_sge perrset$r_bits.perrset$v_sge #define perrset$v_ape perrset$r_bits.perrset$v_ape #define perrset$v_ta perrset$r_bits.perrset$v_ta #define perrset$v_rdpe perrset$r_bits.perrset$v_rdpe #define perrset$v_nds perrset$r_bits.perrset$v_nds #define perrset$v_rto perrset$r_bits.perrset$v_rto #define perrset$v_uecc perrset$r_bits.perrset$v_uecc #define perrset$v_cre perrset$r_bits.perrset$v_cre #define perrset$v_rsvd_0 perrset$r_bits.perrset$v_rsvd_0 #define perrset$v_addr perrset$r_bits.perrset$v_addr #define perrset$v_addr_h perrset$r_bits.perrset$v_addr_h #define perrset$v_rsvd_1 perrset$r_bits.perrset$v_rsvd_1 #define perrset$v_cmd perrset$r_bits.perrset$v_cmd #define perrset$v_syn perrset$r_bits.perrset$v_syn #endif /* #if !defined(__VAXC) */ /* */ /* */ /* TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */ /* */ #define TLBIV$M_RSVD_0 0xF #define TLBIV$M_ADDR 0xFFFF0 #define TLBIV$M_RSVD_1 0xFFF00000 #define TLBIV$M_RSVD_2 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _tlbiv { #pragma __nomember_alignment unsigned __int64 tlbiv$iq_data; __struct { unsigned int tlbiv$il_l; unsigned int tlbiv$il_h; } tlbiv$r_longwords; __struct { unsigned tlbiv$v_rsvd_0 : 4; /* 3:0 reserved */ unsigned tlbiv$v_addr : 16; /* 19:4 invalidate if matches PCI addr<31:16> */ unsigned tlbiv$v_rsvd_1 : 12; /* 31:20 reserved */ unsigned tlbiv$v_rsvd_2 : 32; /* 63:32 reserved */ } tlbiv$r_bits; } TLBIV; #if !defined(__VAXC) #define tlbiv$il_l tlbiv$r_longwords.tlbiv$il_l #define tlbiv$il_h tlbiv$r_longwords.tlbiv$il_h #define tlbiv$v_rsvd_0 tlbiv$r_bits.tlbiv$v_rsvd_0 #define tlbiv$v_addr tlbiv$r_bits.tlbiv$v_addr #define tlbiv$v_rsvd_1 tlbiv$r_bits.tlbiv$v_rsvd_1 #define tlbiv$v_rsvd_2 tlbiv$r_bits.tlbiv$v_rsvd_2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* TLBIA - P-Chip Translation Buffer Invalidate all Register */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _tlbia { #pragma __nomember_alignment unsigned __int64 tlbia$iq_data; __struct { unsigned int tlbia$il_l; unsigned int tlbia$il_h; } tlbia$r_longwords; } TLBIA; #if !defined(__VAXC) #define tlbia$il_l tlbia$r_longwords.tlbia$il_l #define tlbia$il_h tlbia$r_longwords.tlbia$il_h #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PMONCTL - P-Chip Monitor Control Register */ /* */ #define PMONCTL$M_SLCT0 0xFF #define PMONCTL$M_SLCT1 0xFF00 #define PMONCTL$M_STKDIS0 0x10000 #define PMONCTL$M_STKDIS1 0x20000 #define PMONCTL$M_RSVD_0 0xFFFC0000 #define PMONCTL$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _pmonctl { #pragma __nomember_alignment unsigned __int64 pmonctl$iq_data; __struct { unsigned int pmonctl$il_l; unsigned int pmonctl$il_h; } pmonctl$r_longwords; __struct { unsigned pmonctl$v_slct0 : 8; /* 7:0 Select Monitor 0 */ unsigned pmonctl$v_slct1 : 8; /* 15:8 Select Monitor 1 */ unsigned pmonctl$v_stkdis0 : 1; /* 16 Sticky Count 0 Disable */ unsigned pmonctl$v_stkdis1 : 1; /* 17 Sticky Count 1 Disable */ unsigned pmonctl$v_rsvd_0 : 14; /* 31:18 reserved */ unsigned pmonctl$v_rsvd_1 : 32; /* 63:32 reserved */ } pmonctl$r_bits; } PMONCTL; #if !defined(__VAXC) #define pmonctl$il_l pmonctl$r_longwords.pmonctl$il_l #define pmonctl$il_h pmonctl$r_longwords.pmonctl$il_h #define pmonctl$v_slct0 pmonctl$r_bits.pmonctl$v_slct0 #define pmonctl$v_slct1 pmonctl$r_bits.pmonctl$v_slct1 #define pmonctl$v_stkdis0 pmonctl$r_bits.pmonctl$v_stkdis0 #define pmonctl$v_stkdis1 pmonctl$r_bits.pmonctl$v_stkdis1 #define pmonctl$v_rsvd_0 pmonctl$r_bits.pmonctl$v_rsvd_0 #define pmonctl$v_rsvd_1 pmonctl$r_bits.pmonctl$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* PMONCNT - P-Chip Monitor Counters Register */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _pmoncnt { #pragma __nomember_alignment unsigned __int64 pmoncnt$iq_data; __struct { unsigned int pmoncnt$il_cnt0; unsigned int pmoncnt$il_cnt1; } pmoncnt$r_longwords; } PMONCNT; #if !defined(__VAXC) #define pmoncnt$il_cnt0 pmoncnt$r_longwords.pmoncnt$il_cnt0 #define pmoncnt$il_cnt1 pmoncnt$r_longwords.pmoncnt$il_cnt1 #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __TSUNAMIDEF_LOADED */