/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:55 by OpenVMS SDL EV3-3 */ /* Source: 26-SEP-2001 15:19:04 $1$DGA7274:[LIB_H.SRC]TITANDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $TITANDEF ***/ #ifndef __TITANDEF_LOADED #define __TITANDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* Version: 'X-6' */ /* */ /* */ /************************************************************************* */ /* * */ /* Copyright 2000 Compaq Computer Corporation * */ /* * */ /* COMPAQ Registered in U.S. Patent and Trademark Office. * */ /* * */ /* Confidential computer software. Valid license from Compaq or * */ /* authorized sublicensor required for possession, use or copying. * */ /* Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * */ /* Computer Software Documentation, and Technical Data for Commercial * */ /* Items are licensed to the U.S. Government under vendor's standard * */ /* commercial license. * */ /* * */ /* Compaq shall not be liable for technical or editorial errors or * */ /* omissions contained herein. The information in this document is * */ /* subject to change without notice. * */ /* * */ /************************************************************************* */ /* */ /* FACILITY: OpenVMS AXP System Macro Libraries */ /* */ /* ABSTRACT: */ /* */ /* This file defines the control and status registers of the Titan Chip */ /* Set (an extemsion of Tsunami), designed for use in EV6-8 based platforms. */ /* */ /* Because of the disparities in the address spaces for the various chips */ /* in the Titan Chip Set, it structure is defined as three distinct data stuctures, */ /* C chip (TITAN_C), D chip (TITAN_D), and the P chip (TITAN_P). There is one C Chip */ /* (C4+ - up to four processors), as many as eight D Chips (D+) and as many as two P Chips, */ /* (the PA-chip [PCI + AGP] and the PP-chip [2 PCIs] - each of these P-Chips */ /* supports 2 busses) This simplifies the definition, but puts an extra burden on */ /* the programmer to use the correct base addresses for the three chips. */ /* */ /* The following table shows the regions for the Titan Chip Set address */ /* space. */ /* */ /* -------------------------------------------------------------------- */ /* C chip Address Space */ /* -------------------------------------------------------------------- */ /* 801 0000 0000 1 GB TIG Bus, addr<5:0> = 0, single byte valid in */ /* quadword access, 16 MB accessible */ /* 801 a000 0000 256 MB C chip CSRs, addr<5:0> = 0, quadword access */ /* -------------------------------------------------------------------- */ /* */ /* -------------------------------------------------------------------- */ /* D chip Address Space */ /* -------------------------------------------------------------------- */ /* 801 b000 0000 256 MB D chip CSRs, addr<5:0> = 0, all eight bytes in */ /* quadword access must be identical. */ /* -------------------------------------------------------------------- */ /* */ /* -------------------------------------------------------------------- */ /* P chip-0 Address Space */ /* -------------------------------------------------------------------- */ /* 801 8000 0000 256 MB P chip CSRs, addr<5:0> = 0, quadword access */ /* */ /* 800 0000 0000 4 GB GPCI Memory */ /* 801 f800 0000 64 MB GPCI IACK/Special */ /* 801 fc00 0000 32 MB GPCI IO */ /* 801 fe00 0000 16 MB GPCI config space */ /* */ /* 804 0000 0000 4 GB APCI Memory */ /* 805 f800 0000 64 MB APCI IACK/Special */ /* 805 fc00 0000 32 MB APCI IO */ /* 805 fe00 0000 16 MB APCI config space */ /* -------------------------------------------------------------------- */ /* */ /* -------------------------------------------------------------------- */ /* P chip-1 Address Space */ /* -------------------------------------------------------------------- */ /* 803 8000 0000 256 MB P chip CSRs, addr<5:0> = 0, quadword access */ /* */ /* 802 0000 0000 4 GB GPCI Memory */ /* 803 f800 0000 64 MB GPCI IACK/Special */ /* 803 fc00 0000 32 MB GPCI IO */ /* 803 fe00 0000 16 MB GPCI config space */ /* */ /* 806 0000 0000 4 MB APCI Memory */ /* 807 f800 0000 64 MB APCI IACK/Special */ /* 807 fc00 0000 32 MB APCI IO */ /* 807 fe00 0000 16 MB APCI config space */ /* */ /* */ /* -------------------------------------------------------------------- */ /* */ /* AUTHOR: */ /* */ /* Walt Arbo 03-Jan-2000 */ /* */ /* MODIFIED BY: */ /* */ /* X-6 GBH Gary Huff 26-Sep-2001 */ /* Add AGP bit definitions to apctl. */ /* */ /* X-5 TLC Tony Camuso 29-Aug-2001 */ /* Bug: without MCTL register at 801.A000.0500, as in Tsunami, */ /* displacement for for MPR3 register must be %xC0, not %x80. */ /* */ /* X-4 WDA W.D. Arbo 26-Apr-2001 */ /* Add overlays to the Pchip for AGPERROR, AGPERREN, */ /* AGPERRSET and AGPLASTWR. They mirror SERROR, SERREN, */ /* SERRSET and Reserved. It all depends on whether the Pchip */ /* definition maps Pchip's 0 and 1 (SERROR etc.) or 2 and 3 */ /* (AGPERROR etc). */ /* */ /* X-3 WDA W.D. Arbo 15-May-2000 */ /* When I put this file into LIB, it had duplicate */ /* symbol definitions with TSUNAMIDEF.SDL for things like */ /* C_CHIP (duh!). Put TITAN into all the names (TITAN_C */ /* for C_CHIP etc.) */ /* */ /* X-2 WDA W.D. Arbo 10-May-2000 */ /* A few fixes. */ /* */ /* X-1 WDA W.D. Arbo 03-Jan-2000 */ /* Based on Tony Camuso's work on Tsunami support */ /* (TSUNAMIDEF.SDL). */ /* */ /*-- */ /* The maximum number of CPUs supported by the Titan chipset */ /* */ #define TITAN$K_MAX_CPU 4 #define TITAN$C_MAX_CPU 4 /* */ /* Since SDL currently doesn't support constants greater 2**32, the high-order */ /* bits (%X80x) have their own constants defined. */ /* */ /* Titan Chip Set CSR base addresses <63:32> (High longword) */ /* =========================================================== */ /* */ #define TITAN$L_C_CHIP_H 2049 #define TITAN$L_D_CHIP_H 2049 /* */ #define TITAN$L_P0_CHIP_CSR_H 2049 #define TITAN$L_P0_CHIP_GMEM_H 2048 #define TITAN$L_P0_CHIP_GIO_H 2049 #define TITAN$L_P0_CHIP_GCONFIG_H 2049 #define TITAN$L_P0_CHIP_AMEM_H 2052 #define TITAN$L_P0_CHIP_AIO_H 2053 #define TITAN$L_P0_CHIP_ACONFIG_H 2053 /* */ #define TITAN$L_P1_CHIP_CSR_H 2051 #define TITAN$L_P1_CHIP_GMEM_H 2050 #define TITAN$L_P1_CHIP_GIO_H 2051 #define TITAN$L_P1_CHIP_GCONFIG_H 2051 #define TITAN$L_P1_CHIP_AMEM_H 2054 #define TITAN$L_P1_CHIP_AIO_H 2055 #define TITAN$L_P1_CHIP_ACONFIG_H 2055 /* */ /* */ /* Titan Chip Set CSR base addresses <31:0> (Low longword) */ /* ========================================================= */ /* */ #define TITAN$L_C_CHIP_L -1610612736 /* Cchip */ #define TITAN$L_D_CHIP_L -1342177280 /* Dchip */ /* */ /* */ /* P-Chip */ /* ------ */ #define TITAN$L_P_CHIP_CSR_0_L -2147483648 #define TITAN$L_P_CHIP_CSR_1_L -2147479552 #define TITAN$L_P_CHIP_MEM_L 0 #define TITAN$L_P_CHIP_IO_L -67108864 #define TITAN$L_P_CHIP_IACK_L -134217728 #define TITAN$L_P_CHIP_CONFIG_L -33554432 /* */ /* */ /*************************************************************************** */ /* */ /* Titan Chip Set Structures */ /* */ /*************************************************************************** */ /* */ /*========================================================================== */ /* */ /* C-CHIP Structure */ /*========================================================================== */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _titan_c { /* */ /* 801.A000.000 */ /* */ /* CSC - C-Chip System Configuration Register */ /* */ #pragma __nomember_alignment __union { unsigned __int64 titan_c$iq_csc; unsigned char csc$b_pad [64]; } titan_c$r_csc_overlay; /* */ /* 801.A000.0040 */ /* */ /* MTR - C-Chip Memory Timing Register */ /* */ __union { unsigned __int64 titan_c$iq_mtr; unsigned char mtr$b_pad [64]; } titan_c$r_mtr_overlay; /* */ /* 801.A000.0080 */ /* */ /* MISC - C-Chip Miscellaneous Register */ /* */ __union { unsigned __int64 titan_c$iq_misc; unsigned char csc$b_pad [64]; } titan_c$r_misc_overlay; /* */ /* 801.A000.00C0 */ /* */ /* MPD - C-Chip Memory Presence Detect */ /* */ __union { unsigned __int64 titan_c$iq_mpd; unsigned char mpd$b_pad [64]; } titan_c$r_mpd_overlay; /* */ /* 801.A000.0100 */ /* */ /* AAR0 - C-Chip Array Address Register 0 */ /* */ __union { unsigned __int64 titan_c$iq_aar0; unsigned char aar0$b_pad [64]; } titan_c$r_aar0_overlay; /* */ /* 801.A000.0140 */ /* */ /* AAR1 - C-Chip Array Address Register 1 */ /* */ __union { unsigned __int64 titan_c$iq_aar1; unsigned char aar1$b_pad [64]; } titan_c$r_aar1_overlay; /* */ /* 801.A000.0180 */ /* */ /* AAR2 - C-Chip Array Address Register 2 */ /* */ __union { unsigned __int64 titan_c$iq_aar2; unsigned char aar2$b_pad [64]; } titan_c$r_aar2_overlay; /* */ /* 801.A000.01C0 */ /* */ /* AAR3 - C-Chip Array Address Register 3 */ /* */ __union { unsigned __int64 titan_c$iq_aar3; unsigned char aar3$b_pad [64]; } titan_c$r_aar3_overlay; /* */ /* 801.A000.0200 */ /* */ /* DIM0 - C-Chip Device Interrupt Mask Register 0 */ /* */ __union { unsigned __int64 titan_c$iq_dim0; unsigned char dim0$b_pad [64]; } titan_c$r_dim0_overlay; /* */ /* 801.A000.0240 */ /* */ /* DIM1 - C-Chip Device Interrupt Mask Register 1 */ /* */ __union { unsigned __int64 titan_c$iq_dim1; unsigned char dim1$b_pad [64]; } titan_c$r_dim1_overlay; /* */ /* 801.A000.0280 */ /* */ /* DIR0 - C-Chip Device Interrupt Request Register */ /* */ __union { unsigned __int64 titan_c$iq_dir0; unsigned char dir0$b_pad [64]; } titan_c$r_dir0_overlay; /* */ /* 801.A000.02C0 */ /* */ /* DIR1 - C-Chip Device Interrupt Request Register */ /* */ __union { unsigned __int64 titan_c$iq_dir1; unsigned char dir1$b_pad [64]; } titan_c$r_dir1_overlay; /* */ /* 801.A000.0300 */ /* */ /* DRIR - C-Chip Raw Interrupt Request Register */ /* */ __union { unsigned __int64 titan_c$iq_drir; unsigned char drir$b_pad [64]; } titan_c$r_drir_overlay; /* */ /* 801.A000.0340 */ /* */ /* PRBEN - C-Chip Probe Enable Register */ /* */ __union { unsigned __int64 titan_c$iq_prben; unsigned char prben$b_pad [64]; } titan_c$r_prben_overlay; /* */ /* 801.A000.0380 */ /* */ /* IIC0 - C-Chip Interval Ignore Count Register 0 */ /* */ __union { unsigned __int64 titan_c$iq_iic0; unsigned char iic0$b_pad [64]; } titan_c$r_iic0_overlay; /* */ /* 801.A000.03C0 */ /* */ /* IIC1 - C-Chip Interval Ignore Count Register 1 */ /* */ __union { unsigned __int64 titan_c$iq_iic1; unsigned char iic1$b_pad [64]; } titan_c$r_iic1_overlay; /* */ /* 801.A000.0400 */ /* */ /* MPR0 - C-Chip Memory Programming Register 0 */ /* */ __union { unsigned __int64 titan_c$iq_mpr0; unsigned char mpr0$b_pad [64]; } titan_c$r_mpr0_overlay; /* */ /* 801.A000.0440 */ /* */ /* MPR1 - C-Chip Memory Programming Register 1 */ /* */ __union { unsigned __int64 titan_c$iq_mpr1; unsigned char mpr1$b_pad [64]; } titan_c$r_mpr1_overlay; /* */ /* 801.A000.0480 */ /* */ /* MPR2 - C-Chip Memory Programming Register 2 */ /* */ __union { unsigned __int64 titan_c$iq_mpr2; unsigned char mpr2$b_pad [64]; } titan_c$r_mpr2_overlay; /* */ /* 801.A000.04C0 */ /* */ /* MPR3 - C-Chip Memory Programming Register 3 */ /* */ __union { unsigned __int64 titan_c$iq_mpr3; unsigned char mpr3$b_pad [192]; } titan_c$r_mpr3_overlay; /* */ /* 801.A000.0580 */ /* */ /* TTR - C-Chip TIG Bus Timing Register */ /* */ __union { unsigned __int64 titan_c$iq_ttr; unsigned char ttr$b_pad [64]; } titan_c$r_ttr_overlay; /* */ /* 801.A000.05C0 */ /* */ /* TDR - C-Chip TIG Bus Device Timing Register */ /* */ __union { unsigned __int64 titan_c$iq_tdr; unsigned char tdr$b_pad [64]; } titan_c$r_tdr_overlay; /* */ /* 801.A000.0600 */ /* */ /* DIM2 - C-Chip Device Interrupt Mask Register 2 */ /* */ __union { unsigned __int64 titan_c$iq_dim2; unsigned char dim2$b_pad [64]; } titan_c$r_dim2_overlay; /* */ /* 801.A000.0640 */ /* */ /* DIM3 - C-Chip Device Interrupt Mask Register 3 */ /* */ __union { unsigned __int64 titan_c$iq_dim3; unsigned char dim3$b_pad [64]; } titan_c$r_dim3_overlay; /* */ /* 801.A000.0680 */ /* */ /* DIR2 - C-Chip Device Interrupt Request Register 2 */ /* */ __union { unsigned __int64 titan_c$iq_dir2; unsigned char dir2$b_pad [64]; } titan_c$r_dir2_overlay; /* */ /* 801.A000.06C0 */ /* */ /* DIR3 - C-Chip Device Interrupt Request Register 3 */ /* */ __union { unsigned __int64 titan_c$iq_dir3; unsigned char dir3$b_pad [64]; } titan_c$r_dir3_overlay; /* */ /* 801.A000.0700 */ /* */ /* IIC2 - C-Chip Interval Ignore Count Register 2 */ /* */ __union { unsigned __int64 titan_c$iq_iic2; unsigned char iic2$b_pad [64]; } titan_c$r_iic2_overlay; /* */ /* 801.A000.0740 */ /* */ /* IIC3 - C-Chip Interval Ignore Count Register 3 */ /* */ __union { unsigned __int64 titan_c$iq_iic3; unsigned char iic3$b_pad [64]; } titan_c$r_iic3_overlay; /* */ /* 801.A000.A780 */ /* */ /* PWR - C-Chip Power Management Control */ /* */ __union { unsigned __int64 titan_c$iq_pwr; unsigned char pwr$b_pad [1152]; } titan_c$r_pwr_overlay; /* */ /* 801.A000.0C00 */ /* */ /* CMONCTLA - C-Chip Monitor Control A */ /* */ __union { unsigned __int64 titan_c$iq_cmonctla; unsigned char cmonctla$b_pad [64]; } titan_c$r_cmonctla_overlay; /* */ /* 801.A000.0C40 */ /* */ /* CMONCTLB - C-Chip Monitor Control B */ /* */ __union { unsigned __int64 titan_c$iq_cmonctlb; unsigned char cmonctlb$b_pad [64]; } titan_c$r_cmonctlb_overlay; /* */ /* 801.A000.0C80 */ /* */ /* CMONCNT01- C-Chip Monitor Counter 01 */ /* */ __union { unsigned __int64 titan_c$iq_cmoncnt01; unsigned char cmoncnt01$b_pad [64]; } titan_c$r_cmoncnt01_overlay; /* */ /* 801.A000.0CC0 */ /* */ /* CMONCNT23- C-Chip Monitor Counter 23 */ /* */ __union { unsigned __int64 titan_c$iq_cmoncnt23; unsigned char cmoncnt23$b_pad [64]; } titan_c$r_cmoncnt23_overlay; /* */ /* 801.A000.0D00 */ /* */ /* CPEN- C-Chip (Reserved for future use) */ /* */ __union { unsigned __int64 titan_c$iq_cpen; unsigned char cpen$b_pad [4864]; } titan_c$r_cpen_overlay; } TITAN_C; #if !defined(__VAXC) #define titan_c$iq_csc titan_c$r_csc_overlay.titan_c$iq_csc #define titan_c$iq_mtr titan_c$r_mtr_overlay.titan_c$iq_mtr #define titan_c$iq_misc titan_c$r_misc_overlay.titan_c$iq_misc #define titan_c$iq_mpd titan_c$r_mpd_overlay.titan_c$iq_mpd #define titan_c$iq_aar0 titan_c$r_aar0_overlay.titan_c$iq_aar0 #define titan_c$iq_aar1 titan_c$r_aar1_overlay.titan_c$iq_aar1 #define titan_c$iq_aar2 titan_c$r_aar2_overlay.titan_c$iq_aar2 #define titan_c$iq_aar3 titan_c$r_aar3_overlay.titan_c$iq_aar3 #define titan_c$iq_dim0 titan_c$r_dim0_overlay.titan_c$iq_dim0 #define titan_c$iq_dim1 titan_c$r_dim1_overlay.titan_c$iq_dim1 #define titan_c$iq_dir0 titan_c$r_dir0_overlay.titan_c$iq_dir0 #define titan_c$iq_dir1 titan_c$r_dir1_overlay.titan_c$iq_dir1 #define titan_c$iq_drir titan_c$r_drir_overlay.titan_c$iq_drir #define titan_c$iq_prben titan_c$r_prben_overlay.titan_c$iq_prben #define titan_c$iq_iic0 titan_c$r_iic0_overlay.titan_c$iq_iic0 #define titan_c$iq_iic1 titan_c$r_iic1_overlay.titan_c$iq_iic1 #define titan_c$iq_mpr0 titan_c$r_mpr0_overlay.titan_c$iq_mpr0 #define titan_c$iq_mpr1 titan_c$r_mpr1_overlay.titan_c$iq_mpr1 #define titan_c$iq_mpr2 titan_c$r_mpr2_overlay.titan_c$iq_mpr2 #define titan_c$iq_mpr3 titan_c$r_mpr3_overlay.titan_c$iq_mpr3 #define titan_c$iq_ttr titan_c$r_ttr_overlay.titan_c$iq_ttr #define titan_c$iq_tdr titan_c$r_tdr_overlay.titan_c$iq_tdr #define titan_c$iq_dim2 titan_c$r_dim2_overlay.titan_c$iq_dim2 #define titan_c$iq_dim3 titan_c$r_dim3_overlay.titan_c$iq_dim3 #define titan_c$iq_dir2 titan_c$r_dir2_overlay.titan_c$iq_dir2 #define titan_c$iq_dir3 titan_c$r_dir3_overlay.titan_c$iq_dir3 #define titan_c$iq_iic2 titan_c$r_iic2_overlay.titan_c$iq_iic2 #define titan_c$iq_iic3 titan_c$r_iic3_overlay.titan_c$iq_iic3 #define titan_c$iq_pwr titan_c$r_pwr_overlay.titan_c$iq_pwr #define titan_c$iq_cmonctla titan_c$r_cmonctla_overlay.titan_c$iq_cmonctla #define titan_c$iq_cmonctlb titan_c$r_cmonctlb_overlay.titan_c$iq_cmonctlb #define titan_c$iq_cmoncnt01 titan_c$r_cmoncnt01_overlay.titan_c$iq_cmoncnt01 #define titan_c$iq_cmoncnt23 titan_c$r_cmoncnt23_overlay.titan_c$iq_cmoncnt23 #define titan_c$iq_cpen titan_c$r_cpen_overlay.titan_c$iq_cpen #endif /* #if !defined(__VAXC) */ /* */ /* */ /* */ /*========================================================================== */ /* */ /* D-CHIP Structure */ /* */ /* NOTE: All the registers in this structure are abstracted as 64-bit entities. */ /* Therefore, they MUST be accessed and manipulated as quadwords and with */ /* quadwords. */ /* */ /*========================================================================== */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _titan_d { /* */ /* 801.B000.0800 */ /* */ /* DSC - D-Chip System Configuration Register */ /* */ #pragma __nomember_alignment __union { unsigned __int64 titan_d$iq_dsc; unsigned char dsc$b_pad [64]; } titan_d$r_dsc_overlay; /* */ /* 801.B000.0840 */ /* */ /* STR - D-Chip System Timing Register */ /* */ __union { unsigned __int64 titan_d$iq_str; unsigned char str$b_pad [64]; } titan_d$r_str_overlay; /* */ /* 801.B000.0880 */ /* */ /* DREV - D-Chip System Configuration Register */ /* */ __union { unsigned __int64 titan_d$iq_drev; unsigned char drev$b_pad [64]; } titan_d$r_drev_overlay; /* */ /* */ /* 801.B000.08C0 */ /* */ /* DSC2 - D-Chip (Reserved for future use) */ /* */ __union { unsigned __int64 titan_d$iq_dsc2; unsigned char dsc2$b_pad [64]; } titan_d$r_dsc2_overlay; /* */ } TITAN_D; #if !defined(__VAXC) #define titan_d$iq_dsc titan_d$r_dsc_overlay.titan_d$iq_dsc #define titan_d$iq_str titan_d$r_str_overlay.titan_d$iq_str #define titan_d$iq_drev titan_d$r_drev_overlay.titan_d$iq_drev #define titan_d$iq_dsc2 titan_d$r_dsc2_overlay.titan_d$iq_dsc2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* */ /*========================================================================== */ /* */ /* P chip Structure - These are the common registers (G and A) of the */ /* two halves of a PAchip or a PPchip. Remember that hose 2 or hose 3 could */ /* be an AGP bus. */ /* */ /* The four PCI chips have base address as follows: */ /* PCI 0 Pchip 0 Hose 0 G-port 801.8000.0000 */ /* PCI 1 Pchip 1 Hose 1 G-port 803.8000.0000 */ /* PCI 2 Pchip 0 Hose 2 A-port 801.8000.1000 */ /* PCI 3 Pchip 1 Hose 3 A-port 803.8000.1000 */ /* */ /*========================================================================== */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _titan_p { /* */ /* 80x.8000.0000 */ /* */ /* WSBA0 - P-CHip Window Space Base Address Register 0 */ /* */ #pragma __nomember_alignment __union { unsigned __int64 titan_p$iq_wsba0; unsigned char wsba0$b_pad [64]; } titan_p$r_wsba0_overlay; /* */ /* 80x.8000.0040 */ /* */ /* WSBA1 - P-CHip Window Space Base Address Register 1 */ /* */ __union { unsigned __int64 titan_p$iq_wsba1; unsigned char wsba1$b_pad [64]; } titan_p$r_wsba1_overlay; /* */ /* 80x.8000.0080 */ /* */ /* WSBA2 - P-CHip Window Space Base Address Register 2 */ /* */ __union { unsigned __int64 titan_p$iq_wsba2; unsigned char wsba2$b_pad [64]; } titan_p$r_wsba2_overlay; /* */ /* 80x.8000.00C0 */ /* */ /* WSBA3 - P-CHip Window Space Base Address Register 3 */ /* */ __union { unsigned __int64 titan_p$iq_wsba3; unsigned char wsba3$b_pad [64]; } titan_p$r_wsba3_overlay; /* */ /* 80x.8000.0100 */ /* */ /* WSM0 - P-Chip Window Space Mask Register 0 */ /* */ __union { unsigned __int64 titan_p$iq_wsm0; unsigned char wsm0$b_pad [64]; } titan_p$r_wsm0_overlay; /* */ /* 80x.8000.0140 */ /* */ /* WSM1 - P-Chip Window Space Mask Register 1 */ /* */ __union { unsigned __int64 titan_p$iq_wsm1; unsigned char wsm1$b_pad [64]; } titan_p$r_wsm1_overlay; /* */ /* 80x.8000.0180 */ /* */ /* WSM2 - P-Chip Window Space Mask Register 2 */ /* */ __union { unsigned __int64 titan_p$iq_wsm2; unsigned char wsm2$b_pad [64]; } titan_p$r_wsm2_overlay; /* */ /* 80x.8000.01C0 */ /* */ /* WSM3 - P-Chip Window Space Mask Register 3 */ /* */ __union { unsigned __int64 titan_p$iq_wsm3; unsigned char wsm3$b_pad [64]; } titan_p$r_wsm3_overlay; /* */ /* 80x.8000.0200 */ /* */ /* TBA0 - P-Chip Translated Base Address Register 0 */ /* */ __union { unsigned __int64 titan_p$iq_tba0; unsigned char tba0$b_pad [64]; } titan_p$r_tba0_overlay; /* */ /* 80x.8000.0240 */ /* */ /* TBA1 - P-Chip Translated Base Address Register 1 */ /* */ __union { unsigned __int64 titan_p$iq_tba1; unsigned char tba1$b_pad [64]; } titan_p$r_tba1_overlay; /* */ /* 80x.8000.0280 */ /* */ /* TBA2 - P-Chip Translated Base Address Register 2 */ /* */ __union { unsigned __int64 titan_p$iq_tba2; unsigned char tba2$b_pad [64]; } titan_p$r_tba2_overlay; /* */ /* 80x.8000.02C0 */ /* */ /* TBA3 - P-Chip Translated Base Address Register 3 */ /* */ __union { unsigned __int64 titan_p$iq_tba3; unsigned char tba3$b_pad [64]; } titan_p$r_tba3_overlay; /* */ /* 80x.8000.0300 */ /* */ /* PCTL - P-Chip Control Register */ /* */ __union { unsigned __int64 titan_p$iq_pctl; unsigned char pctl$b_pad [64]; } titan_p$r_pctl_overlay; /* */ /* 80x.8000.0340 */ /* */ /* PLAT - P-Chip Master Latency Register */ /* */ __union { unsigned __int64 titan_p$iq_plat; unsigned char plat$b_pad [192]; } titan_p$r_plat_overlay; /* */ /* 80x.8000.0400 */ /* */ /* SERROR - P-Chip System Error Register */ /* */ __union { unsigned __int64 titan_p$iq_serror; unsigned __int64 titan_p$iq_agperror; unsigned char serror$b_pad [64]; } titan_p$r_serror_overlay; /* */ /* 80x.8000.0440 */ /* */ /* SERREN - P-Chip System Error Enable Register */ /* */ __union { unsigned __int64 titan_p$iq_serren; unsigned __int64 titan_p$iq_agperren; unsigned char serren$b_pad [64]; } titan_p$r_serren_overlay; /* */ /* 80x.8000.0480 */ /* */ /* SERRSET - P-Chip System Error Set Register */ /* */ __union { unsigned __int64 titan_p$iq_serrset; unsigned __int64 titan_p$iq_agperrset; unsigned char serrset$b_pad [64]; } titan_p$r_serrset_overlay; /* */ /* 80x.8000.04C0 */ /* */ /* AGPLASTWR - P-Chip Last Write Register */ /* */ __union { unsigned __int64 titan_p$iq_agplastwr; unsigned char agplastwr$b_pad [64]; } titan_p$r_agplastwr_overlay; /* */ /* 80x.8000.0500 */ /* */ /* PERROR - P-Chip Error Register */ /* */ __union { unsigned __int64 titan_p$iq_perror; unsigned char perror$b_pad [64]; } titan_p$r_perror_overlay; /* */ /* 80x.8000.0540 */ /* */ /* PERREN - P-Chip Error Enable Register */ /* */ __union { unsigned __int64 titan_p$iq_perren; unsigned char perren$b_pad [64]; } titan_p$r_perren_overlay; /* */ /* 80x.8000.0580 */ /* */ /* PERRSET - P-Chip Error Set Register */ /* */ __union { unsigned __int64 titan_p$iq_perrset; unsigned char perrset$b_pad [128]; } titan_p$r_perrset_overlay; /* */ /* 80x.8000.0600 */ /* */ /* TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */ /* */ __union { unsigned __int64 titan_p$iq_tlbiv; unsigned char tlbiv$b_pad [64]; } titan_p$r_tlbiv_overlay; /* */ /* 80x.8000.0640 */ /* */ /* TLBIA - P-Chip Translation Buffer Invalidate all Register */ /* */ __union { unsigned __int64 titan_p$iq_tlbia; unsigned char tlbia$b_pad [192]; } titan_p$r_tlbia_overlay; /* */ /* 80x.8000.0700 */ /* */ /* SCTL - P-Chip System Control Register */ /* */ __union { unsigned __int64 titan_p$iq_sctl; unsigned char sctl$b_pad [256]; } titan_p$r_sctl_overlay; /* */ /* 80x.8000.0800 */ /* */ /* SPRST - Software PCI Reset Register */ /* */ __union { unsigned __int64 titan_p$iq_sprst; } titan_p$r_sprst_overlay; } TITAN_P; #if !defined(__VAXC) #define titan_p$iq_wsba0 titan_p$r_wsba0_overlay.titan_p$iq_wsba0 #define titan_p$iq_wsba1 titan_p$r_wsba1_overlay.titan_p$iq_wsba1 #define titan_p$iq_wsba2 titan_p$r_wsba2_overlay.titan_p$iq_wsba2 #define titan_p$iq_wsba3 titan_p$r_wsba3_overlay.titan_p$iq_wsba3 #define titan_p$iq_wsm0 titan_p$r_wsm0_overlay.titan_p$iq_wsm0 #define titan_p$iq_wsm1 titan_p$r_wsm1_overlay.titan_p$iq_wsm1 #define titan_p$iq_wsm2 titan_p$r_wsm2_overlay.titan_p$iq_wsm2 #define titan_p$iq_wsm3 titan_p$r_wsm3_overlay.titan_p$iq_wsm3 #define titan_p$iq_tba0 titan_p$r_tba0_overlay.titan_p$iq_tba0 #define titan_p$iq_tba1 titan_p$r_tba1_overlay.titan_p$iq_tba1 #define titan_p$iq_tba2 titan_p$r_tba2_overlay.titan_p$iq_tba2 #define titan_p$iq_tba3 titan_p$r_tba3_overlay.titan_p$iq_tba3 #define titan_p$iq_pctl titan_p$r_pctl_overlay.titan_p$iq_pctl #define titan_p$iq_plat titan_p$r_plat_overlay.titan_p$iq_plat #define titan_p$iq_serror titan_p$r_serror_overlay.titan_p$iq_serror #define titan_p$iq_agperror titan_p$r_serror_overlay.titan_p$iq_agperror #define titan_p$iq_serren titan_p$r_serren_overlay.titan_p$iq_serren #define titan_p$iq_agperren titan_p$r_serren_overlay.titan_p$iq_agperren #define titan_p$iq_serrset titan_p$r_serrset_overlay.titan_p$iq_serrset #define titan_p$iq_agperrset titan_p$r_serrset_overlay.titan_p$iq_agperrset #define titan_p$iq_agplastwr titan_p$r_agplastwr_overlay.titan_p$iq_agplastwr #define titan_p$iq_perror titan_p$r_perror_overlay.titan_p$iq_perror #define titan_p$iq_perren titan_p$r_perren_overlay.titan_p$iq_perren #define titan_p$iq_perrset titan_p$r_perrset_overlay.titan_p$iq_perrset #define titan_p$iq_tlbiv titan_p$r_tlbiv_overlay.titan_p$iq_tlbiv #define titan_p$iq_tlbia titan_p$r_tlbia_overlay.titan_p$iq_tlbia #define titan_p$iq_sctl titan_p$r_sctl_overlay.titan_p$iq_sctl #define titan_p$iq_sprst titan_p$r_sprst_overlay.titan_p$iq_sprst #endif /* #if !defined(__VAXC) */ /*************************************************************************** */ /* */ /* Bit Definitions for the Titan Chip Set Registers. Since many of these definitions */ /* are not used, I deleted definitions for Tsunami-only registers and updated Titan ones, but */ /* did not add any new Titan ones. */ /* */ /*************************************************************************** */ /*========================================================================== */ /* */ /* C-Chip Registers */ /* */ /*========================================================================== */ /* */ /* */ /* Titan CSC - C-Chip System Configuration Register */ /* */ #define TITAN_CSC$M_BC 0x3 #define TITAN_CSC$M_C0CFP 0x4 #define TITAN_CSC$M_C1CFP 0x8 #define TITAN_CSC$M_SED 0x30 #define TITAN_CSC$M_SFD 0x40 #define TITAN_CSC$M_FW 0x80 #define TITAN_CSC$M_AW 0x100 #define TITAN_CSC$M_IDDR 0xE00 #define TITAN_CSC$M_IDDW 0x3000 #define TITAN_CSC$M_P1P 0x4000 #define TITAN_CSC$M_RSVD_0 0x8000 #define TITAN_CSC$M_DWTP 0x30000 #define TITAN_CSC$M_DWFP 0xC0000 #define TITAN_CSC$M_DRTP 0x300000 #define TITAN_CSC$M_RSVD_1 0xC00000 #define TITAN_CSC$M_PME 0x1000000 #define TITAN_CSC$M_QPM 0x2000000 #define TITAN_CSC$M_FET 0xC000000 #define TITAN_CSC$M_QDI 0x70000000 #define TITAN_CSC$M_EFT 0x80000000 #define TITAN_CSC$M_FTI 0x100000000 #define TITAN_CSC$M_B1D 0x200000000 #define TITAN_CSC$M_B2D 0x400000000 #define TITAN_CSC$M_B3D 0x800000000 #define TITAN_CSC$M_TPQMMAX 0xF000000000 #define TITAN_CSC$M_FPQCMAX 0xF0000000000 #define TITAN_CSC$M_FPQPMAX 0xF00000000000 #define TITAN_CSC$M_PDTMAX 0x7000000000000 #define TITAN_CSC$M_AXD 0x8000000000000 #define TITAN_CSC$M_PRQMAX 0x70000000000000 #define TITAN_CSC$M_ADD4PTP 0x80000000000000 #define TITAN_CSC$M_PBQMAX 0x700000000000000 #define TITAN_CSC$M_RSVD_7 0x3800000000000000 #define TITAN_CSC$M_NODQM 0x4000000000000000 #define TITAN_CSC$M_ISM 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_csc { #pragma __nomember_alignment unsigned __int64 titan_csc$iq_data; __struct { unsigned int titan_csc$il_l; unsigned int titan_csc$il_h; } titan_csc$r_longwords; __struct { unsigned titan_csc$v_bc : 2; /* 1:0 Base Configuration */ unsigned titan_csc$v_c0cfp : 1; /* 2 CPU 0 Clk Fwd Preset */ unsigned titan_csc$v_c1cfp : 1; /* 3 CPU 1 Clk Fwd Preset */ unsigned titan_csc$v_sed : 2; /* 5:4 SysDC Extract Delay */ unsigned titan_csc$v_sfd : 1; /* 6 SysDC Fill Delay */ unsigned titan_csc$v_fw : 1; /* 7 available for firmware */ unsigned titan_csc$v_aw : 1; /* 8 Array Width */ unsigned titan_csc$v_iddr : 3; /* 11:9 Issue to Data Delay on read */ unsigned titan_csc$v_iddw : 2; /* 13:12 Issue to Data Delay for all xactions */ unsigned titan_csc$v_p1p : 1; /* 14 P-Chip 1 present */ unsigned titan_csc$v_rsvd_0 : 1; /* 15 reserved */ unsigned titan_csc$v_dwtp : 2; /* 17:16 Min Dchip Delay from CPU to PAD bus */ unsigned titan_csc$v_dwfp : 2; /* 19:18 Min Dchip Delay from PADbus to CPU or Memory */ unsigned titan_csc$v_drtp : 2; /* 21:20 Min Dchip Delay from Memory to PAD bus */ unsigned titan_csc$v_rsvd_1 : 2; /* 23:22 reserved */ unsigned titan_csc$v_pme : 1; /* 24 Page Mode Enable */ unsigned titan_csc$v_qpm : 1; /* 25 Que Priority Mode */ unsigned titan_csc$v_fet : 2; /* 27:26 Fill to Extract Turnaround cycles */ unsigned titan_csc$v_qdi : 3; /* 30:28 Que Drain Interval */ unsigned titan_csc$v_eft : 1; /* 31 Extract to Fill Turnaround cycles */ /* */ unsigned titan_csc$v_fti : 1; /* 32 Full Throttle Issue */ unsigned titan_csc$v_b1d : 1; /* 33 Bypass 1 Issue Path Disable */ unsigned titan_csc$v_b2d : 1; /* 34 Bypass 2 Issue Path Disable */ unsigned titan_csc$v_b3d : 1; /* 35 Bypass 3 Issue Path Disable */ unsigned titan_csc$v_tpqmmax : 4; /* 39:36 Max entries in TPQM on D-Chips, mod 16 */ unsigned titan_csc$v_fpqcmax : 4; /* 43:40 Max entries in FQP, mod 16 */ unsigned titan_csc$v_fpqpmax : 4; /* 47:44 Max entries in FPQ, mod 8 */ unsigned titan_csc$v_pdtmax : 3; /* 50:48 Max data xfers to one P-Chip until ack, mod 8 */ unsigned titan_csc$v_axd : 1; /* 51 Disable Memory Address XOR */ unsigned titan_csc$v_prqmax : 3; /* 54:52 max reqests to one P-Chip until ack, mod 8 */ unsigned titan_csc$v_add4ptp : 1; /* 55 Additional 4 PTP */ unsigned titan_csc$v_pbqmax : 3; /* 58:56 Max CPU probe queue */ unsigned titan_csc$v_rsvd_7 : 3; /* 61:59 reserved */ unsigned titan_csc$v_nodqm : 1; /* 62 Set to 1, DMA partial writes to memory use DQM */ unsigned titan_csc$v_ism : 1; /* 63 Interrupt Strobe Mode bit */ } titan_csc$r_bits; } TITAN_CSC; #if !defined(__VAXC) #define titan_csc$il_l titan_csc$r_longwords.titan_csc$il_l #define titan_csc$il_h titan_csc$r_longwords.titan_csc$il_h #define titan_csc$v_bc titan_csc$r_bits.titan_csc$v_bc #define titan_csc$v_c0cfp titan_csc$r_bits.titan_csc$v_c0cfp #define titan_csc$v_c1cfp titan_csc$r_bits.titan_csc$v_c1cfp #define titan_csc$v_sed titan_csc$r_bits.titan_csc$v_sed #define titan_csc$v_sfd titan_csc$r_bits.titan_csc$v_sfd #define titan_csc$v_fw titan_csc$r_bits.titan_csc$v_fw #define titan_csc$v_aw titan_csc$r_bits.titan_csc$v_aw #define titan_csc$v_iddr titan_csc$r_bits.titan_csc$v_iddr #define titan_csc$v_iddw titan_csc$r_bits.titan_csc$v_iddw #define titan_csc$v_p1p titan_csc$r_bits.titan_csc$v_p1p #define titan_csc$v_rsvd_0 titan_csc$r_bits.titan_csc$v_rsvd_0 #define titan_csc$v_dwtp titan_csc$r_bits.titan_csc$v_dwtp #define titan_csc$v_dwfp titan_csc$r_bits.titan_csc$v_dwfp #define titan_csc$v_drtp titan_csc$r_bits.titan_csc$v_drtp #define titan_csc$v_rsvd_1 titan_csc$r_bits.titan_csc$v_rsvd_1 #define titan_csc$v_pme titan_csc$r_bits.titan_csc$v_pme #define titan_csc$v_qpm titan_csc$r_bits.titan_csc$v_qpm #define titan_csc$v_fet titan_csc$r_bits.titan_csc$v_fet #define titan_csc$v_qdi titan_csc$r_bits.titan_csc$v_qdi #define titan_csc$v_eft titan_csc$r_bits.titan_csc$v_eft #define titan_csc$v_fti titan_csc$r_bits.titan_csc$v_fti #define titan_csc$v_b1d titan_csc$r_bits.titan_csc$v_b1d #define titan_csc$v_b2d titan_csc$r_bits.titan_csc$v_b2d #define titan_csc$v_b3d titan_csc$r_bits.titan_csc$v_b3d #define titan_csc$v_tpqmmax titan_csc$r_bits.titan_csc$v_tpqmmax #define titan_csc$v_fpqcmax titan_csc$r_bits.titan_csc$v_fpqcmax #define titan_csc$v_fpqpmax titan_csc$r_bits.titan_csc$v_fpqpmax #define titan_csc$v_pdtmax titan_csc$r_bits.titan_csc$v_pdtmax #define titan_csc$v_axd titan_csc$r_bits.titan_csc$v_axd #define titan_csc$v_prqmax titan_csc$r_bits.titan_csc$v_prqmax #define titan_csc$v_add4ptp titan_csc$r_bits.titan_csc$v_add4ptp #define titan_csc$v_pbqmax titan_csc$r_bits.titan_csc$v_pbqmax #define titan_csc$v_rsvd_7 titan_csc$r_bits.titan_csc$v_rsvd_7 #define titan_csc$v_nodqm titan_csc$r_bits.titan_csc$v_nodqm #define titan_csc$v_ism titan_csc$r_bits.titan_csc$v_ism #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan MTR - C-Chip Memory Timing Register */ /* */ #define TITAN_MTR$M_RCD 0x1 #define TITAN_MTR$M_RSVD_0 0x2 #define TITAN_MTR$M_CAT 0x4 #define TITAN_MTR$M_RSVD_1 0x8 #define TITAN_MTR$M_IRD 0x70 #define TITAN_MTR$M_RSVD_2 0x80 #define TITAN_MTR$M_RPW 0x300 #define TITAN_MTR$M_RSVD_3 0xC00 #define TITAN_MTR$M_RPT 0x3000 #define TITAN_MTR$M_RSVD_4 0xC000 #define TITAN_MTR$M_RRD 0x10000 #define TITAN_MTR$M_RSVD_5 0xE0000 #define TITAN_MTR$M_MPD 0x100000 #define TITAN_MTR$M_RSVD_6 0xE00000 #define TITAN_MTR$M_RI 0x3F000000 #define TITAN_MTR$M_RSVD_7 0xC0000000 #define TITAN_MTR$M_PHCR 0xF00000000 #define TITAN_MTR$M_PHCW 0xF000000000 #define TITAN_MTR$M_MPH 0x3F0000000000 #define TITAN_MTR$M_RSVD_8 0xFFFFC00000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_mtr { #pragma __nomember_alignment unsigned __int64 titan_mtr$iq_data; __struct { unsigned int titan_mtr$il_l; unsigned int titan_mtr$il_h; } titan_mtr$r_longwords; __struct { unsigned titan_mtr$v_rcd : 1; /* 0 RAS to CAS Delay */ unsigned titan_mtr$v_rsvd_0 : 1; /* 1 reserved */ unsigned titan_mtr$v_cat : 1; /* 2 CAS Access Time */ unsigned titan_mtr$v_rsvd_1 : 1; /* 3 reserved */ unsigned titan_mtr$v_ird : 3; /* 6:4 Issue to RAS Delay */ unsigned titan_mtr$v_rsvd_2 : 1; /* 7 reserved */ unsigned titan_mtr$v_rpw : 2; /* 9:8 Minimum RAS Pulse Width */ unsigned titan_mtr$v_rsvd_3 : 2; /* 11:10 reserved */ unsigned titan_mtr$v_rpt : 2; /* 13:12 Min RAS Precharge Time */ unsigned titan_mtr$v_rsvd_4 : 2; /* 15:14 reserved */ unsigned titan_mtr$v_rrd : 1; /* 16 Min Same-Array_Diff-Bank RAS-to-RAS Delay */ unsigned titan_mtr$v_rsvd_5 : 3; /* 19:17 reserved */ unsigned titan_mtr$v_mpd : 1; /* 20 Mask Pipeline Delay */ unsigned titan_mtr$v_rsvd_6 : 3; /* 23:21 reserved */ unsigned titan_mtr$v_ri : 6; /* 29:24 Refresh Interval */ unsigned titan_mtr$v_rsvd_7 : 2; /* 31:30 reserved */ /* */ unsigned titan_mtr$v_phcr : 4; /* 35:32 Page Hit Cycles for Reads */ unsigned titan_mtr$v_phcw : 4; /* 39:36 Page Hit Cycles for Writes */ unsigned titan_mtr$v_mph : 6; /* 45:40 Max Page Hits */ unsigned titan_mtr$v_rsvd_8 : 18; /* 63:46 reserved */ } titan_mtr$r_bits; } TITAN_MTR; #if !defined(__VAXC) #define titan_mtr$il_l titan_mtr$r_longwords.titan_mtr$il_l #define titan_mtr$il_h titan_mtr$r_longwords.titan_mtr$il_h #define titan_mtr$v_rcd titan_mtr$r_bits.titan_mtr$v_rcd #define titan_mtr$v_rsvd_0 titan_mtr$r_bits.titan_mtr$v_rsvd_0 #define titan_mtr$v_cat titan_mtr$r_bits.titan_mtr$v_cat #define titan_mtr$v_rsvd_1 titan_mtr$r_bits.titan_mtr$v_rsvd_1 #define titan_mtr$v_ird titan_mtr$r_bits.titan_mtr$v_ird #define titan_mtr$v_rsvd_2 titan_mtr$r_bits.titan_mtr$v_rsvd_2 #define titan_mtr$v_rpw titan_mtr$r_bits.titan_mtr$v_rpw #define titan_mtr$v_rsvd_3 titan_mtr$r_bits.titan_mtr$v_rsvd_3 #define titan_mtr$v_rpt titan_mtr$r_bits.titan_mtr$v_rpt #define titan_mtr$v_rsvd_4 titan_mtr$r_bits.titan_mtr$v_rsvd_4 #define titan_mtr$v_rrd titan_mtr$r_bits.titan_mtr$v_rrd #define titan_mtr$v_rsvd_5 titan_mtr$r_bits.titan_mtr$v_rsvd_5 #define titan_mtr$v_mpd titan_mtr$r_bits.titan_mtr$v_mpd #define titan_mtr$v_rsvd_6 titan_mtr$r_bits.titan_mtr$v_rsvd_6 #define titan_mtr$v_ri titan_mtr$r_bits.titan_mtr$v_ri #define titan_mtr$v_rsvd_7 titan_mtr$r_bits.titan_mtr$v_rsvd_7 #define titan_mtr$v_phcr titan_mtr$r_bits.titan_mtr$v_phcr #define titan_mtr$v_phcw titan_mtr$r_bits.titan_mtr$v_phcw #define titan_mtr$v_mph titan_mtr$r_bits.titan_mtr$v_mph #define titan_mtr$v_rsvd_8 titan_mtr$r_bits.titan_mtr$v_rsvd_8 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan MISC - C-Chip Miscellaneous Register */ /* */ #define TITAN_MISC$M_CPUID 0x3 #define TITAN_MISC$M_RSVD_0 0xC #define TITAN_MISC$M_ITINTR 0xF0 #define TITAN_MISC$M_IPINTR 0xF00 #define TITAN_MISC$M_IPREQ 0xF000 #define TITAN_MISC$M_ABW 0xF0000 #define TITAN_MISC$M_ABT 0xF00000 #define TITAN_MISC$M_ACL 0x1000000 #define TITAN_MISC$M_RSVD_6 0xE000000 #define TITAN_MISC$M_NXM 0x10000000 #define TITAN_MISC$M_NXS 0xE0000000 #define TITAN_MISC$M_REV 0xFF00000000 #define TITAN_MISC$M_DEVSUP 0xF0000000000 #define TITAN_MISC$M_RSVD_7 0xFFFFF00000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_misc { #pragma __nomember_alignment __struct { unsigned titan_misc$v_cpuid : 2; /* 0:1 ID of CPU performing the read */ unsigned titan_misc$v_rsvd_0 : 2; /* 3:2 reserved */ unsigned titan_misc$v_itintr : 4; /* 7:4 Interval Timer Interrupt pending */ unsigned titan_misc$v_ipintr : 4; /* 11:8 Interprocessor Interrupt pending */ unsigned titan_misc$v_ipreq : 4; /* 15:12 Interprocessor Interrupt Request */ unsigned titan_misc$v_abw : 4; /* 19:16 Arbitration Won */ unsigned titan_misc$v_abt : 4; /* 23:20 Arbitration Try */ unsigned titan_misc$v_acl : 1; /* 24 Arbitration Clear */ unsigned titan_misc$v_rsvd_6 : 3; /* 27:25 reserved */ unsigned titan_misc$v_nxm : 1; /* 28 Non eXistent Memory */ unsigned titan_misc$v_nxs : 3; /* 31:29 NXM Source */ /* */ unsigned titan_misc$v_rev : 8; /* 39:32 C-Chip Revision */ unsigned titan_misc$v_devsup : 4; /* 43:40 Suppress IRQ[1] */ unsigned titan_misc$v_rsvd_7 : 20; /* 63:44 reserved */ } titan_misc$r_bits; } TITAN_MISC; #if !defined(__VAXC) #define titan_misc$v_cpuid titan_misc$r_bits.titan_misc$v_cpuid #define titan_misc$v_rsvd_0 titan_misc$r_bits.titan_misc$v_rsvd_0 #define titan_misc$v_itintr titan_misc$r_bits.titan_misc$v_itintr #define titan_misc$v_ipintr titan_misc$r_bits.titan_misc$v_ipintr #define titan_misc$v_ipreq titan_misc$r_bits.titan_misc$v_ipreq #define titan_misc$v_abw titan_misc$r_bits.titan_misc$v_abw #define titan_misc$v_abt titan_misc$r_bits.titan_misc$v_abt #define titan_misc$v_acl titan_misc$r_bits.titan_misc$v_acl #define titan_misc$v_rsvd_6 titan_misc$r_bits.titan_misc$v_rsvd_6 #define titan_misc$v_nxm titan_misc$r_bits.titan_misc$v_nxm #define titan_misc$v_nxs titan_misc$r_bits.titan_misc$v_nxs #define titan_misc$v_rev titan_misc$r_bits.titan_misc$v_rev #define titan_misc$v_devsup titan_misc$r_bits.titan_misc$v_devsup #define titan_misc$v_rsvd_7 titan_misc$r_bits.titan_misc$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan MPD - C-Chip Memory Presence Detect */ /* */ #define TITAN_MPD$M_CKS 0x1 #define TITAN_MPD$M_DS 0x2 #define TITAN_MPD$M_CKR 0x4 #define TITAN_MPD$M_DR 0x8 #define TITAN_MPD$M_RSVD_0 0xFFFFFFF0 #define TITAN_MPD$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_mpd { #pragma __nomember_alignment __struct { unsigned titan_mpd$v_cks : 1; /* 0 ClocK Send */ unsigned titan_mpd$v_ds : 1; /* 1 Data Send */ unsigned titan_mpd$v_ckr : 1; /* 2 ClocK Receive */ unsigned titan_mpd$v_dr : 1; /* 3 Data Receive */ unsigned titan_mpd$v_rsvd_0 : 28; /* 31:4 reserved */ /* */ unsigned titan_mpd$v_rsvd_1 : 32; /* 63:32 reserved */ } titan_mpd$r_bits; } TITAN_MPD; #if !defined(__VAXC) #define titan_mpd$v_cks titan_mpd$r_bits.titan_mpd$v_cks #define titan_mpd$v_ds titan_mpd$r_bits.titan_mpd$v_ds #define titan_mpd$v_ckr titan_mpd$r_bits.titan_mpd$v_ckr #define titan_mpd$v_dr titan_mpd$r_bits.titan_mpd$v_dr #define titan_mpd$v_rsvd_0 titan_mpd$r_bits.titan_mpd$v_rsvd_0 #define titan_mpd$v_rsvd_1 titan_mpd$r_bits.titan_mpd$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan AAR - C-Chip Array Address Register */ /* */ #define TITAN_AAR$M_BNKS 0x3 #define TITAN_AAR$M_ROWS 0xC #define TITAN_AAR$M_RSVD_1 0xF0 #define TITAN_AAR$M_SA 0x100 #define TITAN_AAR$M_DSA 0x200 #define TITAN_AAR$M_RSVD_2 0xC00 #define TITAN_AAR$M_ASIZ 0xF000 #define TITAN_AAR$M_DBG 0x10000 #define TITAN_AAR$M_RSVD_4 0xFE0000 #define TITAN_AAR$M_ADDR 0x7FF000000 #define TITAN_AAR$M_RSVD_5 0x7FFFFFF800000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_aar { #pragma __nomember_alignment unsigned __int64 titan_aar$iq_data; __struct { unsigned int titan_aar$il_l; unsigned int titan_aar$il_h; } titan_aar$r_longwords; __struct { unsigned titan_aar$v_bnks : 2; /* 1:0 Number of Bank bits in SDRAMs */ unsigned titan_aar$v_rows : 2; /* 3:2 Number of Row bits in SDRAMS */ unsigned titan_aar$v_rsvd_1 : 4; /* 7:4 reserved */ unsigned titan_aar$v_sa : 1; /* 8 Split Array */ unsigned titan_aar$v_dsa : 1; /* 9 Doubly (twice) Split Array */ unsigned titan_aar$v_rsvd_2 : 2; /* 11:10 reserved */ unsigned titan_aar$v_asiz : 4; /* 15:12 Array Size */ unsigned titan_aar$v_dbg : 1; /* 16 Enables this memory port as a debug interface */ unsigned titan_aar$v_rsvd_4 : 7; /* 23:17 reserved */ unsigned titan_aar$v_addr : 11; /* 34:24 Base Address */ unsigned titan_aar$v_rsvd_5 : 28; /* 63:35 reserved */ unsigned titan_aar$v_fill_0_ : 1; } titan_aar$r_bits; } TITAN_AAR; #if !defined(__VAXC) #define titan_aar$il_l titan_aar$r_longwords.titan_aar$il_l #define titan_aar$il_h titan_aar$r_longwords.titan_aar$il_h #define titan_aar$v_bnks titan_aar$r_bits.titan_aar$v_bnks #define titan_aar$v_rows titan_aar$r_bits.titan_aar$v_rows #define titan_aar$v_rsvd_1 titan_aar$r_bits.titan_aar$v_rsvd_1 #define titan_aar$v_sa titan_aar$r_bits.titan_aar$v_sa #define titan_aar$v_dsa titan_aar$r_bits.titan_aar$v_dsa #define titan_aar$v_rsvd_2 titan_aar$r_bits.titan_aar$v_rsvd_2 #define titan_aar$v_asiz titan_aar$r_bits.titan_aar$v_asiz #define titan_aar$v_dbg titan_aar$r_bits.titan_aar$v_dbg #define titan_aar$v_rsvd_4 titan_aar$r_bits.titan_aar$v_rsvd_4 #define titan_aar$v_addr titan_aar$r_bits.titan_aar$v_addr #define titan_aar$v_rsvd_5 titan_aar$r_bits.titan_aar$v_rsvd_5 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan DIM - C-Chip Device Interrupt Mask Registers */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_dim { #pragma __nomember_alignment unsigned __int64 titan_dim$iq_data; __struct { unsigned int titan_dim$il_l; unsigned int titan_dim$il_h; } titan_dim$r_longwords; } TITAN_DIM; #if !defined(__VAXC) #define titan_dim$il_l titan_dim$r_longwords.titan_dim$il_l #define titan_dim$il_h titan_dim$r_longwords.titan_dim$il_h #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan DIR - C-Chip Device Interrupt Request Registers */ /* */ #define TITAN_DIR$M_DEV_L 0xFFFFFFFF #define TITAN_DIR$M_DEV_H 0xFFFFFF00000000 #define TITAN_DIR$M_RSVD_0 0x300000000000000 #define TITAN_DIR$M_ERR 0xFC00000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_dir { #pragma __nomember_alignment unsigned __int64 titan_dir$iq_data; __struct { unsigned int titan_dir$il_l; unsigned int titan_dir$il_h; } titan_dir$r_longwords; __struct { unsigned titan_dir$v_dev_l : 32; /* 31:0 IRQ[1] PCI Interrupts Pending */ unsigned titan_dir$v_dev_h : 24; /* 55:32 IRQ[1] PCI Interrupts Pending */ unsigned titan_dir$v_rsvd_0 : 2; /* 57:56 reserved */ unsigned titan_dir$v_err : 6; /* 63:58 IRQ[0] Error Interrupts */ } titan_dir$r_bits; } TITAN_DIR; #if !defined(__VAXC) #define titan_dir$il_l titan_dir$r_longwords.titan_dir$il_l #define titan_dir$il_h titan_dir$r_longwords.titan_dir$il_h #define titan_dir$v_dev_l titan_dir$r_bits.titan_dir$v_dev_l #define titan_dir$v_dev_h titan_dir$r_bits.titan_dir$v_dev_h #define titan_dir$v_rsvd_0 titan_dir$r_bits.titan_dir$v_rsvd_0 #define titan_dir$v_err titan_dir$r_bits.titan_dir$v_err #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan DRIR - C-Chip Raw Interrupt Request Register */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_drir { #pragma __nomember_alignment unsigned __int64 titan_drir$iq_data; __struct { unsigned int titan_drir$il_l; unsigned int titan_drir$il_h; } titan_drir$r_longwords; } TITAN_DRIR; #if !defined(__VAXC) #define titan_drir$il_l titan_drir$r_longwords.titan_drir$il_l #define titan_drir$il_h titan_drir$r_longwords.titan_drir$il_h #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan PRBEN - C-Chip Probe Enable Register */ /* */ #define TITAN_PRBEN$M_PRBEN 0x1 #define TITAN_PRBEN$M_RSVD_0 0xFFFFFFFE #define TITAN_PRBEN$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_prben { #pragma __nomember_alignment unsigned __int64 titan_prben$iq_data; __struct { unsigned int titan_prben$il_l; unsigned int titan_prben$il_h; } titan_prben$r_longwords; __struct { unsigned titan_prben$v_prben : 1; /* 0 Probe Enable bit */ unsigned titan_prben$v_rsvd_0 : 31; /* 31:1 Reserved */ unsigned titan_prben$v_rsvd_1 : 32; /* 63:32 Reserved */ } titan_prben$r_bits; } TITAN_PRBEN; #if !defined(__VAXC) #define titan_prben$il_l titan_prben$r_longwords.titan_prben$il_l #define titan_prben$il_h titan_prben$r_longwords.titan_prben$il_h #define titan_prben$v_prben titan_prben$r_bits.titan_prben$v_prben #define titan_prben$v_rsvd_0 titan_prben$r_bits.titan_prben$v_rsvd_0 #define titan_prben$v_rsvd_1 titan_prben$r_bits.titan_prben$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan IIC - C-Chip Interval Ignore Count Registers */ /* */ #define TITAN_IIC$M_ICNT 0xFFFFFF #define TITAN_IIC$M_OF 0x1000000 #define TITAN_IIC$M_RSVD_0 0xFE000000 #define TITAN_IIC$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_iic { #pragma __nomember_alignment unsigned __int64 titan_iic$iq_data; __struct { unsigned int titan_iic$il_l; unsigned int titan_iic$il_h; } titan_iic$r_longwords; __struct { unsigned titan_iic$v_icnt : 24; /* 23:0 Count of remaining interrupts to ignore */ unsigned titan_iic$v_of : 1; /* 24 Overflow bit */ unsigned titan_iic$v_rsvd_0 : 7; /* 31:25 reserved */ unsigned titan_iic$v_rsvd_1 : 32; /* 63:32 reserved */ } titan_iic$r_bits; } TITAN_IIC; #if !defined(__VAXC) #define titan_iic$il_l titan_iic$r_longwords.titan_iic$il_l #define titan_iic$il_h titan_iic$r_longwords.titan_iic$il_h #define titan_iic$v_icnt titan_iic$r_bits.titan_iic$v_icnt #define titan_iic$v_of titan_iic$r_bits.titan_iic$v_of #define titan_iic$v_rsvd_0 titan_iic$r_bits.titan_iic$v_rsvd_0 #define titan_iic$v_rsvd_1 titan_iic$r_bits.titan_iic$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan MPR - C-Chip Memory Programming Registers */ /* */ #define TITAN_MPR$M_MPRDAT 0x1FFF #define TITAN_MPR$M_RSVD_0 0xFFFFE000 #define TITAN_MPR$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_mpr { #pragma __nomember_alignment unsigned __int64 titan_mpr$iq_data; __struct { unsigned int titan_mpr$il_l; unsigned int titan_mpr$il_h; } titan_mpr$r_longwords; __struct { unsigned titan_mpr$v_mprdat : 13; /* 12:0 Data to be written on address lines 12:0 */ unsigned titan_mpr$v_rsvd_0 : 19; /* 31:13 reserved */ unsigned titan_mpr$v_rsvd_1 : 32; /* 63:32 reserved */ } titan_mpr$r_bits; } TITAN_MPR; #if !defined(__VAXC) #define titan_mpr$il_l titan_mpr$r_longwords.titan_mpr$il_l #define titan_mpr$il_h titan_mpr$r_longwords.titan_mpr$il_h #define titan_mpr$v_mprdat titan_mpr$r_bits.titan_mpr$v_mprdat #define titan_mpr$v_rsvd_0 titan_mpr$r_bits.titan_mpr$v_rsvd_0 #define titan_mpr$v_rsvd_1 titan_mpr$r_bits.titan_mpr$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan TTR - C-Chip TIG Bus Timing Register */ /* */ #define TITAN_TTR$M_AS 0x3 #define TITAN_TTR$M_AH 0xC #define TITAN_TTR$M_IS 0xF0 #define TITAN_TTR$M_IRT 0xF00 #define TITAN_TTR$M_ID 0x7000 #define TITAN_TTR$M_RSVD_3 0xFFFF8000 #define TITAN_TTR$M_RSVD_4 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_ttr { #pragma __nomember_alignment __struct { unsigned titan_ttr$v_as : 2; /* 1:0 Address Setup to the address latch before AS */ unsigned titan_ttr$v_ah : 2; /* 3:2 Address Hold after AS before CS_L */ unsigned titan_ttr$v_is : 4; /* 7:4 Interrupt Setup time */ unsigned titan_ttr$v_irt : 4; /* 11:8 Interrupt Read Time */ unsigned titan_ttr$v_id : 3; /* 14:12 Interrupt starting Device */ unsigned titan_ttr$v_rsvd_3 : 17; /* 31:15 reserved */ unsigned titan_ttr$v_rsvd_4 : 32; /* 63:32 reserved */ } titan_ttr$r_bits; } TITAN_TTR; #if !defined(__VAXC) #define titan_ttr$v_as titan_ttr$r_bits.titan_ttr$v_as #define titan_ttr$v_ah titan_ttr$r_bits.titan_ttr$v_ah #define titan_ttr$v_is titan_ttr$r_bits.titan_ttr$v_is #define titan_ttr$v_irt titan_ttr$r_bits.titan_ttr$v_irt #define titan_ttr$v_id titan_ttr$r_bits.titan_ttr$v_id #define titan_ttr$v_rsvd_3 titan_ttr$r_bits.titan_ttr$v_rsvd_3 #define titan_ttr$v_rsvd_4 titan_ttr$r_bits.titan_ttr$v_rsvd_4 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan TDR - C-Chip TIG Bus Device Timing Register */ /* */ #define TITAN_TDR$M_RA0 0x1F #define TITAN_TDR$M_RD0 0xE0 #define TITAN_TDR$M_WS0 0xF00 #define TITAN_TDR$M_WP0 0x7000 #define TITAN_TDR$M_WH0 0x8000 #define TITAN_TDR$M_RA1 0x1F0000 #define TITAN_TDR$M_RD1 0xE00000 #define TITAN_TDR$M_WS1 0xF000000 #define TITAN_TDR$M_WP1 0x70000000 #define TITAN_TDR$M_WH1 0x80000000 #define TITAN_TDR$M_RA2 0x1F00000000 #define TITAN_TDR$M_RD2 0xE000000000 #define TITAN_TDR$M_WS2 0xF0000000000 #define TITAN_TDR$M_WP2 0x700000000000 #define TITAN_TDR$M_WH2 0x800000000000 #define TITAN_TDR$M_RA3 0x1F000000000000 #define TITAN_TDR$M_RD3 0xE0000000000000 #define TITAN_TDR$M_WS3 0xF00000000000000 #define TITAN_TDR$M_WP3 0x7000000000000000 #define TITAN_TDR$M_WH3 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_tdr { #pragma __nomember_alignment unsigned __int64 titan_tdr$iq_data; __struct { unsigned int titan_tdr$il_l; unsigned int titan_tdr$il_h; } titan_tdr$r_longwords; __struct { unsigned titan_tdr$v_ra0 : 5; /* 4:0 Read Access time */ unsigned titan_tdr$v_rd0 : 3; /* 7:5 Read output Disable time */ unsigned titan_tdr$v_ws0 : 4; /* 11:8 Write Setup time */ unsigned titan_tdr$v_wp0 : 3; /* 14:12 Write Pulse width */ unsigned titan_tdr$v_wh0 : 1; /* 15 Write Hold time */ /* */ unsigned titan_tdr$v_ra1 : 5; /* 20:16 Read Access time */ unsigned titan_tdr$v_rd1 : 3; /* 23:21 Read output Disable time */ unsigned titan_tdr$v_ws1 : 4; /* 27:24 Write Setup time */ unsigned titan_tdr$v_wp1 : 3; /* 30:28 Write Pulse width */ unsigned titan_tdr$v_wh1 : 1; /* 31 Write Hold time */ /* */ unsigned titan_tdr$v_ra2 : 5; /* 36:32 Read Access time */ unsigned titan_tdr$v_rd2 : 3; /* 39:37 Read output Disable time */ unsigned titan_tdr$v_ws2 : 4; /* 43:40 Write Setup time */ unsigned titan_tdr$v_wp2 : 3; /* 46:44 Write Pulse width */ unsigned titan_tdr$v_wh2 : 1; /* 47 Write Hold time */ /* */ unsigned titan_tdr$v_ra3 : 5; /* 52:48 Read Access time */ unsigned titan_tdr$v_rd3 : 3; /* 55:53 Read output Disable time */ unsigned titan_tdr$v_ws3 : 4; /* 59:56 Write Setup time */ unsigned titan_tdr$v_wp3 : 3; /* 62:60 Write Pulse width */ unsigned titan_tdr$v_wh3 : 1; /* 63 Write Hold time */ } titan_tdr$r_bits; } TITAN_TDR; #if !defined(__VAXC) #define titan_tdr$il_l titan_tdr$r_longwords.titan_tdr$il_l #define titan_tdr$il_h titan_tdr$r_longwords.titan_tdr$il_h #define titan_tdr$v_ra0 titan_tdr$r_bits.titan_tdr$v_ra0 #define titan_tdr$v_rd0 titan_tdr$r_bits.titan_tdr$v_rd0 #define titan_tdr$v_ws0 titan_tdr$r_bits.titan_tdr$v_ws0 #define titan_tdr$v_wp0 titan_tdr$r_bits.titan_tdr$v_wp0 #define titan_tdr$v_wh0 titan_tdr$r_bits.titan_tdr$v_wh0 #define titan_tdr$v_ra1 titan_tdr$r_bits.titan_tdr$v_ra1 #define titan_tdr$v_rd1 titan_tdr$r_bits.titan_tdr$v_rd1 #define titan_tdr$v_ws1 titan_tdr$r_bits.titan_tdr$v_ws1 #define titan_tdr$v_wp1 titan_tdr$r_bits.titan_tdr$v_wp1 #define titan_tdr$v_wh1 titan_tdr$r_bits.titan_tdr$v_wh1 #define titan_tdr$v_ra2 titan_tdr$r_bits.titan_tdr$v_ra2 #define titan_tdr$v_rd2 titan_tdr$r_bits.titan_tdr$v_rd2 #define titan_tdr$v_ws2 titan_tdr$r_bits.titan_tdr$v_ws2 #define titan_tdr$v_wp2 titan_tdr$r_bits.titan_tdr$v_wp2 #define titan_tdr$v_wh2 titan_tdr$r_bits.titan_tdr$v_wh2 #define titan_tdr$v_ra3 titan_tdr$r_bits.titan_tdr$v_ra3 #define titan_tdr$v_rd3 titan_tdr$r_bits.titan_tdr$v_rd3 #define titan_tdr$v_ws3 titan_tdr$r_bits.titan_tdr$v_ws3 #define titan_tdr$v_wp3 titan_tdr$r_bits.titan_tdr$v_wp3 #define titan_tdr$v_wh3 titan_tdr$r_bits.titan_tdr$v_wh3 #endif /* #if !defined(__VAXC) */ /*========================================================================== */ /* */ /* D-Chip Registers */ /* */ /*========================================================================== */ /* */ /* */ /* Titan DSC - D-Chip System Configuration Register */ /* */ #define TITAN_DSC$M_BC 0x3 #define TITAN_DSC$M_C0CFP 0x4 #define TITAN_DSC$M_C1CFP 0x8 #define TITAN_DSC$M_C2CFP 0x10 #define TITAN_DSC$M_C3CFP 0x20 #define TITAN_DSC$M_P1P 0x40 #define TITAN_DSC$M_RSVD_0 0x80 #define TITAN_DSC$M_BC1 0x300 #define TITAN_DSC$M_C0CFP1 0x400 #define TITAN_DSC$M_C1CFP1 0x800 #define TITAN_DSC$M_C2CFP1 0x1000 #define TITAN_DSC$M_C3CFP1 0x2000 #define TITAN_DSC$M_P1P1 0x4000 #define TITAN_DSC$M_RSVD_1 0x8000 #define TITAN_DSC$M_BC2 0x30000 #define TITAN_DSC$M_C0CFP2 0x40000 #define TITAN_DSC$M_C1CFP2 0x80000 #define TITAN_DSC$M_C2CFP2 0x100000 #define TITAN_DSC$M_C3CFP2 0x200000 #define TITAN_DSC$M_P1P2 0x400000 #define TITAN_DSC$M_RSVD_2 0x800000 #define TITAN_DSC$M_BC3 0x3000000 #define TITAN_DSC$M_C0CFP3 0x4000000 #define TITAN_DSC$M_C1CFP3 0x8000000 #define TITAN_DSC$M_C2CFP3 0x10000000 #define TITAN_DSC$M_C3CFP3 0x20000000 #define TITAN_DSC$M_P1P3 0x40000000 #define TITAN_DSC$M_RSVD_3 0x80000000 #define TITAN_DSC$M_BC4 0x300000000 #define TITAN_DSC$M_C0CFP4 0x400000000 #define TITAN_DSC$M_C1CFP4 0x800000000 #define TITAN_DSC$M_C2CFP4 0x1000000000 #define TITAN_DSC$M_C3CFP4 0x2000000000 #define TITAN_DSC$M_P1P4 0x4000000000 #define TITAN_DSC$M_RSVD_4 0x8000000000 #define TITAN_DSC$M_BC15 0x30000000000 #define TITAN_DSC$M_C0CFP5 0x40000000000 #define TITAN_DSC$M_C1CFP5 0x80000000000 #define TITAN_DSC$M_C2CFP5 0x100000000000 #define TITAN_DSC$M_C3CFP5 0x200000000000 #define TITAN_DSC$M_P1P5 0x400000000000 #define TITAN_DSC$M_RSVD_5 0x800000000000 #define TITAN_DSC$M_BC6 0x3000000000000 #define TITAN_DSC$M_C0CFP6 0x4000000000000 #define TITAN_DSC$M_C1CFP6 0x8000000000000 #define TITAN_DSC$M_C2CFP6 0x10000000000000 #define TITAN_DSC$M_C3CFP6 0x20000000000000 #define TITAN_DSC$M_P1P6 0x40000000000000 #define TITAN_DSC$M_RSVD_6 0x80000000000000 #define TITAN_DSC$M_BC7 0x300000000000000 #define TITAN_DSC$M_C0CFP7 0x400000000000000 #define TITAN_DSC$M_C1CFP7 0x800000000000000 #define TITAN_DSC$M_C2CFP7 0x1000000000000000 #define TITAN_DSC$M_C3CFP7 0x2000000000000000 #define TITAN_DSC$M_P1P7 0x4000000000000000 #define TITAN_DSC$M_RSVD_7 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_dsc { #pragma __nomember_alignment unsigned __int64 titan_dsc$iq_data; __struct { unsigned int titan_dsc$il_l; unsigned int titan_dsc$il_h; } titan_dsc$r_longwords; __struct { unsigned titan_dsc$v_bc : 2; /* 1:0 Base Configuration */ unsigned titan_dsc$v_c0cfp : 1; /* 2 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp : 1; /* 3 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp : 1; /* 4 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp : 1; /* 5 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p : 1; /* 6 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_0 : 1; /* 7 reserved */ /* */ unsigned titan_dsc$v_bc1 : 2; /* 9:8 Base Configuration */ unsigned titan_dsc$v_c0cfp1 : 1; /* 10 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp1 : 1; /* 11 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp1 : 1; /* 12 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp1 : 1; /* 13 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p1 : 1; /* 14 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_1 : 1; /* 15 reserved */ /* */ unsigned titan_dsc$v_bc2 : 2; /* 17:16 Base Configuration */ unsigned titan_dsc$v_c0cfp2 : 1; /* 18 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp2 : 1; /* 19 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp2 : 1; /* 20 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp2 : 1; /* 21 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p2 : 1; /* 22 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_2 : 1; /* 23 reserved */ /* */ unsigned titan_dsc$v_bc3 : 2; /* 25:24 Base Configuration */ unsigned titan_dsc$v_c0cfp3 : 1; /* 26 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp3 : 1; /* 27 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp3 : 1; /* 28 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp3 : 1; /* 29 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p3 : 1; /* 30 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_3 : 1; /* 31 reserved */ /* */ unsigned titan_dsc$v_bc4 : 2; /* 33:32 Base Configuration */ unsigned titan_dsc$v_c0cfp4 : 1; /* 34 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp4 : 1; /* 35 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp4 : 1; /* 36 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp4 : 1; /* 37 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p4 : 1; /* 38 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_4 : 1; /* 39 reserved */ /* */ unsigned titan_dsc$v_bc15 : 2; /* 41:40 Base Configuration */ unsigned titan_dsc$v_c0cfp5 : 1; /* 42 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp5 : 1; /* 43 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp5 : 1; /* 44 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp5 : 1; /* 45 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p5 : 1; /* 46 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_5 : 1; /* 47 reserved */ /* */ unsigned titan_dsc$v_bc6 : 2; /* 49:48 Base Configuration */ unsigned titan_dsc$v_c0cfp6 : 1; /* 50 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp6 : 1; /* 51 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp6 : 1; /* 52 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp6 : 1; /* 53 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p6 : 1; /* 54 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_6 : 1; /* 55 reserved */ /* */ unsigned titan_dsc$v_bc7 : 2; /* 57:56 Base Configuration */ unsigned titan_dsc$v_c0cfp7 : 1; /* 58 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c1cfp7 : 1; /* 59 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c2cfp7 : 1; /* 60 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_c3cfp7 : 1; /* 61 CPU 0 Clock Forward Preset */ unsigned titan_dsc$v_p1p7 : 1; /* 62 P-Chip_1 Preset */ unsigned titan_dsc$v_rsvd_7 : 1; /* 63 reserved */ } titan_dsc$r_bits; } TITAN_DSC; #if !defined(__VAXC) #define titan_dsc$il_l titan_dsc$r_longwords.titan_dsc$il_l #define titan_dsc$il_h titan_dsc$r_longwords.titan_dsc$il_h #define titan_dsc$v_bc titan_dsc$r_bits.titan_dsc$v_bc #define titan_dsc$v_c0cfp titan_dsc$r_bits.titan_dsc$v_c0cfp #define titan_dsc$v_c1cfp titan_dsc$r_bits.titan_dsc$v_c1cfp #define titan_dsc$v_c2cfp titan_dsc$r_bits.titan_dsc$v_c2cfp #define titan_dsc$v_c3cfp titan_dsc$r_bits.titan_dsc$v_c3cfp #define titan_dsc$v_p1p titan_dsc$r_bits.titan_dsc$v_p1p #define titan_dsc$v_rsvd_0 titan_dsc$r_bits.titan_dsc$v_rsvd_0 #define titan_dsc$v_bc1 titan_dsc$r_bits.titan_dsc$v_bc1 #define titan_dsc$v_c0cfp1 titan_dsc$r_bits.titan_dsc$v_c0cfp1 #define titan_dsc$v_c1cfp1 titan_dsc$r_bits.titan_dsc$v_c1cfp1 #define titan_dsc$v_c2cfp1 titan_dsc$r_bits.titan_dsc$v_c2cfp1 #define titan_dsc$v_c3cfp1 titan_dsc$r_bits.titan_dsc$v_c3cfp1 #define titan_dsc$v_p1p1 titan_dsc$r_bits.titan_dsc$v_p1p1 #define titan_dsc$v_rsvd_1 titan_dsc$r_bits.titan_dsc$v_rsvd_1 #define titan_dsc$v_bc2 titan_dsc$r_bits.titan_dsc$v_bc2 #define titan_dsc$v_c0cfp2 titan_dsc$r_bits.titan_dsc$v_c0cfp2 #define titan_dsc$v_c1cfp2 titan_dsc$r_bits.titan_dsc$v_c1cfp2 #define titan_dsc$v_c2cfp2 titan_dsc$r_bits.titan_dsc$v_c2cfp2 #define titan_dsc$v_c3cfp2 titan_dsc$r_bits.titan_dsc$v_c3cfp2 #define titan_dsc$v_p1p2 titan_dsc$r_bits.titan_dsc$v_p1p2 #define titan_dsc$v_rsvd_2 titan_dsc$r_bits.titan_dsc$v_rsvd_2 #define titan_dsc$v_bc3 titan_dsc$r_bits.titan_dsc$v_bc3 #define titan_dsc$v_c0cfp3 titan_dsc$r_bits.titan_dsc$v_c0cfp3 #define titan_dsc$v_c1cfp3 titan_dsc$r_bits.titan_dsc$v_c1cfp3 #define titan_dsc$v_c2cfp3 titan_dsc$r_bits.titan_dsc$v_c2cfp3 #define titan_dsc$v_c3cfp3 titan_dsc$r_bits.titan_dsc$v_c3cfp3 #define titan_dsc$v_p1p3 titan_dsc$r_bits.titan_dsc$v_p1p3 #define titan_dsc$v_rsvd_3 titan_dsc$r_bits.titan_dsc$v_rsvd_3 #define titan_dsc$v_bc4 titan_dsc$r_bits.titan_dsc$v_bc4 #define titan_dsc$v_c0cfp4 titan_dsc$r_bits.titan_dsc$v_c0cfp4 #define titan_dsc$v_c1cfp4 titan_dsc$r_bits.titan_dsc$v_c1cfp4 #define titan_dsc$v_c2cfp4 titan_dsc$r_bits.titan_dsc$v_c2cfp4 #define titan_dsc$v_c3cfp4 titan_dsc$r_bits.titan_dsc$v_c3cfp4 #define titan_dsc$v_p1p4 titan_dsc$r_bits.titan_dsc$v_p1p4 #define titan_dsc$v_rsvd_4 titan_dsc$r_bits.titan_dsc$v_rsvd_4 #define titan_dsc$v_bc15 titan_dsc$r_bits.titan_dsc$v_bc15 #define titan_dsc$v_c0cfp5 titan_dsc$r_bits.titan_dsc$v_c0cfp5 #define titan_dsc$v_c1cfp5 titan_dsc$r_bits.titan_dsc$v_c1cfp5 #define titan_dsc$v_c2cfp5 titan_dsc$r_bits.titan_dsc$v_c2cfp5 #define titan_dsc$v_c3cfp5 titan_dsc$r_bits.titan_dsc$v_c3cfp5 #define titan_dsc$v_p1p5 titan_dsc$r_bits.titan_dsc$v_p1p5 #define titan_dsc$v_rsvd_5 titan_dsc$r_bits.titan_dsc$v_rsvd_5 #define titan_dsc$v_bc6 titan_dsc$r_bits.titan_dsc$v_bc6 #define titan_dsc$v_c0cfp6 titan_dsc$r_bits.titan_dsc$v_c0cfp6 #define titan_dsc$v_c1cfp6 titan_dsc$r_bits.titan_dsc$v_c1cfp6 #define titan_dsc$v_c2cfp6 titan_dsc$r_bits.titan_dsc$v_c2cfp6 #define titan_dsc$v_c3cfp6 titan_dsc$r_bits.titan_dsc$v_c3cfp6 #define titan_dsc$v_p1p6 titan_dsc$r_bits.titan_dsc$v_p1p6 #define titan_dsc$v_rsvd_6 titan_dsc$r_bits.titan_dsc$v_rsvd_6 #define titan_dsc$v_bc7 titan_dsc$r_bits.titan_dsc$v_bc7 #define titan_dsc$v_c0cfp7 titan_dsc$r_bits.titan_dsc$v_c0cfp7 #define titan_dsc$v_c1cfp7 titan_dsc$r_bits.titan_dsc$v_c1cfp7 #define titan_dsc$v_c2cfp7 titan_dsc$r_bits.titan_dsc$v_c2cfp7 #define titan_dsc$v_c3cfp7 titan_dsc$r_bits.titan_dsc$v_c3cfp7 #define titan_dsc$v_p1p7 titan_dsc$r_bits.titan_dsc$v_p1p7 #define titan_dsc$v_rsvd_7 titan_dsc$r_bits.titan_dsc$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan STR - D-Chip System Timing Register */ /* */ #define TITAN_STR$M_AW 0x1 #define TITAN_STR$M_IDDR 0xE #define TITAN_STR$M_IDDW 0x30 #define TITAN_STR$M_RSVD_0 0xC0 #define TITAN_STR$M_AW1 0x100 #define TITAN_STR$M_IDDR1 0xE00 #define TITAN_STR$M_IDDW1 0x3000 #define TITAN_STR$M_RSVD_1 0xC000 #define TITAN_STR$M_AW2 0x10000 #define TITAN_STR$M_IDDR2 0xE0000 #define TITAN_STR$M_IDDW2 0x300000 #define TITAN_STR$M_RSVD_2 0xC00000 #define TITAN_STR$M_AW3 0x1000000 #define TITAN_STR$M_IDDR3 0xE000000 #define TITAN_STR$M_IDDW3 0x30000000 #define TITAN_STR$M_RSVD_3 0xC0000000 #define TITAN_STR$M_AW4 0x100000000 #define TITAN_STR$M_IDDR4 0xE00000000 #define TITAN_STR$M_IDDW4 0x3000000000 #define TITAN_STR$M_RSVD_4 0xC000000000 #define TITAN_STR$M_AW5 0x10000000000 #define TITAN_STR$M_IDDR5 0xE0000000000 #define TITAN_STR$M_IDDW5 0x300000000000 #define TITAN_STR$M_RSVD_5 0xC00000000000 #define TITAN_STR$M_AW6 0x1000000000000 #define TITAN_STR$M_IDDR6 0xE000000000000 #define TITAN_STR$M_IDDW6 0x30000000000000 #define TITAN_STR$M_RSVD_6 0xC0000000000000 #define TITAN_STR$M_AW7 0x100000000000000 #define TITAN_STR$M_IDDR7 0xE00000000000000 #define TITAN_STR$M_IDDW7 0x3000000000000000 #define TITAN_STR$M_RSVD_7 0xC000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_str { #pragma __nomember_alignment unsigned __int64 titan_str$iq_data; __struct { unsigned int titan_str$il_l; unsigned int titan_str$il_h; } titan_str$r_longwords; __struct { unsigned titan_str$v_aw : 1; /* 0 Array Width */ unsigned titan_str$v_iddr : 3; /* 3:1 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw : 2; /* 5:4 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_0 : 2; /* 7:6 reserved */ /* */ unsigned titan_str$v_aw1 : 1; /* 8 Array Width */ unsigned titan_str$v_iddr1 : 3; /* 11:9 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw1 : 2; /* 13:12 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_1 : 2; /* 15:14 reserved */ /* */ unsigned titan_str$v_aw2 : 1; /* 16 Array Width */ unsigned titan_str$v_iddr2 : 3; /* 19:17 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw2 : 2; /* 21:20 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_2 : 2; /* 23:22 reserved */ /* */ unsigned titan_str$v_aw3 : 1; /* 24 Array Width */ unsigned titan_str$v_iddr3 : 3; /* 27:25 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw3 : 2; /* 29:28 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_3 : 2; /* 31:30 reserved */ /* */ unsigned titan_str$v_aw4 : 1; /* 32 Array Width */ unsigned titan_str$v_iddr4 : 3; /* 35:33 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw4 : 2; /* 37:36 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_4 : 2; /* 39:38 reserved */ /* */ unsigned titan_str$v_aw5 : 1; /* 40 Array Width */ unsigned titan_str$v_iddr5 : 3; /* 43:41 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw5 : 2; /* 45:44 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_5 : 2; /* 47:46 reserved */ /* */ unsigned titan_str$v_aw6 : 1; /* 48 Array Width */ unsigned titan_str$v_iddr6 : 3; /* 51:49 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw6 : 2; /* 53:52 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_6 : 2; /* 55:54 reserved */ /* */ unsigned titan_str$v_aw7 : 1; /* 56 Array Width */ unsigned titan_str$v_iddr7 : 3; /* 59:57 Issue to Data Delay for memory reads */ unsigned titan_str$v_iddw7 : 2; /* 61:60 Issue to Data Delay for xactions other than memory reads */ unsigned titan_str$v_rsvd_7 : 2; /* 63:62 reserved */ } titan_str$r_bits; } TITAN_STR; #if !defined(__VAXC) #define titan_str$il_l titan_str$r_longwords.titan_str$il_l #define titan_str$il_h titan_str$r_longwords.titan_str$il_h #define titan_str$v_aw titan_str$r_bits.titan_str$v_aw #define titan_str$v_iddr titan_str$r_bits.titan_str$v_iddr #define titan_str$v_iddw titan_str$r_bits.titan_str$v_iddw #define titan_str$v_rsvd_0 titan_str$r_bits.titan_str$v_rsvd_0 #define titan_str$v_aw1 titan_str$r_bits.titan_str$v_aw1 #define titan_str$v_iddr1 titan_str$r_bits.titan_str$v_iddr1 #define titan_str$v_iddw1 titan_str$r_bits.titan_str$v_iddw1 #define titan_str$v_rsvd_1 titan_str$r_bits.titan_str$v_rsvd_1 #define titan_str$v_aw2 titan_str$r_bits.titan_str$v_aw2 #define titan_str$v_iddr2 titan_str$r_bits.titan_str$v_iddr2 #define titan_str$v_iddw2 titan_str$r_bits.titan_str$v_iddw2 #define titan_str$v_rsvd_2 titan_str$r_bits.titan_str$v_rsvd_2 #define titan_str$v_aw3 titan_str$r_bits.titan_str$v_aw3 #define titan_str$v_iddr3 titan_str$r_bits.titan_str$v_iddr3 #define titan_str$v_iddw3 titan_str$r_bits.titan_str$v_iddw3 #define titan_str$v_rsvd_3 titan_str$r_bits.titan_str$v_rsvd_3 #define titan_str$v_aw4 titan_str$r_bits.titan_str$v_aw4 #define titan_str$v_iddr4 titan_str$r_bits.titan_str$v_iddr4 #define titan_str$v_iddw4 titan_str$r_bits.titan_str$v_iddw4 #define titan_str$v_rsvd_4 titan_str$r_bits.titan_str$v_rsvd_4 #define titan_str$v_aw5 titan_str$r_bits.titan_str$v_aw5 #define titan_str$v_iddr5 titan_str$r_bits.titan_str$v_iddr5 #define titan_str$v_iddw5 titan_str$r_bits.titan_str$v_iddw5 #define titan_str$v_rsvd_5 titan_str$r_bits.titan_str$v_rsvd_5 #define titan_str$v_aw6 titan_str$r_bits.titan_str$v_aw6 #define titan_str$v_iddr6 titan_str$r_bits.titan_str$v_iddr6 #define titan_str$v_iddw6 titan_str$r_bits.titan_str$v_iddw6 #define titan_str$v_rsvd_6 titan_str$r_bits.titan_str$v_rsvd_6 #define titan_str$v_aw7 titan_str$r_bits.titan_str$v_aw7 #define titan_str$v_iddr7 titan_str$r_bits.titan_str$v_iddr7 #define titan_str$v_iddw7 titan_str$r_bits.titan_str$v_iddw7 #define titan_str$v_rsvd_7 titan_str$r_bits.titan_str$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan DREV - D-Chip System Configuration Register */ /* */ #define TITAN_DREV$M_REV0 0xF #define TITAN_DREV$M_RSVD_0 0xF0 #define TITAN_DREV$M_REV1 0xF00 #define TITAN_DREV$M_RSVD_1 0xF000 #define TITAN_DREV$M_REV2 0xF0000 #define TITAN_DREV$M_RSVD_2 0xF00000 #define TITAN_DREV$M_REV3 0xF000000 #define TITAN_DREV$M_RSVD_3 0xF0000000 #define TITAN_DREV$M_REV4 0xF00000000 #define TITAN_DREV$M_RSVD_4 0xF000000000 #define TITAN_DREV$M_REV5 0xF0000000000 #define TITAN_DREV$M_RSVD_5 0xF00000000000 #define TITAN_DREV$M_REV6 0xF000000000000 #define TITAN_DREV$M_RSVD_6 0xF0000000000000 #define TITAN_DREV$M_REV7 0xF00000000000000 #define TITAN_DREV$M_RSVD_7 0xF000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_drev { #pragma __nomember_alignment unsigned __int64 titan_drev$iq_data; __struct { unsigned int titan_drev$il_l; unsigned int titan_drev$il_h; } titan_drev$r_longwords; __struct { unsigned titan_drev$v_rev0 : 4; /* 3:0 D-Chip 0 Revision */ unsigned titan_drev$v_rsvd_0 : 4; /* 7:4 CPU 0 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev1 : 4; /* 11:8 D-Chip 1 Revision */ unsigned titan_drev$v_rsvd_1 : 4; /* 15:12 CPU 1 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev2 : 4; /* 19:16 D-Chip 2 Revision */ unsigned titan_drev$v_rsvd_2 : 4; /* 23:20 CPU 2 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev3 : 4; /* 27:24 D-Chip 3 Revision */ unsigned titan_drev$v_rsvd_3 : 4; /* 31:28 CPU 3 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev4 : 4; /* 35:32 D-Chip 4 Revision */ unsigned titan_drev$v_rsvd_4 : 4; /* 39:36 CPU 4 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev5 : 4; /* 43:40 D-Chip 5 Revision */ unsigned titan_drev$v_rsvd_5 : 4; /* 47:44 CPU 5 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev6 : 4; /* 51:48 D-Chip 6 Revision */ unsigned titan_drev$v_rsvd_6 : 4; /* 55:52 CPU 6 Clk Fwd Preset */ /* */ unsigned titan_drev$v_rev7 : 4; /* 59:56 D-Chip 7 Revision */ unsigned titan_drev$v_rsvd_7 : 4; /* 63:60 CPU 7 Clk Fwd Preset */ } titan_drev$r_bits; } TITAN_DREV; #if !defined(__VAXC) #define titan_drev$il_l titan_drev$r_longwords.titan_drev$il_l #define titan_drev$il_h titan_drev$r_longwords.titan_drev$il_h #define titan_drev$v_rev0 titan_drev$r_bits.titan_drev$v_rev0 #define titan_drev$v_rsvd_0 titan_drev$r_bits.titan_drev$v_rsvd_0 #define titan_drev$v_rev1 titan_drev$r_bits.titan_drev$v_rev1 #define titan_drev$v_rsvd_1 titan_drev$r_bits.titan_drev$v_rsvd_1 #define titan_drev$v_rev2 titan_drev$r_bits.titan_drev$v_rev2 #define titan_drev$v_rsvd_2 titan_drev$r_bits.titan_drev$v_rsvd_2 #define titan_drev$v_rev3 titan_drev$r_bits.titan_drev$v_rev3 #define titan_drev$v_rsvd_3 titan_drev$r_bits.titan_drev$v_rsvd_3 #define titan_drev$v_rev4 titan_drev$r_bits.titan_drev$v_rev4 #define titan_drev$v_rsvd_4 titan_drev$r_bits.titan_drev$v_rsvd_4 #define titan_drev$v_rev5 titan_drev$r_bits.titan_drev$v_rev5 #define titan_drev$v_rsvd_5 titan_drev$r_bits.titan_drev$v_rsvd_5 #define titan_drev$v_rev6 titan_drev$r_bits.titan_drev$v_rev6 #define titan_drev$v_rsvd_6 titan_drev$r_bits.titan_drev$v_rsvd_6 #define titan_drev$v_rev7 titan_drev$r_bits.titan_drev$v_rev7 #define titan_drev$v_rsvd_7 titan_drev$r_bits.titan_drev$v_rsvd_7 #endif /* #if !defined(__VAXC) */ /*========================================================================== */ /* */ /* P-Chip Registers */ /* */ /*========================================================================== */ /* */ /* */ /* Titan WSBA - P-Chip Window Space Base Address Registers */ /* */ #define TITAN_WSBA$M_ENA 0x1 #define TITAN_WSBA$M_SG 0x2 #define TITAN_WSBA$M_RSVD_0 0xFFFFC #define TITAN_WSBA$M_ADDR 0xFFF00000 #define TITAN_WSBA$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_wsba { #pragma __nomember_alignment unsigned __int64 titan_wsba$iq_data; __struct { unsigned int titan_wsba$il_l; unsigned int titan_wsba$il_h; } titan_wsba$r_longwords; __struct { unsigned titan_wsba$v_ena : 1; /* 0 Enable */ unsigned titan_wsba$v_sg : 1; /* 1 Scatter/Gather */ unsigned titan_wsba$v_rsvd_0 : 18; /* 19:2 reserved */ unsigned titan_wsba$v_addr : 12; /* 31:20 Base Address */ unsigned titan_wsba$v_rsvd_1 : 32; /* 63:32 Reserved */ } titan_wsba$r_bits; } TITAN_WSBA; #if !defined(__VAXC) #define titan_wsba$il_l titan_wsba$r_longwords.titan_wsba$il_l #define titan_wsba$il_h titan_wsba$r_longwords.titan_wsba$il_h #define titan_wsba$v_ena titan_wsba$r_bits.titan_wsba$v_ena #define titan_wsba$v_sg titan_wsba$r_bits.titan_wsba$v_sg #define titan_wsba$v_rsvd_0 titan_wsba$r_bits.titan_wsba$v_rsvd_0 #define titan_wsba$v_addr titan_wsba$r_bits.titan_wsba$v_addr #define titan_wsba$v_rsvd_1 titan_wsba$r_bits.titan_wsba$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan WSM - P-Chip Window Space Mask Registers */ /* */ #define TITAN_WSM$M_RSVD_0 0xFFFFF #define TITAN_WSM$M_AM 0xFFF00000 #define TITAN_WSM$M_RSVD_1 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_wsm { #pragma __nomember_alignment unsigned __int64 titan_wsm$iq_data; __struct { unsigned int titan_wsm$il_l; unsigned int titan_wsm$il_h; } titan_wsm$r_longwords; __struct { unsigned titan_wsm$v_rsvd_0 : 20; /* 19:0 reserved */ unsigned titan_wsm$v_am : 12; /* 31:20 Base Address */ unsigned titan_wsm$v_rsvd_1 : 32; /* 63:32 Reserved */ } titan_wsm$r_bits; } TITAN_WSM; #if !defined(__VAXC) #define titan_wsm$il_l titan_wsm$r_longwords.titan_wsm$il_l #define titan_wsm$il_h titan_wsm$r_longwords.titan_wsm$il_h #define titan_wsm$v_rsvd_0 titan_wsm$r_bits.titan_wsm$v_rsvd_0 #define titan_wsm$v_am titan_wsm$r_bits.titan_wsm$v_am #define titan_wsm$v_rsvd_1 titan_wsm$r_bits.titan_wsm$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan TBA - P-Chip Translated Base Address Registers */ /* */ #define TITAN_TBA$M_RSVD_0 0x3FF #define TITAN_TBA$M_ADDR 0x7FFFFFC00 #define TITAN_TBA$M_RSVD_1 0xFFFFFFF800000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_tba { #pragma __nomember_alignment unsigned __int64 titan_tba$iq_data; __struct { unsigned int titan_tba$il_l; unsigned int titan_tba$il_h; } titan_tba$r_longwords; __struct { unsigned titan_tba$v_rsvd_0 : 10; /* 9:0 reserved */ unsigned titan_tba$v_addr : 25; /* 34:10 Translated Base Address */ unsigned titan_tba$v_rsvd_1 : 29; /* 63:35 reserved */ } titan_tba$r_bits; } TITAN_TBA; #if !defined(__VAXC) #define titan_tba$il_l titan_tba$r_longwords.titan_tba$il_l #define titan_tba$il_h titan_tba$r_longwords.titan_tba$il_h #define titan_tba$v_rsvd_0 titan_tba$r_bits.titan_tba$v_rsvd_0 #define titan_tba$v_addr titan_tba$r_bits.titan_tba$v_addr #define titan_tba$v_rsvd_1 titan_tba$r_bits.titan_tba$v_rsvd_1 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan PCTL - P-Chip Gport Control Register */ /* */ #define TITAN_PCTL$M_FBTB 0x1 #define TITAN_PCTL$M_THDIS 0x2 #define TITAN_PCTL$M_CHAINDIS 0x4 #define TITAN_PCTL$M_TGTLAT 0x18 #define TITAN_PCTL$M_HOLE 0x20 #define TITAN_PCTL$M_MWIN 0x40 #define TITAN_PCTL$M_ARBENA 0x80 #define TITAN_PCTL$M_PRIGRP 0xFF00 #define TITAN_PCTL$M_PPRI 0x10000 #define TITAN_PCTL$M_PCISPD66 0x20000 #define TITAN_PCTL$M_CNGSTLT 0x3C0000 #define TITAN_PCTL$M_PTPDESTEN 0x3FC00000 #define TITAN_PCTL$M_DPCEN 0x40000000 #define TITAN_PCTL$M_APCEN 0x80000000 #define TITAN_PCTL$M_DCRTV 0x300000000 #define TITAN_PCTL$M_EN_STEPPING 0x400000000 #define TITAN_PCTL$M_AGP_RATE 0x30000000000000 #define TITAN_PCTL$M_AGP_SBA_ENABLE 0x40000000000000 #define TITAN_PCTL$M_AGP_ENABLE 0x80000000000000 #define TITAN_PCTL$M_AGP_PRESENT 0x200000000000000 #define TITAN_PCTL$M_AGP_HP_RD 0x1C00000000000000 #define TITAN_PCTL$M_AGP_LP_RD 0xE000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_pctl { #pragma __nomember_alignment unsigned __int64 titan_pctl$iq_data; __struct { unsigned int titan_pctl$il_l; unsigned int titan_pctl$il_h; } titan_pctl$r_longwords; __struct { unsigned titan_pctl$v_fbtb : 1; /* 0 Fast Back-To-Back enable */ unsigned titan_pctl$v_thdis : 1; /* 1 Disable anti-Thrash mechanism for TLB */ unsigned titan_pctl$v_chaindis : 1; /* 2 Disable Chaining */ unsigned titan_pctl$v_tgtlat : 2; /* 4:3 Target Latency Timers timers enable */ unsigned titan_pctl$v_hole : 1; /* 5 512K to 1M window Hole enable */ unsigned titan_pctl$v_mwin : 1; /* 6 Monster Window enable */ unsigned titan_pctl$v_arbena : 1; /* 7 internal Arbiter Enable */ unsigned titan_pctl$v_prigrp : 8; /* 15:8 arbiter Priority Group */ unsigned titan_pctl$v_ppri : 1; /* 16 arbiter Priority Group for the Pchip itself */ unsigned titan_pctl$v_pcispd66 : 1; /* 17 A '1' indicates GPCI frequency is 66 MHz */ unsigned titan_pctl$v_cngstlt : 4; /* 21:18 GPCI congestion limit */ unsigned titan_pctl$v_ptpdesten : 8; /* 29:22 Bit mask enables legal PTP transactions */ unsigned titan_pctl$v_dpcen : 1; /* 30 set to '1' enables checking parity on PCI data xfers */ unsigned titan_pctl$v_apcen : 1; /* 31 set to '1' enables checking parity during address command cycles */ /* */ unsigned titan_pctl$v_dcrtv : 2; /* 33:32 contols value of delayed completion retry timer */ unsigned titan_pctl$v_en_stepping : 1; /* 34 enables address stepping on the PCI during config cycles */ unsigned titan_pctl$v_rsvd_1 : 17; /* 51:35 Reserved */ unsigned titan_pctl$v_agp_rate : 2; /* AGP RATE 1X, 2X, 4X */ unsigned titan_pctl$v_agp_sba_enable : 1; /* AGP SBA ENABLE */ unsigned titan_pctl$v_agp_enable : 1; /* AGP ENABLE */ unsigned titan_pctl$v_rsvd_2 : 1; /* RESERVED FIELD */ unsigned titan_pctl$v_agp_present : 1; /* AGP PRESENT */ unsigned titan_pctl$v_agp_hp_rd : 3; /* AGP HIGH PRIORITY READ DE */ unsigned titan_pctl$v_agp_lp_rd : 3; /* AGP LOW PRIORITY READ DEP */ } titan_pctl$r_bits; } TITAN_PCTL; #if !defined(__VAXC) #define titan_pctl$il_l titan_pctl$r_longwords.titan_pctl$il_l #define titan_pctl$il_h titan_pctl$r_longwords.titan_pctl$il_h #define titan_pctl$v_fbtb titan_pctl$r_bits.titan_pctl$v_fbtb #define titan_pctl$v_thdis titan_pctl$r_bits.titan_pctl$v_thdis #define titan_pctl$v_chaindis titan_pctl$r_bits.titan_pctl$v_chaindis #define titan_pctl$v_tgtlat titan_pctl$r_bits.titan_pctl$v_tgtlat #define titan_pctl$v_hole titan_pctl$r_bits.titan_pctl$v_hole #define titan_pctl$v_mwin titan_pctl$r_bits.titan_pctl$v_mwin #define titan_pctl$v_arbena titan_pctl$r_bits.titan_pctl$v_arbena #define titan_pctl$v_prigrp titan_pctl$r_bits.titan_pctl$v_prigrp #define titan_pctl$v_ppri titan_pctl$r_bits.titan_pctl$v_ppri #define titan_pctl$v_pcispd66 titan_pctl$r_bits.titan_pctl$v_pcispd66 #define titan_pctl$v_cngstlt titan_pctl$r_bits.titan_pctl$v_cngstlt #define titan_pctl$v_ptpdesten titan_pctl$r_bits.titan_pctl$v_ptpdesten #define titan_pctl$v_dpcen titan_pctl$r_bits.titan_pctl$v_dpcen #define titan_pctl$v_apcen titan_pctl$r_bits.titan_pctl$v_apcen #define titan_pctl$v_dcrtv titan_pctl$r_bits.titan_pctl$v_dcrtv #define titan_pctl$v_en_stepping titan_pctl$r_bits.titan_pctl$v_en_stepping #define titan_pctl$v_rsvd_1 titan_pctl$r_bits.titan_pctl$v_rsvd_1 #define titan_pctl$v_agp_rate titan_pctl$r_bits.titan_pctl$v_agp_rate #define titan_pctl$v_agp_sba_enable titan_pctl$r_bits.titan_pctl$v_agp_sba_enable #define titan_pctl$v_agp_enable titan_pctl$r_bits.titan_pctl$v_agp_enable #define titan_pctl$v_rsvd_2 titan_pctl$r_bits.titan_pctl$v_rsvd_2 #define titan_pctl$v_agp_present titan_pctl$r_bits.titan_pctl$v_agp_present #define titan_pctl$v_agp_hp_rd titan_pctl$r_bits.titan_pctl$v_agp_hp_rd #define titan_pctl$v_agp_lp_rd titan_pctl$r_bits.titan_pctl$v_agp_lp_rd #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan PLAT - P-Chip Master Latency Register */ /* */ #define TITAN_PLAT$M_RSVD_0 0xFF #define TITAN_PLAT$M_LAT 0xFF00 #define TITAN_PLAT$M_RSVD_1 0xFFFF0000 #define TITAN_PLAT$M_RSVD_2 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_plat { #pragma __nomember_alignment unsigned __int64 titan_plat$iq_data; __struct { unsigned int titan_plat$il_l; unsigned int titan_plat$il_h; } titan_plat$r_longwords; __struct { unsigned titan_plat$v_rsvd_0 : 8; /* 7:0 reserved */ unsigned titan_plat$v_lat : 8; /* 15:8 Master Latency Timer */ unsigned titan_plat$v_rsvd_1 : 16; /* 31:16 reserved */ unsigned titan_plat$v_rsvd_2 : 32; /* 63:32 reserved */ } titan_plat$r_bits; } TITAN_PLAT; #if !defined(__VAXC) #define titan_plat$il_l titan_plat$r_longwords.titan_plat$il_l #define titan_plat$il_h titan_plat$r_longwords.titan_plat$il_h #define titan_plat$v_rsvd_0 titan_plat$r_bits.titan_plat$v_rsvd_0 #define titan_plat$v_lat titan_plat$r_bits.titan_plat$v_lat #define titan_plat$v_rsvd_1 titan_plat$r_bits.titan_plat$v_rsvd_1 #define titan_plat$v_rsvd_2 titan_plat$r_bits.titan_plat$v_rsvd_2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan PERROR - P-Chip Error Register */ /* */ #define TITAN_PERROR$M_LOST 0x1 #define TITAN_PERROR$M_SERR 0x2 #define TITAN_PERROR$M_PERR 0x4 #define TITAN_PERROR$M_DCRTO 0x8 #define TITAN_PERROR$M_SGE 0x10 #define TITAN_PERROR$M_APE 0x20 #define TITAN_PERROR$M_TA 0x40 #define TITAN_PERROR$M_DPE 0x80 #define TITAN_PERROR$M_NDS 0x100 #define TITAN_PERROR$M_IPTPR 0x200 #define TITAN_PERROR$M_IPTPW 0x400 #define TITAN_PERROR$M_RSVD_0 0x3800 #define TITAN_PERROR$M_ADDR 0x3FFFFFFFC000 #define TITAN_PERROR$M_DAC 0x400000000000 #define TITAN_PERROR$M_MWIN 0x800000000000 #define TITAN_PERROR$M_RSVD_1 0x7000000000000 #define TITAN_PERROR$M_CMD 0x78000000000000 #define TITAN_PERROR$M_RSVD_2 0x7F80000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_perror { #pragma __nomember_alignment unsigned __int64 titan_perror$iq_data; __struct { unsigned int titan_perror$il_l; unsigned int titan_perror$il_h; } titan_perror$r_longwords; __struct { unsigned titan_perror$v_lost : 1; /* 0 Lost an error */ unsigned titan_perror$v_serr : 1; /* 1 SERR# sampled asserted */ unsigned titan_perror$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */ unsigned titan_perror$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */ unsigned titan_perror$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */ unsigned titan_perror$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */ unsigned titan_perror$v_ta : 1; /* 6 Targed Abort as PCI master */ unsigned titan_perror$v_dpe : 1; /* 7 PCI Read Data Parity Error as PCI master */ unsigned titan_perror$v_nds : 1; /* 8 No DevSel as PCI master */ unsigned titan_perror$v_iptpr : 1; /* 9 Invalid Peer-to-peer write */ unsigned titan_perror$v_iptpw : 1; /* 10 Invalid Peep-to-peer read */ unsigned titan_perror$v_rsvd_0 : 3; /* 13:11 reserved */ unsigned titan_perror$v_addr : 32; /* 46:14 contain longword PCI address */ unsigned titan_perror$v_dac : 1; /* 47 Erroneous DAC */ unsigned titan_perror$v_mwin : 1; /* 48 Erroneous access to Monster Window */ unsigned titan_perror$v_rsvd_1 : 3; /* 51:49 Rreserved */ unsigned titan_perror$v_cmd : 4; /* 55:52 PCI Command on error */ unsigned titan_perror$v_rsvd_2 : 8; /* 63:56 Reserved */ unsigned titan_perror$v_fill_1_ : 1; } titan_perror$r_bits; } TITAN_PERROR; #if !defined(__VAXC) #define titan_perror$il_l titan_perror$r_longwords.titan_perror$il_l #define titan_perror$il_h titan_perror$r_longwords.titan_perror$il_h #define titan_perror$v_lost titan_perror$r_bits.titan_perror$v_lost #define titan_perror$v_serr titan_perror$r_bits.titan_perror$v_serr #define titan_perror$v_perr titan_perror$r_bits.titan_perror$v_perr #define titan_perror$v_dcrto titan_perror$r_bits.titan_perror$v_dcrto #define titan_perror$v_sge titan_perror$r_bits.titan_perror$v_sge #define titan_perror$v_ape titan_perror$r_bits.titan_perror$v_ape #define titan_perror$v_ta titan_perror$r_bits.titan_perror$v_ta #define titan_perror$v_dpe titan_perror$r_bits.titan_perror$v_dpe #define titan_perror$v_nds titan_perror$r_bits.titan_perror$v_nds #define titan_perror$v_iptpr titan_perror$r_bits.titan_perror$v_iptpr #define titan_perror$v_iptpw titan_perror$r_bits.titan_perror$v_iptpw #define titan_perror$v_rsvd_0 titan_perror$r_bits.titan_perror$v_rsvd_0 #define titan_perror$v_addr titan_perror$r_bits.titan_perror$v_addr #define titan_perror$v_dac titan_perror$r_bits.titan_perror$v_dac #define titan_perror$v_mwin titan_perror$r_bits.titan_perror$v_mwin #define titan_perror$v_rsvd_1 titan_perror$r_bits.titan_perror$v_rsvd_1 #define titan_perror$v_cmd titan_perror$r_bits.titan_perror$v_cmd #define titan_perror$v_rsvd_2 titan_perror$r_bits.titan_perror$v_rsvd_2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan PERREN - P-Chip Error Enable Register */ /* */ #define TITAN_PERREN$M_RSVD_O 0x1 #define TITAN_PERREN$M_SERR 0x2 #define TITAN_PERREN$M_PERR 0x4 #define TITAN_PERREN$M_DCRTO 0x8 #define TITAN_PERREN$M_SGE 0x10 #define TITAN_PERREN$M_APE 0x20 #define TITAN_PERREN$M_TA 0x40 #define TITAN_PERREN$M_DPE 0x80 #define TITAN_PERREN$M_NDS 0x100 #define TITAN_PERREN$M_IPTPR 0x200 #define TITAN_PERREN$M_IPTPW 0x400 #define TITAN_PERREN$M_RSVD_1 0xFFFFF800 #define TITAN_PERREN$M_RSVD_2 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_perren { #pragma __nomember_alignment unsigned __int64 titan_perren$iq_data; __struct { unsigned int titan_perren$il_l; unsigned int titan_perren$il_h; } titan_perren$r_longwords; __struct { unsigned titan_perren$v_rsvd_o : 1; /* 0 Reserved */ unsigned titan_perren$v_serr : 1; /* 1 Enable logging of SERR */ unsigned titan_perren$v_perr : 1; /* 2 Enable logging of PERR */ unsigned titan_perren$v_dcrto : 1; /* 3 Enable logging of DCRTO */ unsigned titan_perren$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */ unsigned titan_perren$v_ape : 1; /* 5 Enable detection of Address Parity Error */ unsigned titan_perren$v_ta : 1; /* 6 Enable logging of Targed Abort */ unsigned titan_perren$v_dpe : 1; /* 7 Enable detection of parity errors on the PCI */ unsigned titan_perren$v_nds : 1; /* 8 Enable logging of "No DevSel as PCI master"' */ unsigned titan_perren$v_iptpr : 1; /* 9 Enable logging of IPTPR if this bit set */ unsigned titan_perren$v_iptpw : 1; /* 10 Enable logging of IPTPW if this bit set */ unsigned titan_perren$v_rsvd_1 : 21; /* 31:11 reserved */ unsigned titan_perren$v_rsvd_2 : 32; /* 63:32 Reserved */ } titan_perren$r_bits; } TITAN_PERREN; #if !defined(__VAXC) #define titan_perren$il_l titan_perren$r_longwords.titan_perren$il_l #define titan_perren$il_h titan_perren$r_longwords.titan_perren$il_h #define titan_perren$v_rsvd_o titan_perren$r_bits.titan_perren$v_rsvd_o #define titan_perren$v_serr titan_perren$r_bits.titan_perren$v_serr #define titan_perren$v_perr titan_perren$r_bits.titan_perren$v_perr #define titan_perren$v_dcrto titan_perren$r_bits.titan_perren$v_dcrto #define titan_perren$v_sge titan_perren$r_bits.titan_perren$v_sge #define titan_perren$v_ape titan_perren$r_bits.titan_perren$v_ape #define titan_perren$v_ta titan_perren$r_bits.titan_perren$v_ta #define titan_perren$v_dpe titan_perren$r_bits.titan_perren$v_dpe #define titan_perren$v_nds titan_perren$r_bits.titan_perren$v_nds #define titan_perren$v_iptpr titan_perren$r_bits.titan_perren$v_iptpr #define titan_perren$v_iptpw titan_perren$r_bits.titan_perren$v_iptpw #define titan_perren$v_rsvd_1 titan_perren$r_bits.titan_perren$v_rsvd_1 #define titan_perren$v_rsvd_2 titan_perren$r_bits.titan_perren$v_rsvd_2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */ /* */ #define TITAN_TLBIV$M_RSVD_0 0xF #define TITAN_TLBIV$M_ADDR 0xFFFF0 #define TITAN_TLBIV$M_RSVD_1 0xFFF00000 #define TITAN_TLBIV$M_RSVD_2 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_tlbiv { #pragma __nomember_alignment unsigned __int64 titan_tlbiv$iq_data; __struct { unsigned int titan_tlbiv$il_l; unsigned int titan_tlbiv$il_h; } titan_tlbiv$r_longwords; __struct { unsigned titan_tlbiv$v_rsvd_0 : 4; /* 3:0 reserved */ unsigned titan_tlbiv$v_addr : 16; /* 19:4 invalidate if matches PCI addr<31:16> */ unsigned titan_tlbiv$v_rsvd_1 : 12; /* 31:20 reserved */ unsigned titan_tlbiv$v_rsvd_2 : 32; /* 63:32 reserved */ } titan_tlbiv$r_bits; } TITAN_TLBIV; #if !defined(__VAXC) #define titan_tlbiv$il_l titan_tlbiv$r_longwords.titan_tlbiv$il_l #define titan_tlbiv$il_h titan_tlbiv$r_longwords.titan_tlbiv$il_h #define titan_tlbiv$v_rsvd_0 titan_tlbiv$r_bits.titan_tlbiv$v_rsvd_0 #define titan_tlbiv$v_addr titan_tlbiv$r_bits.titan_tlbiv$v_addr #define titan_tlbiv$v_rsvd_1 titan_tlbiv$r_bits.titan_tlbiv$v_rsvd_1 #define titan_tlbiv$v_rsvd_2 titan_tlbiv$r_bits.titan_tlbiv$v_rsvd_2 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* Titan TLBIA - P-Chip Translation Buffer Invalidate all Register */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _titan_tlbia { #pragma __nomember_alignment unsigned __int64 titan_tlbia$iq_data; __struct { unsigned int titan_tlbia$il_l; unsigned int titan_tlbia$il_h; } titan_tlbia$r_longwords; } TITAN_TLBIA; #if !defined(__VAXC) #define titan_tlbia$il_l titan_tlbia$r_longwords.titan_tlbia$il_l #define titan_tlbia$il_h titan_tlbia$r_longwords.titan_tlbia$il_h #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __TITANDEF_LOADED */