/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:53 by OpenVMS SDL EV3-3 */ /* Source: 16-MAY-2006 22:21:09 $1$DGA7274:[LIB_H.SRC]T10DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $T10DEF IDENT X-4 ***/ #ifndef __T10DEF_LOADED #define __T10DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define SCSI$C_OCRW 15 #define SCSI$C_BE 17 #define SCSI$C_OSD 17 #define SCSI$C_ADI 18 #define SCSI$C_WLU 30 #define SCSI$C_MAXCDB 16 #define SCSI$K_MAXCDB 16 struct scsidef1 { unsigned int scsi$l_scsidef_sdl_pacifier; } ; #define DQ$K_DQ_OPCODE 1 #define DQ$K_DQ_FLAGS 0 #define DQ$M_DQ_READ 1 struct dqcmd { unsigned int dq$l_dq_opcode; unsigned int dq$l_dq_flags; void *dq$a_dq_cmdadr; unsigned int dq$l_dq_cmdlen; void *dq$a_dq_datadr; unsigned int dq$l_dq_datlen; unsigned int dq$l_dq_padlen; unsigned int dq$l_dq_phasetmo; unsigned int dq$l_dq_discontmo; unsigned int dq$l_dq_res_1; unsigned int dq$l_dq_res_2; unsigned int dq$l_dq_res_3; unsigned int dq$l_dq_res_4; unsigned int dq$l_dq_res_5; unsigned int dq$l_dq_res_6; } ; struct txc00 { unsigned char t10$b_txc00_opcode; unsigned char t10$b_txc00_rsvd1; unsigned char t10$b_txc00_rsvd2; unsigned char t10$b_txc00_rsvd3; unsigned char t10$b_txc00_rsvd4; unsigned char t10$b_txc00_control; } ; struct txc03 { unsigned char t10$b_txc03_opcode; unsigned char t10$b_txc03_rsvd1; unsigned char t10$b_txc03_rsvd2; unsigned char t10$b_txc03_rsvd3; unsigned char t10$b_txc03_length; unsigned char t10$b_txc03_control; } ; #define T10$K_SKEY_NOSENS 0 #define T10$K_SKEY_FIXERR 1 #define T10$K_SKEY_NOTRDY 2 #define T10$K_SKEY_MEDERR 3 #define T10$K_SKEY_HDWERR 4 #define T10$K_SKEY_ILLREQ 5 #define T10$K_SKEY_UNITAT 6 #define T10$K_SKEY_DATPRT 7 #define T10$K_SKEY_BLKCHK 8 #define T10$K_SKEY_VENDOR 9 #define T10$K_SKEY_RSVD 10 #define T10$K_SKEY_CMDABT 11 struct txr03 { __struct { unsigned t10$v_txr03_code : 7; unsigned t10$v_txr03_valid : 1; } t10$r_txr03s_code; unsigned char t10$b_txr03_obsolete; __struct { unsigned t10$v_txr03_skey : 4; unsigned t10$v_txr03_rsvd4 : 1; unsigned t10$v_txr03_ili : 1; unsigned t10$v_txr03_eom : 1; unsigned t10$v_txr03_filemark : 1; } t10$r_txr03s_skey; unsigned int t10$l_txr03_info; unsigned char t10$b_txr03_addlen; unsigned int t10$l_txr03_cmdinfo; unsigned char t10$b_txr03_asc; unsigned char t10$b_txr03_ascq; unsigned char t10$b_txr03_fru; unsigned char t10$b_txr03_junque [3]; } ; #if !defined(__VAXC) #define t10$v_txr03_code t10$r_txr03s_code.t10$v_txr03_code #define t10$v_txr03_valid t10$r_txr03s_code.t10$v_txr03_valid #define t10$v_txr03_skey t10$r_txr03s_skey.t10$v_txr03_skey #define t10$v_txr03_ili t10$r_txr03s_skey.t10$v_txr03_ili #define t10$v_txr03_eom t10$r_txr03s_skey.t10$v_txr03_eom #define t10$v_txr03_filemark t10$r_txr03s_skey.t10$v_txr03_filemark #endif /* #if !defined(__VAXC) */ #define T10$K_TXC04_PLFMT_LEGACY 7 #define T10$K_TXC04_PLFMT_CURRENT 1 struct txc04 { unsigned char t10$b_txc04_opcode; __struct { unsigned t10$v_txc04_format_code : 3; unsigned t10$v_txc04_cmplst : 1; unsigned t10$v_txc04_fmtdata : 1; unsigned t10$v_txc04_flags_fill : 3; } t10$r_txc04_flags; unsigned char t10$b_txc04_reserved; unsigned short int t10$w_txc04_interleave; unsigned char t10$b_txc04_control; } ; #if !defined(__VAXC) #define t10$v_txc04_format_code t10$r_txc04_flags.t10$v_txc04_format_code #define t10$v_txc04_cmplst t10$r_txc04_flags.t10$v_txc04_cmplst #define t10$v_txc04_fmtdata t10$r_txc04_flags.t10$v_txc04_fmtdata #endif /* #if !defined(__VAXC) */ #define T10$K_TXP04_FIXED 4 struct txp04 { unsigned char t10$b_txp04_fill0; __struct { unsigned t10$v_txp04_vs : 1; unsigned t10$v_txp04_immed : 1; unsigned t10$v_txp04_tryout : 1; unsigned t10$v_txp04_ip : 1; unsigned t10$v_txp04_stpf : 1; unsigned t10$v_txp04_dcrt : 1; unsigned t10$v_txp04_dpry : 1; unsigned t10$v_txp04_fov : 1; } t10$r_txp04_flags; unsigned short int t10$w_txp04_length; } ; #if !defined(__VAXC) #define t10$v_txp04_vs t10$r_txp04_flags.t10$v_txp04_vs #define t10$v_txp04_immed t10$r_txp04_flags.t10$v_txp04_immed #define t10$v_txp04_tryout t10$r_txp04_flags.t10$v_txp04_tryout #define t10$v_txp04_ip t10$r_txp04_flags.t10$v_txp04_ip #define t10$v_txp04_stpf t10$r_txp04_flags.t10$v_txp04_stpf #define t10$v_txp04_dcrt t10$r_txp04_flags.t10$v_txp04_dcrt #define t10$v_txp04_dpry t10$r_txp04_flags.t10$v_txp04_dpry #define t10$v_txp04_fov t10$r_txp04_flags.t10$v_txp04_fov #endif /* #if !defined(__VAXC) */ #define T10$K_TXP04IP_NO_HEADER 0 #define T10$K_TXP04IP_LBA_LOG 1 #define T10$K_TXP04IP_LBA_PHY 2 struct txp04ip { __struct { unsigned t10$v_txp04ip_fill1 : 5; unsigned t10$v_txp04ip_si : 1; unsigned t10$v_txp04ip_ip_modifier : 2; } t10$r_txp04ip_flags; unsigned char t10$b_txp04ip_pattern_type; unsigned short int t10$w_txp04ip_pattern_length; unsigned char t10$x_txp04ip_pattern; } ; #if !defined(__VAXC) #define t10$v_txp04ip_si t10$r_txp04ip_flags.t10$v_txp04ip_si #define t10$v_txp04ip_ip_modifier t10$r_txp04ip_flags.t10$v_txp04ip_ip_modifier #endif /* #if !defined(__VAXC) */ #define T10$K_TXP04FC111_FDLEN 4 #define T10$K_TXP04FC111_LENGTH 8 #define T10$K_TXP04FC001_MAXBLOCKS -1 #define T10$K_TXP04FC001_RWFULL 0 #define T10$K_TXP04FC001_MRWFULL 16 #define T10$K_TXP04FC001_PRWFULL 38 #define T10$K_TXP04FC001_FDLEN 4 #define T10$K_TXP04FC001_LENGTH 8 struct txp04fd { __union { __struct { __struct { unsigned t10$v_txp04fc111_flags_fill1 : 6; unsigned t10$v_txp04fc111_grow : 1; unsigned t10$v_txp04fc111_sess : 1; } t10$r_txp04fc111_flags; unsigned char t10$b_txp04fc111_fill1; unsigned char t10$b_txp04fc111_fill2; unsigned char t10$b_txp04fc111_fill3; unsigned int t10$l_txp04fc111_format_size; } t10$r_txp04fc111; __struct { unsigned int t10$l_txp04fc001_blocks; __struct { unsigned t10$v_txp04fc001_flags_fill1 : 2; unsigned t10$v_txp04fc001_fmttyp : 6; } t10$r_txp04fc001_flags; __union { __struct { unsigned char t10$b_txp04fc001ft00_fill0; unsigned char t10$b_txp04fc001ft00_fill1; unsigned char t10$b_txp04fc001ft00_fill2; } t10$r_txp04fc001ft00; __struct { unsigned char t10$b_txp04fc001ft26_fill0; unsigned char t10$b_txp04fc001ft26_fill1; __struct { unsigned t10$v_txp04fc001ft26_rst : 1; unsigned t10$v_txp04fc001ft26_qst : 1; unsigned t10$v_txp04fc001ft26_fill : 6; } t10$r_txp04fc001ft26_flags; } t10$r_txp04fc001ft26; } t10$r_txp04fc001ftovl; } t10$r_txp04fc001; } t10$r_txp04_fcoverlay; } ; #if !defined(__VAXC) #define t10$r_txp04fc111 t10$r_txp04_fcoverlay.t10$r_txp04fc111 #define t10$r_txp04fc111_flags t10$r_txp04fc111.t10$r_txp04fc111_flags #define t10$v_txp04fc111_grow t10$r_txp04fc111_flags.t10$v_txp04fc111_grow #define t10$v_txp04fc111_sess t10$r_txp04fc111_flags.t10$v_txp04fc111_sess #define t10$b_txp04fc111_fill1 t10$r_txp04fc111.t10$b_txp04fc111_fill1 #define t10$b_txp04fc111_fill2 t10$r_txp04fc111.t10$b_txp04fc111_fill2 #define t10$b_txp04fc111_fill3 t10$r_txp04fc111.t10$b_txp04fc111_fill3 #define t10$l_txp04fc111_format_size t10$r_txp04fc111.t10$l_txp04fc111_format_size #define t10$r_txp04fc001 t10$r_txp04_fcoverlay.t10$r_txp04fc001 #define t10$l_txp04fc001_blocks t10$r_txp04fc001.t10$l_txp04fc001_blocks #define t10$r_txp04fc001_flags t10$r_txp04fc001.t10$r_txp04fc001_flags #define t10$v_txp04fc001_fmttyp t10$r_txp04fc001_flags.t10$v_txp04fc001_fmttyp #define t10$r_txp04fc001ft00 t10$r_txp04fc001.t10$r_txp04fc001ftovl.t10$r_txp04fc001ft00 #define t10$r_txp04fc001ft26 t10$r_txp04fc001.t10$r_txp04fc001ftovl.t10$r_txp04fc001ft26 #define t10$r_txp04fc001ft26_flags t10$r_txp04fc001ft26.t10$r_txp04fc001ft26_flags #define t10$v_txp04fc001ft26_rst t10$r_txp04fc001ft26_flags.t10$v_txp04fc001ft26_rst #define t10$v_txp04fc001ft26_qst t10$r_txp04fc001ft26_flags.t10$v_txp04fc001ft26_qst #endif /* #if !defined(__VAXC) */ struct txc08 { unsigned char t10$b_txc08_opcode; __struct { unsigned t10$v_txc08_lba1 : 5; unsigned t10$v_txc08_fill1 : 3; } t10$r_txc08_lba; unsigned short int t10$w_txc08_lba; unsigned char t10$b_txc08_blocks; unsigned char t10$b_txc08_control; } ; #if !defined(__VAXC) #define t10$v_txc08_lba1 t10$r_txc08_lba.t10$v_txc08_lba1 #endif /* #if !defined(__VAXC) */ #define T10$K_VPD_SUPPORTED 0 #define T10$K_VPD_SERIAL 128 struct txc12 { unsigned char t10$b_txc12_opcode; __struct { unsigned t10$v_txc12_evpd : 1; unsigned t10$v_txc12_cmddt : 1; unsigned t10$v_txc12_flag_fill : 6; } t10$r_txc12_flags; unsigned char t10$b_txc12_page_opcode; unsigned short int t10$w_txc12_max_length; unsigned char t10$b_txc12_control; } ; #if !defined(__VAXC) #define t10$v_txc12_evpd t10$r_txc12_flags.t10$v_txc12_evpd #define t10$v_txc12_cmddt t10$r_txc12_flags.t10$v_txc12_cmddt #endif /* #if !defined(__VAXC) */ #define T10$K_DTYP_DIRATT 0 #define T10$K_DTYP_SEQDEV 1 #define T10$K_DTYP_PRINTER 2 #define T10$K_DTYP_CPU 3 #define T10$K_DTYP_WRTONCE 4 #define T10$K_DTYP_CDROM 5 #define T10$K_DTYP_SCANNER 6 #define T10$K_DTYP_OPTICAL 7 #define T10$K_DTYP_CHANGER 8 #define T10$K_DTYP_COMMDEV 9 #define T10$K_DTYP_ASCIT8A 10 #define T10$K_DTYP_ASCIT8B 11 #define T10$K_DTYP_STORARR 12 #define T10$K_DTYP_ENCSERV 13 #define T10$K_DTYP_SDIRATT 14 #define T10$K_DTYP_CARDRDR 15 #define T10$K_DTYP_OBJDEV 16 #define T10$K_DTYP_AUTOMAT 17 #define T10$K_DTYP_WELLKNOWN 30 #define T10$K_DTYP_UNKNOWN 31 #define T10$K_DEVQ_CONNECT 0 #define T10$K_DEVQ_DISCONN 1 #define T10$K_DEVQ_RSVD010 2 #define T10$K_DEVQ_NOPHYDEV 3 #define T10$K_DEVQ_VENDOR 4 #define T10$K_SPCVA_NOCLAIMS 0 #define T10$K_SPCVA_OBS1 1 #define T10$K_SPCVA_SCSI2 2 #define T10$K_SPCVA_SPC 3 #define T10$K_SPCVA_SPC2 4 #define T10$K_SPCVA_SPC3 5 #define T10$K_ATAPI_UNK0 0 #define T10$K_ATAPI_UNK1 1 #define T10$K_ATAPI_SFF8020 2 #define T10$K_ATAPI_SFF8090 3 #define T10$K_SPCVA_UNK4 4 #define T10$K_TXR12_BASE_LENGTH 5 #define T10$K_TXR12_VERS_DESC 8 #define T10$K_TXR12_VDSC_MMC1 348 #define T10$K_TXR12_VDSC_MMC1_10A 347 #define T10$K_TXR12_VDSC_MMC2 576 #define T10$K_TXR12_VDSC_MMC2_2000 604 #define T10$K_TXR12_VDSC_MMC2_11A 603 #define T10$K_TXR12_VDSC_MMC3 672 #define T10$K_TXR12_VDSC_MMC3_200X 696 #define T10$K_TXR12_VDSC_MMC3_10G 694 #define T10$K_TXR12_VDSC_MMC3_9 693 #define T10$K_TXR12_VDSC_MMC4 928 #define T10$K_TXR12_GENERIC_LENGTH 255 struct txr12 { __struct { unsigned t10$v_txr12_devtype : 5; unsigned t10$v_txr12_devqual : 3; } t10$r_txr12_peripheral; __struct { unsigned t10$v_txr12_removable_fill1 : 7; unsigned t10$v_txr12_removable : 1; } t10$r_txr12_removable; __struct { unsigned t10$v_txr12_ansi_version : 3; unsigned t10$v_txr12_ecma_version : 3; unsigned t10$v_txr12_isoiec_version : 2; } t10$r_txr12_version; __union { __struct { unsigned t10$v_txr12_scsi_rdf : 4; unsigned t10$v_txr12_hisup : 1; unsigned t10$v_txr12_normaca : 1; unsigned t10$v_txr12_addrsupp_obs : 1; unsigned t10$v_txr12_aerc : 1; } t10$r_txr12_addrscsi; __struct { unsigned t10$v_txr12_atapi_rdf : 4; unsigned t10$v_txr12_atapi_version : 4; } t10$r_txr12_addratapi; } t10$r_txr12_addroverlay; unsigned char t10$b_txr12_extra_length; __struct { unsigned t10$v_txr12_flags1_fill1 : 3; unsigned t10$v_txr12_3pc : 1; unsigned t10$v_txr12_alua : 2; unsigned t10$v_txr12_acc : 1; unsigned t10$v_txr12_sccs : 1; } t10$r_txr12_flags1; __struct { unsigned t10$v_txr12_addr16 : 1; unsigned t10$v_txr12_flags2_fill1 : 2; unsigned t10$v_txr12_mchngr : 1; unsigned t10$v_txr12_multip : 1; unsigned t10$v_txr12_vs1 : 1; unsigned t10$v_txr12_encserv : 1; unsigned t10$v_txr12_bque : 1; } t10$r_txr12_flags2; __struct { unsigned t10$v_txr12_vs2 : 1; unsigned t10$v_txr12_cmdque : 1; unsigned t10$v_txr12_flags3_fill1 : 1; unsigned t10$v_txr12_linked : 1; unsigned t10$v_txr12_sync : 1; unsigned t10$v_txr12_wbus16 : 1; unsigned t10$v_txr12_flags3_fill2 : 1; unsigned t10$v_txr12_reladr : 1; } t10$r_txr12_flags3; char t10$t_txr12_vendname [8]; char t10$t_txr12_prodname [16]; char t10$t_txr12_prodrev [4]; unsigned char t10$x_txr12_vendor_data [20]; __struct { unsigned t10$v_txr12_ius : 1; unsigned t10$v_txr12_qas : 1; unsigned t10$v_txr12_clocking : 2; unsigned t10$v_txr12_fill564 : 4; } t10$r_txr12_tx_flags4; unsigned char t10$b_txr12_fill570; unsigned short int t10$w_txr12_vers_desc [8]; unsigned char t10$b_txr12_reserved75255 [181]; } ; #if !defined(__VAXC) #define t10$v_txr12_devtype t10$r_txr12_peripheral.t10$v_txr12_devtype #define t10$v_txr12_devqual t10$r_txr12_peripheral.t10$v_txr12_devqual #define t10$v_txr12_removable t10$r_txr12_removable.t10$v_txr12_removable #define t10$v_txr12_ansi_version t10$r_txr12_version.t10$v_txr12_ansi_version #define t10$v_txr12_ecma_version t10$r_txr12_version.t10$v_txr12_ecma_version #define t10$v_txr12_isoiec_version t10$r_txr12_version.t10$v_txr12_isoiec_version #define t10$r_txr12_addrscsi t10$r_txr12_addroverlay.t10$r_txr12_addrscsi #define t10$v_txr12_scsi_rdf t10$r_txr12_addrscsi.t10$v_txr12_scsi_rdf #define t10$v_txr12_hisup t10$r_txr12_addrscsi.t10$v_txr12_hisup #define t10$v_txr12_normaca t10$r_txr12_addrscsi.t10$v_txr12_normaca #define t10$v_txr12_aerc t10$r_txr12_addrscsi.t10$v_txr12_aerc #define t10$r_txr12_addratapi t10$r_txr12_addroverlay.t10$r_txr12_addratapi #define t10$v_txr12_atapi_rdf t10$r_txr12_addratapi.t10$v_txr12_atapi_rdf #define t10$v_txr12_atapi_version t10$r_txr12_addratapi.t10$v_txr12_atapi_version #define t10$v_txr12_3pc t10$r_txr12_flags1.t10$v_txr12_3pc #define t10$v_txr12_alua t10$r_txr12_flags1.t10$v_txr12_alua #define t10$v_txr12_acc t10$r_txr12_flags1.t10$v_txr12_acc #define t10$v_txr12_sccs t10$r_txr12_flags1.t10$v_txr12_sccs #define t10$v_txr12_addr16 t10$r_txr12_flags2.t10$v_txr12_addr16 #define t10$v_txr12_mchngr t10$r_txr12_flags2.t10$v_txr12_mchngr #define t10$v_txr12_multip t10$r_txr12_flags2.t10$v_txr12_multip #define t10$v_txr12_vs1 t10$r_txr12_flags2.t10$v_txr12_vs1 #define t10$v_txr12_encserv t10$r_txr12_flags2.t10$v_txr12_encserv #define t10$v_txr12_bque t10$r_txr12_flags2.t10$v_txr12_bque #define t10$v_txr12_vs2 t10$r_txr12_flags3.t10$v_txr12_vs2 #define t10$v_txr12_cmdque t10$r_txr12_flags3.t10$v_txr12_cmdque #define t10$v_txr12_linked t10$r_txr12_flags3.t10$v_txr12_linked #define t10$v_txr12_sync t10$r_txr12_flags3.t10$v_txr12_sync #define t10$v_txr12_wbus16 t10$r_txr12_flags3.t10$v_txr12_wbus16 #define t10$v_txr12_reladr t10$r_txr12_flags3.t10$v_txr12_reladr #define t10$v_txr12_ius t10$r_txr12_tx_flags4.t10$v_txr12_ius #define t10$v_txr12_qas t10$r_txr12_tx_flags4.t10$v_txr12_qas #define t10$v_txr12_clocking t10$r_txr12_tx_flags4.t10$v_txr12_clocking #endif /* #if !defined(__VAXC) */ #define T10$K_VPD00_FIXED 4 struct vpd00 { __struct { unsigned t10$v_vpd00_devtype : 5; unsigned t10$v_vpd00_devqual : 3; } t10$r_vpd00_peripheral; unsigned char t10$b_vpd00_page_code; unsigned char t10$b_vpd00_rsvd02; unsigned char t10$b_vpd00_length; } ; #if !defined(__VAXC) #define t10$v_vpd00_devtype t10$r_vpd00_peripheral.t10$v_vpd00_devtype #define t10$v_vpd00_devqual t10$r_vpd00_peripheral.t10$v_vpd00_devqual #endif /* #if !defined(__VAXC) */ #define T10$K_VPD80_FIXED 4 struct vpd80 { __struct { unsigned t10$v_vpd80_devtype : 5; unsigned t10$v_vpd80_devqual : 3; } t10$r_vpd80_peripheral; unsigned char t10$b_vpd80_page_code; unsigned char t10$b_vpd80_rsvd02; unsigned char t10$b_vpd80_length; } ; #if !defined(__VAXC) #define t10$v_vpd80_devtype t10$r_vpd80_peripheral.t10$v_vpd80_devtype #define t10$v_vpd80_devqual t10$r_vpd80_peripheral.t10$v_vpd80_devqual #endif /* #if !defined(__VAXC) */ #define T10$S_TXR12_PRODREV 4 #define T10$S_TXR12_VENDOR_DATA 20 #define T10$S_TXR12_VENDNAME 8 #define T10$S_TXR12_PRODNAME 16 struct txr12a { short int t10$w_txr12a_sdl_pacifier; } ; struct txc15 { unsigned char t10$b_txc15_opcode; __struct { unsigned t10$v_txc15_sp : 1; unsigned t10$v_txc15_fill11 : 3; unsigned t10$v_txc15_pf : 1; unsigned t10$v_txc15_fill15 : 3; } t10$r_txc15_flags; unsigned char t10$b_txc15_fill20; unsigned char t10$b_txc15_fill30; unsigned char t10$b_txc15_length; unsigned char t10$b_txc15_control; } ; #if !defined(__VAXC) #define t10$v_txc15_sp t10$r_txc15_flags.t10$v_txc15_sp #define t10$v_txc15_pf t10$r_txc15_flags.t10$v_txc15_pf #endif /* #if !defined(__VAXC) */ #define T10$K_TXC1A_PC_CURR 0 #define T10$K_TXC1A_PC_CHNG 1 #define T10$K_TXC1A_PC_DFLT 2 #define T10$K_TXC1A_PC_SAVE 3 struct txc1a { unsigned char t10$b_txc1a_opcode; __struct { unsigned t10$v_txc1a_fill0 : 3; unsigned t10$v_txc1a_dbd : 1; unsigned t10$v_txc1a_fill4 : 4; } t10$r_txc1a_flags; __struct { unsigned t10$v_txc1a_page : 6; unsigned t10$v_txc1a_ctrl : 2; } t10$r_txc1a_pagectrl; unsigned char t10$b_txc1a_subpage; unsigned char t10$b_txc1a_length; unsigned char t10$b_txc1a_control; } ; #if !defined(__VAXC) #define t10$v_txc1a_dbd t10$r_txc1a_flags.t10$v_txc1a_dbd #define t10$v_txc1a_fill4 t10$r_txc1a_flags.t10$v_txc1a_fill4 #define t10$v_txc1a_page t10$r_txc1a_pagectrl.t10$v_txc1a_page #define t10$v_txc1a_ctrl t10$r_txc1a_pagectrl.t10$v_txc1a_ctrl #endif /* #if !defined(__VAXC) */ #define T10$K_OPC_STOPDISK 0 #define T10$K_OPC_STARTDISK 1 #define T10$K_OPC_EJECTDISK 2 #define T10$K_OPC_LOADDISK 3 #define T10$K_PWR_NOCHANGE 0 #define T10$K_PWR_RSVD1 1 #define T10$K_PWR_IDLE 2 #define T10$K_PWR_STANDBY 3 #define T10$K_PWR_RSVD4 4 #define T10$K_PWR_SLEEP 5 #define T10$K_PWR_RSVD6 6 #define T10$K_PWR_RSVD7 7 #define T10$K_PWR_RSVD8 8 #define T10$K_PWR_RSVD9 9 #define T10$K_PWR_RSVDA 10 #define T10$K_PWR_RSVDB 11 #define T10$K_PWR_RSVDC 12 #define T10$K_PWR_RSVDD 13 #define T10$K_PWR_RSVDE 14 #define T10$K_PWR_RSVDF 15 struct txc1b { unsigned char t10$b_txc1b_opcode; __struct { unsigned t10$v_txc1b_immed : 1; unsigned t10$v_txc1b_fill11 : 7; } t10$r_txc1b_flags; unsigned char t10$b_txc1b_fill20; unsigned char t10$b_txc1b_fill30; __struct { unsigned t10$v_txc1b_action : 2; unsigned t10$v_txc1b_fill42 : 2; unsigned t10$v_txc1b_state : 4; } t10$r_txc1b_power; unsigned char t10$b_txc1b_control; } ; #if !defined(__VAXC) #define t10$v_txc1b_immed t10$r_txc1b_flags.t10$v_txc1b_immed #define t10$v_txc1b_fill11 t10$r_txc1b_flags.t10$v_txc1b_fill11 #define t10$v_txc1b_action t10$r_txc1b_power.t10$v_txc1b_action #define t10$v_txc1b_fill42 t10$r_txc1b_power.t10$v_txc1b_fill42 #define t10$v_txc1b_state t10$r_txc1b_power.t10$v_txc1b_state #endif /* #if !defined(__VAXC) */ struct txc23 { unsigned char t10$b_txc23_opcode; unsigned char t10$b_txc23_fill1; unsigned char t10$b_txc23_fill2; unsigned char t10$b_txc23_fill3; unsigned char t10$b_txc23_fill4; unsigned char t10$b_txc23_fill5; unsigned char t10$b_txc23_fill6; unsigned short int t10$w_txc23_length; unsigned char t10$b_txc23_control; } ; #define T10$K_TXR23FL_DT_RSVDMED 0 #define T10$K_TXR23FL_DT_UNFMTMED 1 #define T10$K_TXR23FL_DT_FMTMED 2 #define T10$K_TXR23FL_DT_NOMEDIA 3 #define T10$K_FMTTYP_WHOLE 0 #define T10$K_FMTTYP_EXPAND 1 #define T10$K_FMTTYP_RSVD02 2 #define T10$K_FMTTYP_RSVD03 3 #define T10$K_FMTTYP_ZONE 4 #define T10$K_FMTTYP_HIZONE 5 #define T10$K_FMTTYP_RSVD06 6 #define T10$K_FMTTYP_RSVD07 7 #define T10$K_FMTTYP_RSVD08 8 #define T10$K_FMTTYP_RSVD09 9 #define T10$K_FMTTYP_RSVD0A 10 #define T10$K_FMTTYP_RSVD0B 11 #define T10$K_FMTTYP_RSVD0C 12 #define T10$K_FMTTYP_RSVD0D 13 #define T10$K_FMTTYP_RSVD0E 14 #define T10$K_FMTTYP_RSVD0F 15 #define T10$K_FMTTYP_MAXRW 16 #define T10$K_FMTTYP_GROWSESS 17 #define T10$K_FMTTYP_ADDSESS 18 #define T10$K_FMTTYP_GROWSESINT 19 #define T10$K_FMTTYP_ADDSESSINT 20 #define T10$K_FMTTYP_MAXRWINT 21 #define T10$K_FMTTYP_RSVD16 22 #define T10$K_FMTTYP_RSVD17 23 #define T10$K_FMTTYP_RSVD18 24 #define T10$K_FMTTYP_RSVD19 25 #define T10$K_FMTTYP_RSVD1A 26 #define T10$K_FMTTYP_RSVD1B 27 #define T10$K_FMTTYP_RSVD1C 28 #define T10$K_FMTTYP_RSVD1D 29 #define T10$K_FMTTYP_RSVD1E 30 #define T10$K_FMTTYP_RSVD1F 31 #define T10$K_FMTTYP_RSVD20 32 #define T10$K_FMTTYP_RSVD21 33 #define T10$K_FMTTYP_RSVD22 34 #define T10$K_FMTTYP_RSVD23 35 #define T10$K_FMTTYP_MRWDMAADD 36 #define T10$K_FMTTYP_RSVD25 37 #define T10$K_FMTTYP_PLUSRW 38 #define T10$K_FMTTYP_RSVD27 39 struct txr23fl { unsigned char t10$b_txr23fl_fill0; unsigned char t10$b_txr23fl_fill1; unsigned char t10$b_txr23fl_fill2; unsigned char t10$b_txr23fl_length; unsigned int t10$l_txr23fl_blocks; __struct { unsigned t10$v_txr23fl_dsctype : 2; unsigned t10$v_txr23fl_flags_fill : 6; } t10$r_txr23fl_flags; unsigned char t10$x_txr23fl_block_size [3]; __struct { unsigned int t10$l_txr23flfc_blocks; __struct { unsigned t10$v_txr23flfc_rsvd : 2; unsigned t10$v_txr23flfc_fmttype : 2; unsigned t10$v_fill_0_ : 4; } t10$r_txr23flfc_fcflags; unsigned char t10$x_txr23flfc_typdep [3]; } t10$r_txr23flfc [32]; } ; #if !defined(__VAXC) #define t10$v_txr23fl_dsctype t10$r_txr23fl_flags.t10$v_txr23fl_dsctype #define t10$l_txr23flfc_blocks t10$l_txr23flfc_blocks #define t10$r_txr23flfc_fcflags t10$r_txr23flfc_fcflags #define t10$v_txr23flfc_rsvd t10$r_txr23flfc_fcflags.t10$v_txr23flfc_rsvd #define t10$v_txr23flfc_fmttype t10$r_txr23flfc_fcflags.t10$v_txr23flfc_fmttype #define t10$x_txr23flfc_typdep t10$x_txr23flfc_typdep #endif /* #if !defined(__VAXC) */ struct txc25 { unsigned char t10$b_txc25_opcode; __struct { unsigned t10$v_txc25_reladr : 1; unsigned t10$v_txc25_fill1 : 7; } t10$r_txc25_flags; unsigned int t10$l_txc25_lba; unsigned char t10$b_txc25_fill6; unsigned char t10$b_txc25_fill7; __struct { unsigned t10$v_txc25_fill100 : 7; unsigned t10$v_txc25_pmi : 1; } t10$r_txc25_flags10; unsigned char t10$b_txc25_control; } ; #if !defined(__VAXC) #define t10$v_txc25_reladr t10$r_txc25_flags.t10$v_txc25_reladr #define t10$v_txc25_pmi t10$r_txc25_flags10.t10$v_txc25_pmi #endif /* #if !defined(__VAXC) */ struct txr25 { unsigned int t10$l_txr25_max_lba; unsigned int t10$l_txr25_block_size; } ; struct txc28 { unsigned char t10$b_txc28_opcode; __struct { unsigned t10$v_txc28_reladr : 1; unsigned t10$v_txc28_fill1 : 2; unsigned t10$v_txc28_fua : 1; unsigned t10$v_txc28_dpo : 1; unsigned t10$v_txc28_fill2 : 3; } t10$r_txc28_flags; unsigned int t10$l_txc28_lba; unsigned char t10$b_txc28_fill6; unsigned short int t10$w_txc28_blocks; unsigned char t10$b_txc28_control; } ; #if !defined(__VAXC) #define t10$v_txc28_reladr t10$r_txc28_flags.t10$v_txc28_reladr #define t10$v_txc28_fua t10$r_txc28_flags.t10$v_txc28_fua #define t10$v_txc28_dpo t10$r_txc28_flags.t10$v_txc28_dpo #endif /* #if !defined(__VAXC) */ struct txc2a { unsigned char t10$b_txc2a_opcode; __struct { unsigned t10$v_txc2a_reladr : 1; unsigned t10$v_txc2a_fill1 : 1; unsigned t10$v_txc2a_ebp : 1; unsigned t10$v_txc2a_fua : 1; unsigned t10$v_txc2a_dpo : 1; unsigned t10$v_txc2a_fill2 : 3; } t10$r_txc2a_flags; unsigned int t10$l_txc2a_lba; unsigned char t10$b_txc2a_fill6; unsigned short int t10$w_txc2a_blocks; unsigned char t10$b_txc2a_control; } ; #if !defined(__VAXC) #define t10$v_txc2a_reladr t10$r_txc2a_flags.t10$v_txc2a_reladr #define t10$v_txc2a_ebp t10$r_txc2a_flags.t10$v_txc2a_ebp #define t10$v_txc2a_fua t10$r_txc2a_flags.t10$v_txc2a_fua #define t10$v_txc2a_dpo t10$r_txc2a_flags.t10$v_txc2a_dpo #endif /* #if !defined(__VAXC) */ struct txc2e { unsigned char t10$b_txc2e_opcode; __struct { unsigned t10$v_txc2e_reladr : 1; unsigned t10$v_txc2e_bytchk : 1; unsigned t10$v_txc2e_fill1 : 2; unsigned t10$v_txc2e_dpo : 1; unsigned t10$v_txc2e_fill2 : 3; } t10$r_txc2e_flags; unsigned int t10$l_txc2e_lba; unsigned char t10$b_txc2e_fill6; unsigned short int t10$w_txc2e_blocks; unsigned char t10$b_txc2e_control; } ; #if !defined(__VAXC) #define t10$v_txc2e_reladr t10$r_txc2e_flags.t10$v_txc2e_reladr #define t10$v_txc2e_bytchk t10$r_txc2e_flags.t10$v_txc2e_bytchk #define t10$v_txc2e_dpo t10$r_txc2e_flags.t10$v_txc2e_dpo #endif /* #if !defined(__VAXC) */ struct txc35 { unsigned char t10$b_txc35_opcode; __struct { unsigned t10$v_txc35_reladr : 1; unsigned t10$v_txc35_immed : 1; unsigned t10$v_txc35_fill : 6; } t10$r_txc35_flags; unsigned int t10$l_txc35_lba; unsigned char t10$b_txc35_fill6; unsigned short int t10$w_txc35_blocks; unsigned char t10$b_txc35_control; } ; #if !defined(__VAXC) #define t10$v_txc35_reladr t10$r_txc35_flags.t10$v_txc35_reladr #define t10$v_txc35_immed t10$r_txc35_flags.t10$v_txc35_immed #endif /* #if !defined(__VAXC) */ #define T10$K_TXC43_FMT_ALLTRKS 0 #define T10$K_TXC43_FMT_LASTTRK 1 #define T10$K_TXC43_FMT_QSUBTOC 2 #define T10$K_TXC43_FMT_QSUBPMA 3 #define T10$K_TXC43_FMT_ATIP 4 #define T10$K_TXC43_FMT_TEXT 5 struct txc43 { unsigned char t10$b_txc43_opcode; __struct { unsigned t10$v_txc43_time_rsvd0 : 1; unsigned t10$v_txc43_time_or_lba : 1; unsigned t10$v_txc43_time_rsvd3 : 6; } t10$r_txc43_flags; __struct { unsigned t10$v_txc43_format : 4; unsigned t10$v_txc43_fmt_rsvd5 : 4; } t10$r_txc43s_format; unsigned char t10$b_txc43_fill3; unsigned char t10$b_txc43_fill4; unsigned char t10$b_txc43_fill5; unsigned char t10$b_txc43_trksess; unsigned short int t10$w_txc43_length; unsigned char t10$b_txc43_control; } ; #if !defined(__VAXC) #define t10$v_txc43_time_or_lba t10$r_txc43_flags.t10$v_txc43_time_or_lba #define t10$v_txc43_format t10$r_txc43s_format.t10$v_txc43_format #endif /* #if !defined(__VAXC) */ struct txr43 { unsigned short int t10$w_txr43_data_length; unsigned char t10$b_txr43_1st_track; unsigned char t10$b_txr43_last_track; } ; #define T10$K_TX43ADRTD_NO 0 #define T10$K_TX43ADRTD_PS 1 #define T10$K_TX43ADRTD_CT 2 #define T10$K_TX43ADRTD_IS 3 struct txr43td { unsigned char t10$b_txr43td_fill0; __struct { unsigned t10$v_txr43td_control : 4; unsigned t10$v_txr43td_adr : 4; } t10$r_txr43td_flags; unsigned char t10$b_txr43td_track; unsigned char t10$b_txr43td_fill3; unsigned int t10$l_txr43td_track_start; } ; #if !defined(__VAXC) #define t10$v_txr43td_control t10$r_txr43td_flags.t10$v_txr43td_control #define t10$v_txr43td_adr t10$r_txr43td_flags.t10$v_txr43td_adr #endif /* #if !defined(__VAXC) */ #define T10$K_TXC46_RT_ALL 0 #define T10$K_TXC46_RT_CURRENT 1 #define T10$K_TXC46_RT_ONE 2 #define T10$K_TXC46_RT_RESERVED 3 #define T10$K_FCOD_LIST 0 #define T10$K_FCOD_CORE 1 #define T10$K_FCOD_MORPH 2 #define T10$K_FCOD_REMOVABLE 3 #define T10$K_FCOD_WRPROT 4 #define T10$K_FCOD_RSVD05 5 #define T10$K_FCOD_RSVD06 6 #define T10$K_FCOD_RSVD07 7 #define T10$K_FCOD_RSVD08 8 #define T10$K_FCOD_RSVD09 9 #define T10$K_FCOD_RSVD0A 10 #define T10$K_FCOD_RSVD0B 11 #define T10$K_FCOD_RSVD0C 12 #define T10$K_FCOD_RSVD0D 13 #define T10$K_FCOD_RSVD0E 14 #define T10$K_FCOD_RSVD0F 15 #define T10$K_FCOD_RANDRD 16 #define T10$K_FCOD_RSVD11 17 #define T10$K_FCOD_RSVD12 18 #define T10$K_FCOD_RSVD13 19 #define T10$K_FCOD_RSVD14 20 #define T10$K_FCOD_RSVD15 21 #define T10$K_FCOD_RSVD16 22 #define T10$K_FCOD_RSVD17 23 #define T10$K_FCOD_RSVD18 24 #define T10$K_FCOD_RSVD19 25 #define T10$K_FCOD_RSVD1A 26 #define T10$K_FCOD_RSVD1B 27 #define T10$K_FCOD_RSVD1C 28 #define T10$K_FCOD_MULTIREAD 29 #define T10$K_FCOD_CDREAD 30 #define T10$K_FCOD_DVDREAD 31 #define T10$K_FCOD_RANDWR 32 #define T10$K_FCOD_INCSTRMWR 33 #define T10$K_FCOD_SECTORERASE 34 #define T10$K_FCOD_FORMATTABLE 35 #define T10$K_FCOD_DEFECTMGMT1 36 #define T10$K_FCOD_WRITEONCE 37 #define T10$K_FCOD_RESTROVRWR1 38 #define T10$K_FCOD_CDRWCAV 39 #define T10$K_FCOD_MRW 40 #define T10$K_FCOD_DEFECTMGMT2 41 #define T10$K_FCOD_DVDPLUSRW 42 #define T10$K_FCOD_DVDPLUSR 43 #define T10$K_FCOD_RESTOVRWR2 44 #define T10$K_FCOD_CDTAO 45 #define T10$K_FCOD_CDMASTER 46 #define T10$K_FCOD_DVDMINUSRW 47 #define T10$K_FCOD_DDCD 48 #define T10$K_FCOD_DDCDR 49 #define T10$K_FCOD_DDCDRW 50 #define T10$K_FCOD_LAYERJMP 51 #define T10$K_FCOD_RSVD34 52 #define T10$K_FCOD_RSVD35 53 #define T10$K_FCOD_RSVD36 54 #define T10$K_FCOD_CDRWMEDRPT 55 #define T10$K_FCOD_BDPOW 56 #define T10$K_FCOD_RSVD39 57 #define T10$K_FCOD_DVDPLUSRWDL 58 #define T10$K_FCOD_DVDPLUSRDL 59 #define T10$K_FCOD_RSVD3C 60 #define T10$K_FCOD_RSVD3D 61 #define T10$K_FCOD_RSVD3E 62 #define T10$K_FCOD_RSVD3F 63 #define T10$K_FCOD_BDR 64 #define T10$K_FCOD_BDW 65 #define T10$K_FCOD_TSR 66 #define T10$K_FCOD_RSVD43 67 #define T10$K_FCOD_RSVD44 68 #define T10$K_FCOD_RSVD45 69 #define T10$K_FCOD_RSVD46 70 #define T10$K_FCOD_RSVD47 71 #define T10$K_FCOD_RSVD48 72 #define T10$K_FCOD_RSVD49 73 #define T10$K_FCOD_RSVD4A 74 #define T10$K_FCOD_RSVD4B 75 #define T10$K_FCOD_RSVD4C 76 #define T10$K_FCOD_RSVD4D 77 #define T10$K_FCOD_RSVD4E 78 #define T10$K_FCOD_RSVD4F 79 #define T10$K_FCOD_HDR 80 #define T10$K_FCOD_HDW 81 #define T10$K_FCOD_PWRMGMT 256 #define T10$K_FCOD_RSVD101 257 #define T10$K_FCOD_EMBCHNGR 258 #define T10$K_FCOD_CDAUDIO 259 #define T10$K_FCOD_FWUPGR 260 #define T10$K_FCOD_TIMEOUT 261 #define T10$K_FCOD_DVDCSS 262 #define T10$K_FCOD_RTSTREAM 263 #define T10$K_FCOD_SERIALNUM 264 #define T10$K_FCOD_RSVD109 265 #define T10$K_FCOD_CNTLBLKS 266 #define T10$K_FCOD_DVDCPRM 267 #define T10$K_FCOD_FWINFO 268 #define T10$K_FCOD_AACS 269 #define T10$K_FCOD_RSVD10E 270 #define T10$K_FCOD_RSVD10F 271 #define T10$K_FCOD_VCPS 272 #define T10$K_FCOD_FWDATE 511 struct txc46 { unsigned char t10$b_txc46_opcode; __struct { unsigned t10$v_txc46_reqtyp : 2; unsigned t10$v_txc46_flags_fill : 6; } t10$r_txc46_flags; unsigned short int t10$w_txc46_1st_feat; unsigned char t10$b_txc46_fill4; unsigned char t10$b_txc46_fill5; unsigned char t10$b_txc46_fill6; unsigned short int t10$w_txc46_rsp_length; unsigned char t10$b_txc46_control; } ; #if !defined(__VAXC) #define t10$v_txc46_reqtyp t10$r_txc46_flags.t10$v_txc46_reqtyp #endif /* #if !defined(__VAXC) */ #define T10$K_TXR46FH_LENGTH 8 struct txr46fh { unsigned int t10$l_txr46fh_length; unsigned char t10$b_txr46fh_fill4; unsigned char t10$b_txr46fh_fill5; unsigned short int t10$w_txr46fh_curr_profile; } ; #define T10$K_TXR46FD_MRW 40 #define T10$K_TXR46FD_DVDPRW 42 #define T10$K_TXR46FD_DVDPR 43 #define T10$K_TXR46FD_LENGTH 4 #define T10$K_TXR46FD00_SIZE 64 #define T10$K_PROF_RSVD00 0 #define T10$K_PROF_FIXEDDISK 1 #define T10$K_PROF_REMOVABLE 2 #define T10$K_PROF_MOERASABLE 3 #define T10$K_PROF_WORMDISK 4 #define T10$K_PROF_ASMO 5 #define T10$K_PROF_RSVD06 6 #define T10$K_PROF_RSVD07 7 #define T10$K_PROF_CDROM 8 #define T10$K_PROF_CDR 9 #define T10$K_PROF_CDRW 10 #define T10$K_PROF_RSVD0B 11 #define T10$K_PROF_RSVD0C 12 #define T10$K_PROF_RSVD0D 13 #define T10$K_PROF_RSVD0E 14 #define T10$K_PROF_RSVD0F 15 #define T10$K_PROF_DVDROM 16 #define T10$K_PROF_DVDMINUSRSEQ 17 #define T10$K_PROF_DVDRAM 18 #define T10$K_PROF_DVDMINUSRWRO 19 #define T10$K_PROF_DVDMINUSRWSEQ 20 #define T10$K_PROF_DVDMINUSRDLSEQ 21 #define T10$K_PROF_DVDMINUSRDLJMP 22 #define T10$K_PROF_RSVD17 23 #define T10$K_PROF_RSVD18 24 #define T10$K_PROF_RSVD19 25 #define T10$K_PROF_DVDPLUSRW 26 #define T10$K_PROF_DVDPLUSR 27 #define T10$K_PROF_RSVD1C 28 #define T10$K_PROF_RSVD1D 29 #define T10$K_PROF_RSVD1E 30 #define T10$K_PROF_RSVD1F 31 #define T10$K_PROF_DDCDROM 32 #define T10$K_PROF_DDCDR 33 #define T10$K_PROF_DDCDRW 34 #define T10$K_PROF_RSVD23 35 #define T10$K_PROF_RSVD24 36 #define T10$K_PROF_RSVD25 37 #define T10$K_PROF_RSVD26 38 #define T10$K_PROF_RSVD27 39 #define T10$K_PROF_RSVD28 40 #define T10$K_PROF_RSVD29 41 #define T10$K_PROF_DVDPLUSRWDL 42 #define T10$K_PROF_DVDPLUSRDL 43 #define T10$K_PROF_RSVD2C 44 #define T10$K_PROF_RSVD2D 45 #define T10$K_PROF_RSVD2E 46 #define T10$K_PROF_RSVD2F 47 #define T10$K_PROF_RSVD30 48 #define T10$K_PROF_RSVD31 49 #define T10$K_PROF_RSVD32 50 #define T10$K_PROF_RSVD33 51 #define T10$K_PROF_RSVD34 52 #define T10$K_PROF_RSVD35 53 #define T10$K_PROF_RSVD36 54 #define T10$K_PROF_RSVD37 55 #define T10$K_PROF_RSVD38 56 #define T10$K_PROF_RSVD39 57 #define T10$K_PROF_RSVD3A 58 #define T10$K_PROF_RSVD3B 59 #define T10$K_PROF_RSVD3C 60 #define T10$K_PROF_RSVD3D 61 #define T10$K_PROF_RSVD3E 62 #define T10$K_PROF_RSVD3F 63 #define T10$K_PROF_BDROM 64 #define T10$K_PROF_BDRSRM 65 #define T10$K_PROF_BDRRRM 66 #define T10$K_PROF_BDRE 67 #define T10$K_PROF_RSVD44 68 #define T10$K_PROF_RSVD45 69 #define T10$K_PROF_RSVD46 70 #define T10$K_PROF_RSVD47 71 #define T10$K_PROF_RSVD48 72 #define T10$K_PROF_RSVD49 73 #define T10$K_PROF_RSVD4A 74 #define T10$K_PROF_RSVD4B 75 #define T10$K_PROF_RSVD4C 76 #define T10$K_PROF_RSVD4D 77 #define T10$K_PROF_RSVD4E 78 #define T10$K_PROF_RSVD4F 79 #define T10$K_PROF_HDDVDROM 80 #define T10$K_PROF_HDDVDR 81 #define T10$K_PROF_HDDVDRW 82 #define T10$K_PROF_RSVD53 83 #define T10$K_PROF_RSVD54 84 #define T10$K_PROF_RSVD55 85 #define T10$K_PROF_RSVD56 86 #define T10$K_PROF_RSVD57 87 #define T10$K_PROF_RSVD58 88 #define T10$K_PROF_RSVD59 89 #define T10$K_PROF_RSVD5A 90 #define T10$K_PROF_RSVD5B 91 #define T10$K_PROF_RSVD5C 92 #define T10$K_PROF_RSVD5D 93 #define T10$K_PROF_RSVD5E 94 #define T10$K_PROF_RSVD5F 95 #define T10$K_PROF_NONCONFORM 65535 #define T10$M_TXR46_MEDV1 1 #define T10$M_TXR46_MEDV2 2 #define T10$M_TXR46_MEDV3 4 #define T10$M_TXR46_MEDVX 248 struct txr46fd { unsigned short int t10$w_txr46fd_feature_code; __struct { unsigned t10$v_txr46fd_current : 1; unsigned t10$v_txr46fd_persistent : 1; unsigned t10$v_txr46fd_version : 4; unsigned t10$v_txr46fd_flags_fill : 2; } t10$r_txr46fd_flags; unsigned char t10$b_txr46fd_extra_length; __union { __struct { unsigned short int t10$w_txr46fd00_feature_code; __struct { unsigned t10$v_txr46fd00_current : 1; unsigned t10$v_txr46fd00_persistent : 1; unsigned t10$v_txr46fd00_version : 4; unsigned t10$v_txr46fd00_flags_fill : 2; } t10$r_txr46fd00_flags; unsigned char t10$b_txr46fd00_extra_length; } t10$r_txr46fd00 [64]; __struct { __struct { unsigned t10$v_txr46fd2a_write : 1; unsigned t10$v_txr46fd2a_fill41 : 7; unsigned t10$v_txr46fd2a_closeonly : 1; unsigned t10$v_txr46fd2a_quickst : 1; unsigned t10$v_txr46fd2a_fill52 : 6; } t10$r_txr46fd2a_flags; unsigned char t10$b_txr46fd_fill60; unsigned char t10$b_txr46fd_fill70; __union { unsigned char t10$b_txr46fd2a_suppmedvers; __struct { unsigned t10$v_txr46fd2a_suppvers1 : 1; unsigned t10$v_txr46fd2a_suppvers2 : 1; unsigned t10$v_txr46fd2a_suppvers3 : 1; unsigned t10$v_txr46fd2a_suppother : 5; } t10$r_txr46fd2a_suppmedvers; } t10$r_txr46fd2a_smvunion; unsigned char t10$b_txr46fd2a_fill90; unsigned char t10$b_txr46fd2a_filla0; unsigned char t10$b_txr46fd2a_fillb0; __union { unsigned char t10$b_txr46fd2a_currmedvers; __struct { unsigned t10$v_txr46fd2a_currvers1 : 1; unsigned t10$v_txr46fd2a_currvers2 : 1; unsigned t10$v_txr46fd2a_currvers3 : 1; unsigned t10$v_txr46fd2a_currother : 5; } t10$r_txr46fd2a_currmedvers; } t10$r_txr46fd2a_cmvunion; unsigned char t10$b_txr46fd2a_filld0; unsigned char t10$b_txr46fd2a_fille0; unsigned char t10$b_txr46fd2a_fillf0; } t10$r_txr46fd2a; __struct { __struct { unsigned t10$v_txr46fd2b_write : 1; unsigned t10$v_txr46fd2b_fill41 : 7; } t10$r_txr46fd2b_flags; unsigned char t10$b_txr46fd2b_fill50; unsigned char t10$b_txr46fd2b_fill60; unsigned char t10$b_txr46fd2b_fill70; __union { unsigned char t10$b_txr46fd2b_suppmedvers; __struct { unsigned t10$v_txr46fd2b_suppvers1 : 1; unsigned t10$v_txr46fd2b_suppvers2 : 1; unsigned t10$v_txr46fd2b_suppvers3 : 1; unsigned t10$v_txr46fd2b_fill83 : 5; } t10$r_txr46fd2b_suppmedvers; } t10$r_txr46fd2b_smvunion; unsigned char t10$b_txr46fd2b_fill90; unsigned char t10$b_txr46fd2b_filla0; unsigned char t10$b_txr46fd2b_fillb0; __union { unsigned char t10$b_txr46fd2b_currmedvers; __struct { unsigned t10$v_txr46fd2b_currvers1 : 1; unsigned t10$v_txr46fd2b_currvers2 : 1; unsigned t10$v_txr46fd2b_currvers3 : 1; unsigned t10$v_txr46fd2b_fillb3 : 5; } t10$r_txr46fd2b_currmedvers; } t10$r_txr46fd2b_cmvunion; unsigned char t10$b_txr46fd2b_filld0; unsigned char t10$b_txr46fd2b_fille0; unsigned char t10$b_txr46fd2b_fillf0; } t10$r_txr46fd2b; __struct { unsigned char t10$b_txr46fd2f_additional_len; __struct { unsigned t10$v_txr46fd2f_rsvd40 : 1; unsigned t10$v_txr46fd2f_rw : 1; unsigned t10$v_txr46fd2f_test_wr : 1; unsigned t10$v_txr46fd2f_fill43 : 3; unsigned t10$v_txr46fd2f_buf : 1; unsigned t10$v_txr46fd2f_fill47 : 1; } t10$r_txr46fd2f_flags; unsigned char t10$b_txr46fd2f_fill50; unsigned char t10$b_txr46fd2f_fill60; unsigned char t10$b_txr46fd2f_fill70; } t10$r_txr46fd2f; } t10$r_txr46fd_overlay; } ; #if !defined(__VAXC) #define t10$v_txr46fd_current t10$r_txr46fd_flags.t10$v_txr46fd_current #define t10$v_txr46fd_persistent t10$r_txr46fd_flags.t10$v_txr46fd_persistent #define t10$v_txr46fd_version t10$r_txr46fd_flags.t10$v_txr46fd_version #define t10$r_txr46fd00 t10$r_txr46fd_overlay.t10$r_txr46fd00 #define t10$w_txr46fd00_feature_code t10$w_txr46fd00_feature_code #define t10$r_txr46fd00_flags t10$r_txr46fd00_flags #define t10$v_txr46fd00_current t10$r_txr46fd00_flags.t10$v_txr46fd00_current #define t10$v_txr46fd00_persistent t10$r_txr46fd00_flags.t10$v_txr46fd00_persistent #define t10$v_txr46fd00_version t10$r_txr46fd00_flags.t10$v_txr46fd00_version #define t10$b_txr46fd00_extra_length t10$b_txr46fd00_extra_length #define t10$r_txr46fd2a t10$r_txr46fd_overlay.t10$r_txr46fd2a #define t10$r_txr46fd2a_flags t10$r_txr46fd2a.t10$r_txr46fd2a_flags #define t10$v_txr46fd2a_write t10$r_txr46fd2a_flags.t10$v_txr46fd2a_write #define t10$v_txr46fd2a_closeonly t10$r_txr46fd2a_flags.t10$v_txr46fd2a_closeonly #define t10$v_txr46fd2a_quickst t10$r_txr46fd2a_flags.t10$v_txr46fd2a_quickst #define t10$b_txr46fd2a_suppmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_smvunion.t10$b_txr46fd2a_suppmedvers #define t10$r_txr46fd2a_suppmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_smvunion.t10$r_txr46fd2a_suppmedvers #define t10$v_txr46fd2a_suppvers1 t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppvers1 #define t10$v_txr46fd2a_suppvers2 t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppvers2 #define t10$v_txr46fd2a_suppvers3 t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppvers3 #define t10$v_txr46fd2a_suppother t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppother #define t10$b_txr46fd2a_currmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_cmvunion.t10$b_txr46fd2a_currmedvers #define t10$r_txr46fd2a_currmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_cmvunion.t10$r_txr46fd2a_currmedvers #define t10$v_txr46fd2a_currvers1 t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currvers1 #define t10$v_txr46fd2a_currvers2 t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currvers2 #define t10$v_txr46fd2a_currvers3 t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currvers3 #define t10$v_txr46fd2a_currother t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currother #define t10$r_txr46fd2b t10$r_txr46fd_overlay.t10$r_txr46fd2b #define t10$r_txr46fd2b_flags t10$r_txr46fd2b.t10$r_txr46fd2b_flags #define t10$v_txr46fd2b_write t10$r_txr46fd2b_flags.t10$v_txr46fd2b_write #define t10$b_txr46fd2b_suppmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_smvunion.t10$b_txr46fd2b_suppmedvers #define t10$r_txr46fd2b_suppmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_smvunion.t10$r_txr46fd2b_suppmedvers #define t10$v_txr46fd2b_suppvers1 t10$r_txr46fd2b_suppmedvers.t10$v_txr46fd2b_suppvers1 #define t10$v_txr46fd2b_suppvers2 t10$r_txr46fd2b_suppmedvers.t10$v_txr46fd2b_suppvers2 #define t10$v_txr46fd2b_suppvers3 t10$r_txr46fd2b_suppmedvers.t10$v_txr46fd2b_suppvers3 #define t10$b_txr46fd2b_currmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_cmvunion.t10$b_txr46fd2b_currmedvers #define t10$r_txr46fd2b_currmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_cmvunion.t10$r_txr46fd2b_currmedvers #define t10$v_txr46fd2b_currvers1 t10$r_txr46fd2b_currmedvers.t10$v_txr46fd2b_currvers1 #define t10$v_txr46fd2b_currvers2 t10$r_txr46fd2b_currmedvers.t10$v_txr46fd2b_currvers2 #define t10$v_txr46fd2b_currvers3 t10$r_txr46fd2b_currmedvers.t10$v_txr46fd2b_currvers3 #define t10$r_txr46fd2f t10$r_txr46fd_overlay.t10$r_txr46fd2f #define t10$b_txr46fd2f_additional_len t10$r_txr46fd2f.t10$b_txr46fd2f_additional_len #define t10$r_txr46fd2f_flags t10$r_txr46fd2f.t10$r_txr46fd2f_flags #define t10$v_txr46fd2f_rw t10$r_txr46fd2f_flags.t10$v_txr46fd2f_rw #define t10$v_txr46fd2f_test_wr t10$r_txr46fd2f_flags.t10$v_txr46fd2f_test_wr #define t10$v_txr46fd2f_buf t10$r_txr46fd2f_flags.t10$v_txr46fd2f_buf #endif /* #if !defined(__VAXC) */ struct txr46fl { unsigned short int t10$w_txr46fl_feature_code; __struct { unsigned t10$v_txr46fl_current : 1; unsigned t10$v_txr46fl_persistent : 1; unsigned t10$v_txr46fl_version : 4; unsigned t10$v_txr46fl_flags_fill : 2; } t10$r_txr46fl_flags; unsigned char t10$b_txr46fl_additional_len; __struct { unsigned short int t10$w_txr46flpd_feature_code; __struct { unsigned t10$v_txr46flpd_current : 1; unsigned t10$v_txr46flpd_fill1 : 7; } t10$r_txr46flpd_flags; unsigned char t10$b_txr46flpd_reserved; } t10$r_txr46flpd [65536]; } ; #if !defined(__VAXC) #define t10$v_txr46fl_current t10$r_txr46fl_flags.t10$v_txr46fl_current #define t10$v_txr46fl_persistent t10$r_txr46fl_flags.t10$v_txr46fl_persistent #define t10$v_txr46fl_version t10$r_txr46fl_flags.t10$v_txr46fl_version #define t10$w_txr46flpd_feature_code t10$w_txr46flpd_feature_code #define t10$r_txr46flpd_flags t10$r_txr46flpd_flags #define t10$v_txr46flpd_current t10$r_txr46flpd_flags.t10$v_txr46flpd_current #endif /* #if !defined(__VAXC) */ #define T10$K_TXR46PD_LENGTH 4 struct txr46pd { unsigned short int t10$w_txr46pd_profile; __struct { unsigned t10$v_txr46pd_current : 1; unsigned t10$v_txr46pd_fill21 : 7; } t10$r_txr46pd_flags; unsigned char t10$b_txr46pd_fill30; } ; #if !defined(__VAXC) #define t10$v_txr46pd_current t10$r_txr46pd_flags.t10$v_txr46pd_current #endif /* #if !defined(__VAXC) */ struct txc4a { unsigned char t10$b_txc4a_opcode; __struct { unsigned t10$v_txc4a_polled : 1; unsigned t10$v_txc4a_flags_rsvd1 : 7; } t10$r_txc4a_flags; unsigned char t10$b_txc4a_fill2; unsigned char t10$b_txc4a_fill3; __struct { unsigned t10$v_txc4a_gesn_rsvd0 : 1; unsigned t10$v_txc4a_gesn_opchange : 1; unsigned t10$v_txc4a_gesn_power : 1; unsigned t10$v_txc4a_gesn_extreq : 1; unsigned t10$v_txc4a_gesn_media : 1; unsigned t10$v_txc4a_gesn_multi : 1; unsigned t10$v_txc4a_gesn_devbusy : 1; unsigned t10$v_txc4a_gesn_rsvd7 : 1; } t10$r_txc4a_req_classes; unsigned char t10$b_txc4a_fill5; unsigned char t10$b_txc4a_fill6; unsigned short int t10$w_txc4a_length; unsigned char t10$b_txc4a_control; } ; #if !defined(__VAXC) #define t10$v_txc4a_polled t10$r_txc4a_flags.t10$v_txc4a_polled #define t10$v_txc4a_gesn_opchange t10$r_txc4a_req_classes.t10$v_txc4a_gesn_opchange #define t10$v_txc4a_gesn_power t10$r_txc4a_req_classes.t10$v_txc4a_gesn_power #define t10$v_txc4a_gesn_extreq t10$r_txc4a_req_classes.t10$v_txc4a_gesn_extreq #define t10$v_txc4a_gesn_media t10$r_txc4a_req_classes.t10$v_txc4a_gesn_media #define t10$v_txc4a_gesn_multi t10$r_txc4a_req_classes.t10$v_txc4a_gesn_multi #define t10$v_txc4a_gesn_devbusy t10$r_txc4a_req_classes.t10$v_txc4a_gesn_devbusy #endif /* #if !defined(__VAXC) */ #define T10$K_TXR4A_GESN_NONE 0 #define T10$K_TXR4A_GESN_OPCHANGE 1 #define T10$K_TXR4A_GESN_POWER 2 #define T10$K_TXR4A_GESN_EXTREQ 3 #define T10$K_TXR4A_GESN_MEDIA 4 #define T10$K_TXR4A_GESN_MULTI 5 #define T10$K_TXR4A_GESN_DEVBUSY 272 #define T10$K_TXR4ANC001_EVT_NOCHG 0 #define T10$K_TXR4ANC001_EVT_CHGING 1 #define T10$K_TXR4ANC001_EVT_CHGED 2 #define T10$K_TXR4ANC001_STS_AVAIL 0 #define T10$K_TXR4ANC001_STS_BUSY 1 #define T10$K_TXR4ANC001_STS_RSVD 2 #define T10$K_TXR4ANC001_CHG_NOCHG 0 #define T10$K_TXR4ANC001_CHG_CFEAT 1 #define T10$K_TXR4ANC001_CHG_NFEAT 2 #define T10$K_TXR4ANC001_CHG_RESET 3 #define T10$K_TXR4ANC001_CHG_CFIRM 4 #define T10$K_TXR4ANC001_CHG_CINQD 5 #define T10$K_TXR4ANC010_EVT_NOCHG 0 #define T10$K_TXR4ANC010_EVT_CHGOK 1 #define T10$K_TXR4ANC010_EVT_CHGNG 2 #define T10$K_TXR4ANC010_STS_RSVD 0 #define T10$K_TXR4ANC010_STS_ACTIVE 1 #define T10$K_TXR4ANC010_STS_IDLE 2 #define T10$K_TXR4ANC010_STS_STNDBY 3 #define T10$K_TXR4ANC010_STS_SLEEP 4 #define T10$K_TXR4ANC011_EVT_NOCHG 0 #define T10$K_TXR4ANC011_EVT_KEYDN 1 #define T10$K_TXR4ANC011_EVT_KEYUP 2 #define T10$K_TXR4ANC011_EVT_EXTREQ 3 #define T10$K_TXR4ANC011_STS_READY 0 #define T10$K_TXR4ANC011_STS_OTHPRV 1 #define T10$K_TXR4ANC011_EXT_NOREQ 0 #define T10$K_TXR4ANC011_EXT_OVRUN 1 #define T10$K_TXR4ANC011_EXT_PLAY 257 #define T10$K_TXR4ANC011_EXT_REW 258 #define T10$K_TXR4ANC011_EXT_FFWD 259 #define T10$K_TXR4ANC011_EXT_PAUS 260 #define T10$K_TXR4ANC011_EXT_STOP 262 #define T10$K_TXR4ANC011_EXT_ASCL 512 #define T10$K_TXR4ANC011_EXT_ASCH 767 #define T10$K_TXR4ANC011_EXT_VNDL 61440 #define T10$K_TXR4ANC011_EXT_VNDH 65535 #define T10$K_TXR4ANC100_MED_NOCHG 0 #define T10$K_TXR4ANC100_MED_EJECT 1 #define T10$K_TXR4ANC100_MED_NEW 2 #define T10$K_TXR4ANC100_MED_REM 3 #define T10$K_TXR4ANC100_MED_CHG 4 #define T10$K_TXR4ANC100_MED_BGFDON 5 #define T10$K_TXR4ANC100_MED_BGFRES 6 #define T10$K_TXR4ANC110_BSY_NOCHG 0 #define T10$K_TXR4ANC110_BSY_CHG 1 #define T10$K_TXR4ANC110_BSY_NOT 0 #define T10$K_TXR4ANC110_BSY_BUSY 1 struct txr4a { unsigned short int t10$w_txr4a_data_length; __struct { unsigned t10$v_txr4a_gesn_curr_event : 3; unsigned t10$v_txc4a_flags_rsvd4 : 4; unsigned t10$v_txr4a_nea : 1; } t10$r_txr4a_flags; __struct { unsigned t10$v_txr4a_gesn_rsvd0 : 1; unsigned t10$v_txr4a_gesn_opchange : 1; unsigned t10$v_txr4a_gesn_power : 1; unsigned t10$v_txr4a_gesn_extreq : 1; unsigned t10$v_txr4a_gesn_media : 1; unsigned t10$v_txr4a_gesn_multi : 1; unsigned t10$v_txr4a_gesn_devbusy : 1; unsigned t10$v_txr4a_gesn_rsvd7 : 1; } t10$r_txr4a_supp_classes; __union { __struct { __struct { unsigned t10$v_txr4anc001_event : 4; unsigned t10$v_txr4anc001_rsvd4 : 4; } t10$r_txr4anc001_flags; __struct { unsigned t10$v_txr4anc001_status : 4; unsigned t10$v_txr4anc001_rsvd4 : 3; unsigned t10$v_txr4anc001_persprev : 1; } t10$r_txr4anc001_state; unsigned short int t10$w_txr4anc001_change; } t10$r_txr4anc001; __struct { __struct { unsigned t10$v_txr4anc010_event : 4; unsigned t10$v_txr4anc010_rsvd4 : 4; } t10$r_txr4anc010_flags; unsigned char t10$b_txr4anc010_status; unsigned char t10$b_txr4anc010_rsvd2; unsigned char t10$b_txr4anc010_rsvd3; } t10$r_txr4anc010; __struct { __struct { unsigned t10$v_txr4anc011_event : 4; unsigned t10$v_txr4anc011_rsvd4 : 4; } t10$r_txr4anc011_flags; __struct { unsigned t10$v_txr4anc011_status : 4; unsigned t10$v_txr4anc011_rsvd4 : 3; unsigned t10$v_txr4anc011_persprev : 1; } t10$r_txr4anc011_state; unsigned short int t10$w_txr4anc011_extreq; } t10$r_txr4anc011; __struct { __struct { unsigned t10$v_txr4anc100_event : 4; unsigned t10$v_txr4anc100_rsvd4 : 4; } t10$r_txr4anc100_flags; __struct { unsigned t10$v_txr4anc100_door_open : 1; unsigned t10$v_txr4anc100_media_present : 1; unsigned t10$v_txr4anc100_rsvd3 : 6; } t10$r_txr4anc100_status; unsigned char t10$b_txr4anc100_rsvd2; unsigned char t10$b_txr4anc100_rsvd3; } t10$r_txr4anc100; __struct { __struct { unsigned t10$v_txr4anc110_event : 4; unsigned t10$v_txr4anc110_rsvd4 : 4; } t10$r_txr4anc110_flags; unsigned char t10$b_txr4anc110_bsy_status; unsigned short int t10$w_txr4anc110_time; } t10$r_txr4anc110; } t10$r_txr4a_ncoverlay; } ; #if !defined(__VAXC) #define t10$v_txr4a_gesn_curr_event t10$r_txr4a_flags.t10$v_txr4a_gesn_curr_event #define t10$v_txr4a_nea t10$r_txr4a_flags.t10$v_txr4a_nea #define t10$v_txr4a_gesn_opchange t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_opchange #define t10$v_txr4a_gesn_power t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_power #define t10$v_txr4a_gesn_extreq t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_extreq #define t10$v_txr4a_gesn_media t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_media #define t10$v_txr4a_gesn_multi t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_multi #define t10$v_txr4a_gesn_devbusy t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_devbusy #define t10$r_txr4anc001 t10$r_txr4a_ncoverlay.t10$r_txr4anc001 #define t10$r_txr4anc001_flags t10$r_txr4anc001.t10$r_txr4anc001_flags #define t10$v_txr4anc001_event t10$r_txr4anc001_flags.t10$v_txr4anc001_event #define t10$r_txr4anc001_state t10$r_txr4anc001.t10$r_txr4anc001_state #define t10$v_txr4anc001_status t10$r_txr4anc001_state.t10$v_txr4anc001_status #define t10$v_txr4anc001_persprev t10$r_txr4anc001_state.t10$v_txr4anc001_persprev #define t10$w_txr4anc001_change t10$r_txr4anc001.t10$w_txr4anc001_change #define t10$r_txr4anc010 t10$r_txr4a_ncoverlay.t10$r_txr4anc010 #define t10$r_txr4anc010_flags t10$r_txr4anc010.t10$r_txr4anc010_flags #define t10$v_txr4anc010_event t10$r_txr4anc010_flags.t10$v_txr4anc010_event #define t10$b_txr4anc010_status t10$r_txr4anc010.t10$b_txr4anc010_status #define t10$b_txr4anc010_rsvd2 t10$r_txr4anc010.t10$b_txr4anc010_rsvd2 #define t10$b_txr4anc010_rsvd3 t10$r_txr4anc010.t10$b_txr4anc010_rsvd3 #define t10$r_txr4anc011 t10$r_txr4a_ncoverlay.t10$r_txr4anc011 #define t10$r_txr4anc011_flags t10$r_txr4anc011.t10$r_txr4anc011_flags #define t10$v_txr4anc011_event t10$r_txr4anc011_flags.t10$v_txr4anc011_event #define t10$r_txr4anc011_state t10$r_txr4anc011.t10$r_txr4anc011_state #define t10$v_txr4anc011_status t10$r_txr4anc011_state.t10$v_txr4anc011_status #define t10$v_txr4anc011_persprev t10$r_txr4anc011_state.t10$v_txr4anc011_persprev #define t10$w_txr4anc011_extreq t10$r_txr4anc011.t10$w_txr4anc011_extreq #define t10$r_txr4anc100 t10$r_txr4a_ncoverlay.t10$r_txr4anc100 #define t10$r_txr4anc100_flags t10$r_txr4anc100.t10$r_txr4anc100_flags #define t10$v_txr4anc100_event t10$r_txr4anc100_flags.t10$v_txr4anc100_event #define t10$r_txr4anc100_status t10$r_txr4anc100.t10$r_txr4anc100_status #define t10$v_txr4anc100_door_open t10$r_txr4anc100_status.t10$v_txr4anc100_door_open #define t10$v_txr4anc100_media_present t10$r_txr4anc100_status.t10$v_txr4anc100_media_present #define t10$b_txr4anc100_rsvd2 t10$r_txr4anc100.t10$b_txr4anc100_rsvd2 #define t10$b_txr4anc100_rsvd3 t10$r_txr4anc100.t10$b_txr4anc100_rsvd3 #define t10$r_txr4anc110 t10$r_txr4a_ncoverlay.t10$r_txr4anc110 #define t10$r_txr4anc110_flags t10$r_txr4anc110.t10$r_txr4anc110_flags #define t10$v_txr4anc110_event t10$r_txr4anc110_flags.t10$v_txr4anc110_event #define t10$b_txr4anc110_bsy_status t10$r_txr4anc110.t10$b_txr4anc110_bsy_status #define t10$w_txr4anc110_time t10$r_txr4anc110.t10$w_txr4anc110_time #endif /* #if !defined(__VAXC) */ struct txc51 { unsigned char t10$b_txc51_opcode; unsigned char t10$b_txc51_rsvd1; unsigned char t10$b_txc51_rsvd2; unsigned char t10$b_txc51_rsvd3; unsigned char t10$b_txc51_rsvd4; unsigned char t10$b_txc51_rsvd5; unsigned char t10$b_txc51_rsvd6; unsigned short int t10$w_txc51_length; unsigned char t10$b_txc51_control; } ; #define T10$K_TXR51_DSTAT_EMP 0 #define T10$K_TXR51_DSTAT_INC 1 #define T10$K_TXR51_DSTAT_FIN 2 #define T10$K_TXR51_DSTAT_OTH 3 #define T10$K_TXR51_SSTAT_EMP 0 #define T10$K_TXR51_SSTAT_INC 1 #define T10$K_TXR51_SSTAT_RSV 2 #define T10$K_TXR51_SSTAT_OK 3 #define T10$K_TXR51_BGFS_UNF 0 #define T10$K_TXR51_BGFS_PAUS 1 #define T10$K_TXR51_BGFS_UNDW 2 #define T10$K_TXR51_BGFS_FMTD 3 #define T10$K_TXR51_CDTYP_CDROM 0 #define T10$K_TXR51_CDTYP_CDI 16 #define T10$K_TXR51_CDTYP_CDXA 32 #define T10$K_TXR51_CDTYP_OTHER 255 struct txr51 { unsigned short int t10$w_txr51_length; __struct { unsigned t10$v_txr51_disk_status : 2; unsigned t10$v_txr51_sess_status : 2; unsigned t10$v_txr51_erasable : 1; unsigned t10$v_txr51_rsvd25 : 1; unsigned t10$v_fill_1_ : 2; } t10$r_txr51_state; unsigned char t10$b_txr51_1st_track; unsigned char t10$b_txr51_sess_lsb; unsigned char t10$b_txr51_1st_track_lsb; unsigned char t10$b_txr51_last_track_lsb; __struct { unsigned t10$v_txr51_bgf_status : 2; unsigned t10$v_txr51_dbit : 1; unsigned t10$v_txr51_rsvd73 : 1; unsigned t10$v_txr51_uru : 1; unsigned t10$v_txr51_dbc_v : 1; unsigned t10$v_txr51_did_v : 1; unsigned t10$v_fill_2_ : 1; } t10$r_txr51_format; unsigned char t10$b_txr51_disktype; unsigned char t10$b_txr51_sess_msb; unsigned char t10$b_txr51_1st_track_msb; unsigned char t10$b_txr51_last_track_msb; unsigned int t10$l_txr51_disk_id; unsigned int t10$l_txr51_leadin_addr; unsigned int t10$l_txr51_leadout_addr; unsigned int t10$l_txr51_barcode; unsigned char t10$b_txr51_rsvd32; unsigned char t10$b_txr51_opc_tables; __struct { unsigned short int t10$w_txr51_speed; unsigned char t10$x_txr51_opc_vendor_data [6]; } t10$r_txr51opc [32]; } ; #if !defined(__VAXC) #define t10$v_txr51_disk_status t10$r_txr51_state.t10$v_txr51_disk_status #define t10$v_txr51_sess_status t10$r_txr51_state.t10$v_txr51_sess_status #define t10$v_txr51_erasable t10$r_txr51_state.t10$v_txr51_erasable #define t10$v_txr51_bgf_status t10$r_txr51_format.t10$v_txr51_bgf_status #define t10$v_txr51_dbit t10$r_txr51_format.t10$v_txr51_dbit #define t10$v_txr51_uru t10$r_txr51_format.t10$v_txr51_uru #define t10$v_txr51_dbc_v t10$r_txr51_format.t10$v_txr51_dbc_v #define t10$v_txr51_did_v t10$r_txr51_format.t10$v_txr51_did_v #define t10$w_txr51_speed t10$w_txr51_speed #define t10$x_txr51_opc_vendor_data t10$x_txr51_opc_vendor_data #endif /* #if !defined(__VAXC) */ #define T10$K_TXC52_LBA 0 #define T10$K_TXC52_TRACK_RZONE 1 #define T10$K_TXC52_SESSION 2 #define T10$K_TXC52_RSVD 3 struct txc52 { unsigned char t10$b_txc52_opcode; __struct { unsigned t10$v_txc52_addr_num : 2; unsigned t10$v_txc52_flag_fill : 6; } t10$r_txc52_flags; unsigned int t10$l_txc52_address; unsigned char t10$b_txc52_rsvd6; unsigned short int t10$w_txc52_alloc_len; unsigned char t10$b_txc52_control; } ; #if !defined(__VAXC) #define t10$v_txc52_addr_num t10$r_txc52_flags.t10$v_txc52_addr_num #endif /* #if !defined(__VAXC) */ #define T10$M_QSUB_AUD_MASK 13 #define T10$M_QSUB_DATA_MASK 4 #define T10$M_QSUB_COPY_MASK 2 #define T10$K_QSUB_00X0 0 #define T10$K_QSUB_00X1 1 #define T10$K_QSUB_10X0 8 #define T10$K_QSUB_10X1 9 #define T10$K_QSUB_01X0 4 #define T10$K_QSUB_01X1 5 #define T10$K_QSUB_DDCD 4 #define T10$K_TX52_SESSION 2 #define T10$K_TX52_RSVD 3 #define T10$K_DATA_MODE1 1 #define T10$K_DATA_MODE2 2 #define T10$K_DATA_UNKNOWN 15 struct txr52 { unsigned short int t10$w_txr52_data_length; unsigned char t10$b_txr52_track_lsb; unsigned char t10$b_txr52_sess_lsb; unsigned char t10$b_txr52_fill4; __struct { unsigned t10$v_txr52_trk_mode : 4; unsigned t10$v_txr52_copy : 1; unsigned t10$v_txr52_damage : 1; unsigned t10$v_txr52_rsvd6 : 2; } t10$r_txr52_flags5; __struct { unsigned t10$v_txr52_data_mode : 4; unsigned t10$v_txr52_fp : 1; unsigned t10$v_txr52_pck_inc : 1; unsigned t10$v_txr52_blank : 1; unsigned t10$v_txr52_rt : 1; } t10$r_txr52_flags6; __struct { unsigned t10$v_txr52_nwa_v : 1; unsigned t10$v_txr52_lra_v : 1; unsigned t10$v_txr52_flags7_rsvd6 : 6; } t10$r_txr52_flags7; unsigned int t10$l_txr52_track_start; unsigned int t10$l_txr52_next_write; unsigned int t10$l_txr52_free_blocks; unsigned int t10$l_txr52_block_factor; unsigned int t10$l_txr52_track_size; unsigned int t10$l_txr52_last_address; unsigned char t10$b_txr52_track_msb; unsigned char t10$b_txr52_sess_msb; unsigned short int t10$w_txr52_fill34; } ; #if !defined(__VAXC) #define t10$v_txr52_trk_mode t10$r_txr52_flags5.t10$v_txr52_trk_mode #define t10$v_txr52_copy t10$r_txr52_flags5.t10$v_txr52_copy #define t10$v_txr52_damage t10$r_txr52_flags5.t10$v_txr52_damage #define t10$v_txr52_data_mode t10$r_txr52_flags6.t10$v_txr52_data_mode #define t10$v_txr52_fp t10$r_txr52_flags6.t10$v_txr52_fp #define t10$v_txr52_pck_inc t10$r_txr52_flags6.t10$v_txr52_pck_inc #define t10$v_txr52_blank t10$r_txr52_flags6.t10$v_txr52_blank #define t10$v_txr52_rt t10$r_txr52_flags6.t10$v_txr52_rt #define t10$v_txr52_nwa_v t10$r_txr52_flags7.t10$v_txr52_nwa_v #define t10$v_txr52_lra_v t10$r_txr52_flags7.t10$v_txr52_lra_v #endif /* #if !defined(__VAXC) */ struct txc53 { unsigned char t10$b_txc53_opcode; unsigned char t10$b_txc53_rsvd1; unsigned char t10$b_txc53_rsvd2; unsigned char t10$b_txc53_rsvd3; unsigned char t10$b_txc53_rsvd4; unsigned int t10$l_txc53_sectors; unsigned char t10$b_txc53_control; } ; struct txc55 { unsigned char t10$b_txc55_opcode; __struct { unsigned t10$v_txc55_sp : 1; unsigned t10$v_txc55_fill11 : 3; unsigned t10$v_txc55_pf : 1; unsigned t10$v_txc55_fill15 : 3; } t10$r_txc55_flags; unsigned char t10$b_txc55_fill20; unsigned char t10$b_txc55_fill30; unsigned char t10$b_txc55_fill40; unsigned char t10$b_txc55_fill50; unsigned char t10$b_txc55_fill60; unsigned short int t10$w_txc55_length; unsigned char t10$b_txc55_control; } ; #if !defined(__VAXC) #define t10$v_txc55_sp t10$r_txc55_flags.t10$v_txc55_sp #define t10$v_txc55_pf t10$r_txc55_flags.t10$v_txc55_pf #endif /* #if !defined(__VAXC) */ #define T10$K_TXC5B_FUNC_FMT 0 #define T10$K_TXC5B_FUNC_TRK 1 #define T10$K_TXC5B_FUNC_SES 2 #define T10$K_TXC5B_FUNC_SPC 3 #define T10$K_TXC5B_FUNC_SESFD 5 #define T10$K_TXC5B_FINALIZE 154 struct txc5b { unsigned char t10$b_txc5b_opcode; __struct { unsigned t10$v_txc5b_fl_immed : 1; unsigned t10$v_txc5b_fl_fill : 7; } t10$r_txc5b_flags; __struct { unsigned t10$v_txc5b_func_close : 3; unsigned t10$v_txc5b_func_fill : 5; } t10$r_txc5b_func; unsigned char t10$b_txc5b_rsvd30; unsigned short int t10$w_txc5b_track; unsigned char t10$b_txc5b_rsvd6; unsigned char t10$b_txc5b_rsvd7; unsigned char t10$b_txc5b_rsvd8; unsigned char t10$b_txc5b_control; } ; #if !defined(__VAXC) #define t10$v_txc5b_fl_immed t10$r_txc5b_flags.t10$v_txc5b_fl_immed #define t10$v_txc5b_func_close t10$r_txc5b_func.t10$v_txc5b_func_close #endif /* #if !defined(__VAXC) */ #define T10$K_MP_MMCAP 42 #define T10$K_MP_WRITEPARAM 5 #define T10$K_MP_TMO_PROT 5 #define T10$K_TXC5A_PC_CURR 0 #define T10$K_TXC5A_PC_CHNG 1 #define T10$K_TXC5A_PC_DFLT 2 #define T10$K_TXC5A_PC_SAVE 3 struct txc5a { unsigned char t10$b_txc5a_opcode; __struct { unsigned t10$v_txc5a_fill10 : 3; unsigned t10$v_txc5a_dbd : 1; unsigned t10$v_txc5a_llba : 1; unsigned t10$v_txc5a_fill15 : 3; } t10$r_txc5a_flags; __struct { unsigned t10$v_txc5a_page : 6; unsigned t10$v_txc5a_ctrl : 2; } t10$r_txc5a_pagectrl; unsigned char t10$b_txc5a_subpage; unsigned char t10$b_txc5a_fill40; unsigned char t10$b_txc5a_fill50; unsigned char t10$b_txc5a_fill60; unsigned short int t10$w_txc5a_length; unsigned char t10$b_txc5a_control; } ; #if !defined(__VAXC) #define t10$v_txc5a_dbd t10$r_txc5a_flags.t10$v_txc5a_dbd #define t10$v_txc5a_llba t10$r_txc5a_flags.t10$v_txc5a_llba #define t10$v_txc5a_fill15 t10$r_txc5a_flags.t10$v_txc5a_fill15 #define t10$v_txc5a_page t10$r_txc5a_pagectrl.t10$v_txc5a_page #define t10$v_txc5a_ctrl t10$r_txc5a_pagectrl.t10$v_txc5a_ctrl #endif /* #if !defined(__VAXC) */ struct txca8 { unsigned char t10$b_txca8_opcode; __struct { unsigned t10$v_txca8_reladr : 1; unsigned t10$v_txca8_fill1 : 2; unsigned t10$v_txca8_fua : 1; unsigned t10$v_txca8_dpo : 1; unsigned t10$v_txca8_fill2 : 3; } t10$r_txca8_flags1; unsigned int t10$l_txca8_lba; unsigned int t10$l_txca8_blocks; __struct { unsigned t10$v_txca8_fill100 : 7; unsigned t10$v_txca8_stream : 1; } t10$r_txca8_flags10; unsigned char t10$b_txca8_control; } ; #if !defined(__VAXC) #define t10$v_txca8_reladr t10$r_txca8_flags1.t10$v_txca8_reladr #define t10$v_txca8_fua t10$r_txca8_flags1.t10$v_txca8_fua #define t10$v_txca8_dpo t10$r_txca8_flags1.t10$v_txca8_dpo #define t10$v_txca8_stream t10$r_txca8_flags10.t10$v_txca8_stream #endif /* #if !defined(__VAXC) */ #define T10$K_BT_FULL 0 #define T10$K_BT_QUICK 1 #define T10$K_BT_TRACK 2 #define T10$K_BT_UNRES_TRACK 3 #define T10$K_BT_TAIL_TRACK 4 #define T10$K_BT_UNCLOSE_SESS 5 #define T10$K_BT_ERASE_SESS 6 struct txca1 { unsigned char t10$b_txca1_opcode; __struct { unsigned t10$v_txca1_blanktype : 3; unsigned t10$v_txca1_fill13 : 1; unsigned t10$v_txca1_immed : 1; unsigned t10$v_txca1_fill15 : 3; } t10$r_txca1_flags1; unsigned int t10$l_txca1_start; unsigned char t10$b_txca1_fill60; unsigned char t10$b_txca1_fill70; unsigned char t10$b_txca1_fill80; unsigned char t10$b_txca1_fill90; unsigned char t10$b_txca1_filla0; unsigned char t10$b_txca1_control; } ; #if !defined(__VAXC) #define t10$v_txca1_blanktype t10$r_txca1_flags1.t10$v_txca1_blanktype #define t10$v_txca1_immed t10$r_txca1_flags1.t10$v_txca1_immed #endif /* #if !defined(__VAXC) */ struct txcaa { unsigned char t10$b_txcaa_opcode; __struct { unsigned t10$v_txcaa_fill1 : 3; unsigned t10$v_txcaa_fua : 1; unsigned t10$v_txcaa_fill2 : 4; } t10$r_txcaa_flags; unsigned int t10$l_txcaa_lba; unsigned int t10$l_txcaa_blocks; __struct { unsigned t10$v_txcaa_fill100 : 7; unsigned t10$v_txcaa_stream : 1; } t10$r_txcaa_flags10; unsigned char t10$b_txcaa_control; } ; #if !defined(__VAXC) #define t10$v_txcaa_fua t10$r_txcaa_flags.t10$v_txcaa_fua #define t10$v_txcaa_stream t10$r_txcaa_flags10.t10$v_txcaa_stream #endif /* #if !defined(__VAXC) */ #define T10$K_TXCAD_FMT_PHY 0 struct txcad { unsigned char t10$b_txcad_opcode; unsigned char t10$b_txcad_fill1; unsigned int t10$l_txcad_addr; unsigned char t10$b_txcad_layer; unsigned char t10$b_txcad_format; unsigned short int t10$w_txcad_length; __struct { unsigned t10$v_txcad_rsvd : 6; unsigned t10$v_txcad_agid : 2; } t10$r_txcad_flags; unsigned char t10$b_txcad_control; } ; #if !defined(__VAXC) #define t10$v_txcad_agid t10$r_txcad_flags.t10$v_txcad_agid #endif /* #if !defined(__VAXC) */ #define T10$K_TXRAD_FIXED 4 #define T10$K_BKT_DVDROM 0 #define T10$K_BKT_DVDRAM 1 #define T10$K_BKT_DVDMR 2 #define T10$K_BKT_DVDMRW 3 #define T10$K_BKT_DVDRW 9 #define T10$K_BKT_DVDPR 10 #define T10$K_MXR_1X 0 #define T10$K_MXR_2X 1 #define T10$K_MXR_4X 2 #define T10$K_MXR_8X 3 #define T10$K_MXR_NOTSPEC 15 #define T10$K_DSZ_120MM 0 #define T10$K_DSZ_80MM 0 #define T10$K_TXRAD_LENGTH 2052 struct txrad { unsigned short int t10$w_txrad_data_length; unsigned char t10$b_txab_rsvd1; unsigned char t10$b_txab_rsvd2; __union { __struct { __struct { unsigned t10$v_txrad_fc00_partver : 4; unsigned t10$v_txrad_fc00_bktype : 4; unsigned t10$v_txrad_fc00_maxrate : 4; unsigned t10$v_txrad_fc00_dvdsize : 4; unsigned t10$v_txrad_fc00_romlayer : 1; unsigned t10$v_txrad_fc00_r_layer : 1; unsigned t10$v_txrad_fc00_rw_layer : 1; unsigned t10$v_txrad_fc00_unklayer : 1; unsigned t10$v_txrad_fc00_tkpath : 1; unsigned t10$v_txrad_fc00_layers : 2; unsigned t10$v_txrad_fc00_rsvd27 : 1; unsigned t10$v_txrad_fc00_tkdens : 4; unsigned t10$v_txrad_fc00_lndense : 4; } t10$r_txrad_fc00_hdr; unsigned int t10$l_txrad_fc00_datalo; unsigned int t10$l_txrad_fc00_datahi; unsigned int t10$l_txrad_fc00_zerohi; __struct { unsigned t10$v_txrad_fc00_fill100 : 7; unsigned t10$v_txrad_fc00_bca : 4; unsigned t10$v_fill_3_ : 5; } t10$r_txrads_fc00_bca; unsigned char t10$b_txrad_fc00_junque [2030]; } t10$r_txrad_fc00; } t10$r_txrad_fcoverlay; } ; #if !defined(__VAXC) #define t10$r_txrad_fc00 t10$r_txrad_fcoverlay.t10$r_txrad_fc00 #define t10$r_txrad_fc00_hdr t10$r_txrad_fc00.t10$r_txrad_fc00_hdr #define t10$v_txrad_fc00_partver t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_partver #define t10$v_txrad_fc00_bktype t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_bktype #define t10$v_txrad_fc00_maxrate t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_maxrate #define t10$v_txrad_fc00_dvdsize t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_dvdsize #define t10$v_txrad_fc00_romlayer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_romlayer #define t10$v_txrad_fc00_r_layer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_r_layer #define t10$v_txrad_fc00_rw_layer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_rw_layer #define t10$v_txrad_fc00_unklayer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_unklayer #define t10$v_txrad_fc00_tkpath t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_tkpath #define t10$v_txrad_fc00_layers t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_layers #define t10$v_txrad_fc00_tkdens t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_tkdens #define t10$v_txrad_fc00_lndense t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_lndense #define t10$l_txrad_fc00_datalo t10$r_txrad_fc00.t10$l_txrad_fc00_datalo #define t10$l_txrad_fc00_datahi t10$r_txrad_fc00.t10$l_txrad_fc00_datahi #define t10$l_txrad_fc00_zerohi t10$r_txrad_fc00.t10$l_txrad_fc00_zerohi #define t10$r_txrads_fc00_bca t10$r_txrad_fc00.t10$r_txrads_fc00_bca #define t10$v_txrad_fc00_bca t10$r_txrads_fc00_bca.t10$v_txrad_fc00_bca #define t10$b_txrad_fc00_junque t10$r_txrad_fc00.t10$b_txrad_fc00_junque #endif /* #if !defined(__VAXC) */ #define T10$K_STRM_PERFORM 0 #define T10$K_STRM_UNUSABLE 1 #define T10$K_STRM_DEFECT 2 #define T10$K_STRM_WRITE 3 #define T10$K_STRM_DBI 4 #define T10$K_STRM_DBI_CACHE 5 struct txcb6 { unsigned char t10$b_txcb6_opcode; unsigned char t10$b_txcb6_fill1; unsigned char t10$b_txcb6_fill2; unsigned char t10$b_txcb6_fill3; unsigned char t10$b_txcb6_fill4; unsigned char t10$b_txcb6_fill5; unsigned char t10$b_txcb6_fill6; unsigned char t10$b_txcb6_fill7; unsigned char t10$b_txcb6_type; unsigned short int t10$w_txcb6_length; unsigned char t10$b_txcb6_control; } ; struct txpb6 { __struct { unsigned t10$v_txpb6_ra : 1; unsigned t10$v_txpb6_exact : 1; unsigned t10$v_txpb6_rdd : 1; unsigned t10$v_txpb6_wrc : 2; unsigned t10$v_txpb6_rsvd05 : 3; } t10$r_txpb6_flags; unsigned char t10$b_txpb6_fill1; unsigned char t10$b_txpb6_fill2; unsigned char t10$b_txpb6_fill3; unsigned int t10$l_txpb6_start_lba; unsigned int t10$l_txpb6_end_lba; unsigned int t10$l_txpb6_read_size; unsigned int t10$l_txpb6_read_time; unsigned int t10$l_txpb6_write_size; unsigned int t10$l_txpb6_write_time; } ; #if !defined(__VAXC) #define t10$v_txpb6_ra t10$r_txpb6_flags.t10$v_txpb6_ra #define t10$v_txpb6_exact t10$r_txpb6_flags.t10$v_txpb6_exact #define t10$v_txpb6_rdd t10$r_txpb6_flags.t10$v_txpb6_rdd #define t10$v_txpb6_wrc t10$r_txpb6_flags.t10$v_txpb6_wrc #endif /* #if !defined(__VAXC) */ #define T10$K_TXCBB_RC_CLV 0 #define T10$K_TXCBB_RC_CAV 1 struct txcbb { unsigned char t10$b_txcbb_opcode; __struct { unsigned t10$v_txcbb_rotcon : 2; unsigned t10$v_txcbb_fill1 : 3; unsigned t10$v_txcbb_lun : 3; } t10$r_txcbb_flags1; unsigned short int t10$w_txcbb_read_speed; unsigned short int t10$w_txcbb_write_speed; unsigned char t10$b_txcbb_rsvd06; unsigned char t10$b_txcbb_rsvd07; unsigned char t10$b_txcbb_rsvd08; unsigned char t10$b_txcbb_rsvd09; unsigned char t10$b_txcbb_rsvd10; unsigned char t10$b_txcbb_control; } ; #if !defined(__VAXC) #define t10$v_txcbb_rotcon t10$r_txcbb_flags1.t10$v_txcbb_rotcon #define t10$v_txcbb_lun t10$r_txcbb_flags1.t10$v_txcbb_lun #endif /* #if !defined(__VAXC) */ struct dqiosb { unsigned short int t13$w_dqio_status; __union { __struct { unsigned int t13$l_dqio_bytes; unsigned char t13$b_dqio_rsvd_xfr; unsigned char t13$b_dqio_sensekey; } t13$r_dqio_transfer; __struct { unsigned short int t13$w_dqio_rsvd_rst; unsigned int t13$l_dqio_resets; } t13$r_dqio_reset; } t13$r_dqio_overlay; } ; #if !defined(__VAXC) #define t13$r_dqio_transfer t13$r_dqio_overlay.t13$r_dqio_transfer #define t13$l_dqio_bytes t13$r_dqio_transfer.t13$l_dqio_bytes #define t13$b_dqio_rsvd_xfr t13$r_dqio_transfer.t13$b_dqio_rsvd_xfr #define t13$b_dqio_sensekey t13$r_dqio_transfer.t13$b_dqio_sensekey #define t13$r_dqio_reset t13$r_dqio_overlay.t13$r_dqio_reset #define t13$w_dqio_rsvd_rst t13$r_dqio_reset.t13$w_dqio_rsvd_rst #define t13$l_dqio_resets t13$r_dqio_reset.t13$l_dqio_resets #endif /* #if !defined(__VAXC) */ #define T13$K_T13_NOP 0 #define T13$K_T13_SOFT_RESET 8 #define T13$K_T13_RECALIBRATE 16 #define T13$K_T13_READ_SECS 32 #define T13$K_T13_READ_SECS_WO_RET 33 #define T13$K_T13_READ_LONG 34 #define T13$K_T13_READ_LONG_WO_RET 35 #define T13$K_T13_WRITE_SECS 48 #define T13$K_T13_WRITE_SECS_WO_RET 49 #define T13$K_T13_WRITE_LONG 50 #define T13$K_T13_WRITE_LONG_WO_RET 51 #define T13$K_T13_WRITE_VFY 60 #define T13$K_T13_READ_VFY_SECS 64 #define T13$K_T13_READ_VFY_SECS_WO_RET 65 #define T13$K_T13_FORMAT_TRACK 80 #define T13$K_T13_SEEK 112 #define T13$K_T13_80 128 #define T13$K_T13_EXEC_DEV_DIAGS 144 #define T13$K_T13_INIT_DEV_PARAMS 145 #define T13$K_T13_DOWNLOAD_UCODE 146 #define T13$K_T13_STANDBY_IMMED_94 148 #define T13$K_T13_IDLE_IMMED_95 149 #define T13$K_T13_STANDBY_96 150 #define T13$K_T13_IDLE_97 151 #define T13$K_T13_CHK_PWR_MODE_98 152 #define T13$K_T13_SLEEP_99 153 #define T13$K_T13_PACKET_CMD 160 #define T13$K_T13_PACKET_IDENTIFY 161 #define T13$K_T13_SMART_DSBL_OPS 176 #define T13$K_T13_SMART_ATTR_AUTO 176 #define T13$K_T13_SMART_ENBL_OPER 176 #define T13$K_T13_SMART_ATTR_THRESH 176 #define T13$K_T13_SMART_RETURN_STATUS 176 #define T13$K_T13_SEC_SET_PSWD_OBS 186 #define T13$K_T13_SEC_UNLOCK_OBS 187 #define T13$K_T13_SEC_ERASE_PREP_OBS 188 #define T13$K_T13_SEC_ERASE_UNIT_OBS 189 #define T13$K_T13_SEC_FREEZE_LOCK_OBS 190 #define T13$K_T13_SEC_DSBL_PSWD_OBS 191 #define T13$K_T13_READ_MULTIPLE 196 #define T13$K_T13_WRITE_MULTI 197 #define T13$K_T13_SET_MULTI_MODE 198 #define T13$K_T13_READ_DMA 200 #define T13$K_T13_READ_DMA_WO_RET 201 #define T13$K_T13_WRITE_DMA 202 #define T13$K_T13_WRITE_DMA_WO_RET 203 #define T13$K_T13_DOOR_LOCK 222 #define T13$K_T13_DOOR_UNLOCK 223 #define T13$K_T13_STANDBY_IMMED_E0 224 #define T13$K_T13_IDLE_IMMED_E1 225 #define T13$K_T13_STANDBY_E2 226 #define T13$K_T13_IDLE_E3 227 #define T13$K_T13_READ_BUFFER 228 #define T13$K_T13_CHK_PWR_MODE_E5 229 #define T13$K_T13_SLEEP_E6 230 #define T13$K_T13_WRITE_BUFFER 232 #define T13$K_T13_IDENTIFY_DEV 236 #define T13$K_T13_MEDIA_EJECT 237 #define T13$K_T13_IDENTIFY_DEV_DMA 238 #define T13$K_T13_SET_FEATURES 239 #define T13$K_T13_SECUR_SET_PSWD 241 #define T13$K_T13_SECUR_UNLOCK 242 #define T13$K_T13_SECUR_ERASE_PREPARE 243 #define T13$K_T13_SECUR_ERASE_UNIT 244 #define T13$K_T13_SECUR_FREEZE_LOCK 245 #define T13$K_T13_SECUR_DSBL_PSWD 246 struct atacmd { unsigned char t13$b_cmd_features; unsigned char t13$b_cmd_sector_count; unsigned char t13$b_cmd_sector_number; unsigned short int t13$w_cmd_cylinder; __struct { unsigned t13$v_cmd_na03 : 4; unsigned t13$v_cmd_dev : 1; unsigned t13$v_cmd_na57 : 3; } t13$r_cmd_device_head; unsigned char t13$b_cmd_command; } ; #if !defined(__VAXC) #define t13$v_cmd_dev t13$r_cmd_device_head.t13$v_cmd_dev #endif /* #if !defined(__VAXC) */ #define T10$K_BLK_SIZE_512 512 #define T10$K_BLK_SIZE_2048 2048 #define T10$K_BLK_SIZE_2352 2352 #define T10$K_T10_TEST_UNIT_READY 0 #define T10$K_T10_REQUEST_SENSE 3 #define T10$K_T10_FORMAT_UNIT 4 #define T10$K_T10_READ_6 8 #define T10$K_T10_WRITE_6 10 #define T10$K_T10_INQUIRY 18 #define T10$K_T10_MODE_SELECT_6 21 #define T10$K_T10_MODE_SENSE_6 26 #define T10$K_T10_START_STOP_UNIT 27 #define T10$K_T10_PREVENT_ALLOW 30 #define T10$K_T10_READ_FORMAT_CAP 35 #define T10$K_T10_READ_CAPACITY 37 #define T10$K_T10_READ_10 40 #define T10$K_T10_WRITE_10 42 #define T10$K_T10_SEEK 43 #define T10$K_T10_WRITE_VERIFY_10 46 #define T10$K_T10_SYNCHRONIZE_CACHE 53 #define T10$K_T10_WRITE_BUFFER 59 #define T10$K_T10_READ_SUBCHANNEL 66 #define T10$K_T10_READ_TOC_PMA_ATIP 67 #define T10$K_T10_READ_HEADER 68 #define T10$K_T10_PLAY_AUDIO_10 69 #define T10$K_T10_GET_CONFIG 70 #define T10$K_T10_PLAY_AUDIO_MSF 71 #define T10$K_T10_GET_EVENT_STATUS 74 #define T10$K_T10_PAUSE_RESUME 75 #define T10$K_T10_STOP_PLAY_SCAN 78 #define T10$K_T10_READ_DISK_INFO 81 #define T10$K_T10_READ_TRACK_INFO 82 #define T10$K_T10_RESERVE_TRACK 83 #define T10$K_T10_SEND_OPC_INFO 84 #define T10$K_T10_MODE_SELECT_10 85 #define T10$K_T10_REPAIR_TRACK 88 #define T10$K_T10_READ_MASTER_CUE 89 #define T10$K_T10_MODE_SENSE_10 90 #define T10$K_T10_CLOSE_TRACK 91 #define T10$K_T10_READ_BUFFER_CAP 92 #define T10$K_T10_SEND_CUE_SHEET 93 #define T10$K_T10_60 96 #define T10$K_T10_70 112 #define T10$K_T10_80 128 #define T10$K_T10_90 144 #define T10$K_T10_BLANK 161 #define T10$K_T10_SEND_KEY 163 #define T10$K_T10_PLAY_AUDIO_12 165 #define T10$K_T10_LOAD_UNLOAD_CD 166 #define T10$K_T10_READ_12 168 #define T10$K_T10_WRITE_12 170 #define T10$K_T10_READ_DVD_STRUCT 173 #define T10$K_T10_SET_STREAMING 182 #define T10$K_T10_READ_CD_MSF 185 #define T10$K_T10_SCAN 186 #define T10$K_T10_SET_CD_SPEED 187 #define T10$K_T10_PLAY_CD 188 #define T10$K_T10_MECHANISM_STATUS 189 #define T10$K_T10_READ_CD 190 #define T10$K_T10_SEND_DVD_STRUCT 191 #define T10$K_T10_C0 192 #define T10$K_T10_D0 208 #define T10$K_T10_E0 224 #define T10$K_T10_F0 240 struct atapicmd { unsigned char t10$b_sdl_pacifier; } ; struct atar { unsigned char t13$b_atar_error; unsigned char t13$b_atar_sector_count; unsigned char t13$b_atar_sector_number; unsigned short int t13$w_atar_cylinder; __struct { unsigned t13$v_atar_na03 : 4; unsigned t13$v_atar_dev : 1; unsigned t13$v_atar_na57 : 3; } t13$r_atar_device_head; __struct { unsigned t13$v_atar_err : 1; unsigned t13$v_atar_na12 : 2; unsigned t13$v_atar_drq : 1; unsigned t13$v_atar_na4 : 1; unsigned t13$v_atar_df : 1; unsigned t13$v_atar_drdy : 1; unsigned t13$v_atar_bsy : 1; } t13$r_atar_status; } ; #if !defined(__VAXC) #define t13$v_atar_dev t13$r_atar_device_head.t13$v_atar_dev #define t13$v_atar_err t13$r_atar_status.t13$v_atar_err #define t13$v_atar_drq t13$r_atar_status.t13$v_atar_drq #define t13$v_atar_df t13$r_atar_status.t13$v_atar_df #define t13$v_atar_drdy t13$r_atar_status.t13$v_atar_drdy #define t13$v_atar_bsy t13$r_atar_status.t13$v_atar_bsy #endif /* #if !defined(__VAXC) */ #define T13$K_IPDPS_12BYTE 0 #define T13$K_IPDPS_16BYTE 1 #define T13$K_IPDPS_RSVD10 2 #define T13$K_IPDPS_RSVD11 3 #define T13$K_IPDDRQ_3MS 0 #define T13$K_IPDDRQ_RSVD01 1 #define T13$K_IPDDRQ_50US 2 #define T13$K_IPDDRQ_RSVD11 3 #define T13$K_IPDA_RSVD00 0 #define T13$K_IPDA_RSVD01 1 #define T13$K_IPDA_ATAPI 2 #define T13$K_IPDA_RSVD11 3 #define T13$K_SCFG_SETFSU_INC 14280 #define T13$K_SCFG_SETFSU_CMP 14220 #define T13$K_SCFG_AUTOSU_INC 35955 #define T13$K_SCFG_AUTOSU_CMP 51255 #define T13$V_MAJV_ATA3 3 #define T13$M_MAJV_ATA3 8 #define T13$V_MAJV_ATAPI4 4 #define T13$M_MAJV_ATAPI4 16 #define T13$V_MAJV_ATAPI5 5 #define T13$M_MAJV_ATAPI5 32 #define T13$V_MAJV_ATAPI6 6 #define T13$M_MAJV_ATAPI6 64 #define T13$V_MAJV_ATAPI7 7 #define T13$M_MAJV_ATAPI7 128 #define T13$V_MAJV_ATAPI8 8 #define T13$M_MAJV_ATAPI8 256 #define T13$V_MAJV_ATAPI9 9 #define T13$M_MAJV_ATAPI9 512 #define T13$V_MAJV_ATAPI10 10 #define T13$M_MAJV_ATAPI10 1024 #define T13$V_MAJV_ATAPI11 11 #define T13$M_MAJV_ATAPI11 2048 #define T13$V_MAJV_ATAPI12 12 #define T13$M_MAJV_ATAPI12 4096 #define T13$V_MAJV_ATAPI13 13 #define T13$M_MAJV_ATAPI13 8192 #define T13$V_MAJV_ATAPI14 14 #define T13$M_MAJV_ATAPI14 16384 #define T13$K_HRR_UNIT_RSVD 0 #define T13$K_HRR_UNIT_PLUG 1 #define T13$K_HRR_UNIT_CSEL 2 #define T13$K_HRR_UNIT_OTHR 3 #define T13$K_SIGNATURE 165 struct atapira1 { __union { __struct { unsigned t13$v_id_rsvd00 : 1; unsigned t13$v_id_retired01 : 1; unsigned t13$v_id_incomplete : 1; unsigned t13$v_id_retired0305 : 3; unsigned t13$v_id_obsolete06 : 1; unsigned t13$v_id_removable : 1; unsigned t13$v_id_retired0814 : 7; unsigned t13$v_id_ata : 1; } t13$r_id_general; __struct { unsigned t13$v_ipd_packet_size : 2; unsigned t13$v_ipd_incomplete : 1; unsigned t13$v_ipd_rsvd34 : 2; unsigned t13$v_ipd_drq : 2; unsigned t13$v_ipd_removable : 1; unsigned t13$v_ipd_cmdpktset : 5; unsigned t13$v_ipd_rsvd13 : 1; unsigned t13$v_ipd_atapi : 2; } t13$r_ipd_general; } t13$r_id_ipd_overlay; unsigned short int t13$w_chs_cylinders; unsigned short int t13$w_specific_config; unsigned short int t13$w_chs_heads; unsigned short int t13$w_retired04; unsigned short int t13$w_retired05; unsigned short int t13$w_chs_sectors_per_track; unsigned short int t13$w_retired07; unsigned short int t13$w_retired08; unsigned short int t13$w_retired09; char t13$t_serial_number [20]; unsigned short int t13$w_retired20; unsigned short int t13$w_retired21; unsigned short int t13$w_obsolete22; char t13$t_firmware_revision [20]; char t13$t_model_number [40]; __struct { unsigned t13$v_sector_transfer : 8; unsigned t13$v_hex80 : 8; } t13$r_multiple47; unsigned short int t13$w_reserved48; __struct { unsigned t13$v_retired0007 : 8; unsigned t13$v_dma_supported : 1; unsigned t13$v_lba_supported : 1; unsigned t13$v_iordy_selectable : 1; unsigned t13$v_iordy_supported : 1; unsigned t13$v_ata_reset : 1; unsigned t13$v_timer_compliant : 1; unsigned t13$v_command_queuing : 1; unsigned t13$v_interleaved_dma : 1; } t13$r_capabilities49; __struct { unsigned t13$v_local_timer : 1; unsigned t13$v_reserved0113 : 13; unsigned t13$v_c50_mb1 : 1; unsigned t13$v_c50_mb0 : 1; } t13$r_capabilities50; unsigned short int t13$w_retired51; unsigned short int t13$w_retired52; __struct { unsigned t13$v_valid5458 : 1; unsigned t13$v_valid6470 : 1; unsigned t13$v_valid88 : 1; unsigned t13$v_reserved0315 : 13; } t13$r_field_status53; unsigned short int t13$w_retired54; unsigned short int t13$w_retired55; unsigned short int t13$w_retired56; unsigned short int t13$w_retired57; unsigned short int t13$w_retired58; __struct { unsigned t13$v_sectors_per_interrupt : 8; unsigned t13$v_valid : 1; unsigned t13$v_reserved915 : 7; } t13$r_interrupt_sectors59; unsigned int t13$l_user_sectors; unsigned short int t13$w_obsolete62; __struct { unsigned t13$v_mw_dma_mode_0_ok : 1; unsigned t13$v_mw_dma_mode_1_ok : 1; unsigned t13$v_mw_dma_mode_2_ok : 1; unsigned t13$v_reserved0307 : 5; unsigned t13$v_mw_dma_mode_0_on : 1; unsigned t13$v_mw_dma_mode_1_on : 1; unsigned t13$v_mw_dma_mode_2_on : 1; unsigned t13$v_reserved1115 : 5; } t13$r_mw_dma_mode63; __struct { unsigned t13$v_pio_modes_supp : 8; unsigned t13$v_reserved0815 : 8; } t13$r_adv_pio_mode64; unsigned short int t13$w_min_mw_dma_cycle; unsigned short int t13$w_rec_mw_dma_cycle; unsigned short int t13$w_min_pio_cycle; unsigned short int t13$w_min_pio_iordy_cycle; unsigned short int t13$w_reserved69; unsigned short int t13$w_reserved70; unsigned short int t13$w_reserved71; unsigned short int t13$w_reserved72; unsigned short int t13$w_reserved73; unsigned short int t13$w_reserved74; __struct { unsigned t13$v_max_queue_depth : 5; unsigned t13$v_reserved615 : 11; } t13$r_queue_depth75; unsigned short int t13$w_reserved76; unsigned short int t13$w_reserved77; unsigned short int t13$w_reserved78; unsigned short int t13$w_reserved79; unsigned short int t13$w_major_version; unsigned short int t13$w_minor_version; __struct { unsigned t13$v_smart : 1; unsigned t13$v_security : 1; unsigned t13$v_removable : 1; unsigned t13$v_power : 1; unsigned t13$v_packet : 1; unsigned t13$v_write_cache : 1; unsigned t13$v_lookahead : 1; unsigned t13$v_release_int : 1; unsigned t13$v_service_int : 1; unsigned t13$v_device_reset : 1; unsigned t13$v_host_protected : 1; unsigned t13$v_obsolete11 : 1; unsigned t13$v_write_buffer : 1; unsigned t13$v_read_buffer : 1; unsigned t13$v_nop : 1; unsigned t13$v_obsolete15 : 1; unsigned t13$v_microcode : 1; unsigned t13$v_dma_queued : 1; unsigned t13$v_cfa : 1; unsigned t13$v_adv_power : 1; unsigned t13$v_media_status : 1; unsigned t13$v_pwrup_standby : 1; unsigned t13$v_host_spinup : 1; unsigned t13$v_rsvd_area_boot : 1; unsigned t13$v_set_max_security : 1; unsigned t13$v_auto_accoustics : 1; unsigned t13$v_48b_addressing : 1; unsigned t13$v_config_overlay : 1; unsigned t13$v_flush_cache : 1; unsigned t13$v_flush_cache_ext : 1; unsigned t13$v_fs82_mb1 : 1; unsigned t13$v_fs82_mb0 : 1; } t13$r_command_sets82; __struct { unsigned t13$v_reserved0013 : 14; unsigned t13$v_fs84_mb1 : 1; unsigned t13$v_fs84_mb0 : 1; } t13$r_feature_sets84; __struct { unsigned t13$v_smart_on : 1; unsigned t13$v_security_on : 1; unsigned t13$v_removable_on : 1; unsigned t13$v_power_on : 1; unsigned t13$v_packet_on : 1; unsigned t13$v_write_cache_on : 1; unsigned t13$v_lookahead_on : 1; unsigned t13$v_release_int_on : 1; unsigned t13$v_service_int_on : 1; unsigned t13$v_device_reset_on : 1; unsigned t13$v_host_protected_on : 1; unsigned t13$v_obsolete11_on : 1; unsigned t13$v_write_buffer_on : 1; unsigned t13$v_read_buffer_on : 1; unsigned t13$v_nop_on : 1; unsigned t13$v_obsolete15_on : 1; unsigned t13$v_microcode_on : 1; unsigned t13$v_dma_queued_on : 1; unsigned t13$v_cfa_on : 1; unsigned t13$v_adv_power_on : 1; unsigned t13$v_media_status_on : 1; unsigned t13$v_pwrup_standby_on : 1; unsigned t13$v_host_spinup_on : 1; unsigned t13$v_rsvd_area_boot_on : 1; unsigned t13$v_set_max_security_on : 1; unsigned t13$v_auto_accoustics_on : 1; unsigned t13$v_48b_addressing_on : 1; unsigned t13$v_config_overlay_on : 1; unsigned t13$v_flush_cache_on : 1; unsigned t13$v_flush_cache_ext_on : 1; unsigned t13$v_cs85_mb1_on : 1; unsigned t13$v_cs85_mb0_on : 1; } t13$r_command_sets_on85; __struct { unsigned t13$v_reserved0013 : 14; unsigned t13$v_fs87_mb1 : 1; unsigned t13$v_fs87_mb0 : 1; } t13$r_feature_sets_on87; __struct { unsigned t13$v_ul_dma_mode_0_ok : 1; unsigned t13$v_ul_dma_mode_1_ok : 1; unsigned t13$v_ul_dma_mode_2_ok : 1; unsigned t13$v_ul_reserved0307 : 5; unsigned t13$v_ul_dma_mode_0_on : 1; unsigned t13$v_ul_dma_mode_1_on : 1; unsigned t13$v_ul_dma_mode_2_on : 1; unsigned t13$v_ul_reserved1115 : 5; } t13$r_ul_dma_mode88; unsigned short int t13$w_erase_time; unsigned short int t13$w_adv_erase_time; unsigned short int t13$w_adv_power; unsigned short int t13$w_pwd_revision; __struct { unsigned t13$v_hrr_d0_mb1 : 1; unsigned t13$v_hrr_d0_unit : 2; unsigned t13$v_hrr_d0_diag_ok : 1; unsigned t13$v_hrr_d0_pdiag_ok : 1; unsigned t13$v_hrr_d0_dasp_ok : 1; unsigned t13$v_hrr_d0_confused : 1; unsigned t13$v_hrr_d1_mb1 : 1; unsigned t13$v_hrr_d1_unit : 2; unsigned t13$v_hrr_d1_pdiag_ok : 1; unsigned t13$v_hrr_d1_rsvd : 1; unsigned t13$v_hrr_cblid_hi : 1; unsigned t13$v_hrr_mb1 : 1; unsigned t13$v_hrr_mb0 : 1; unsigned t13$v_fill_4_ : 1; } t13$r_hw_reset_results; __struct { unsigned t13$v_al_current : 8; unsigned t13$v_al_recommended : 8; } t13$r_accoustic_level; unsigned short int t13$w_reserved95; unsigned short int t13$w_reserved96; unsigned short int t13$w_reserved97; unsigned short int t13$w_reserved98; unsigned short int t13$w_reserved99; unsigned __int64 t13$q_48b_addr_limit; unsigned short int t13$w_reserved104126 [23]; __struct { unsigned t13$v_rms_supported : 2; unsigned t13$v_ul_reserved0315 : 14; } t13$r_rms_features127; __struct { unsigned t13$v_security_support : 1; unsigned t13$v_security_enabled : 1; unsigned t13$v_security_locked : 1; unsigned t13$v_security_frozen : 1; unsigned t13$v_security_expired : 1; unsigned t13$v_security_adv_erase : 1; unsigned t13$v_security_reserved0607 : 2; unsigned t13$v_security_maximum : 1; unsigned t13$v_security_reserved0915 : 7; } t13$r_security_status128; unsigned short int t13$x_vendor_data [31]; unsigned short int t13$w_reserved160254 [95]; __struct { unsigned t13$v_signature : 8; unsigned t13$v_checksum : 8; } t13$r_integrity_word255; } ; #if !defined(__VAXC) #define t13$r_id_general t13$r_id_ipd_overlay.t13$r_id_general #define t13$v_id_incomplete t13$r_id_general.t13$v_id_incomplete #define t13$v_id_removable t13$r_id_general.t13$v_id_removable #define t13$v_id_ata t13$r_id_general.t13$v_id_ata #define t13$r_ipd_general t13$r_id_ipd_overlay.t13$r_ipd_general #define t13$v_ipd_packet_size t13$r_ipd_general.t13$v_ipd_packet_size #define t13$v_ipd_incomplete t13$r_ipd_general.t13$v_ipd_incomplete #define t13$v_ipd_rsvd34 t13$r_ipd_general.t13$v_ipd_rsvd34 #define t13$v_ipd_drq t13$r_ipd_general.t13$v_ipd_drq #define t13$v_ipd_removable t13$r_ipd_general.t13$v_ipd_removable #define t13$v_ipd_cmdpktset t13$r_ipd_general.t13$v_ipd_cmdpktset #define t13$v_ipd_atapi t13$r_ipd_general.t13$v_ipd_atapi #define t13$v_sector_transfer t13$r_multiple47.t13$v_sector_transfer #define t13$v_hex80 t13$r_multiple47.t13$v_hex80 #define t13$v_dma_supported t13$r_capabilities49.t13$v_dma_supported #define t13$v_lba_supported t13$r_capabilities49.t13$v_lba_supported #define t13$v_iordy_selectable t13$r_capabilities49.t13$v_iordy_selectable #define t13$v_iordy_supported t13$r_capabilities49.t13$v_iordy_supported #define t13$v_ata_reset t13$r_capabilities49.t13$v_ata_reset #define t13$v_timer_compliant t13$r_capabilities49.t13$v_timer_compliant #define t13$v_command_queuing t13$r_capabilities49.t13$v_command_queuing #define t13$v_interleaved_dma t13$r_capabilities49.t13$v_interleaved_dma #define t13$v_local_timer t13$r_capabilities50.t13$v_local_timer #define t13$v_c50_mb1 t13$r_capabilities50.t13$v_c50_mb1 #define t13$v_c50_mb0 t13$r_capabilities50.t13$v_c50_mb0 #define t13$v_valid5458 t13$r_field_status53.t13$v_valid5458 #define t13$v_valid6470 t13$r_field_status53.t13$v_valid6470 #define t13$v_valid88 t13$r_field_status53.t13$v_valid88 #define t13$v_sectors_per_interrupt t13$r_interrupt_sectors59.t13$v_sectors_per_interrupt #define t13$v_valid t13$r_interrupt_sectors59.t13$v_valid #define t13$v_mw_dma_mode_0_ok t13$r_mw_dma_mode63.t13$v_mw_dma_mode_0_ok #define t13$v_mw_dma_mode_1_ok t13$r_mw_dma_mode63.t13$v_mw_dma_mode_1_ok #define t13$v_mw_dma_mode_2_ok t13$r_mw_dma_mode63.t13$v_mw_dma_mode_2_ok #define t13$v_mw_dma_mode_0_on t13$r_mw_dma_mode63.t13$v_mw_dma_mode_0_on #define t13$v_mw_dma_mode_1_on t13$r_mw_dma_mode63.t13$v_mw_dma_mode_1_on #define t13$v_mw_dma_mode_2_on t13$r_mw_dma_mode63.t13$v_mw_dma_mode_2_on #define t13$v_pio_modes_supp t13$r_adv_pio_mode64.t13$v_pio_modes_supp #define t13$v_max_queue_depth t13$r_queue_depth75.t13$v_max_queue_depth #define t13$v_smart t13$r_command_sets82.t13$v_smart #define t13$v_security t13$r_command_sets82.t13$v_security #define t13$v_removable t13$r_command_sets82.t13$v_removable #define t13$v_power t13$r_command_sets82.t13$v_power #define t13$v_packet t13$r_command_sets82.t13$v_packet #define t13$v_write_cache t13$r_command_sets82.t13$v_write_cache #define t13$v_lookahead t13$r_command_sets82.t13$v_lookahead #define t13$v_release_int t13$r_command_sets82.t13$v_release_int #define t13$v_service_int t13$r_command_sets82.t13$v_service_int #define t13$v_device_reset t13$r_command_sets82.t13$v_device_reset #define t13$v_host_protected t13$r_command_sets82.t13$v_host_protected #define t13$v_write_buffer t13$r_command_sets82.t13$v_write_buffer #define t13$v_read_buffer t13$r_command_sets82.t13$v_read_buffer #define t13$v_nop t13$r_command_sets82.t13$v_nop #define t13$v_microcode t13$r_command_sets82.t13$v_microcode #define t13$v_dma_queued t13$r_command_sets82.t13$v_dma_queued #define t13$v_cfa t13$r_command_sets82.t13$v_cfa #define t13$v_adv_power t13$r_command_sets82.t13$v_adv_power #define t13$v_media_status t13$r_command_sets82.t13$v_media_status #define t13$v_pwrup_standby t13$r_command_sets82.t13$v_pwrup_standby #define t13$v_host_spinup t13$r_command_sets82.t13$v_host_spinup #define t13$v_rsvd_area_boot t13$r_command_sets82.t13$v_rsvd_area_boot #define t13$v_set_max_security t13$r_command_sets82.t13$v_set_max_security #define t13$v_auto_accoustics t13$r_command_sets82.t13$v_auto_accoustics #define t13$v_48b_addressing t13$r_command_sets82.t13$v_48b_addressing #define t13$v_config_overlay t13$r_command_sets82.t13$v_config_overlay #define t13$v_flush_cache t13$r_command_sets82.t13$v_flush_cache #define t13$v_flush_cache_ext t13$r_command_sets82.t13$v_flush_cache_ext #define t13$v_fs82_mb1 t13$r_command_sets82.t13$v_fs82_mb1 #define t13$v_fs82_mb0 t13$r_command_sets82.t13$v_fs82_mb0 #define t13$v_fs84_mb1 t13$r_feature_sets84.t13$v_fs84_mb1 #define t13$v_fs84_mb0 t13$r_feature_sets84.t13$v_fs84_mb0 #define t13$v_smart_on t13$r_command_sets_on85.t13$v_smart_on #define t13$v_security_on t13$r_command_sets_on85.t13$v_security_on #define t13$v_removable_on t13$r_command_sets_on85.t13$v_removable_on #define t13$v_power_on t13$r_command_sets_on85.t13$v_power_on #define t13$v_packet_on t13$r_command_sets_on85.t13$v_packet_on #define t13$v_write_cache_on t13$r_command_sets_on85.t13$v_write_cache_on #define t13$v_lookahead_on t13$r_command_sets_on85.t13$v_lookahead_on #define t13$v_release_int_on t13$r_command_sets_on85.t13$v_release_int_on #define t13$v_service_int_on t13$r_command_sets_on85.t13$v_service_int_on #define t13$v_device_reset_on t13$r_command_sets_on85.t13$v_device_reset_on #define t13$v_host_protected_on t13$r_command_sets_on85.t13$v_host_protected_on #define t13$v_write_buffer_on t13$r_command_sets_on85.t13$v_write_buffer_on #define t13$v_read_buffer_on t13$r_command_sets_on85.t13$v_read_buffer_on #define t13$v_nop_on t13$r_command_sets_on85.t13$v_nop_on #define t13$v_microcode_on t13$r_command_sets_on85.t13$v_microcode_on #define t13$v_dma_queued_on t13$r_command_sets_on85.t13$v_dma_queued_on #define t13$v_cfa_on t13$r_command_sets_on85.t13$v_cfa_on #define t13$v_adv_power_on t13$r_command_sets_on85.t13$v_adv_power_on #define t13$v_media_status_on t13$r_command_sets_on85.t13$v_media_status_on #define t13$v_pwrup_standby_on t13$r_command_sets_on85.t13$v_pwrup_standby_on #define t13$v_host_spinup_on t13$r_command_sets_on85.t13$v_host_spinup_on #define t13$v_rsvd_area_boot_on t13$r_command_sets_on85.t13$v_rsvd_area_boot_on #define t13$v_set_max_security_on t13$r_command_sets_on85.t13$v_set_max_security_on #define t13$v_auto_accoustics_on t13$r_command_sets_on85.t13$v_auto_accoustics_on #define t13$v_48b_addressing_on t13$r_command_sets_on85.t13$v_48b_addressing_on #define t13$v_config_overlay_on t13$r_command_sets_on85.t13$v_config_overlay_on #define t13$v_flush_cache_on t13$r_command_sets_on85.t13$v_flush_cache_on #define t13$v_flush_cache_ext_on t13$r_command_sets_on85.t13$v_flush_cache_ext_on #define t13$v_cs85_mb1_on t13$r_command_sets_on85.t13$v_cs85_mb1_on #define t13$v_cs85_mb0_on t13$r_command_sets_on85.t13$v_cs85_mb0_on #define t13$v_fs87_mb1 t13$r_feature_sets_on87.t13$v_fs87_mb1 #define t13$v_fs87_mb0 t13$r_feature_sets_on87.t13$v_fs87_mb0 #define t13$v_ul_dma_mode_0_ok t13$r_ul_dma_mode88.t13$v_ul_dma_mode_0_ok #define t13$v_ul_dma_mode_1_ok t13$r_ul_dma_mode88.t13$v_ul_dma_mode_1_ok #define t13$v_ul_dma_mode_2_ok t13$r_ul_dma_mode88.t13$v_ul_dma_mode_2_ok #define t13$v_ul_dma_mode_0_on t13$r_ul_dma_mode88.t13$v_ul_dma_mode_0_on #define t13$v_ul_dma_mode_1_on t13$r_ul_dma_mode88.t13$v_ul_dma_mode_1_on #define t13$v_ul_dma_mode_2_on t13$r_ul_dma_mode88.t13$v_ul_dma_mode_2_on #define t13$v_hrr_d0_mb1 t13$r_hw_reset_results.t13$v_hrr_d0_mb1 #define t13$v_hrr_d0_unit t13$r_hw_reset_results.t13$v_hrr_d0_unit #define t13$v_hrr_d0_diag_ok t13$r_hw_reset_results.t13$v_hrr_d0_diag_ok #define t13$v_hrr_d0_pdiag_ok t13$r_hw_reset_results.t13$v_hrr_d0_pdiag_ok #define t13$v_hrr_d0_dasp_ok t13$r_hw_reset_results.t13$v_hrr_d0_dasp_ok #define t13$v_hrr_d0_confused t13$r_hw_reset_results.t13$v_hrr_d0_confused #define t13$v_hrr_d1_mb1 t13$r_hw_reset_results.t13$v_hrr_d1_mb1 #define t13$v_hrr_d1_unit t13$r_hw_reset_results.t13$v_hrr_d1_unit #define t13$v_hrr_d1_pdiag_ok t13$r_hw_reset_results.t13$v_hrr_d1_pdiag_ok #define t13$v_hrr_d1_rsvd t13$r_hw_reset_results.t13$v_hrr_d1_rsvd #define t13$v_hrr_cblid_hi t13$r_hw_reset_results.t13$v_hrr_cblid_hi #define t13$v_hrr_mb1 t13$r_hw_reset_results.t13$v_hrr_mb1 #define t13$v_hrr_mb0 t13$r_hw_reset_results.t13$v_hrr_mb0 #define t13$v_al_current t13$r_accoustic_level.t13$v_al_current #define t13$v_al_recommended t13$r_accoustic_level.t13$v_al_recommended #define t13$v_rms_supported t13$r_rms_features127.t13$v_rms_supported #define t13$v_security_support t13$r_security_status128.t13$v_security_support #define t13$v_security_enabled t13$r_security_status128.t13$v_security_enabled #define t13$v_security_locked t13$r_security_status128.t13$v_security_locked #define t13$v_security_frozen t13$r_security_status128.t13$v_security_frozen #define t13$v_security_expired t13$r_security_status128.t13$v_security_expired #define t13$v_security_adv_erase t13$r_security_status128.t13$v_security_adv_erase #define t13$v_security_maximum t13$r_security_status128.t13$v_security_maximum #define t13$v_signature t13$r_integrity_word255.t13$v_signature #define t13$v_checksum t13$r_integrity_word255.t13$v_checksum #endif /* #if !defined(__VAXC) */ #define T13$S_SERIAL_NUMBER 20 #define T13$S_FIRMWARE_REVISION 20 #define T13$S_MODEL_NUMBER 40 struct atapira1a { short int t13$w_atapira1a_sdl_pacifier; } ; struct mphdr10 { unsigned short int t10$w_mphdr10_data_length; unsigned char t10$b_mphdr10_medium_type; unsigned char t10$b_mphdr10_fill3; unsigned char t10$b_mphdr10_fill4; unsigned char t10$b_mphdr10_fill5; unsigned short int t10$w_mphdr10_block_length; } ; struct mphdr6 { unsigned char t10$b_mphdr6_data_length; unsigned char t10$b_mphdr6_medium_type; unsigned char t10$b_mphdr6_device; unsigned char t10$b_mphdr6_block_length; } ; struct mpbdg { unsigned char t10$b_mpbdg_density; unsigned char t10$x_mpbdg_blocks [3]; unsigned char t10$b_mpbdg_rsvd; unsigned char t10$x_mpbdg_block_size [3]; } ; struct mpbdda { unsigned int t10$l_mpbdda_blocks; unsigned char t10$b_mpbdda_density; unsigned char t10$x_mpbdda_block_size [3]; } ; #define T10$K_WRT_PACKET 0 #define T10$K_WRT_TAO 1 #define T10$K_WRT_SAO 2 #define T10$K_WRT_DAO 2 #define T10$K_WRT_RAW 3 #define T10$K_QTM_2AUD_PE0 2 #define T10$K_QTM_2AUD_PE0_NOCOPY 0 #define T10$K_QTM_2AUD_PE5015 3 #define T10$K_QTM_2AUD_PE5015_NOCOPY 1 #define T10$K_QTM_4AUD_PE0 10 #define T10$K_QTM_4AUD_PE0_NOCOPY 8 #define T10$K_QTM_4AUD_PE5015 11 #define T10$K_QTM_4AUD_PE5015_NOCOPY 9 #define T10$K_QTM_DATA_UNINT 6 #define T10$K_QTM_DATA_UNINT_NOCOPY 4 #define T10$K_QTM_DATA_INCRE 7 #define T10$K_QTM_DATA_INCRE_NOCOPY 5 #define T10$M_QTM_COPYALLOWED 2 #define T10$K_MSC_NO_B0 0 #define T10$K_MSC_MAX_B0 1 #define T10$K_MSC_RSVD 16 #define T10$K_MSC_OK 17 #define T10$K_BT_RAW_2352 0 #define T10$K_BT_RAW_2368 1 #define T10$K_BT_RAW_2448 2 #define T10$K_BT_RAW_2448_RAW 3 #define T10$K_BT_MODE_1 8 #define T10$K_BT_MODE_2_2336 9 #define T10$K_BT_MODE_2_2048 10 #define T10$K_BT_MODE_2_2056 11 #define T10$K_BT_MODE_2_2324 12 #define T10$K_BT_MODE_2_2332 13 #define T10$K_SF_CDDA_CDROM 0 #define T10$K_SF_CDI 16 #define T10$K_SF_CDROMXA_DDCD 32 #define T10$K_MP05_BASE_LENGTH 50 #define T10$K_MP05_MAX_LENGTH 54 struct mp05 { __struct { unsigned t10$v_mp05_hdr_mpcode : 6; unsigned t10$v_mp05_hdr_fill1 : 1; unsigned t10$v_mp05_hdr_ps : 1; } t10$r_mp05_hdr_flags; unsigned char t10$b_mp05_length; __struct { unsigned t10$v_mp05_2_wrt_type : 4; unsigned t10$v_mp05_2_test_wr : 1; unsigned t10$v_mp05_2_ls_v : 1; unsigned t10$v_mp05_2_bufe : 1; unsigned t10$v_mp05_2_fill1 : 1; } t10$r_mp05_2_flags; __struct { unsigned t10$v_mp05_3_trk_mode : 4; unsigned t10$v_mp05_3_copyprot : 1; unsigned t10$v_mp05_3_fixedpkt : 1; unsigned t10$v_mp05_3_multisess : 2; } t10$r_mp05_3_flags; __struct { unsigned t10$v_mp05_4_bt_type : 4; unsigned t10$v_mp05_4_fill : 4; } t10$r_mp05_4_flags; unsigned char t10$b_mp05_link_size; unsigned char t10$b_mp05_fill6; __struct { unsigned t10$v_mp05_7_code : 6; unsigned t10$v_mp05_7_fill : 2; } t10$r_mp05_7_flags; unsigned char t10$b_mp05_sess_format; unsigned char t10$b_mp05_fill9; unsigned int t10$l_mp05_pkt_size; unsigned short int t10$w_mp05_audio_pause; unsigned char t10$x_mp05_media_cat_num [16]; unsigned char t10$x_mp05_isrc [14]; unsigned char t10$x_mp05_subheader [4]; unsigned char t10$x_mp05_vendor_data [4]; } ; #if !defined(__VAXC) #define t10$v_mp05_hdr_mpcode t10$r_mp05_hdr_flags.t10$v_mp05_hdr_mpcode #define t10$v_mp05_hdr_ps t10$r_mp05_hdr_flags.t10$v_mp05_hdr_ps #define t10$v_mp05_2_wrt_type t10$r_mp05_2_flags.t10$v_mp05_2_wrt_type #define t10$v_mp05_2_test_wr t10$r_mp05_2_flags.t10$v_mp05_2_test_wr #define t10$v_mp05_2_ls_v t10$r_mp05_2_flags.t10$v_mp05_2_ls_v #define t10$v_mp05_2_bufe t10$r_mp05_2_flags.t10$v_mp05_2_bufe #define t10$v_mp05_3_trk_mode t10$r_mp05_3_flags.t10$v_mp05_3_trk_mode #define t10$v_mp05_3_copyprot t10$r_mp05_3_flags.t10$v_mp05_3_copyprot #define t10$v_mp05_3_fixedpkt t10$r_mp05_3_flags.t10$v_mp05_3_fixedpkt #define t10$v_mp05_3_multisess t10$r_mp05_3_flags.t10$v_mp05_3_multisess #define t10$v_mp05_4_bt_type t10$r_mp05_4_flags.t10$v_mp05_4_bt_type #define t10$v_mp05_7_code t10$r_mp05_7_flags.t10$v_mp05_7_code #endif /* #if !defined(__VAXC) */ struct mp1d { __struct { unsigned t10$v_mp1d_hdr_mpcode : 6; unsigned t10$v_mp1d_hdr_fill1 : 1; unsigned t10$v_mp1d_hdr_ps : 1; } t10$r_mp1d_hdr_flags; unsigned char t10$b_mp1d_length; unsigned char t10$b_mp1d_fill2; unsigned char t10$b_mp1d_fill3; __struct { unsigned t10$v_mp1d_4_swpp : 1; unsigned t10$v_mp1d_4_disp : 1; unsigned t10$v_mp1d_4_tmoe : 1; unsigned t10$v_mp1d_4_g3enable : 1; unsigned t10$v_mp1d_4_fill47 : 4; } t10$r_mp1d_4_flags; unsigned char t10$b_mp1d_fill5; unsigned short int t10$w_mp1d_g1timeout; unsigned short int t10$w_mp1d_g2timeout; } ; #if !defined(__VAXC) #define t10$v_mp1d_hdr_mpcode t10$r_mp1d_hdr_flags.t10$v_mp1d_hdr_mpcode #define t10$v_mp1d_hdr_ps t10$r_mp1d_hdr_flags.t10$v_mp1d_hdr_ps #define t10$v_mp1d_4_swpp t10$r_mp1d_4_flags.t10$v_mp1d_4_swpp #define t10$v_mp1d_4_disp t10$r_mp1d_4_flags.t10$v_mp1d_4_disp #define t10$v_mp1d_4_tmoe t10$r_mp1d_4_flags.t10$v_mp1d_4_tmoe #define t10$v_mp1d_4_g3enable t10$r_mp1d_4_flags.t10$v_mp1d_4_g3enable #endif /* #if !defined(__VAXC) */ #define T10$K_LMT_CADDY 0 #define T10$K_LMT_TRAY 1 #define T10$K_LMT_POPUP 2 #define T10$K_LMT_RSVD011 3 #define T10$K_LMT_CHANGER 4 #define T10$K_LMT_MAGAZINE 5 #define T10$K_LMT_RSVD110 6 #define T10$K_LMT_RSVD111 7 #define T10$K_SPEED_X1 1723 #define T10$K_SPEED_XMAX 65535 #define T10$K_MP2A_X0001 1722 #define T10$K_MP2A_X0002 3445 #define T10$K_MP2A_X0004 6890 #define T10$K_MP2A_X0008 13781 #define T10$K_MP2A_X0010 17226 #define T10$K_MP2A_X0012 20671 #define T10$K_MP2A_X0016 27562 #define T10$K_MP2A_X0020 34453 #define T10$K_MP2A_X0024 41343 #define T10$K_MP2A_X0032 55125 #define T10$K_MP2A_X0040 68906 #define T10$K_MP2A_X0048 82687 #define T10$K_MP2A_X0052 89578 #define T10$K_MP2A_X0056 96468 #define T10$K_MP2A_X0064 110250 #define T10$K_MP2A_RC_CLV 0 #define T10$K_MP2A_RC_CAV 1 struct mp2a { __struct { unsigned t10$v_mp2a_hdr_mpcode : 6; unsigned t10$v_mp2a_hdr_fill1 : 1; unsigned t10$v_mp2a_hdr_ps : 1; } t10$r_mp2a_hdr_flags; unsigned char t10$b_mp2a_length; __struct { unsigned t10$v_mp2a_2_cdr_rd : 1; unsigned t10$v_mp2a_2_cdrw_rd : 1; unsigned t10$v_mp2a_2_method_2 : 1; unsigned t10$v_mp2a_2_dvdrom_rd : 1; unsigned t10$v_mp2a_2_dvdr_rd : 1; unsigned t10$v_mp2a_2_dvdram_rd : 1; unsigned t10$v_mp2a_2_rsvd6 : 2; } t10$r_mp2a_2_flags; __struct { unsigned t10$v_mp2a_3_cdr_wr : 1; unsigned t10$v_mp2a_3_cdrw_wr : 1; unsigned t10$v_mp2a_3_test_wr : 1; unsigned t10$v_mp2a_3_rsvd3 : 1; unsigned t10$v_mp2a_3_dvdr_wr : 1; unsigned t10$v_mp2a_3_dvdram_wr : 1; unsigned t10$v_mp2a_3_rsvd6 : 2; } t10$r_mp2a_3_flags; __struct { unsigned t10$v_mp2a_4_play : 1; unsigned t10$v_mp2a_4_composite : 1; unsigned t10$v_mp2a_4_digital_1 : 1; unsigned t10$v_mp2a_4_digital_2 : 1; unsigned t10$v_mp2a_4_mode2_form1 : 1; unsigned t10$v_mp2a_4_mode2_form2 : 1; unsigned t10$v_mp2a_4_multisession : 1; unsigned t10$v_mp2a_4_buf : 1; } t10$r_mp2a_4_flags; __struct { unsigned t10$v_mp2a_5_supported : 1; unsigned t10$v_mp2a_5_accurate : 1; unsigned t10$v_mp2a_5_rw : 1; unsigned t10$v_mp2a_5_corrected : 1; unsigned t10$v_mp2a_5_c2pointers : 1; unsigned t10$v_mp2a_5_isrc : 1; unsigned t10$v_mp2a_5_upc : 1; unsigned t10$v_mp2a_5_barcode : 1; } t10$r_mp2a_5_flags; __struct { unsigned t10$v_mp2a_6_lock : 1; unsigned t10$v_mp2a_6_state : 1; unsigned t10$v_mp2a_6_prevent : 1; unsigned t10$v_mp2a_6_eject : 1; unsigned t10$v_mp2a_6_rsvd4 : 1; unsigned t10$v_mp2a_6_loadmechtype : 3; } t10$r_mp2a_6_flags; __struct { unsigned t10$v_mp2a_7_sepvol : 1; unsigned t10$v_mp2a_7_sepmute : 1; unsigned t10$v_mp2a_7_present : 1; unsigned t10$v_mp2a_7_sss : 1; unsigned t10$v_mp2a_7_sidechange : 1; unsigned t10$v_mp2a_7_rw_leadin : 1; unsigned t10$v_mp2a_7_rsvd6 : 2; } t10$r_mp2a_7_flags; unsigned short int t10$w_mp2a_max_read; unsigned short int t10$w_mp2a_vollevels; unsigned short int t10$w_mp2a_bufsize; unsigned short int t10$w_mp2a_curr_read; unsigned char t10$b_mp2a_rsvd16; __struct { unsigned t10$v_mp2a_17_rsvd1 : 1; unsigned t10$v_mp2a_17_bckf : 1; unsigned t10$v_mp2a_17_rck : 1; unsigned t10$v_mp2a_17_lsbf : 1; unsigned t10$v_mp2a_17_length : 2; unsigned t10$v_mp2a_17_rsvd6 : 2; } t10$r_mp2a_17_flags; unsigned short int t10$w_mp2a_max_write; unsigned short int t10$w_mp2a_curr_write; unsigned short int t10$w_mp2a_copymgmt; unsigned char t10$b_mp2a_rsvd240; unsigned char t10$b_mp2a_rsvd250; unsigned char t10$b_mp2a_rsvd260; __struct { unsigned t10$v_mp2a_27_rotcon : 2; unsigned t10$v_mp2a_27_rsvd3 : 6; } t10$r_mp2a_27_flags; unsigned short int t10$w_mp2a_curr_write_unit; unsigned short int t10$w_mp2a_wrtspd_size; __struct { unsigned char t10$b_mp2a_ws_rsvd0; __struct { unsigned t10$v_mp2a_ws_rotcon : 3; unsigned t10$v_mp2a_ws_rsvd3 : 5; } t10$r_mp2a_ws_rotctrl; unsigned short int t10$w_mp2a_write_speed; } t10$r_mp2a_wrtspd [256]; } ; #if !defined(__VAXC) #define t10$v_mp2a_hdr_mpcode t10$r_mp2a_hdr_flags.t10$v_mp2a_hdr_mpcode #define t10$v_mp2a_hdr_ps t10$r_mp2a_hdr_flags.t10$v_mp2a_hdr_ps #define t10$v_mp2a_2_cdr_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_cdr_rd #define t10$v_mp2a_2_cdrw_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_cdrw_rd #define t10$v_mp2a_2_method_2 t10$r_mp2a_2_flags.t10$v_mp2a_2_method_2 #define t10$v_mp2a_2_dvdrom_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_dvdrom_rd #define t10$v_mp2a_2_dvdr_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_dvdr_rd #define t10$v_mp2a_2_dvdram_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_dvdram_rd #define t10$v_mp2a_3_cdr_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_cdr_wr #define t10$v_mp2a_3_cdrw_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_cdrw_wr #define t10$v_mp2a_3_test_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_test_wr #define t10$v_mp2a_3_dvdr_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_dvdr_wr #define t10$v_mp2a_3_dvdram_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_dvdram_wr #define t10$v_mp2a_4_play t10$r_mp2a_4_flags.t10$v_mp2a_4_play #define t10$v_mp2a_4_composite t10$r_mp2a_4_flags.t10$v_mp2a_4_composite #define t10$v_mp2a_4_digital_1 t10$r_mp2a_4_flags.t10$v_mp2a_4_digital_1 #define t10$v_mp2a_4_digital_2 t10$r_mp2a_4_flags.t10$v_mp2a_4_digital_2 #define t10$v_mp2a_4_mode2_form1 t10$r_mp2a_4_flags.t10$v_mp2a_4_mode2_form1 #define t10$v_mp2a_4_mode2_form2 t10$r_mp2a_4_flags.t10$v_mp2a_4_mode2_form2 #define t10$v_mp2a_4_multisession t10$r_mp2a_4_flags.t10$v_mp2a_4_multisession #define t10$v_mp2a_4_buf t10$r_mp2a_4_flags.t10$v_mp2a_4_buf #define t10$v_mp2a_5_supported t10$r_mp2a_5_flags.t10$v_mp2a_5_supported #define t10$v_mp2a_5_accurate t10$r_mp2a_5_flags.t10$v_mp2a_5_accurate #define t10$v_mp2a_5_rw t10$r_mp2a_5_flags.t10$v_mp2a_5_rw #define t10$v_mp2a_5_corrected t10$r_mp2a_5_flags.t10$v_mp2a_5_corrected #define t10$v_mp2a_5_c2pointers t10$r_mp2a_5_flags.t10$v_mp2a_5_c2pointers #define t10$v_mp2a_5_isrc t10$r_mp2a_5_flags.t10$v_mp2a_5_isrc #define t10$v_mp2a_5_upc t10$r_mp2a_5_flags.t10$v_mp2a_5_upc #define t10$v_mp2a_5_barcode t10$r_mp2a_5_flags.t10$v_mp2a_5_barcode #define t10$v_mp2a_6_lock t10$r_mp2a_6_flags.t10$v_mp2a_6_lock #define t10$v_mp2a_6_state t10$r_mp2a_6_flags.t10$v_mp2a_6_state #define t10$v_mp2a_6_prevent t10$r_mp2a_6_flags.t10$v_mp2a_6_prevent #define t10$v_mp2a_6_eject t10$r_mp2a_6_flags.t10$v_mp2a_6_eject #define t10$v_mp2a_6_rsvd4 t10$r_mp2a_6_flags.t10$v_mp2a_6_rsvd4 #define t10$v_mp2a_6_loadmechtype t10$r_mp2a_6_flags.t10$v_mp2a_6_loadmechtype #define t10$v_mp2a_7_sepvol t10$r_mp2a_7_flags.t10$v_mp2a_7_sepvol #define t10$v_mp2a_7_sepmute t10$r_mp2a_7_flags.t10$v_mp2a_7_sepmute #define t10$v_mp2a_7_present t10$r_mp2a_7_flags.t10$v_mp2a_7_present #define t10$v_mp2a_7_sss t10$r_mp2a_7_flags.t10$v_mp2a_7_sss #define t10$v_mp2a_7_sidechange t10$r_mp2a_7_flags.t10$v_mp2a_7_sidechange #define t10$v_mp2a_7_rw_leadin t10$r_mp2a_7_flags.t10$v_mp2a_7_rw_leadin #define t10$v_mp2a_7_rsvd6 t10$r_mp2a_7_flags.t10$v_mp2a_7_rsvd6 #define t10$v_mp2a_17_bckf t10$r_mp2a_17_flags.t10$v_mp2a_17_bckf #define t10$v_mp2a_17_rck t10$r_mp2a_17_flags.t10$v_mp2a_17_rck #define t10$v_mp2a_17_lsbf t10$r_mp2a_17_flags.t10$v_mp2a_17_lsbf #define t10$v_mp2a_17_length t10$r_mp2a_17_flags.t10$v_mp2a_17_length #define t10$v_mp2a_17_rsvd6 t10$r_mp2a_17_flags.t10$v_mp2a_17_rsvd6 #define t10$v_mp2a_27_rotcon t10$r_mp2a_27_flags.t10$v_mp2a_27_rotcon #define t10$b_mp2a_ws_rsvd0 t10$b_mp2a_ws_rsvd0 #define t10$r_mp2a_ws_rotctrl t10$r_mp2a_ws_rotctrl #define t10$v_mp2a_ws_rotcon t10$r_mp2a_ws_rotctrl.t10$v_mp2a_ws_rotcon #define t10$w_mp2a_write_speed t10$w_mp2a_write_speed #endif /* #if !defined(__VAXC) */ struct mp3f { __struct { unsigned t10$v_mp3f_hdr_mpcode : 6; unsigned t10$v_mp3f_hdr_fill1 : 1; unsigned t10$v_mp3f_hdr_ps : 1; } t10$r_mp3f_hdr_flags; } ; #if !defined(__VAXC) #define t10$v_mp3f_hdr_mpcode t10$r_mp3f_hdr_flags.t10$v_mp3f_hdr_mpcode #define t10$v_mp3f_hdr_ps t10$r_mp3f_hdr_flags.t10$v_mp3f_hdr_ps #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __T10DEF_LOADED */