/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:25:58 by OpenVMS SDL EV3-3 */ /* Source: 19-NOV-2009 01:21:59 $1$DGA7274:[LIB_H.SRC]RIHDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $RIHDEF ***/ #ifndef __RIHDEF_LOADED #define __RIHDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*+ */ /* RAD Information Header - Structure containing information about the Resource Affinity Domain (RAD) */ /* characteristics of the current system. This is used for NUMA support. */ /* */ /* */ #define RIH$M_RAD_ENABLE 0x1 #define RIH$M_AFFINITY 0x2 #define RIH$M_SYSTEM_REPL 0x4 #define RIH$M_COPY_SOFT_FAULT 0x8 #define RIH$M_SPECIAL 0x10 #define RIH$M_FORCE_RAD 0x20 #define RIH$M_RAD_POOL 0x40 #define RIH$M_PLATFORM_DECISION 0x80 #define RIH$M_PROCESS_ALLOC 0x30000 #define RIH$M_SWAPPER_ALLOC 0xC0000 #define RIH$M_GLOBAL_ALLOC 0x300000 #define RIH$M_SYSTEM_ALLOC 0xC00000 #define RIH$M_SKIP_COUNT 0xF000000 #define RIH$C_CPU_MASK_OFFSET 64 #define RIH$C_CPU_MASK_BYTES 8 /* CPU Mask size in bytes */ #define RIH$C_CPU_MASK_QUADS 1 /* CPU Mask size in bytes */ #define RIH$C_CPU_MASK_SHIFT 7 /* Shift value to index to a RAD's CPU Mask */ #define RIH$C_MAX_RAD_COUNT 32 /* Maximum supported RADs */ #ifdef __cplusplus /* Define structure prototypes */ struct _rha; #endif /* #ifdef __cplusplus */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _rih { #pragma __nomember_alignment unsigned int rih$l_max_rads; /* The maximum RADs possible on system */ __union { unsigned int rih$l_flags; /* Copy of RAD_SUPPORT sysgen parameter */ __struct { unsigned rih$v_rad_enable : 1; /* Enable RAD support */ unsigned rih$v_affinity : 1; /* Enable Soft RAD affinity support */ unsigned rih$v_system_repl : 1; /* Enable read-only system space replication */ unsigned rih$v_copy_soft_fault : 1; /* Enable copy on soft fault */ unsigned rih$v_special : 1; /* Enable special allocation flags */ unsigned rih$v_force_rad : 1; /* Debug: RAD support software on non-RAD machines */ unsigned rih$v_rad_pool : 1; /* Enable per-RAD non-paged pool */ unsigned rih$v_platform_decision : 1; /* if set platform code will decide if RAD is on/off */ unsigned rih$v_reserved_2 : 8; /* Reserved for future use */ unsigned rih$v_process_alloc : 2; /* Process page allocation */ unsigned rih$v_swapper_alloc : 2; /* Swapper page allocation */ unsigned rih$v_global_alloc : 2; /* Global page allocation */ unsigned rih$v_system_alloc : 2; /* System space page allocation */ unsigned rih$v_skip_count : 4; /* How many times scheduler skips a process before going off-RAD */ /* The actual count is 2**SKIP_COUNT */ unsigned rih$v_reserved_3 : 4; /* Reserved for future use */ } rih$r_flags_bits; } rih$r_flags_overlay; unsigned short int rih$w_size; /* Size of structure in bytes */ unsigned char rih$b_type; /* DYN$C_MISC */ unsigned char rih$b_subtype; /* DYN$C_RIH */ int rih$l_cpu_shift_value; /* Shift from CPU ID to RAD, -1 if it does not work that way */ int rih$l_pfn_shift_value; /* Shift from PFN to RAD, -1 if it does not work that way */ int rih$l_pa_shift_value; /* Shift from PA to RAD, -1 if it does not work that way */ unsigned int rih$l_base_rad; /* The RAD that contains SYS$BASE_IMAGE et al */ unsigned int rih$l_cpu_mask_offset; /* Offset from beginning of RIH to CPU_MASK */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ struct _rha *rih$pq_gblsec_rads; /* Pointer to global section RAD hint array */ #else unsigned __int64 rih$pq_gblsec_rads; #endif #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif int (*rih$l_pa_to_rad)(); /* pointer to routine converting PA to RAD id */ int (*rih$l_cpu_to_rad)(); /* pointer to routine converting CPU id to RAD id */ void (*rih$l_rad_to_pa_range)(); /* pointer to routine returning a PA range for a given RAD id */ int rih$l_alt_base_rad; /* Will contain a RAD of equal cost to the base RAD if present (IA64) */ char rih$t_align [8]; /* pad to next cache line */ __struct { unsigned __int64 rih$q_cpu_mask_array [1]; /* array of CPU Masks */ } rih$r_cpu_array [32]; } RIH; #if !defined(__VAXC) #define rih$l_flags rih$r_flags_overlay.rih$l_flags #define rih$v_rad_enable rih$r_flags_overlay.rih$r_flags_bits.rih$v_rad_enable #define rih$v_affinity rih$r_flags_overlay.rih$r_flags_bits.rih$v_affinity #define rih$v_system_repl rih$r_flags_overlay.rih$r_flags_bits.rih$v_system_repl #define rih$v_copy_soft_fault rih$r_flags_overlay.rih$r_flags_bits.rih$v_copy_soft_fault #define rih$v_special rih$r_flags_overlay.rih$r_flags_bits.rih$v_special #define rih$v_force_rad rih$r_flags_overlay.rih$r_flags_bits.rih$v_force_rad #define rih$v_rad_pool rih$r_flags_overlay.rih$r_flags_bits.rih$v_rad_pool #define rih$v_platform_decision rih$r_flags_overlay.rih$r_flags_bits.rih$v_platform_decision #define rih$v_reserved_2 rih$r_flags_overlay.rih$r_flags_bits.rih$v_reserved_2 #define rih$v_process_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_process_alloc #define rih$v_swapper_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_swapper_alloc #define rih$v_global_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_global_alloc #define rih$v_system_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_system_alloc #define rih$v_skip_count rih$r_flags_overlay.rih$r_flags_bits.rih$v_skip_count #define rih$v_reserved_3 rih$r_flags_overlay.rih$r_flags_bits.rih$v_reserved_3 #define rih$q_cpu_mask_array rih$q_cpu_mask_array #endif /* #if !defined(__VAXC) */ #define RIH$C_LENGTH 320 /* Length of RAD info header */ #define RIH$C_CURRENT_RAD 0 /* Allocate from the current CPU's RAD */ #define RIH$C_RANDOM_RAD 1 /* Allocate randomly from all RADs */ #define RIH$C_BASE_RAD 2 /* Allocate from the BASE RAD */ #define RIH$C_HOME_RAD 3 /* Allocate from the home RAD */ #define RIH$C_DEFAULT_SKIP 16 /* Skip count for soft RAD affinity */ #define RIH$C_DEFAULT_PROCESS_ALLOC 3 /*Default process allocation algorithm */ #define RIH$C_DEFAULT_SWAPPER_ALLOC 1 /*Default swapper allocation algorithm */ #define RIH$C_DEFAULT_GLOBAL_ALLOC 1 /*Default global allocation algorithm */ #define RIH$C_DEFAULT_SYSTEM_ALLOC 0 /*Default system allocation algorithm */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _rha { #pragma __nomember_alignment unsigned __int64 rha$q_unused1; unsigned short int rha$w_mbo; /* Must Be One (if 65535 Global Sections, size too big) */ unsigned char rha$b_type; /* DYN$C_MISC */ unsigned char rha$b_subtype; /* DYN$C_RHA */ unsigned int rha$l_unused2; unsigned __int64 rha$q_size; /* Size of structure */ char rha$t_hint_array [1]; /* The actual RAD hint array */ char rha$b_fill_0_ [7]; } RHA; #ifdef __INITIAL_POINTER_SIZE #pragma __required_pointer_size __save /* Save current pointer size */ #pragma __required_pointer_size __long /* Pointers are 64-bit */ typedef struct _rih * RIH_PQ; /* Pointer to a RIH structure. */ typedef struct _rha * RHA_PQ; /* Pointer to a RHA structure. */ #pragma __required_pointer_size __restore /* Return to previous pointer size */ #else typedef unsigned __int64 RIH_PQ; #endif /* __INITIAL_POINTER_SIZE */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __RIHDEF_LOADED */