/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:07 by OpenVMS SDL EV3-3 */ /* Source: 31-MAR-1998 13:28:17 $1$DGA7274:[LIB_H.SRC]PYXISDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $PYXISDEF ***/ #ifndef __PYXISDEF_LOADED #define __PYXISDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define PYXIS$L_NODE_PA_H 135 /* High order word */ #define PYXIS$L_PYXIS_CONTROL_L 1073741824 #define PYXIS$L_PYXIS_ERROR_L 1073774592 #define PYXIS$L_PYXIS_MEMORY_L 1342177280 #define PYXIS$L_PYXIS_PCI_ADDR_L 1610612736 #define PYXIS$L_PYXIS_CLOCK_RESET_L -2147483648 #define PYXIS$L_PYXIS_SERVER_MGMT_L -1879048192 #define PYXIS$L_PYXIS_INTERRUPT_L -1610612736 #define PYXIS$L_CUSCO_L -1072693248 #define PYXIS$K_PCI_REV 128 /*PCI revision */ #define PYXIS$K_PCI_LAT 192 /*PCI Latency */ #define PYXIS$K_PYXIS_CTRL 256 /*PYXIS COntrol */ #define PYXIS$K_PYXIS_CTRL1 320 /*PYXIS COntrol */ #define PYXIS$K_PYXIS_FLASH_CTRL 512 /*Flash COntrol */ #define PYXIS$K_HAE_MEM 1024 /*HAE memory */ #define PYXIS$K_HAE_IO 1088 /*HAE I/O */ #define PYXIS$K_HAE_CFG 1152 /*COnfig */ #define PYXIS$K_PYXIS_DIAG 8192 /*Diag control */ #define PYXIS$K_PYXIS_CHECK 12288 /*Diag check */ #define PYXIS$K_PERF_MON 16384 /*Perf monitor */ #define PYXIS$K_PERF_CNTR 16448 /*Perf control */ #define PYXIS$K_PYXIS_ERR_REG 512 /*PYXIS status */ #define PYXIS$K_PYXIS_STAT 576 /*PYXIS status */ #define PYXIS$K_PYXIS_ERR_MSK 640 /*PYXIS err mask */ #define PYXIS$K_PYXIS_SYN 768 /*PYXIS syndrome */ #define PYXIS$K_PYXIS_ERR_DATA 776 /*PYXIS error data */ #define PYXIS$K_CPU_MEAR 1024 /*Mem Error Address */ #define PYXIS$K_CPU_MESR 1088 /*Mem Error Status */ #define PYXIS$K_PCI_ERR0 2048 /*PCI Err 0 */ #define PYXIS$K_PCI_ERR1 2112 /*PCI Err 1 */ #define PYXIS$K_PCI_ERR2 2176 /*PCI Err 1 */ #define PYXIS$K_MEM_CONTROL 0 /*Memory config */ #define PYXIS$K_MEM_CLOCK_MASK 64 #define PYXIS$K_MEM_GTR 512 #define PYXIS$K_MEM_RTR 768 #define PYXIS$K_MEM_RHPR 1024 #define PYXIS$K_MEM_MDR1 1280 #define PYXIS$K_MEM_MDR2 1344 #define PYXIS$K_MEM_BA0 1536 /*Mem base addr0 */ #define PYXIS$K_MEM_BA1 1600 /*Mem base addr2 */ #define PYXIS$K_MEM_BA2 1664 /*Mem base addr4 */ #define PYXIS$K_MEM_BA3 1728 /*Mem base addr6 */ #define PYXIS$K_MEM_BA4 1792 /*Mem base addr8 */ #define PYXIS$K_MEM_BA5 1856 /*Mem base addrA */ #define PYXIS$K_MEM_BA6 1920 /*Mem base addrC */ #define PYXIS$K_MEM_BA7 1984 /*Mem base addrE */ #define PYXIS$K_MEM_BC0 2048 /*Mem base contr0 */ #define PYXIS$K_MEM_BC1 2112 /*Mem base contr2 */ #define PYXIS$K_MEM_BC2 2176 /*Mem base contr4 */ #define PYXIS$K_MEM_BC3 2240 /*Mem base contr6 */ #define PYXIS$K_MEM_BC4 2304 /*Mem base contr8 */ #define PYXIS$K_MEM_BC5 2368 /*Mem base contrA */ #define PYXIS$K_MEM_BC6 2432 /*Mem base contrC */ #define PYXIS$K_MEM_BC7 2496 /*Mem base contrE */ #define PYXIS$K_MEM_BTR0 2560 /*Mem base timing0 */ #define PYXIS$K_MEM_BTR1 2624 /*Mem base timing2 */ #define PYXIS$K_MEM_BTR2 2688 /*Mem base timing4 */ #define PYXIS$K_MEM_BTR3 2752 /*Mem base timing6 */ #define PYXIS$K_MEM_BTR4 2816 /*Mem base timing8 */ #define PYXIS$K_MEM_BTR5 2880 /*Mem base timingA */ #define PYXIS$K_MEM_BTR6 2944 /*Mem base timingC */ #define PYXIS$K_MEM_BTR7 3008 /*Mem base timingE */ #define PYXIS$K_MEM_CVM 3072 /*cache valid mask */ #define PYXIS$K_MEM_TBIA 3072 /*cache valid mask */ #define PYXIS$K_MEM_TMG0 2816 /*Mem timing 0 */ #define PYXIS$K_MEM_TMG1 2880 /*Mem timing 1 */ #define PYXIS$K_MEM_TMG2 2944 /*Mem timing 2 */ #define PYXIS$K_PCI_TBIA 256 /*SG TB inval */ #define PYXIS$K_PCI_W0_BASE 1024 /*Window base0 */ #define PYXIS$K_PCI_W0_MASK 1088 /*Window mask0 */ #define PYXIS$K_PCI_T0_BASE 1152 /*Trans base0 */ #define PYXIS$K_PCI_W1_BASE 1280 /*Window base1 */ #define PYXIS$K_PCI_W1_MASK 1344 /*Window mask1 */ #define PYXIS$K_PCI_T1_BASE 1408 /*Trans base1 */ #define PYXIS$K_PCI_W2_BASE 1536 /*Window base2 */ #define PYXIS$K_PCI_W2_MASK 1600 /*Window mask2 */ #define PYXIS$K_PCI_T2_BASE 1664 /*Trans base2 */ #define PYXIS$K_PCI_W3_BASE 1792 /*Window base3 */ #define PYXIS$K_PCI_W3_MASK 1856 /*Window mask3 */ #define PYXIS$K_PCI_T3_BASE 1920 /*Trans base3 */ #define PYXIS$K_PCI_DAC_BASE 1984 /*DAC Base */ #define PYXIS$K_PCI_LTB_TAG0 2048 /*Lock TB tag0 */ #define PYXIS$K_PCI_LTB_TAG1 2112 /*Lock TB tag1 */ #define PYXIS$K_PCI_LTB_TAG2 2176 /*Lock TB tag2 */ #define PYXIS$K_PCI_LTB_TAG3 2240 /*Lock TB tag3 */ #define PYXIS$K_PCI_TB_TAG0 2304 /* TB tag0 */ #define PYXIS$K_PCI_TB_TAG1 2368 /* TB tag1 */ #define PYXIS$K_PCI_TB_TAG2 2432 /* TB tag2 */ #define PYXIS$K_PCI_TB_TAG3 2496 /* TB tag3 */ #define PYXIS$K_PCI_TB0_PAGE0 4096 /* TB0 page0 */ #define PYXIS$K_PCI_TB0_PAGE1 4160 /* TB0 page1 */ #define PYXIS$K_PCI_TB0_PAGE2 4224 /* TB0 page2 */ #define PYXIS$K_PCI_TB0_PAGE3 4288 /* TB0 page3 */ #define PYXIS$K_PCI_TB1_PAGE0 4352 /* TB1 page0 */ #define PYXIS$K_PCI_TB1_PAGE1 4416 /* TB1 page1 */ #define PYXIS$K_PCI_TB1_PAGE2 4480 /* TB1 page2 */ #define PYXIS$K_PCI_TB1_PAGE3 4544 /* TB1 page3 */ #define PYXIS$K_PCI_TB2_PAGE0 4608 /* TB2 page0 */ #define PYXIS$K_PCI_TB2_PAGE1 4672 /* TB2 page1 */ #define PYXIS$K_PCI_TB2_PAGE2 4736 /* TB2 page2 */ #define PYXIS$K_PCI_TB2_PAGE3 4800 /* TB2 page3 */ #define PYXIS$K_PCI_TB3_PAGE0 4864 /* TB3 page0 */ #define PYXIS$K_PCI_TB3_PAGE1 4928 /* TB3 page1 */ #define PYXIS$K_PCI_TB3_PAGE2 4992 /* TB3 page2 */ #define PYXIS$K_PCI_TB3_PAGE3 5056 /* TB3 page3 */ #define PYXIS$K_PCI_TB4_PAGE0 5120 /* TB4 page0 */ #define PYXIS$K_PCI_TB4_PAGE1 5184 /* TB4 page1 */ #define PYXIS$K_PCI_TB4_PAGE2 5248 /* TB4 page2 */ #define PYXIS$K_PCI_TB4_PAGE3 5312 /* TB4 page3 */ #define PYXIS$K_PCI_TB5_PAGE0 5376 /* TB5 page0 */ #define PYXIS$K_PCI_TB5_PAGE1 5440 /* TB5 page1 */ #define PYXIS$K_PCI_TB5_PAGE2 5504 /* TB5 page2 */ #define PYXIS$K_PCI_TB5_PAGE3 5568 /* TB5 page3 */ #define PYXIS$K_PCI_TB6_PAGE0 5632 /* TB6 page0 */ #define PYXIS$K_PCI_TB6_PAGE1 5696 /* TB6 page1 */ #define PYXIS$K_PCI_TB6_PAGE2 5760 /* TB6 page2 */ #define PYXIS$K_PCI_TB6_PAGE3 5824 /* TB6 page3 */ #define PYXIS$K_PCI_TB7_PAGE0 5888 /* TB7 page0 */ #define PYXIS$K_PCI_TB7_PAGE1 5952 /* TB7 page1 */ #define PYXIS$K_PCI_TB7_PAGE2 6016 /* TB7 page2 */ #define PYXIS$K_PCI_TB7_PAGE3 6080 /* TB7 page3 */ #define PYXIS$K_CLOCK_CONFIG 0 #define PYXIS$K_RESET 2304 #define PYXIS$K_FAN_ACCUM 0 #define PYXIS$K_FAN_CTL 64 #define PYXIS$K_FAN_THRESH 128 #define PYXIS$K_POWER_CTL 192 #define PYXIS$K_PWRDWN_TIM 256 #define PYXIS$K_POWER_STATE 320 #define PYXIS$K_INT_REQ 0 #define PYXIS$K_INT_MASK 64 #define PYXIS$K_INT_HILO 192 #define PYXIS$K_INT_ROUTE 320 #define PYXIS$K_GPO 384 #define PYXIS$K_INT_CNFG 448 #define PYXIS$K_RT_COUNT 512 #define PYXIS$K_INT_TIME 576 #define PYXIS$K_IIC_CTRL 704 #define PYXIS$K_CLOCK_1286 64 #define PYXIS$K_COMMAND_1286 75 #define PYXIS$K_WDOG_1286 76 #define PYXIS$K_VDIVR 128 #define PYXIS$K_V1ISR 129 #define PYXIS$K_V2ISR 130 #define PYXIS$K_V3ISR 131 #define PYXIS$K_VDIER 132 #define PYXIS$K_V1IER 133 #define PYXIS$K_V2IER 134 #define PYXIS$K_V3IER 135 #define PYXIS$K_VMCSR 136 #define PYXIS$K_VACSR 138 #define PYXIS$K_BIDR 139 #define PYXIS$K_VSICSR0 160 #define PYXIS$K_VSICSR1 161 #define PYXIS$K_VSICSR2 162 #define PYXIS$K_VSICSR3 163 #define PYXIS$K_VSICSR4 164 #define PYXIS$K_VSICSR5 165 #define PYXIS$K_VSICSR6 166 #define PYXIS$K_VSICSR9 169 #define PYXIS$K_VSICSRA 170 #define PYXIS$K_VSICSRB 171 #define PYXIS$K_VSICSRC 172 #define PYXIS$K_VSICSR11 177 #define PYXIS$K_VSICSR12 178 #define PYXIS$K_VSICSR13 179 #define PYXIS$K_VSICSR14 180 #define PYXIS$K_VSICSR15 181 #define PYXIS$K_VSICSR16 182 #define PYXIS$K_VSICSR17 183 #define PYXIS$M_PYXIS_CTRL_PCI_EN 0x1 #define PYXIS$M_PYXIS_CTRL_PCI_LOCK_EN 0x2 #define PYXIS$M_PYXIS_CTRL_PCI_LOOP_EN 0x4 #define PYXIS$M_PYXIS_CTRL_FST_BB_EN 0x8 #define PYXIS$M_PYXIS_CTRL_MST_EN 0x10 #define PYXIS$M_PYXIS_CTRL_MEM_EN 0x20 #define PYXIS$M_PYXIS_CTRL_REQ64_EN 0x40 #define PYXIS$M_PYXIS_CTRL_ACK64_EN 0x80 #define PYXIS$M_PYXIS_CTRL_ADDR_PE_EN 0x100 #define PYXIS$M_PYXIS_CTRL_PERR_EN 0x200 #define PYXIS$M_PYXIS_CTRL_FILL_ERR_EN 0x400 #define PYXIS$M_PYXIS_CTRL_ECC_CHK_EN 0x1000 #define PYXIS$M_PYXIS_CTRL_CACK_EN_PE 0x2000 #define PYXIS$M_PYXIS_CTRL_CON_IDLE_BC 0x4000 #define PYXIS$M_PYXIS_CTRL_CSR_IOA_BYP 0x8000 #define PYXIS$M_PYXIS_CTRL_IO_FLUSH_REQ 0x10000 #define PYXIS$M_PYXIS_CTRL_CPU_FLUSH_REQ 0x20000 #define PYXIS$M_PYXIS_CTRL_ARB_EV5_EN 0x40000 #define PYXIS$M_PYXIS_CTRL_EN_ARB_LINK 0x80000 #define PYXIS$M_PYXIS_CTRL_RD_TYP 0x300000 #define PYXIS$M_PYXIS_CTRL_RL_TYP 0x3000000 #define PYXIS$M_PYXIS_CTRL_RM_TYP 0x30000000 #define PYXIS$M_PYXIS_CTRL1_IOA_BEN 0x1 #define PYXIS$M_PYXIS_CTRL1_PCI_MWIN_ENA 0x10 #define PYXIS$M_PYXIS_CTRL1_PCI_LINK_ENA 0x100 #define PYXIS$M_PYXIS_CTRL1_LW_PAR_MODE 0x1000 #define PYXIS$M_PYXIS_CNFG_PCI_WIDTH 0x100 #define PYXIS$M_PYXIS_CNFG_IOD_WIDTH 0x10000 #define PYXIS$M_HAE_MEM_REG_3 0xFC #define PYXIS$M_HAE_MEM_REG_2 0xF800 #define PYXIS$M_HAE_MEM_REG_1 0xE0000000 #define PYXIS$M_HAE_IO 0xFE000000 #define PYXIS$M_FROM_EN 0x1 #define PYXIS$M_USE_CHECK 0x2 #define PYXIS$M_FPE_PCI 0x30000000 #define PYXIS$M_FPE_TO_EV5 0x80000000 #define PYXIS$M_ERR_CORR_ECC 0x1 #define PYXIS$M_ERR_UNC_ECC 0x2 #define PYXIS$M_ERR_CPU_PE 0x4 #define PYXIS$M_ERR_MEM_NEM 0x8 #define PYXIS$M_ERR_PCI_SERR 0x10 #define PYXIS$M_ERR_PCI_PERR 0x20 #define PYXIS$M_ERR_PCI_ADR_PE 0x40 #define PYXIS$M_ERR_M_ABORT 0x80 #define PYXIS$M_ERR_T_ABORT 0x100 #define PYXIS$M_ERR_PA_PTE_INV 0x200 #define PYXIS$M_ERR_IOA_TIMEOUT 0x800 #define PYXIS$M_ERR_LOST_CORR_ECC 0x10000 #define PYXIS$M_ERR_LOST_UNC_ECC 0x20000 #define PYXIS$M_ERR_LOST_CPU_PE 0x40000 #define PYXIS$M_ERR_LOST_MEM_NEM 0x80000 #define PYXIS$M_ERR_LOST_PCI_PERR 0x200000 #define PYXIS$M_ERR_LOST_PCI_ADR_PE 0x400000 #define PYXIS$M_ERR_LOST_M_ABORT 0x800000 #define PYXIS$M_ERR_LOST_T_ABORT 0x1000000 #define PYXIS$M_ERR_LOST_PA_PTE_INV 0x2000000 #define PYXIS$M_ERR_LOST_IOA_TIMEOUT 0x8000000 #define PYXIS$M_ERR_VALID 0x80000000 #define PYXIS$M_STAT_PCI_0 0x1 #define PYXIS$M_STAT_PCI_1 0x2 #define PYXIS$M_STAT_IOA_VALID 0xF0 #define PYXIS$M_STAT_TLB_MISS 0x800 #define PYXIS$M_MASK_CORR_ECC_ERR 0x1 #define PYXIS$M_MASK_UNC_ECC_ERR 0x2 #define PYXIS$M_MASK_CPU_PE 0x4 #define PYXIS$M_MASK_MEM_NEM 0x8 #define PYXIS$M_MASK_PCI_SERR 0x10 #define PYXIS$M_MASK_PCI_PERR 0x20 #define PYXIS$M_MASK_PCI_ADR_PE 0x40 #define PYXIS$M_MASK_M_ABORT 0x80 #define PYXIS$M_MASK_T_ABORT 0x100 #define PYXIS$M_MASK_PA_PTE_INV 0x200 #define PYXIS$M_MASK_IOA_TIMEOUT 0x800 #define PYXIS$M_PYXIS_SYNDROME0 0xFF #define PYXIS$M_PYXIS_SYNDROME1 0xFF00 #define PYXIS$M_PYXIS_RAW_CHECK_BITS 0xFF0000 #define PYXIS$M_PYXIS_SYND_CE0 0x1000000 #define PYXIS$M_PYXIS_SYND_CE1 0x2000000 #define PYXIS$M_PYXIS_SYND_UCE0 0x4000000 #define PYXIS$M_PYXIS_SYND_UCE1 0x8000000 #define PYXIS$M_MEAR_ADDR_H 0xFFFFFFF0 #define PYXIS$M_MESR_ADDR_3932 0xFF #define PYXIS$M_MESR_DMA_RD_NXM 0x100 #define PYXIS$M_MESR_DMA_WR_NXM 0x200 #define PYXIS$M_MESR_CPU_RD_NXM 0x400 #define PYXIS$M_MESR_CPU_WR_NXM 0x800 #define PYXIS$M_MESR_IO_RD_NXM 0x1000 #define PYXIS$M_MESR_IO_WR_NXM 0x2000 #define PYXIS$M_MESR_VICTIM_NXM 0x4000 #define PYXIS$M_MESR_TLBFILL_NXM 0x8000 #define PYXIS$M_MESR_OWORD_INDEX 0x30000 #define PYXIS$M_MESR_DATA_CYCLE_TYP 0x1F00000 #define PYXIS$M_MESR_SEQ_ST 0xFE000000 #define PYXIS$M_PCIE_DMA_CMD 0xF #define PYXIS$M_PCIE_DMA_DAC 0x20 #define PYXIS$M_PCIE_WINDOW 0xF00 #define PYXIS$M_PCIE_MSTR_STATE 0xF0000 #define PYXIS$M_PCIE_TRGT_STATE 0xF00000 #define PYXIS$M_PCIE_PCI_CMD 0xF000000 #define PYXIS$M_PCIE_PCI_DAC 0x10000000 #define PYXIS$M_MCR_MODE_REQ 0x1 #define PYXIS$M_MCR_SERVER_MODE 0x100 #define PYXIS$M_MCR_BCACHE_STAT 0x200 #define PYXIS$M_MCR_BCACHE_EN 0x400 #define PYXIS$M_MCR_PIPELINED_CACHE 0x800 #define PYXIS$M_MCR_OVERLAP_DIS 0x1000 #define PYXIS$M_MCR_SEQ_TRACE 0x2000 #define PYXIS$M_MCR_CKE_AUTO 0x4000 #define PYXIS$M_MCR_DRAM_CLK_AUTO 0x8000 #define PYXIS$M_MCR_DRAM_MODE 0x3FFF0000 #define PYXIS$M_MCMR_DRAM_CLOCK_MASK 0xFFFF #define PYXIS$M_MGTR_MIN_RAS_PRE 0x7 #define PYXIS$M_MGTR_CAS_LAT 0x30 #define PYXIS$M_MGTR_IDLE_BC_WIDTH 0x700 #define PYXIS$M_MRTR_REF_WIDTH 0x70 #define PYXIS$M_MRTR_REF_INT 0x1F80 #define PYXIS$M_MRTR_FORCE_REF 0x8000 #define PYXIS$M_MRPHR_POLICY_MASK 0xFFFF #define PYXIS$M_MDR1_SEL0 0x3F #define PYXIS$M_MDR1_SEL1 0x3F00 #define PYXIS$M_MDR1_SEL2 0x3F0000 #define PYXIS$M_MDR1_SEL3 0x3F000000 #define PYXIS$M_MDR1_ENABLE 0x80000000 #define PYXIS$M_MDR2_SEL0 0x3F #define PYXIS$M_MDR2_SEL1 0x3F00 #define PYXIS$M_MDR2_SEL2 0x3F0000 #define PYXIS$M_MDR2_SEL3 0x3F000000 #define PYXIS$M_MDR2_ENABLE 0x80000000 #define PYXIS$M_BBAR0_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR1_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR2_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR3_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR4_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR5_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR6_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_BBAR7_BASE_ADDR_3324 0xFFC0 #define PYXIS$M_MBCR0_BANK_ENABLE 0x1 #define PYXIS$M_MBCR0_BANK_SIZE 0x1E #define PYXIS$M_MBCR0_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR0_COLSEL 0x40 #define PYXIS$M_MBCR0_4BANK 0x80 #define PYXIS$M_MBCR1_BANK_ENABLE 0x1 #define PYXIS$M_MBCR1_BANK_SIZE 0x1E #define PYXIS$M_MBCR1_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR1_COLSEL 0x40 #define PYXIS$M_MBCR1_4BANK 0x80 #define PYXIS$M_MBCR2_BANK_ENABLE 0x1 #define PYXIS$M_MBCR2_BANK_SIZE 0x1E #define PYXIS$M_MBCR2_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR2_COLSEL 0x40 #define PYXIS$M_MBCR2_4BANK 0x80 #define PYXIS$M_MBCR3_BANK_ENABLE 0x1 #define PYXIS$M_MBCR3_BANK_SIZE 0x1E #define PYXIS$M_MBCR3_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR3_COLSEL 0x40 #define PYXIS$M_MBCR3_4BANK 0x80 #define PYXIS$M_MBCR4_BANK_ENABLE 0x1 #define PYXIS$M_MBCR4_BANK_SIZE 0x1E #define PYXIS$M_MBCR4_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR4_COLSEL 0x40 #define PYXIS$M_MBCR4_4BANK 0x80 #define PYXIS$M_MBCR5_BANK_ENABLE 0x1 #define PYXIS$M_MBCR5_BANK_SIZE 0x1E #define PYXIS$M_MBCR5_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR5_COLSEL 0x40 #define PYXIS$M_MBCR5_4BANK 0x80 #define PYXIS$M_MBCR6_BANK_ENABLE 0x1 #define PYXIS$M_MBCR6_BANK_SIZE 0x1E #define PYXIS$M_MBCR6_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR6_COLSEL 0x40 #define PYXIS$M_MBCR6_4BANK 0x80 #define PYXIS$M_MBCR7_BANK_ENABLE 0x1 #define PYXIS$M_MBCR7_BANK_SIZE 0x1E #define PYXIS$M_MBCR7_SUBBANK_ENABLE 0x20 #define PYXIS$M_MBCR7_COLSEL 0x40 #define PYXIS$M_MBCR7_4BANK 0x80 #define PYXIS$M_MBTR0_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR0_TOSHIBA 0x10 #define PYXIS$M_MBTR0_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR1_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR1_TOSHIBA 0x10 #define PYXIS$M_MBTR1_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR2_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR2_TOSHIBA 0x10 #define PYXIS$M_MBTR2_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR3_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR3_TOSHIBA 0x10 #define PYXIS$M_MBTR3_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR4_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR4_TOSHIBA 0x10 #define PYXIS$M_MBTR4_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR5_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR5_TOSHIBA 0x10 #define PYXIS$M_MBTR5_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR6_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR6_TOSHIBA 0x10 #define PYXIS$M_MBTR6_SLOW_CHARGE 0x20 #define PYXIS$M_MBTR7_ROW_ADDR_HOLD 0x7 #define PYXIS$M_MBTR7_TOSHIBA 0x10 #define PYXIS$M_MBTR7_SLOW_CHARGE 0x20 #define PYXIS$M_CVM_CACHE_VALID_MASK 0x7FFFFFFF #define PYXIS$M_TBIA_CSR_WR_DATA 0x3 #define PYXIS$M_WBASE0_W_EN 0x1 #define PYXIS$M_WBASE0_SG_EN 0x2 #define PYXIS$M_WBASE0_MEMCS_EN 0x4 #define PYXIS$M_WBASE0_DAC_EN 0x8 #define PYXIS$M_WBASE0_BASE 0xFFF00000 #define PYXIS$M_WMASK0_MASK 0xFFF00000 #define PYXIS$M_TBASE0_BASE 0xFFFFFF00 #define PYXIS$M_WBASE1_W_EN 0x1 #define PYXIS$M_WBASE1_SG_EN 0x2 #define PYXIS$M_WBASE1_MEMCS_EN 0x4 #define PYXIS$M_WBASE1_DAC_EN 0x8 #define PYXIS$M_WBASE1_BASE 0xFFF00000 #define PYXIS$M_WMASK1_MASK 0xFFF00000 #define PYXIS$M_TBASE1_BASE 0xFFFFFF00 #define PYXIS$M_WBASE2_W_EN 0x1 #define PYXIS$M_WBASE2_SG_EN 0x2 #define PYXIS$M_WBASE2_MEMCS_EN 0x4 #define PYXIS$M_WBASE2_DAC_EN 0x8 #define PYXIS$M_WBASE2_BASE 0xFFF00000 #define PYXIS$M_WMASK2_MASK 0xFFF00000 #define PYXIS$M_TBASE2_BASE 0xFFFFFF00 #define PYXIS$M_WBASE3_W_EN 0x1 #define PYXIS$M_WBASE3_SG_EN 0x2 #define PYXIS$M_WBASE3_MEMCS_EN 0x4 #define PYXIS$M_WBASE3_DAC_EN 0x8 #define PYXIS$M_WBASE3_BASE 0xFFF00000 #define PYXIS$M_WMASK3_MASK 0xFFF00000 #define PYXIS$M_TBASE3_BASE 0xFFFFFF00 #define PYXIS$M_DAC_BASE 0xFF #define PYXIS$M_LTB0_VALID 0x1 #define PYXIS$M_LTB0_LOCKED 0x2 #define PYXIS$M_LTB0_DAC 0x4 #define PYXIS$M_LTB0_TAG 0xFFFF8000 #define PYXIS$M_LTB1_VALID 0x1 #define PYXIS$M_LTB1_LOCKED 0x2 #define PYXIS$M_LTB1_DAC 0x4 #define PYXIS$M_LTB1_TAG 0xFFFF8000 #define PYXIS$M_LTB2_VALID 0x1 #define PYXIS$M_LTB2_LOCKED 0x2 #define PYXIS$M_LTB2_DAC 0x4 #define PYXIS$M_LTB2_TAG 0xFFFF8000 #define PYXIS$M_LTB3_VALID 0x1 #define PYXIS$M_LTB3_LOCKED 0x2 #define PYXIS$M_LTB3_DAC 0x4 #define PYXIS$M_LTB3_TAG 0xFFFF8000 #define PYXIS$M_TB0_VALID 0x1 #define PYXIS$M_TB0_DAC 0x4 #define PYXIS$M_TB0_TAG 0xFFFF8000 #define PYXIS$M_TB1_VALID 0x1 #define PYXIS$M_TB1_DAC 0x4 #define PYXIS$M_TB1_TAG 0xFFFF8000 #define PYXIS$M_TB2_VALID 0x1 #define PYXIS$M_TB2_DAC 0x4 #define PYXIS$M_TB2_TAG 0xFFFF8000 #define PYXIS$M_TB3_VALID 0x1 #define PYXIS$M_TB3_DAC 0x4 #define PYXIS$M_TB3_TAG 0xFFFF8000 #define PYXIS$M_TB0_PAGE0_VALID 0x1 #define PYXIS$M_TB0_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB0_PAGE1_VALID 0x1 #define PYXIS$M_TB0_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB0_PAGE2_VALID 0x1 #define PYXIS$M_TB0_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB0_PAGE3_VALID 0x1 #define PYXIS$M_TB0_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB1_PAGE0_VALID 0x1 #define PYXIS$M_TB1_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB1_PAGE1_VALID 0x1 #define PYXIS$M_TB1_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB1_PAGE2_VALID 0x1 #define PYXIS$M_TB1_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB1_PAGE3_VALID 0x1 #define PYXIS$M_TB1_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB2_PAGE0_VALID 0x1 #define PYXIS$M_TB2_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB2_PAGE1_VALID 0x1 #define PYXIS$M_TB2_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB2_PAGE2_VALID 0x1 #define PYXIS$M_TB2_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB2_PAGE3_VALID 0x1 #define PYXIS$M_TB2_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB3_PAGE0_VALID 0x1 #define PYXIS$M_TB3_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB3_PAGE1_VALID 0x1 #define PYXIS$M_TB3_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB3_PAGE2_VALID 0x1 #define PYXIS$M_TB3_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB3_PAGE3_VALID 0x1 #define PYXIS$M_TB3_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB4_PAGE0_VALID 0x1 #define PYXIS$M_TB4_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB4_PAGE1_VALID 0x1 #define PYXIS$M_TB4_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB4_PAGE2_VALID 0x1 #define PYXIS$M_TB4_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB4_PAGE3_VALID 0x1 #define PYXIS$M_TB4_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB5_PAGE0_VALID 0x1 #define PYXIS$M_TB5_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB5_PAGE1_VALID 0x1 #define PYXIS$M_TB5_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB5_PAGE2_VALID 0x1 #define PYXIS$M_TB5_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB5_PAGE3_VALID 0x1 #define PYXIS$M_TB5_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB6_PAGE0_VALID 0x1 #define PYXIS$M_TB6_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB6_PAGE1_VALID 0x1 #define PYXIS$M_TB6_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB6_PAGE2_VALID 0x1 #define PYXIS$M_TB6_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB6_PAGE3_VALID 0x1 #define PYXIS$M_TB6_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_TB7_PAGE0_VALID 0x1 #define PYXIS$M_TB7_PAGE0_ADDR 0x3FFFFE #define PYXIS$M_TB7_PAGE1_VALID 0x1 #define PYXIS$M_TB7_PAGE1_ADDR 0x3FFFFE #define PYXIS$M_TB7_PAGE2_VALID 0x1 #define PYXIS$M_TB7_PAGE2_ADDR 0x3FFFFE #define PYXIS$M_TB7_PAGE3_VALID 0x1 #define PYXIS$M_TB7_PAGE3_ADDR 0x3FFFFE #define PYXIS$M_CCR_CLOCK_DIVIDE 0x3 #define PYXIS$M_CCR_PCLK_DIVIDE 0x380 #define PYXIS$M_CCR_SEL_CFG 0x800 #define PYXIS$M_CCR_DCLK_INV 0x8000 #define PYXIS$M_CCR_DCLK_FORCE 0x10000 #define PYXIS$M_CCR_DCLK_DELAY 0xFF000000 #define PYXIS$M_FAR_HEAT 0xFFFFFF #define PYXIS$M_FCR_ON_HEAT 0xFF #define PYXIS$M_FCR_SAMPLE 0xFF00 #define PYXIS$M_FCR_OFF_DELAY 0xFFF0000 #define PYXIS$M_FCR_FORCE_FAN 0x10000000 #define PYXIS$M_FCR_FORCE_FAN_HI 0x20000000 #define PYXIS$M_FCR_FAN_ON 0x40000000 #define PYXIS$M_FCR_FAN_ON_HI 0x80000000 #define PYXIS$M_FTR_FAN_ON 0xFF #define PYXIS$M_FTR_FAN_HI 0xFF00 #define PYXIS$M_FTR_FAN_HI_LO 0xFF0000 #define PYXIS$M_FTR_FAN_OFF 0xFF000000 #define PYXIS$M_PCR_POWER_DOWN 0x1 #define PYXIS$M_PCR_ABUS_DIS 0x10 #define PYXIS$M_PCR_IINT_DIS 0x100 #define PYXIS$M_PCR_DO_RESET 0x1000 #define PYXIS$M_PTR_PLL_DELAY 0xFF #define PYXIS$M_PTR_OFF_DELAY 0xFF00 #define PYXIS$M_PTR_RESET_PULSE_WIDTH 0xFF0000 #define PYXIS$M_PTR_MIN_OFF_TIME 0xFF000000 #define PYXIS$M_INT_REQ_31_0 0xFFFFFFFF #define PYXIS$M_INT_REQ_61_32 0x3FFFFFFF00000000 #define PYXIS$M_INT_REQ_CLK_PEND 0x4000000000000000 #define PYXIS$M_INT_REQ_ERR_INT 0x8000000000000000 #define PYXIS$M_INT_MASK_31_0 0xFFFFFFFF #define PYXIS$M_INT_MASK_61_32 0x3FFFFFFF00000000 #define PYXIS$M_INT_HILO_BYTE 0xFF #define PYXIS$M_INT_RTE 0x7F #define PYXIS$M_ICNFG_CLK_DIV 0xF #define PYXIS$M_ICNFG_IRQ_CNT 0x70 #define PYXIS$M_ICNFG_IRQ_CFG 0x7F00 #define PYXIS$M_ICNFG_DRIVE_IRQ 0x10000 #define PYXIS$M_IIC_READ_DATA 0x1 #define PYXIS$M_IIC_READ_CLK 0x2 #define PYXIS$M_IIC_DATA_EN 0x4 #define PYXIS$M_IIC_DATA 0x8 #define PYXIS$M_IIC_CLK_EN 0x10 #define PYXIS$M_IIC_CLK 0x20 #define PYXIS$M_SEC_01 0xF #define PYXIS$M_SEC_1 0xF0 #define PYXIS$M_SECOND 0xF #define PYXIS$M_SEC_10 0x70 #define PYXIS$M_MINUTE 0xF #define PYXIS$M_MIN_10 0x70 #define PYXIS$M_ALARM_MIN 0xF #define PYXIS$M_ALARM_MIN_10 0x70 #define PYXIS$M_SET_MIN_ALARM 0x80 #define PYXIS$M_HOUR 0xF #define PYXIS$M_HOUR_10 0x10 #define PYXIS$M_AP_10HR 0x20 #define PYXIS$M_TWELVE 0x40 #define PYXIS$M_ALARM_HOUR 0xF #define PYXIS$M_ALARM_HOUR_10 0x10 #define PYXIS$M_ALARM_AP_10HR 0x20 #define PYXIS$M_ALARM_TWELVE 0x40 #define PYXIS$M_SET_HOUR_ALARM 0x80 #define PYXIS$M_DAY 0x7 #define PYXIS$M_DAY_ALARM 0x7 #define PYXIS$M_DAY_ALARM_MBZ 0x78 #define PYXIS$M_SET_DAY_ALARM 0x80 #define PYXIS$M_DATE 0xF #define PYXIS$M_DATE_10 0x30 #define PYXIS$M_MONTH 0xF #define PYXIS$M_MONTH_10 0x10 #define PYXIS$M_MONTH_MBZ 0x20 #define PYXIS$M_ESQW 0x40 #define PYXIS$M_EOSC 0x80 #define PYXIS$M_YEAR 0xF #define PYXIS$M_YEAR_10 0xF0 #define PYXIS$M_TDF 0x1 #define PYXIS$M_WAF 0x2 #define PYXIS$M_TDM 0x4 #define PYXIS$M_WAM 0x8 #define PYXIS$M_PU_LVL 0x10 #define PYXIS$M_IBH_LO 0x20 #define PYXIS$M_IPSW 0x40 #define PYXIS$M_TE 0x80 #define PYXIS$M_WDOG_01_SEC 0xF #define PYXIS$M_WDOG_1_SEC 0xF0 #define PYXIS$M_WDOG_SEC 0xF #define PYXIS$M_WDOG_10SEC 0xF0 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _pyxis { /* PYXIS ASIC revision 8740000080 */ #pragma __nomember_alignment unsigned char pyxis$b_fill00 [128]; __union { int pyxis$l_pci_pyxis_rev; __struct { char pyxis$b_pyxis_rev; /* PYXIS revision */ unsigned pyxis$v_fill01 : 24; } pyxis$r_rev_bits; } pyxis$r_pci_pyxis_revision; unsigned char pyxis$b_fill02 [60]; /* PCI master latency timeout 87400000C0 */ __union { int pyxis$l_pci_lat; __struct { char pyxis$b_fill10; char pyxis$b_pci_latency; /* PYXIS revision */ unsigned pyxis$v_fill11 : 16; } pyxis$r_latency_bits; } pyxis$r_pci_latency; unsigned char pyxis$b_fill20 [60]; /* PYXIS Control register 8740000100 */ __union { int pyxis$l_pyxis_ctl; __struct { unsigned pyxis$v_pyxis_ctrl_pci_en : 1; /*PYXIS disable/enable resets to PCI */ unsigned pyxis$v_pyxis_ctrl_pci_lock_en : 1; /*PYXIS locks from PCI enable */ unsigned pyxis$v_pyxis_ctrl_pci_loop_en : 1; /*PYXIS loopback enable */ unsigned pyxis$v_pyxis_ctrl_fst_bb_en : 1; /*PYXIS fast back-to-back enable */ unsigned pyxis$v_pyxis_ctrl_mst_en : 1; /*PYXIS is a PCI master enable */ unsigned pyxis$v_pyxis_ctrl_mem_en : 1; /*PYXIS is a PCI target enable */ unsigned pyxis$v_pyxis_ctrl_req64_en : 1; /*PYXIS will request 64bit PCI txactions */ unsigned pyxis$v_pyxis_ctrl_ack64_en : 1; /*PYXIS will accept 64bit PCI txactions */ unsigned pyxis$v_pyxis_ctrl_addr_pe_en : 1; /*PYXIS will check address parity enable */ unsigned pyxis$v_pyxis_ctrl_perr_en : 1; /*PYXIS will check PCI data enable */ unsigned pyxis$v_pyxis_ctrl_fill_err_en : 1; /*PYXIS will assert fill_err enable */ unsigned pyxis$v_fill20 : 1; unsigned pyxis$v_pyxis_ctrl_ecc_chk_en : 1; /*PYXIS checks IOD data enable */ unsigned pyxis$v_pyxis_ctrl_cack_en_pe : 1; /*PYXIS checks c/a parity on CACK */ unsigned pyxis$v_pyxis_ctrl_con_idle_bc : 1; /*PYXIS generated contig. IDLE_BC */ unsigned pyxis$v_pyxis_ctrl_csr_ioa_byp : 1; /*PYXIS bypasses I/O addr queue */ unsigned pyxis$v_pyxis_ctrl_io_flush_req : 1; /*Controls response to PCI FLUSH_REQ */ unsigned pyxis$v_pyxis_ctrl_cpu_flush_req : 1; /*Controls response to PCI FLUSH_REQ */ unsigned pyxis$v_pyxis_ctrl_arb_ev5_en : 1; /*Enable bypass path ev5 to mem/io */ unsigned pyxis$v_pyxis_ctrl_en_arb_link : 1; unsigned pyxis$v_pyxis_ctrl_rd_typ : 2; /*Control prefetch algorithm RD */ unsigned pyxis$v_fill21 : 2; unsigned pyxis$v_pyxis_ctrl_rl_typ : 2; /*Control prefetch algorithm RL */ unsigned pyxis$v_fill22 : 2; unsigned pyxis$v_pyxis_ctrl_rm_typ : 2; /*Control prefetch algorithm RM */ unsigned pyxis$v_fill23 : 2; } pyxis$r_pyxis_control_bits; } pyxis$r_pyxis_ctrl; unsigned char pyxis$b_fill30 [60]; /* PYXIS CTRL1 register 8740000140 */ __union { int pyxis$l_pyxis_ctl1; __struct { unsigned pyxis$v_pyxis_ctrl1_ioa_ben : 1; /*PYXIS disable/enable */ unsigned pyxis$v_fillaa : 3; unsigned pyxis$v_pyxis_ctrl1_pci_mwin_ena : 1; /*PYXIS disable/enable Monster window */ unsigned pyxis$v_fillab : 3; unsigned pyxis$v_pyxis_ctrl1_pci_link_ena : 1; /*PYXIS disable/enable */ unsigned pyxis$v_fillac : 3; unsigned pyxis$v_pyxis_ctrl1_lw_par_mode : 1; /*PYXIS */ unsigned pyxis$v_fill_0_ : 3; } pyxis$r_pyxis_control1_bits; } pyxis$r_pyxis_ctrl1; unsigned char pyxis$b_fill30i [188]; /* PYXIS Config => Size information of the two busses 8740000200 */ __union { int pyxis$l_pyxis_config; __struct { char pyxis$b_fill30a; unsigned pyxis$v_pyxis_cnfg_pci_width : 1; /* Bit is set -> 64bit PCI */ unsigned pyxis$v_fill31 : 7; unsigned pyxis$v_pyxis_cnfg_iod_width : 1; /* Bit is set -> 64bit IOD */ unsigned pyxis$v_fill32 : 15; } pyxis$r_pyxis_config_bits; } pyxis$r_pyxis_config_overlay; unsigned char pyxis$b_fill40 [508]; /* HAE MEM => Extends sparse space addr to full 32 bits 8740000400 */ __union { int pyxis$l_hae_mem; __struct { unsigned pyxis$v_fill40a : 2; unsigned pyxis$v_hae_mem_reg_3 : 6; /* High order sparse bits */ unsigned pyxis$v_fill41 : 3; unsigned pyxis$v_hae_mem_reg_2 : 5; /* High order sparse bits */ unsigned pyxis$v_fill42 : 13; unsigned pyxis$v_hae_mem_reg_1 : 3; /* High order sparse bits */ } pyxis$r_hae_mem_bits; } pyxis$r_hae_mem_overlay; unsigned char pyxis$b_fill50 [60]; /* HAE IO => Extends sparse space addr to full 32 bits 8740000440 */ __union { int pyxis$l_hae_io; __struct { unsigned pyxis$v_fill51 : 25; unsigned pyxis$v_hae_io : 7; /* High order sparse bits */ } pyxis$r_hae_io_bits; } pyxis$r_hae_io_overlay; unsigned char pyxis$b_fill60 [60]; /* CFG => Low two address bits during access to PCI COnfig space 8740000480 */ __union { int pyxis$l_cfg; __struct { unsigned pyxis$v_cfg_bits : 2; /* Low order bits of config space ref */ unsigned pyxis$v_fill61 : 29; unsigned pyxis$v_fill_1_ : 1; } pyxis$r_cgf_bits_overlay; } pyxis$r_cfg_overlay; unsigned char pyxis$b_fill70 [7036]; /* PYXIS_DIAG Diagnostic control enable 840002000 */ __union { int pyxis$l_pyxis_diag; __struct { unsigned pyxis$v_from_en : 1; /* FROM write enable */ unsigned pyxis$v_use_check : 1; /* USed with DIA_CHECK for ECC testing */ unsigned pyxis$v_fill81 : 26; unsigned pyxis$v_fpe_pci : 2; /* Force bad parity on PCI */ unsigned pyxis$v_fill82 : 1; unsigned pyxis$v_fpe_to_ev5 : 1; /* Force parity error */ } pyxis$r_pyxis_diag_bits; } pyxis$r_pyxis_diag_overlay; unsigned char pyxis$b_fill90 [4092]; /* DIAG_CHECK Diagnostic used to write a known ECC pattern 840003000 */ __union { int pyxis$l_diag_check; __struct { char pyxis$b_diag_check_ecc; /* ECC to be used */ unsigned pyxis$v_fill91 : 24; } pyxis$r_diag_check_bits; } pyxis$r_diag_check_overlay; unsigned char pyxis$b_fill100 [4092]; /* Perf Monitor counts 8740004000 */ __union { int pyxis$l_perf_monitor; } pyxis$r_perf_monitor_overlay; unsigned char pyxis$b_fill110 [60]; /* Perf Monitor control 8740004040 */ __union { int pyxis$l_perf_control; } pyxis$r_perf_control_overlay; unsigned char pyxis$b_fill120 [8124]; /* PYXIS Error register 8740008200 */ unsigned char pyxis$b_fill120a [512]; __union { int pyxis$l_pyxis_err; __struct { unsigned pyxis$v_err_corr_ecc : 1; /* [0] */ unsigned pyxis$v_err_unc_ecc : 1; /* [1] */ unsigned pyxis$v_err_cpu_pe : 1; /* [2] */ unsigned pyxis$v_err_mem_nem : 1; /* [3] */ unsigned pyxis$v_err_pci_serr : 1; /* [4] */ unsigned pyxis$v_err_pci_perr : 1; /* [5] */ unsigned pyxis$v_err_pci_adr_pe : 1; /* [6] */ unsigned pyxis$v_err_m_abort : 1; /* [7] */ unsigned pyxis$v_err_t_abort : 1; /* [8] */ unsigned pyxis$v_err_pa_pte_inv : 1; /* [9] */ unsigned pyxis$v_err_fill : 1; /* [10] */ unsigned pyxis$v_err_ioa_timeout : 1; /* [11] */ unsigned pyxis$v_err_ioa_reserved_0 : 4; /* [15:12] */ unsigned pyxis$v_err_lost_corr_ecc : 1; unsigned pyxis$v_err_lost_unc_ecc : 1; unsigned pyxis$v_err_lost_cpu_pe : 1; unsigned pyxis$v_err_lost_mem_nem : 1; unsigned pyxis$v_err_lost_pci_fill : 1; unsigned pyxis$v_err_lost_pci_perr : 1; unsigned pyxis$v_err_lost_pci_adr_pe : 1; unsigned pyxis$v_err_lost_m_abort : 1; unsigned pyxis$v_err_lost_t_abort : 1; unsigned pyxis$v_err_lost_pa_pte_inv : 1; unsigned pyxis$v_err_lost_from_wrt_err_fill : 1; unsigned pyxis$v_err_lost_ioa_timeout : 1; unsigned pyxis$v_err_lost_reserved_1 : 3; /* */ unsigned pyxis$v_err_valid : 1; } pyxis$r_pyxis_err_bits; } pyxis$r_pyxis_err_overlay; unsigned char pyxis$b_fill150 [60]; /* */ /* PYXIS Error status register - 0x8740008240 */ /* */ __union { int pyxis$l_pyxis_stat; __struct { unsigned pyxis$v_stat_pci_0 : 1; /* [0] */ unsigned pyxis$v_stat_pci_1 : 1; /* [1] */ unsigned pyxis$v_stat_fill : 2; /* [3:2] */ unsigned pyxis$v_stat_ioa_valid : 4; /* [7:4] */ unsigned pyxis$v_stat_fill2 : 3; /* [10:8] */ unsigned pyxis$v_stat_tlb_miss : 1; /* [11] */ unsigned pyxis$v_stat_reserved_0 : 20; /* [31:12] */ } pyxis$r_pyxis_stat_bits; } pyxis$r_pyxis_stat_overlay; unsigned char pyxis$b_fill160 [60]; /* */ /* */ /* PYXIS Error mask register - 0x8740008280 */ /* */ __union { int pyxis$l_pyxis_error_mask; __struct { unsigned pyxis$v_mask_corr_ecc_err : 1; /* [0] */ unsigned pyxis$v_mask_unc_ecc_err : 1; /* [1] */ unsigned pyxis$v_mask_cpu_pe : 1; /* [2] */ unsigned pyxis$v_mask_mem_nem : 1; /* [3] */ unsigned pyxis$v_mask_pci_serr : 1; /* [4] */ unsigned pyxis$v_mask_pci_perr : 1; /* [5] */ unsigned pyxis$v_mask_pci_adr_pe : 1; /* [6] */ unsigned pyxis$v_mask_m_abort : 1; /* [7] */ unsigned pyxis$v_mask_t_abort : 1; /* [8] */ unsigned pyxis$v_mask_pa_pte_inv : 1; /* [9] */ unsigned pyxis$v_mask_fill : 1; /* [10] */ unsigned pyxis$v_mask_ioa_timeout : 1; /* [11] */ unsigned pyxis$v_mask_reserved_1 : 20; /* [30:12] */ } pyxis$r_pyxis_error_mask_bits; } pyxis$r_pyxis_error_mask_overlay; unsigned char pyxis$b_fill170 [124]; /* */ /* PYXIS Error Syndrome register - 0x8740008300 */ /* */ __union { int pyxis$l_pyxis_synd; __struct { unsigned pyxis$v_pyxis_syndrome0 : 8; unsigned pyxis$v_pyxis_syndrome1 : 8; unsigned pyxis$v_pyxis_raw_check_bits : 8; unsigned pyxis$v_pyxis_synd_ce0 : 1; /* [24] */ unsigned pyxis$v_pyxis_synd_ce1 : 1; /* [25] */ unsigned pyxis$v_pyxis_synd_uce0 : 1; /* [26] */ unsigned pyxis$v_pyxis_synd_uce1 : 1; /* [27] */ unsigned pyxis$v_fill : 4; } pyxis$r_pyxis_synd_bits; } pyxis$r_pyxis_syndrome; unsigned char pyxis$b_fill171 [4]; /* */ /* PYXIS Error data register - 0x8740008308 */ /* */ __union { __int64 pyxis$q_pyxis_errdata; } pyxis$r_pyxis_errdat_overlay; unsigned char pyxis$b_fill180 [240]; /* */ /* PYXIS Memory Error Address register 0 - 0x8740008400 */ /* */ __union { int pyxis$l_pyxis_mear; __struct { unsigned pyxis$v_unused_0 : 4; unsigned pyxis$v_mear_addr_h : 28; } pyxis$r_pyxis_mear_bits; } pyxis$r_pyxis_mear_overlay; unsigned char pyxis$b_fill190 [60]; /* */ /* PYXIS Memory Error status register 1 - 0x8740008440 */ /* */ __union { int pyxis$l_pyxis_mesr; __struct { unsigned pyxis$v_mesr_addr_3932 : 8; /* [7:0] */ unsigned pyxis$v_mesr_dma_rd_nxm : 1; /* [8] */ unsigned pyxis$v_mesr_dma_wr_nxm : 1; /* [9] */ unsigned pyxis$v_mesr_cpu_rd_nxm : 1; /* [10] */ unsigned pyxis$v_mesr_cpu_wr_nxm : 1; /* [11] */ unsigned pyxis$v_mesr_io_rd_nxm : 1; /* [12] */ unsigned pyxis$v_mesr_io_wr_nxm : 1; /* [13] */ unsigned pyxis$v_mesr_victim_nxm : 1; /* [14] */ unsigned pyxis$v_mesr_tlbfill_nxm : 1; /* [15] */ unsigned pyxis$v_mesr_oword_index : 2; /* [17:16] */ unsigned pyxis$v_mesr_reserved_2 : 2; /* [19:18] */ unsigned pyxis$v_mesr_data_cycle_typ : 5; /* [24:20] */ unsigned pyxis$v_mesr_seq_st : 7; /* [31:25] */ } pyxis$r_pyxis_mesr_bits; } pyxis$r_pyxis_mesr_overlay; unsigned char pyxis$b_fill200 [956]; /* */ /* PCI Error register 0 - 0x8740008800 */ /* */ __union { int pyxis$l_pyxis_pcie0; __struct { unsigned pyxis$v_pcie_dma_cmd : 4; /* [3:0] */ unsigned pyxis$v_pcie_reserved0 : 1; /* [4] */ unsigned pyxis$v_pcie_dma_dac : 1; /* [5] */ unsigned pyxis$v_pcie_reserved : 2; /* [7:6] */ unsigned pyxis$v_pcie_window : 4; /* [11:8] */ unsigned pyxis$v_pcie_reserved_2 : 4; /* [15:12] */ unsigned pyxis$v_pcie_mstr_state : 4; /* [19:16] */ unsigned pyxis$v_pcie_trgt_state : 4; /* [23:20] */ unsigned pyxis$v_pcie_pci_cmd : 4; /* [27:24] */ unsigned pyxis$v_pcie_pci_dac : 1; /* [28] */ unsigned pyxis$v_pcie_unused_2 : 3; /* [31:29] */ } pyxis$r_pyxis_pcie_bits; } pyxis$r_pyxis_pcie0_overlay; unsigned char pyxis$b_fill210 [60]; /* */ /* PYXIS PCI error register 1 - 0x8740008840 */ /* */ __union { int pyxis$l_pcie1_dma_addr_h; } pyxis$r_pyxis_pcie1_overlay; unsigned char pyxis$b_fill220 [60]; /* */ /* PYXIS PCI error register 2 - 0x8740008880 */ /* */ __union { int pyxis$l_pcie2_pci_addr_h; } pyxis$r_pyxis_pcie2_overlay; unsigned char pyxis$b_fill221 [6012]; /* */ /* Memory Configuration Register - 0x8750000000 */ /* */ __union { int pyxis$l_mem_mcr; __struct { unsigned pyxis$v_mcr_mode_req : 1; /* 0 */ unsigned pyxis$v_mcr_reserved : 7; /* */ unsigned pyxis$v_mcr_server_mode : 1; /* 8 */ unsigned pyxis$v_mcr_bcache_stat : 1; /* 9 */ unsigned pyxis$v_mcr_bcache_en : 1; /* 10 */ unsigned pyxis$v_mcr_pipelined_cache : 1; /* 11 */ unsigned pyxis$v_mcr_overlap_dis : 1; /* 12 */ unsigned pyxis$v_mcr_seq_trace : 1; /* 13 */ unsigned pyxis$v_mcr_cke_auto : 1; /* 14 */ unsigned pyxis$v_mcr_dram_clk_auto : 1; /* 15 */ unsigned pyxis$v_mcr_dram_mode : 14; /* 29:16 */ unsigned pyxis$v_mcr_reserved_2 : 2; /* 31:30 */ } pyxis$r_mem_mcr_bits; } pyxis$r_mem_mcr_overlay; unsigned char pyxis$b_fill230 [60]; /* */ /* Memory Clock Mask Register - 0x8750000040 */ /* */ __union { int pyxis$l_mem_mcmr; __struct { unsigned pyxis$v_mcmr_dram_clock_mask : 16; /* 15:0 */ unsigned pyxis$v_mcmr_reserved_1 : 16; /* 31:16 */ } pyxis$r_mem_mcmr_data; } pyxis$r_mem_mcmr_overlay; unsigned char pyxis$b_fill231 [444]; /* */ /* Memory Global Timing Register - 0x8750000200 */ /* */ __union { int pyxis$l_mem_mgtr; __struct { unsigned pyxis$v_mgtr_min_ras_pre : 3; /* 2:0 */ unsigned pyxis$v_mgtr_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mgtr_cas_lat : 2; /* 5:4 */ unsigned pyxis$v_mgtr_reserved_2 : 2; /* 7:6 */ unsigned pyxis$v_mgtr_idle_bc_width : 3; /* 10:8 */ unsigned pyxis$v_mgtr_reserved_3 : 21; /* 31:11 */ } pyxis$r_mem_mgtr_data; } pyxis$r_mem_mgtr_overlay; unsigned char pyxis$b_fill232 [252]; /* */ /* Memory Refresh Timing Register - 0x8750000300 */ /* */ __union { int pyxis$l_mem_mrtr; __struct { unsigned pyxis$v_mrtr_reserved_1 : 4; /* 3:0 */ unsigned pyxis$v_mrtr_ref_width : 3; /* 6:4 */ unsigned pyxis$v_mrtr_ref_int : 6; /* 12:7 */ unsigned pyxis$v_mrtr_reserved_2 : 2; /* 14:13 */ unsigned pyxis$v_mrtr_force_ref : 1; /* 15 */ unsigned pyxis$v_mrtr_reserved_3 : 16; /* 31:16 */ } pyxis$r_mem_mrtr_data; } pyxis$r_mem_mrtr_overlay; unsigned char pyxis$b_fill233 [252]; /* */ /* Memory Row History Policy Register - 0x8750000400 */ /* */ __union { int pyxis$l_mem_mrphr; __struct { unsigned pyxis$v_mrphr_policy_mask : 16; /* 15:0 */ unsigned pyxis$v_mrphr_reserved_3 : 16; /* 31:16 */ } pyxis$r_mem_mrphr_data; } pyxis$r_mem_mrphr_overlay; unsigned char pyxis$b_fill234 [252]; /* */ /* Memory Debug Register 1 - 0x8750000500 */ /* */ __union { int pyxis$l_mem_mdr1; __struct { unsigned pyxis$v_mdr1_sel0 : 6; /* 5:0 */ unsigned pyxis$v_mdr1_reserved_1 : 2; /* 7:6 */ unsigned pyxis$v_mdr1_sel1 : 6; /* 13:8 */ unsigned pyxis$v_mdr1_reserved_2 : 2; /* 15:14 */ unsigned pyxis$v_mdr1_sel2 : 6; /* 21:16 */ unsigned pyxis$v_mdr1_reserved_3 : 2; /* 23:22 */ unsigned pyxis$v_mdr1_sel3 : 6; /* 29:24 */ unsigned pyxis$v_mdr1_reserved_4 : 1; /* 30 */ unsigned pyxis$v_mdr1_enable : 1; /* 31 */ } pyxis$r_mem_mdr1_data; } pyxis$r_mem_mdr1_overlay; unsigned char pyxis$b_fill235 [60]; /* */ /* Memory Debug Register 2 - 0x8750000540 */ /* */ __union { int pyxis$l_mem_mdr2; __struct { unsigned pyxis$v_mdr2_sel0 : 6; /* 5:0 */ unsigned pyxis$v_mdr2_reserved_1 : 2; /* 7:6 */ unsigned pyxis$v_mdr2_sel1 : 6; /* 13:8 */ unsigned pyxis$v_mdr2_reserved_2 : 2; /* 15:14 */ unsigned pyxis$v_mdr2_sel2 : 6; /* 21:16 */ unsigned pyxis$v_mdr2_reserved_3 : 2; /* 23:22 */ unsigned pyxis$v_mdr2_sel3 : 6; /* 29:24 */ unsigned pyxis$v_mdr2_reserved_4 : 1; /* 30 */ unsigned pyxis$v_mdr2_enable : 1; /* 31 */ } pyxis$r_mem_mdr2_data; } pyxis$r_mem_mdr2_overlay; unsigned char pyxis$b_fill236 [188]; /* */ /* Memory Base Address Register 0 - 0x8750000600 */ /* */ __union { int pyxis$l_mem_bbar0; __struct { unsigned pyxis$v_bbar0_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar0_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar0_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar0_data; } pyxis$r_mem_bbar0_overlay; unsigned char pyxis$b_fill237a [60]; /* */ /* Memory Base Address Register 1 - 0x8750000640 */ /* */ __union { int pyxis$l_mem_bbar1; __struct { unsigned pyxis$v_bbar1_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar1_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar1_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar1_data; } pyxis$r_mem_bbar1_overlay; unsigned char pyxis$b_fill237b [60]; /* */ /* Memory Base Address Register 2 - 0x8750000680 */ /* */ __union { int pyxis$l_mem_bbar2; __struct { unsigned pyxis$v_bbar2_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar2_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar2_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar2_data; } pyxis$r_mem_bbar2_overlay; unsigned char pyxis$b_fill237c [60]; /* */ /* Memory Base Address Register 3 - 0x87500006c0 */ /* */ __union { int pyxis$l_mem_bbar3; __struct { unsigned pyxis$v_bbar3_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar3_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar3_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar3_data; } pyxis$r_mem_bbar3_overlay; unsigned char pyxis$b_fill237d [60]; /* */ /* Memory Base Address Register 4 - 0x8750000700 */ /* */ __union { int pyxis$l_mem_bbar4; __struct { unsigned pyxis$v_bbar4_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar4_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar4_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar4_data; } pyxis$r_mem_bbar4_overlay; unsigned char pyxis$b_fill237e [60]; /* */ /* Memory Base Address Register 5 - 0x8750000740 */ /* */ __union { int pyxis$l_mem_bbar5; __struct { unsigned pyxis$v_bbar5_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar5_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar5_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar5_data; } pyxis$r_mem_bbar5_overlay; unsigned char pyxis$b_fill237f [60]; /* */ /* Memory Base Address Register 6 - 0x8750000780 */ /* */ __union { int pyxis$l_mem_bbar6; __struct { unsigned pyxis$v_bbar6_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar6_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar6_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar6_data; } pyxis$r_mem_bbar6_overlay; unsigned char pyxis$b_fill237g [60]; /* */ /* Memory Base Address Register 7 - 0x87500007c0 */ /* */ __union { int pyxis$l_mem_bbar7; __struct { unsigned pyxis$v_bbar7_reserved_1 : 6; /* 5:0 */ unsigned pyxis$v_bbar7_base_addr_3324 : 10; /* 15:6 */ unsigned pyxis$v_bbar7_reserved_2 : 16; /* 31:16 */ } pyxis$r_mem_bbar7_data; } pyxis$r_mem_bbar7_overlay; unsigned char pyxis$b_fill237h [60]; /* */ /* Start of Bank Config */ /* */ /* Memory Bank Configuration Register 0 - 0x8750000800 */ /* */ __union { int pyxis$l_mem_mbcr0; __struct { unsigned pyxis$v_mbcr0_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr0_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr0_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr0_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr0_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr0_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr0_data; } pyxis$r_mem_mbcr0_overlay; unsigned char pyxis$b_fill238a [60]; /* */ /* Memory Bank Configuration Register 1 - 0x8750000840 */ /* */ __union { int pyxis$l_mem_mbcr1; __struct { unsigned pyxis$v_mbcr1_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr1_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr1_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr1_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr1_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr1_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr1_data; } pyxis$r_mem_mbcr1_overlay; unsigned char pyxis$b_fill238b [60]; /* */ /* Memory Bank Configuration Register 2 - 0x8750000880 */ /* */ __union { int pyxis$l_mem_mbcr2; __struct { unsigned pyxis$v_mbcr2_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr2_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr2_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr2_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr2_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr2_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr2_data; } pyxis$r_mem_mbcr2_overlay; unsigned char pyxis$b_fill238c [60]; /* */ /* Memory Bank Configuration Register 3 - 0x87500008c0 */ /* */ __union { int pyxis$l_mem_mbcr3; __struct { unsigned pyxis$v_mbcr3_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr3_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr3_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr3_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr3_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr3_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr3_data; } pyxis$r_mem_mbcr3_overlay; unsigned char pyxis$b_fill238d [60]; /* */ /* Memory Bank Configuration Register 4 - 0x8750000900 */ /* */ __union { int pyxis$l_mem_mbcr4; __struct { unsigned pyxis$v_mbcr4_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr4_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr4_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr4_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr4_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr4_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr4_data; } pyxis$r_mem_mbcr4_overlay; unsigned char pyxis$b_fill238e [60]; /* */ /* Memory Bank Configuration Register 5 - 0x8750000940 */ /* */ __union { int pyxis$l_mem_mbcr5; __struct { unsigned pyxis$v_mbcr5_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr5_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr5_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr5_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr5_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr5_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr5_data; } pyxis$r_mem_mbcr5_overlay; unsigned char pyxis$b_fill238f [60]; /* */ /* Memory Bank Configuration Register 6 - 0x8750000980 */ /* */ __union { int pyxis$l_mem_mbcr6; __struct { unsigned pyxis$v_mbcr6_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr6_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr6_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr6_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr6_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr6_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr6_data; } pyxis$r_mem_mbcr6_overlay; unsigned char pyxis$b_fill238g [60]; /* */ /* Memory Bank Configuration Register 7 - 0x87500009c0 */ /* */ __union { int pyxis$l_mem_mbcr7; __struct { unsigned pyxis$v_mbcr7_bank_enable : 1; /* 0 */ unsigned pyxis$v_mbcr7_bank_size : 4; /* 4:1 */ unsigned pyxis$v_mbcr7_subbank_enable : 1; /* 5 */ unsigned pyxis$v_mbcr7_colsel : 1; /* 6 */ unsigned pyxis$v_mbcr7_4bank : 1; /* 7 */ unsigned pyxis$v_mbcr7_reserved_2 : 24; /* 31:8 */ } pyxis$r_mem_mbcr7_data; } pyxis$r_mem_mbcr7_overlay; unsigned char pyxis$b_fill238h [60]; /* */ /* Start of Bank TIming Registers */ /* Memory Bank TIming Register 0 - 0x8750000A00 */ /* */ __union { int pyxis$l_mem_mbtr0; __struct { unsigned pyxis$v_mbtr0_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr0_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr0_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr0_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr0_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr0_data; } pyxis$r_mem_mbtr0_overlay; unsigned char pyxis$b_fill239a [60]; /* */ /* Memory Bank TIming Register 1 - 0x8750000A40 */ /* */ __union { int pyxis$l_mem_mbtr1; __struct { unsigned pyxis$v_mbtr1_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr1_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr1_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr1_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr1_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr1_data; } pyxis$r_mem_mbtr1_overlay; unsigned char pyxis$b_fill239b [60]; /* */ /* Memory Bank TIming Register 2 - 0x8750000A80 */ /* */ __union { int pyxis$l_mem_mbtr2; __struct { unsigned pyxis$v_mbtr2_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr2_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr2_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr2_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr2_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr2_data; } pyxis$r_mem_mbtr2_overlay; unsigned char pyxis$b_fill239c [60]; /* */ /* Memory Bank TIming Register 3 - 0x8750000Ac0 */ /* */ __union { int pyxis$l_mem_mbtr3; __struct { unsigned pyxis$v_mbtr3_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr3_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr3_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr3_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr3_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr3_data; } pyxis$r_mem_mbtr3_overlay; unsigned char pyxis$b_fill239d [60]; /* */ /* Memory Bank TIming Register 4 - 0x8750000B00 */ /* */ __union { int pyxis$l_mem_mbtr4; __struct { unsigned pyxis$v_mbtr4_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr4_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr4_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr4_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr4_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr4_data; } pyxis$r_mem_mbtr4_overlay; unsigned char pyxis$b_fill239e [60]; /* */ /* Memory Bank TIming Register 5 - 0x8750000B40 */ /* */ __union { int pyxis$l_mem_mbtr5; __struct { unsigned pyxis$v_mbtr5_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr5_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr5_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr5_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr5_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr5_data; } pyxis$r_mem_mbtr5_overlay; unsigned char pyxis$b_fill239f [60]; /* */ /* Memory Bank TIming Register 6 - 0x8750000B80 */ /* */ __union { int pyxis$l_mem_mbtr6; __struct { unsigned pyxis$v_mbtr6_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr6_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr6_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr6_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr6_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr6_data; } pyxis$r_mem_mbtr6_overlay; unsigned char pyxis$b_fill239g [60]; /* */ /* Memory Bank TIming Register 7 - 0x8750000BC0 */ /* */ __union { int pyxis$l_mem_mbtr7; __struct { unsigned pyxis$v_mbtr7_row_addr_hold : 3; /* 2:0 */ unsigned pyxis$v_mbtr7_reserved_1 : 1; /* 3 */ unsigned pyxis$v_mbtr7_toshiba : 1; /* 4 */ unsigned pyxis$v_mbtr7_slow_charge : 1; /* 5 */ unsigned pyxis$v_mbtr7_reserved_2 : 26; /* 31:6 */ } pyxis$r_mem_mbtr7_data; } pyxis$r_mem_mbtr7_overlay; unsigned char pyxis$b_fill239h [60]; /* */ /* Memory Cache Valid Mask - 0x8750000C00 */ /* */ __union { int pyxis$l_mem_cvm; __struct { unsigned pyxis$v_cvm_cache_valid_mask : 31; /* 31:0 */ unsigned pyxis$v_fill_2_ : 1; } pyxis$r_mem_cvm_data; } pyxis$r_mem_cvm_overlay; unsigned char pyxis$b_fill239i [5116]; /* */ /* PCI Scatter/Gather TBIA - 0x8760000100 */ /* */ unsigned char pyxis$b_fill345 [256]; __union { int pyxis$l_pci_tbia; __struct { unsigned pyxis$v_tbia_csr_wr_data : 2; /* */ unsigned pyxis$v_tbia_reserved : 29; /* */ unsigned pyxis$v_fill_3_ : 1; } pyxis$r_pci_tbia_bits; } pyxis$r_pci_tbia_overlay; unsigned char pyxis$b_fill350 [764]; /* */ /* PCI Window Base 0 - 0x8760000400 */ /* */ __union { int pyxis$l_pci_wbase0; __struct { unsigned pyxis$v_wbase0_w_en : 1; /* */ unsigned pyxis$v_wbase0_sg_en : 1; /* enable scatter/gather */ unsigned pyxis$v_wbase0_memcs_en : 1; /* enable MEMCS */ unsigned pyxis$v_wbase0_dac_en : 1; /* enable 64BIT PCI */ unsigned pyxis$v_wbase0_reserved : 16; /* */ unsigned pyxis$v_wbase0_base : 12; } pyxis$r_pci_wbase0_bits; } pyxis$r_pci_wbase0_overlay; unsigned char pyxis$b_fill360 [60]; /* */ /* PCI Window Mask 0 - 0x8760000440 */ /* */ __union { int pyxis$l_pci_wmask0; __struct { unsigned pyxis$v_wmask0_reserved : 20; /* */ unsigned pyxis$v_wmask0_mask : 12; } pyxis$r_pci_wmask0_bits; } pyxis$r_pci_wmask0_overlay; unsigned char pyxis$b_fill370 [60]; /* */ /* PCI Window Translated Base 0 - 0x8760000480 */ /* */ __union { int pyxis$l_pci_tbase0; __struct { unsigned pyxis$v_tbase0_reserved : 8; /* */ unsigned pyxis$v_tbase0_base : 24; } pyxis$r_pci_tbase0_bits; } pyxis$r_pci_tbase0_overlay; unsigned char pyxis$b_fill380 [124]; /****** */ /* */ /* PCI Window Base 1 - 0x8760000500 */ /* */ __union { int pyxis$l_pci_wbase1; __struct { unsigned pyxis$v_wbase1_w_en : 1; /* */ unsigned pyxis$v_wbase1_sg_en : 1; /* enable scatter/gather */ unsigned pyxis$v_wbase1_memcs_en : 1; /* enable MEMCS */ unsigned pyxis$v_wbase1_dac_en : 1; /* enable 64BIT PCI */ unsigned pyxis$v_wbase1_reserved : 16; /* */ unsigned pyxis$v_wbase1_base : 12; } pyxis$r_pci_wbase1_bits; } pyxis$r_pci_wbase1_overlay; unsigned char pyxis$b_fill390 [60]; /* */ /* PCI Window Mask 1 - 0x8760000540 */ /* */ __union { int pyxis$l_pci_wmask1; __struct { unsigned pyxis$v_wmask1_reserved : 20; /* */ unsigned pyxis$v_wmask1_mask : 12; } pyxis$r_pci_wmask1_bits; } pyxis$r_pci_wmask1_overlay; unsigned char pyxis$b_fill400 [60]; /* */ /* PCI Window Translated Base 1 - 0x8760000580 */ /* */ __union { int pyxis$l_pci_tbase1; __struct { unsigned pyxis$v_tbase1_reserved : 8; /* */ unsigned pyxis$v_tbase1_base : 24; } pyxis$r_pci_tbase1_bits; } pyxis$r_pci_tbase1_overlay; unsigned char pyxis$b_fill410 [124]; /* */ /* PCI Window Base 2 - 0x8760000600 */ /* */ __union { int pyxis$l_pci_wbase2; __struct { unsigned pyxis$v_wbase2_w_en : 1; /* */ unsigned pyxis$v_wbase2_sg_en : 1; /* enable scatter/gather */ unsigned pyxis$v_wbase2_memcs_en : 1; /* enable MEMCS */ unsigned pyxis$v_wbase2_dac_en : 1; /* enable 64BIT PCI */ unsigned pyxis$v_wbase2_reserved : 16; /* */ unsigned pyxis$v_wbase2_base : 12; } pyxis$r_pci_wbase2_bits; } pyxis$r_pci_wbase2_overlay; unsigned char pyxis$b_fill420 [60]; /* */ /* PCI Window Mask 2 - 0x8760000640 */ /* */ __union { int pyxis$l_pci_wmask2; __struct { unsigned pyxis$v_wmask2_reserved : 20; /* */ unsigned pyxis$v_wmask2_mask : 12; } pyxis$r_pci_wmask2_bits; } pyxis$r_pci_wmask2_overlay; unsigned char pyxis$b_fill430 [60]; /* */ /* PCI Window Translated Base 2 - 0x8760000680 */ /* */ __union { int pyxis$l_pci_tbase2; __struct { unsigned pyxis$v_tbase2_reserved : 8; /* */ unsigned pyxis$v_tbase2_base : 24; } pyxis$r_pci_tbase2_bits; } pyxis$r_pci_tbase2_overlay; unsigned char pyxis$b_fill440 [124]; /* */ /* PCI Window Base 3 - 0x8760000700 */ /* */ __union { int pyxis$l_pci_wbase3; __struct { unsigned pyxis$v_wbase3_w_en : 1; /* */ unsigned pyxis$v_wbase3_sg_en : 1; /* enable scatter/gather */ unsigned pyxis$v_wbase3_memcs_en : 1; /* enable MEMCS */ unsigned pyxis$v_wbase3_dac_en : 1; /* enable 64BIT PCI */ unsigned pyxis$v_wbase3_reserved : 16; /* */ unsigned pyxis$v_wbase3_base : 12; } pyxis$r_pci_wbase3_bits; } pyxis$r_pci_wbase3_overlay; unsigned char pyxis$b_fill450 [60]; /* */ /* PCI Window Mask 3 - 0x8760000740 */ /* */ __union { int pyxis$l_pci_wmask3; __struct { unsigned pyxis$v_wmask3_reserved : 20; /* */ unsigned pyxis$v_wmask3_mask : 12; } pyxis$r_pci_wmask3_bits; } pyxis$r_pci_wmask3_overlay; unsigned char pyxis$b_fill460 [60]; /* */ /* PCI Window Translated Base 3 - 0x8760000780 */ /* */ __union { int pyxis$l_pci_tbase3; __struct { unsigned pyxis$v_tbase3_reserved : 8; /* */ unsigned pyxis$v_tbase3_base : 24; } pyxis$r_pci_tbase3_bits; } pyxis$r_pci_tbase3_overlay; unsigned char pyxis$b_fill470 [60]; /* */ /* PCI DAC Base Register - 0x87600007C0 */ /* */ __union { int pyxis$l_pci_dac; __struct { unsigned pyxis$v_dac_base : 8; unsigned pyxis$v_dac_reserved : 24; /* */ } pyxis$r_pci_dac_bits; } pyxis$r_pci_dac_overlay; unsigned char pyxis$b_fill480 [60]; /* */ /* PCI Lockable TB Tag 0- 0x8760000800 */ /* */ __union { int pyxis$l_pci_ltb0; __struct { unsigned pyxis$v_ltb0_valid : 1; /* */ unsigned pyxis$v_ltb0_locked : 1; /* enable scatter/gather */ unsigned pyxis$v_ltb0_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_ltb0_reserved : 12; /* */ unsigned pyxis$v_ltb0_tag : 17; } pyxis$r_pci_ltb0_bits; } pyxis$r_pci_ltb0_overlay; unsigned char pyxis$b_fill490 [60]; /* */ /* PCI Lockable TB Tag 1- 0x8760000840 */ /* */ __union { int pyxis$l_pci_ltb1; __struct { unsigned pyxis$v_ltb1_valid : 1; /* */ unsigned pyxis$v_ltb1_locked : 1; /* enable scatter/gather */ unsigned pyxis$v_ltb1_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_ltb1_reserved : 12; /* */ unsigned pyxis$v_ltb1_tag : 17; } pyxis$r_pci_ltb1_bits; } pyxis$r_pci_ltb1_overlay; unsigned char pyxis$b_fill500 [60]; /* */ /* PCI Lockable TB Tag 2- 0x8760000880 */ /* */ __union { int pyxis$l_pci_ltb2; __struct { unsigned pyxis$v_ltb2_valid : 1; /* */ unsigned pyxis$v_ltb2_locked : 1; /* enable scatter/gather */ unsigned pyxis$v_ltb2_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_ltb2_reserved : 12; /* */ unsigned pyxis$v_ltb2_tag : 17; } pyxis$r_pci_ltb2_bits; } pyxis$r_pci_ltb2_overlay; unsigned char pyxis$b_fill510 [60]; /* */ /* PCI Lockable TB Tag 3- 0x87600008C0 */ /* */ __union { int pyxis$l_pci_ltb3; __struct { unsigned pyxis$v_ltb3_valid : 1; /* */ unsigned pyxis$v_ltb3_locked : 1; /* enable scatter/gather */ unsigned pyxis$v_ltb3_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_ltb3_reserved : 12; /* */ unsigned pyxis$v_ltb3_tag : 17; } pyxis$r_pci_ltb3_bits; } pyxis$r_pci_ltb3_overlay; unsigned char pyxis$b_fill520 [60]; /* */ /* PCI TB Tag 0- 0x8760000900 */ /* */ __union { int pyxis$l_pci_tb0; __struct { unsigned pyxis$v_tb0_valid : 1; /* */ unsigned pyxis$v_reserved : 1; /* */ unsigned pyxis$v_tb0_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_tb0_reserved2 : 12; /* */ unsigned pyxis$v_tb0_tag : 17; } pyxis$r_pci_tb0_bits; } pyxis$r_pci_tb0_overlay; unsigned char pyxis$b_fill530 [60]; /* */ /* PCI TB Tag 1 - 0x8760000940 */ /* */ __union { int pyxis$l_pci_tb1; __struct { unsigned pyxis$v_tb1_valid : 1; /* */ unsigned pyxis$v_tb1_reserved : 1; /* */ unsigned pyxis$v_tb1_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_tb1_reserved2 : 12; /* */ unsigned pyxis$v_tb1_tag : 17; } pyxis$r_pci_tb1_bits; } pyxis$r_pci_tb1_overlay; unsigned char pyxis$b_fill540 [60]; /* */ /* PCI TB Tag 2 - 0x8760000980 */ /* */ __union { int pyxis$l_pci_tb2; __struct { unsigned pyxis$v_tb2_valid : 1; /* */ unsigned pyxis$v_tb2_reserved : 1; /* */ unsigned pyxis$v_tb2_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_tb2_reserved2 : 12; /* */ unsigned pyxis$v_tb2_tag : 17; } pyxis$r_pci_tb2_bits; } pyxis$r_pci_tb2_overlay; unsigned char pyxis$b_fill550 [60]; /* */ /* PCI TB Tag 3- 0x87600009C0 */ /* */ __union { int pyxis$l_pci_tb3; __struct { unsigned pyxis$v_tb3_valid : 1; /* */ unsigned pyxis$v_tb3_reserved : 1; /* */ unsigned pyxis$v_tb3_dac : 1; /* enable 64BIT PCI */ unsigned pyxis$v_tb3_reserved2 : 12; /* */ unsigned pyxis$v_tb3_tag : 17; } pyxis$r_pci_tb3_bits; } pyxis$r_pci_tb3_overlay; unsigned char pyxis$b_fill560 [1596]; /* */ /* PCI TB0 Page 0- 0x8760001000 */ /* */ __union { int pyxis$l_pci_tb0_page0; __struct { unsigned pyxis$v_tb0_page0_valid : 1; /* */ unsigned pyxis$v_tb0_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb0_page0_bits; } pyxis$r_pci_tb0_page0_overlay; unsigned char pyxis$b_fill570 [60]; /* */ /* PCI TB0 Page 1 - 0x8760001040 */ /* */ __union { int pyxis$l_pci_tb0_page1; __struct { unsigned pyxis$v_tb0_page1_valid : 1; /* */ unsigned pyxis$v_tb0_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb0_page1_bits; } pyxis$r_pci_tb0_page1_overlay; unsigned char pyxis$b_fill580 [60]; /* */ /* PCI TB0 Page 2 - 0x8760001080 */ /* */ __union { int pyxis$l_pci_tb0_page2; __struct { unsigned pyxis$v_tb0_page2_valid : 1; /* */ unsigned pyxis$v_tb0_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb0_page2_bits; } pyxis$r_pci_tb0_page2_overlay; unsigned char pyxis$b_fill590 [60]; /* */ /* PCI TB0 Page 3- 0x87600010C0 */ /* */ __union { int pyxis$l_pci_tb0_page3; __struct { unsigned pyxis$v_tb0_page3_valid : 1; /* */ unsigned pyxis$v_tb0_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb0_page3_bits; } pyxis$r_pci_tb0_page3_overlay; unsigned char pyxis$b_fill600 [60]; /* */ /* PCI TB1 Page 0- 0x8760001100 */ /* */ __union { int pyxis$l_pci_tb1_page0; __struct { unsigned pyxis$v_tb1_page0_valid : 1; /* */ unsigned pyxis$v_tb1_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb1_page0_bits; } pyxis$r_pci_tb1_page0_overlay; unsigned char pyxis$b_fill610 [60]; /* */ /* PCI TB1 Page 1 - 0x8760001140 */ /* */ __union { int pyxis$l_pci_tb1_page1; __struct { unsigned pyxis$v_tb1_page1_valid : 1; /* */ unsigned pyxis$v_tb1_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb1_page1_bits; } pyxis$r_pci_tb1_page1_overlay; unsigned char pyxis$b_fill620 [60]; /* */ /* PCI TB1 Page 2 - 0x8760001180 */ /* */ __union { int pyxis$l_pci_tb1_page2; __struct { unsigned pyxis$v_tb1_page2_valid : 1; /* */ unsigned pyxis$v_tb1_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb1_page2_bits; } pyxis$r_pci_tb1_page2_overlay; unsigned char pyxis$b_fill630 [60]; /* */ /* PCI TB1 Page 3- 0x87600011C0 */ /* */ __union { int pyxis$l_pci_tb1_page3; __struct { unsigned pyxis$v_tb1_page3_valid : 1; /* */ unsigned pyxis$v_tb1_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb1_page3_bits; } pyxis$r_pci_tb1_page3_overlay; unsigned char pyxis$b_fill640 [60]; /* */ /* PCI TB2 Page 0- 0x8760001200 */ /* */ __union { int pyxis$l_pci_tb2_page0; __struct { unsigned pyxis$v_tb2_page0_valid : 1; /* */ unsigned pyxis$v_tb2_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb2_page0_bits; } pyxis$r_pci_tb2_page0_overlay; unsigned char pyxis$b_fill650 [60]; /* */ /* PCI TB2 Page 1 - 0x8760001240 */ /* */ __union { int pyxis$l_pci_tb2_page1; __struct { unsigned pyxis$v_tb2_page1_valid : 1; /* */ unsigned pyxis$v_tb2_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb2_page1_bits; } pyxis$r_pci_tb2_page1_overlay; unsigned char pyxis$b_fill660 [60]; /* */ /* PCI TB2 Page 2 - 0x8760001280 */ /* */ __union { int pyxis$l_pci_tb2_page2; __struct { unsigned pyxis$v_tb2_page2_valid : 1; /* */ unsigned pyxis$v_tb2_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb2_page2_bits; } pyxis$r_pci_tb2_page2_overlay; unsigned char pyxis$b_fill670 [60]; /* */ /* PCI TB2 Page 3- 0x87600012C0 */ /* */ __union { int pyxis$l_pci_tb2_page3; __struct { unsigned pyxis$v_tb2_page3_valid : 1; /* */ unsigned pyxis$v_tb2_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb2_page3_bits; } pyxis$r_pci_tb2_page3_overlay; unsigned char pyxis$b_fill680 [60]; /* */ /* PCI TB3 Page 0- 0x8760001300 */ /* */ __union { int pyxis$l_pci_tb3_page0; __struct { unsigned pyxis$v_tb3_page0_valid : 1; /* */ unsigned pyxis$v_tb3_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb3_page0_bits; } pyxis$r_pci_tb3_page0_overlay; unsigned char pyxis$b_fill690 [60]; /* */ /* PCI TB3 Page 1 - 0x8760001340 */ /* */ __union { int pyxis$l_pci_tb3_page1; __struct { unsigned pyxis$v_tb3_page1_valid : 1; /* */ unsigned pyxis$v_tb3_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb3_page1_bits; } pyxis$r_pci_tb3_page1_overlay; unsigned char pyxis$b_fill700 [60]; /* */ /* PCI TB3 Page 2 - 0x8760001380 */ /* */ __union { int pyxis$l_pci_tb3_page2; __struct { unsigned pyxis$v_tb3_page2_valid : 1; /* */ unsigned pyxis$v_tb3_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb3_page2_bits; } pyxis$r_pci_tb3_page2_overlay; unsigned char pyxis$b_fill710 [60]; /* */ /* PCI TB3 Page 3- 0x87600013C0 */ /* */ __union { int pyxis$l_pci_tb3_page3; __struct { unsigned pyxis$v_tb3_page3_valid : 1; /* */ unsigned pyxis$v_tb3_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb3_page3_bits; } pyxis$r_pci_tb3_page3_overlay; unsigned char pyxis$b_fill720 [60]; /* */ /* PCI TB4 Page 0- 0x8760001400 */ /* */ __union { int pyxis$l_pci_tb4_page0; __struct { unsigned pyxis$v_tb4_page0_valid : 1; /* */ unsigned pyxis$v_tb4_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb4_page0_bits; } pyxis$r_pci_tb4_page0_overlay; unsigned char pyxis$b_fill730 [60]; /* */ /* PCI TB4 Page 1 - 0x8760001440 */ /* */ __union { int pyxis$l_pci_tb4_page1; __struct { unsigned pyxis$v_tb4_page1_valid : 1; /* */ unsigned pyxis$v_tb4_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb4_page1_bits; } pyxis$r_pci_tb4_page1_overlay; unsigned char pyxis$b_fill740 [60]; /* */ /* PCI TB4 Page 2 - 0x8760001480 */ /* */ __union { int pyxis$l_pci_tb4_page2; __struct { unsigned pyxis$v_tb4_page2_valid : 1; /* */ unsigned pyxis$v_tb4_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb4_page2_bits; } pyxis$r_pci_tb4_page2_overlay; unsigned char pyxis$b_fill750 [60]; /* */ /* PCI TB4 Page 3- 0x87600014C0 */ /* */ __union { int pyxis$l_pci_tb4_page3; __struct { unsigned pyxis$v_tb4_page3_valid : 1; /* */ unsigned pyxis$v_tb4_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb4_page3_bits; } pyxis$r_pci_tb4_page3_overlay; unsigned char pyxis$b_fill760 [60]; /* */ /* PCI TB5 Page 0- 0x8760001500 */ /* */ __union { int pyxis$l_pci_tb5_page0; __struct { unsigned pyxis$v_tb5_page0_valid : 1; /* */ unsigned pyxis$v_tb5_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb5_page0_bits; } pyxis$r_pci_tb5_page0_overlay; unsigned char pyxis$b_fill770 [60]; /* */ /* PCI TB5 Page 1 - 0x8760001540 */ /* */ __union { int pyxis$l_pci_tb5_page1; __struct { unsigned pyxis$v_tb5_page1_valid : 1; /* */ unsigned pyxis$v_tb5_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb5_page1_bits; } pyxis$r_pci_tb5_page1_overlay; unsigned char pyxis$b_fill780 [60]; /* */ /* PCI TB5 Page 2 - 0x8760001580 */ /* */ __union { int pyxis$l_pci_tb5_page2; __struct { unsigned pyxis$v_tb5_page2_valid : 1; /* */ unsigned pyxis$v_tb5_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb5_page2_bits; } pyxis$r_pci_tb5_page2_overlay; unsigned char pyxis$b_fill790 [60]; /* */ /* PCI TB5 Page 3- 0x87600015C0 */ /* */ __union { int pyxis$l_pci_tb5_page3; __struct { unsigned pyxis$v_tb5_page3_valid : 1; /* */ unsigned pyxis$v_tb5_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb5_page3_bits; } pyxis$r_pci_tb5_page3_overlay; unsigned char pyxis$b_fill800 [60]; /* */ /* PCI TB6 Page 0- 0x8760001600 */ /* */ __union { int pyxis$l_pci_tb6_page0; __struct { unsigned pyxis$v_tb6_page0_valid : 1; /* */ unsigned pyxis$v_tb6_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb6_page0_bits; } pyxis$r_pci_tb6_page0_overlay; unsigned char pyxis$b_fill810 [60]; /* */ /* PCI TB6 Page 1 - 0x8760001640 */ /* */ __union { int pyxis$l_pci_tb6_page1; __struct { unsigned pyxis$v_tb6_page1_valid : 1; /* */ unsigned pyxis$v_tb6_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb6_page1_bits; } pyxis$r_pci_tb6_page1_overlay; unsigned char pyxis$b_fill820 [60]; /* */ /* PCI TB6 Page 2 - 0x8760001680 */ /* */ __union { int pyxis$l_pci_tb6_page2; __struct { unsigned pyxis$v_tb6_page2_valid : 1; /* */ unsigned pyxis$v_tb6_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb6_page2_bits; } pyxis$r_pci_tb6_page2_overlay; unsigned char pyxis$b_fill830 [60]; /* */ /* PCI TB6 Page 3- 0x87600016C0 */ /* */ __union { int pyxis$l_pci_tb6_page3; __struct { unsigned pyxis$v_tb6_page3_valid : 1; /* */ unsigned pyxis$v_tb6_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb6_page3_bits; } pyxis$r_pci_tb6_page3_overlay; unsigned char pyxis$b_fill840 [60]; /* */ /* PCI TB7 Page 0- 0x8760001700 */ /* */ __union { int pyxis$l_pci_tb7_page0; __struct { unsigned pyxis$v_tb7_page0_valid : 1; /* */ unsigned pyxis$v_tb7_page0_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb7_page0_bits; } pyxis$r_pci_tb7_page0_overlay; unsigned char pyxis$b_fill850 [60]; /* */ /* PCI TB7 Page 1 - 0x8760001740 */ /* */ __union { int pyxis$l_pci_tb7_page1; __struct { unsigned pyxis$v_tb7_page1_valid : 1; /* */ unsigned pyxis$v_tb7_page1_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb7_page1_bits; } pyxis$r_pci_tb7_page1_overlay; unsigned char pyxis$b_fill860 [60]; /* */ /* PCI TB7 Page 2 - 0x8760001780 */ /* */ __union { int pyxis$l_pci_tb7_page2; __struct { unsigned pyxis$v_tb7_page2_valid : 1; /* */ unsigned pyxis$v_tb7_page2_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb7_page2_bits; } pyxis$r_pci_tb7_page2_overlay; unsigned char pyxis$b_fill870 [60]; /* */ /* PCI TB7 Page 3- 0x87600017C0 */ /* */ __union { int pyxis$l_pci_tb7_page3; __struct { unsigned pyxis$v_tb7_page3_valid : 1; /* */ unsigned pyxis$v_tb7_page3_addr : 21; unsigned pyxis$v_fill : 10; /* */ } pyxis$r_pci_tb7_page3_bits; } pyxis$r_pci_tb7_page3_overlay; unsigned char pyxis$b_fill880 [2108]; /* */ /* Clock Configuration register - 0x8780000000 */ /* */ __union { int pyxis$l_clock_config; __struct { unsigned pyxis$v_ccr_clock_divide : 2; /* 1:0 */ unsigned pyxis$v_ccr_reserved_1 : 5; unsigned pyxis$v_ccr_pclk_divide : 3; /* 10:8 */ unsigned pyxis$v_ccr_reserved_2 : 1; unsigned pyxis$v_ccr_sel_cfg : 1; /* 12 */ unsigned pyxis$v_ccr_reserved_3 : 3; unsigned pyxis$v_ccr_dclk_inv : 1; /* 16 */ unsigned pyxis$v_ccr_dclk_force : 1; /* 17 */ unsigned pyxis$v_ccr_reserved_4 : 7; unsigned pyxis$v_ccr_dclk_delay : 8; /* 31:24 */ } pyxis$r_ccr_bits; } pyxis$r_clock_config_overlay; unsigned char pyxis$b_fill890 [2300]; /* */ /* RESET register - 0x8780000900 */ /* */ __union { int pyxis$l_reset; } pyxis$r_reset_overlay; unsigned char pyxis$b_fill892 [5884]; /* */ /* Fan Accumulation register - 0x8790000000 */ /* */ __union { int pyxis$l_far_reg; __struct { unsigned pyxis$v_far_heat : 24; /* 23:0 */ unsigned pyxis$v_far_reserved_1 : 7; unsigned pyxis$v_fill_4_ : 1; } pyxis$r_far_bits; } pyxis$r_far_overlay; unsigned char pyxis$b_fillaa00 [60]; /* */ /* Fan Control register - 0x8790000040 */ /* */ __union { int pyxis$l_fcr_reg; __struct { unsigned pyxis$v_fcr_on_heat : 8; /* 7:0 */ unsigned pyxis$v_fcr_sample : 8; /* 15:8 */ unsigned pyxis$v_fcr_off_delay : 12; /* 27:16 */ unsigned pyxis$v_fcr_force_fan : 1; /* 28 */ unsigned pyxis$v_fcr_force_fan_hi : 1; /* 29 */ unsigned pyxis$v_fcr_fan_on : 1; /* 30 */ unsigned pyxis$v_fcr_fan_on_hi : 1; /* 31 */ } pyxis$r_fcr_bits; } pyxis$r_fcr_overlay; unsigned char pyxis$b_fillaa01 [60]; /* */ /* Fan THRESHOLD register - 0x8790000080 */ /* */ __union { int pyxis$l_ftr_reg; __struct { unsigned pyxis$v_ftr_fan_on : 8; /* 7:0 */ unsigned pyxis$v_ftr_fan_hi : 8; /* 15:8 */ unsigned pyxis$v_ftr_fan_hi_lo : 8; /* 23:16 */ unsigned pyxis$v_ftr_fan_off : 8; /* 31:24 */ } pyxis$r_ftr_bits; } pyxis$r_ftr_overlay; unsigned char pyxis$b_fillaa02 [60]; /* */ /* Power Control register - 0x87900000C0 */ /* */ __union { int pyxis$l_pcr_reg; __struct { unsigned pyxis$v_pcr_power_down : 1; /* 0 */ unsigned pyxis$v_pcr_fill1 : 3; unsigned pyxis$v_pcr_abus_dis : 1; /* 4 */ unsigned pyxis$v_pcr_fill2 : 3; unsigned pyxis$v_pcr_iint_dis : 1; /* 8 */ unsigned pyxis$v_pcr_fill3 : 3; unsigned pyxis$v_pcr_do_reset : 1; /* 12 */ unsigned pyxis$v_pcr_fill4 : 19; } pyxis$r_pcr_bits; } pyxis$r_pcr_overlay; unsigned char pyxis$b_fillaa03 [60]; /* */ /* Powerdown Timing register - 0x8790000100 */ /* */ __union { int pyxis$l_ptr_reg; __struct { unsigned pyxis$v_ptr_pll_delay : 8; /* 7:0 */ unsigned pyxis$v_ptr_off_delay : 8; /* 15:8 */ unsigned pyxis$v_ptr_reset_pulse_width : 8; /* 23:16 */ unsigned pyxis$v_ptr_min_off_time : 8; /* 31:24 */ } pyxis$r_ptr_bits; } pyxis$r_ptr_overlay; unsigned char pyxis$b_fillaa04 [60]; /* */ /* Power Management register - 0x8790000140 */ /* */ __union { int pyxis$l_psr_reg; } pyxis$r_psr_overlay; unsigned char pyxis$b_fillaa05 [7868]; /* */ /* Int Request Register - 0x87A0000000 */ /* */ __union { __int64 pyxis$q_int_req; __struct { unsigned pyxis$v_int_req_31_0 : 32; /* 31:0 */ unsigned pyxis$v_int_req_61_32 : 30; /* 61:32 */ unsigned pyxis$v_int_req_clk_pend : 1; /* 62 */ unsigned pyxis$v_int_req_err_int : 1; /* 63 */ } pyxis$r_int_req_bits; } pyxis$r_int_req_overlay; unsigned char pyxis$b_fillab00 [56]; /* */ /* Int Mask Register - 0x87A0000040 */ /* */ __union { __int64 pyxis$q_int_mask; __struct { unsigned pyxis$v_int_mask_31_0 : 32; /* 31:0 */ unsigned pyxis$v_int_mask_61_32 : 30; /* 61:32 */ unsigned pyxis$v_int_mask_fill : 2; /* 63 */ } pyxis$r_int_mask_bits; } pyxis$r_int_mask_overlay; unsigned char pyxis$b_fillab01 [120]; /* */ /* Interrupt High/Low select register - 0x87A00000C0 */ /* */ __union { int pyxis$l_int_hilo; __struct { unsigned pyxis$v_int_hilo_byte : 8; unsigned pyxis$v_int_hilo_fill : 24; } pyxis$r_int_hilo_bits; } pyxis$r_int_hilo_overlay; unsigned char pyxis$b_fillab02 [124]; /* */ /* Interrupt Routing register - 0x87A0000140 */ /* */ __union { int pyxis$l_int_route; __struct { unsigned pyxis$v_int_rte : 7; /* */ unsigned pyxis$v_int_rte_fill : 24; unsigned pyxis$v_fill_5_ : 1; } pyxis$r_int_route_bits; } pyxis$r_int_route_overlay; unsigned char pyxis$b_fillab03 [60]; /* */ /* General Purpose Output register - 0x87A0000180 */ /* */ __union { __int64 pyxis$q_gpo_register; } pyxis$r_gpo_overlay; unsigned char pyxis$b_fillab04 [56]; /* */ /* Interrupt Config register - 0x87A00001C0 */ /* */ __union { int pyxis$l_int_config; __struct { unsigned pyxis$v_icnfg_clk_div : 4; /* */ unsigned pyxis$v_icnfg_irq_cnt : 3; /* */ unsigned pyxis$v_icnfg_fill1 : 1; unsigned pyxis$v_icnfg_irq_cfg : 7; /* */ unsigned pyxis$v_icnfg_fill2 : 1; unsigned pyxis$v_icnfg_drive_irq : 1; /* */ unsigned pyxis$v_fill_6_ : 7; } pyxis$r_int_cnfg_bits; } pyxis$r_int_config_overlay; unsigned char pyxis$b_fillab05 [60]; /* */ /* Real Time Counter - 0x87A0000200 */ /* */ __union { __int64 pyxis$q_real_time_counter; } pyxis$r_real_time_counter_overlay; unsigned char pyxis$b_fillab06 [56]; /* */ /* Interrupt Timer - 0x87A0000240 */ /* */ __union { __int64 pyxis$q_interrupt_timer; } pyxis$r_int_time_overlay; unsigned char pyxis$b_fillab07 [120]; /* */ /* IIC Control register - 0x87A00002C0 */ /* */ __union { int pyxis$l_iic_control; __struct { unsigned pyxis$v_iic_read_data : 1; /* */ unsigned pyxis$v_iic_read_clk : 1; /* */ unsigned pyxis$v_iic_data_en : 1; /* */ unsigned pyxis$v_iic_data : 1; /* */ unsigned pyxis$v_iic_clk_en : 1; /* */ unsigned pyxis$v_iic_clk : 1; /* */ unsigned pyxis$v_iic_fill : 26; } pyxis$r_iic_ctrl_bits; } pyxis$r_iic_control_overlay; unsigned char pyxis$b_fillab08 [7484]; /* */ /* CUSCO CPU CSR Registers 87C0100000 */ /* */ char pyxis$b_cpu_csr0; char pyxis$b_cpu_csr1; unsigned char pyxis$b_fillab09 [4094]; /* */ /* CUSCO Clock registers 87.C010.1000 */ /* */ __union { char pyxis$b_fraction_sec; __struct { unsigned pyxis$v_sec_01 : 4; unsigned pyxis$v_sec_1 : 4; } pyxis$r_fraction_sec_bits; } pyxis$r_fraction_sec_overlay; __union { char pyxis$b_second_byte; __struct { unsigned pyxis$v_second : 4; unsigned pyxis$v_sec_10 : 3; unsigned pyxis$v_fill_7_ : 1; } pyxis$r_second_bits; } pyxis$r_second_overlay; __union { char pyxis$b_minute_byte; __struct { unsigned pyxis$v_minute : 4; unsigned pyxis$v_min_10 : 3; unsigned pyxis$v_fill_8_ : 1; } pyxis$r_minute_bits; } pyxis$r_minute_overlay; __union { char pyxis$b_min_alarm_byte; __struct { unsigned pyxis$v_alarm_min : 4; unsigned pyxis$v_alarm_min_10 : 3; unsigned pyxis$v_set_min_alarm : 1; } pyxis$r_min_alarm_bits; } pyxis$r_min_alarm_overlay; __union { char pyxis$b_hour_byte; __struct { unsigned pyxis$v_hour : 4; unsigned pyxis$v_hour_10 : 1; unsigned pyxis$v_ap_10hr : 1; unsigned pyxis$v_twelve : 1; unsigned pyxis$v_fill_9_ : 1; } pyxis$r_hour_bits; } pyxis$r_hour_overlay; __union { char pyxis$b_hour_alarm_byte; __struct { unsigned pyxis$v_alarm_hour : 4; unsigned pyxis$v_alarm_hour_10 : 1; unsigned pyxis$v_alarm_ap_10hr : 1; unsigned pyxis$v_alarm_twelve : 1; unsigned pyxis$v_set_hour_alarm : 1; } pyxis$r_hour_alarm_bits; } pyxis$r_hour_alarm_overlay; __union { char pyxis$b_day_byte; __struct { unsigned pyxis$v_day : 3; unsigned pyxis$v_fill_10_ : 5; } pyxis$r_day_bits; } pyxis$r_day_overlay; __union { char pyxis$b_day_alarm_byte; __struct { unsigned pyxis$v_day_alarm : 3; unsigned pyxis$v_day_alarm_mbz : 4; unsigned pyxis$v_set_day_alarm : 1; } pyxis$r_day_alarm_bits; } pyxis$r_day_alarm_overlay; __union { char pyxis$b_date_byte; __struct { unsigned pyxis$v_date : 4; unsigned pyxis$v_date_10 : 2; unsigned pyxis$v_fill_11_ : 2; } pyxis$r_date_bits; } pyxis$r_date_overlay; __union { char pyxis$b_month_byte; __struct { unsigned pyxis$v_month : 4; unsigned pyxis$v_month_10 : 1; unsigned pyxis$v_month_mbz : 1; unsigned pyxis$v_esqw : 1; unsigned pyxis$v_eosc : 1; } pyxis$r_month_bits; } pyxis$r_month_overlay; __union { char pyxis$b_year_byte; __struct { unsigned pyxis$v_year : 4; unsigned pyxis$v_year_10 : 4; } pyxis$r_year_bits; } pyxis$r_year_overlay; /* */ /* The CUSCO Clock Command Register 87.C010.000B */ /* */ __union { char pyxis$b_command_1286_byte; __struct { unsigned pyxis$v_tdf : 1; unsigned pyxis$v_waf : 1; unsigned pyxis$v_tdm : 1; unsigned pyxis$v_wam : 1; unsigned pyxis$v_pu_lvl : 1; unsigned pyxis$v_ibh_lo : 1; unsigned pyxis$v_ipsw : 1; unsigned pyxis$v_te : 1; } pyxis$r_command_1286_bits; } pyxis$r_command_1286_overlay; /* */ /* The CUSCO Watchdog Alarm Register 87.C010.000C */ /* */ __union { char pyxis$b_wdog_c_byte; __struct { unsigned pyxis$v_wdog_01_sec : 4; unsigned pyxis$v_wdog_1_sec : 4; } pyxis$r_wdog_c_bits; } pyxis$r_wdog_1286_c_overlay; __union { char pyxis$b_wdog_d_byte; __struct { unsigned pyxis$v_wdog_sec : 4; unsigned pyxis$v_wdog_10sec : 4; } pyxis$r_wdog_d_bits; } pyxis$r_wdog_1286_d_overlay; /* */ /* 0x32 (50) unused User Registers */ /* */ unsigned char pyxis$b_fillab10 [50]; /* */ /* A bunch more fill to get up to the PASS 2 base, */ /* 87.C010.2000 */ /* */ unsigned char pyxis$b_fillab11 [8128]; /* */ /* CUSCO Vintage Interrupt Registers 87.C010.2000 */ /* */ /* */ /* VDIVR - Device Interrupt Vector Register - 87.C010.2000 */ /* */ __union { char pyxis$b_vdivr; } pyxis$r_vdivr_overlay; unsigned char pyxis$b_fillab12 [31]; /* */ /* V1ISR - IPL 1 Interrupt Summary Register - 87.C010.2020 */ /* */ __union { char pyxis$b_v1isr; } pyxis$r_v1isr_overlay; unsigned char pyxis$b_fillab13 [31]; /* */ /* V2ISR - IPL 2 Interrupt Summary Register - 87.C010.2040 */ /* */ __union { char pyxis$b_v2isr; } pyxis$r_v2isr_overlay; unsigned char pyxis$b_fillab14 [31]; /* */ /* V3ISR - IPL 3 Interrupt Summary Register - 87.C010.2060 */ /* */ __union { char pyxis$b_v3isr; } pyxis$r_v3isr_overlay; unsigned char pyxis$b_fillab15 [31]; /* */ /* VDIER - Device Interrupt Enable Register - 87C010.2080 */ /* */ __union { char pyxis$b_vdier; } pyxis$r_vdier_overlay; unsigned char pyxis$b_fillab16 [31]; /* */ /* V1IER - IPL1 Interrupt Enable Register - 87.C010.20A0 */ /* */ __union { char pyxis$b_v1ier; } pyxis$r_v1ier_overlay; unsigned char pyxis$b_fillab17 [31]; /* */ /* V2IER - IPL2 Interrupt Enable Register - 87.C010.20C0 */ /* */ __union { char pyxis$b_v2ier; } pyxis$r_v2ier_overlay; unsigned char pyxis$b_fillab18 [31]; /* */ /* V3IER - IPL3 Interrupt Enable Register - 87.C010.20E0 */ /* */ __union { char pyxis$b_v3ier; } pyxis$r_v3ier_overlay; unsigned char pyxis$b_fillab19 [31]; /* */ /* VMCSR - Master Control and Status Register - 87.C010.2100 */ /* */ __union { char pyxis$b_vmcsr; } pyxis$r_vmcsr_overlay; unsigned char pyxis$b_fillab20 [63]; /* */ /* VACSR - Agent Control and Status Register - 87.C010.2140 */ /* */ __union { char pyxis$b_vacsr; } pyxis$r_vacsr_overlay; unsigned char pyxis$b_fillab21 [31]; /* */ /* BIDR- Backplane ID - 87.C010.2160 */ /* */ __union { char pyxis$b_bidr; } pyxis$r_bidr_overlay; unsigned char pyxis$b_fillab22 [671]; /* */ /* Following are the interrupt control and status registers. They */ /* all have the same format, except for VSICSR0 which only has one */ /* active control and one active status bit. That format is: */ /* */ /* bit <0> INTA# Enable */ /* bit <1> INTB# Enable */ /* bit <2> INTC# Enable */ /* bit <3> INTC# Enable */ /* bit <4> INTA# Status */ /* bit <5> INTB# Status */ /* bit <6> INTC# Status */ /* bit <7> INTD# Status */ /* 0: Disabled */ /* 1: Enabled */ /* */ /* I have not defined the bits for each register, since the code will */ /* not use them. The code simply sets the bit indicated by the int */ /* portion of the INT_LINE register. */ /* */ /* */ /* VSICSR0 - Bus 0 I/O Slot 0 Interrupt Control and Status Reg. - 87.C010.2400 */ /* */ __union { char pyxis$b_vsicsr0; } pyxis$r_vsicsr0_overlay; unsigned char pyxis$b_fillab23 [31]; /* */ /* VSICSR1 - Bus 0 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2420 */ /* */ __union { char pyxis$b_vsicsr1; } pyxis$r_vsicsr1_overlay; unsigned char pyxis$b_fillab24 [31]; /* */ /* VSICSR2 - Bus 0 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2440 */ /* */ __union { char pyxis$b_vsicsr2; } pyxis$r_vsicsr2_overlay; unsigned char pyxis$b_fillab25 [31]; /* */ /* VSICSR3 - Bus 0 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2460 */ /* */ __union { char pyxis$b_vsicsr3; } pyxis$r_vsicsr3_overlay; unsigned char pyxis$b_fillab26 [31]; /* */ /* VSICSR4 - Bus 0 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2480 */ /* */ __union { char pyxis$b_vsicsr4; } pyxis$r_vsicsr4_overlay; unsigned char pyxis$b_fillab27 [31]; /* */ /* VSICSR5 - Bus 0 I/O Slot 5 Interrupt Control and Status Reg. - 87.C010.24A0 */ /* */ __union { char pyxis$b_vsicsr5; } pyxis$r_vsicsr5_overlay; unsigned char pyxis$b_fillab28 [31]; /* */ /* VSICSR6 - Bus 0 I/O Slot 6 Interrupt Control and Status Reg. - 87.C010.24C0 */ /* */ __union { char pyxis$b_vsicsr6; } pyxis$r_vsicsr6_overlay; unsigned char pyxis$b_fillab29 [95]; /* */ /* VSICSR9 - Bus 1 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2520 */ /* */ __union { char pyxis$b_vsicsr9; } pyxis$r_vsicsr9_overlay; unsigned char pyxis$b_fillab30 [31]; /* */ /* VSICSRA - Bus 1 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2540 */ /* */ __union { char pyxis$b_vsicsra; } pyxis$r_vsicsra_overlay; unsigned char pyxis$b_fillab31 [31]; /* */ /* VSICSRB - Bus 1 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2560 */ /* */ __union { char pyxis$b_vsicsrb; } pyxis$r_vsicsrb_overlay; unsigned char pyxis$b_fillab32 [31]; /* */ /* VSICSRC - Bus 1 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2580 */ /* */ __union { char pyxis$b_vsicsrc; } pyxis$r_vsicsrc_overlay; unsigned char pyxis$b_fillab33 [159]; /* */ /* VSICSR11 - Bus 2 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2620 */ /* */ __union { char pyxis$b_vsicsr11; } pyxis$r_vsicsr11_overlay; unsigned char pyxis$b_fillab34 [31]; /* */ /* VSICSR12 - Bus 2 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2640 */ /* */ __union { char pyxis$b_vsicsr12; } pyxis$r_vsicsr12_overlay; unsigned char pyxis$b_fillab35 [31]; /* */ /* VSICSR13 - Bus 2 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2660 */ /* */ __union { char pyxis$b_vsicsr13; } pyxis$r_vsicsr13_overlay; unsigned char pyxis$b_fillab36 [31]; /* */ /* VSICSR14 - Bus 2 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2680 */ /* */ __union { char pyxis$b_vsicsr14; } pyxis$r_vsicsr14_overlay; unsigned char pyxis$b_fillab37 [31]; /* */ /* VSICSR15 - Bus 2 I/O Slot 5 Interrupt Control and Status Reg. - 87.C010.26A0 */ /* */ __union { char pyxis$b_vsicsr15; } pyxis$r_vsicsr15_overlay; unsigned char pyxis$b_fillab38 [31]; /* */ /* VSICSR16 - Bus 2 I/O Slot 6 Interrupt Control and Status Reg. - 87.C010.26C0 */ /* */ __union { char pyxis$b_vsicsr16; } pyxis$r_vsicsr16_overlay; unsigned char pyxis$b_fillab39 [31]; /* */ /* VSICSR17 - Bus 2 I/O Slot 7 Interrupt Control and Status Reg. - 87.C010.26E0 */ /* */ __union { char pyxis$b_vsicsr17; } pyxis$r_vsicsr17_overlay; char pyxis$b_fill_12_ [7]; } PYXIS; #if !defined(__VAXC) #define pyxis$l_pci_pyxis_rev pyxis$r_pci_pyxis_revision.pyxis$l_pci_pyxis_rev #define pyxis$b_pyxis_rev pyxis$r_pci_pyxis_revision.pyxis$r_rev_bits.pyxis$b_pyxis_rev #define pyxis$l_pci_lat pyxis$r_pci_latency.pyxis$l_pci_lat #define pyxis$b_pci_latency pyxis$r_pci_latency.pyxis$r_latency_bits.pyxis$b_pci_latency #define pyxis$l_pyxis_ctl pyxis$r_pyxis_ctrl.pyxis$l_pyxis_ctl #define pyxis$v_pyxis_ctrl_pci_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_pci_en #define pyxis$v_pyxis_ctrl_pci_lock_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_pci_lock_en #define pyxis$v_pyxis_ctrl_pci_loop_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_pci_loop_en #define pyxis$v_pyxis_ctrl_fst_bb_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_fst_bb_en #define pyxis$v_pyxis_ctrl_mst_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_mst_en #define pyxis$v_pyxis_ctrl_mem_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_mem_en #define pyxis$v_pyxis_ctrl_req64_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_req64_en #define pyxis$v_pyxis_ctrl_ack64_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_ack64_en #define pyxis$v_pyxis_ctrl_addr_pe_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_addr_pe_en #define pyxis$v_pyxis_ctrl_perr_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_perr_en #define pyxis$v_pyxis_ctrl_fill_err_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_fill_err_en #define pyxis$v_pyxis_ctrl_ecc_chk_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_ecc_chk_en #define pyxis$v_pyxis_ctrl_cack_en_pe pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_cack_en_pe #define pyxis$v_pyxis_ctrl_con_idle_bc pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_con_idle_bc #define pyxis$v_pyxis_ctrl_csr_ioa_byp pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_csr_ioa_byp #define pyxis$v_pyxis_ctrl_io_flush_req pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_io_flush_req #define pyxis$v_pyxis_ctrl_cpu_flush_req pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_cpu_flush_req #define pyxis$v_pyxis_ctrl_arb_ev5_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_arb_ev5_en #define pyxis$v_pyxis_ctrl_en_arb_link pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_en_arb_link #define pyxis$v_pyxis_ctrl_rd_typ pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_rd_typ #define pyxis$v_pyxis_ctrl_rl_typ pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_rl_typ #define pyxis$v_pyxis_ctrl_rm_typ pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_rm_typ #define pyxis$l_pyxis_ctl1 pyxis$r_pyxis_ctrl1.pyxis$l_pyxis_ctl1 #define pyxis$v_pyxis_ctrl1_ioa_ben pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_ioa_ben #define pyxis$v_pyxis_ctrl1_pci_mwin_ena pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_pci_mwin_ena #define pyxis$v_pyxis_ctrl1_pci_link_ena pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_pci_link_ena #define pyxis$v_pyxis_ctrl1_lw_par_mode pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_lw_par_mode #define pyxis$l_pyxis_config pyxis$r_pyxis_config_overlay.pyxis$l_pyxis_config #define pyxis$v_pyxis_cnfg_pci_width pyxis$r_pyxis_config_overlay.pyxis$r_pyxis_config_bits.pyxis$v_pyxis_cnfg_pci_width #define pyxis$v_pyxis_cnfg_iod_width pyxis$r_pyxis_config_overlay.pyxis$r_pyxis_config_bits.pyxis$v_pyxis_cnfg_iod_width #define pyxis$l_hae_mem pyxis$r_hae_mem_overlay.pyxis$l_hae_mem #define pyxis$v_hae_mem_reg_3 pyxis$r_hae_mem_overlay.pyxis$r_hae_mem_bits.pyxis$v_hae_mem_reg_3 #define pyxis$v_hae_mem_reg_2 pyxis$r_hae_mem_overlay.pyxis$r_hae_mem_bits.pyxis$v_hae_mem_reg_2 #define pyxis$v_hae_mem_reg_1 pyxis$r_hae_mem_overlay.pyxis$r_hae_mem_bits.pyxis$v_hae_mem_reg_1 #define pyxis$l_hae_io pyxis$r_hae_io_overlay.pyxis$l_hae_io #define pyxis$v_hae_io pyxis$r_hae_io_overlay.pyxis$r_hae_io_bits.pyxis$v_hae_io #define pyxis$l_cfg pyxis$r_cfg_overlay.pyxis$l_cfg #define pyxis$v_cfg_bits pyxis$r_cfg_overlay.pyxis$r_cgf_bits_overlay.pyxis$v_cfg_bits #define pyxis$l_pyxis_diag pyxis$r_pyxis_diag_overlay.pyxis$l_pyxis_diag #define pyxis$v_from_en pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_from_en #define pyxis$v_use_check pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_use_check #define pyxis$v_fpe_pci pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_fpe_pci #define pyxis$v_fpe_to_ev5 pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_fpe_to_ev5 #define pyxis$l_diag_check pyxis$r_diag_check_overlay.pyxis$l_diag_check #define pyxis$b_diag_check_ecc pyxis$r_diag_check_overlay.pyxis$r_diag_check_bits.pyxis$b_diag_check_ecc #define pyxis$l_perf_monitor pyxis$r_perf_monitor_overlay.pyxis$l_perf_monitor #define pyxis$l_perf_control pyxis$r_perf_control_overlay.pyxis$l_perf_control #define pyxis$l_pyxis_err pyxis$r_pyxis_err_overlay.pyxis$l_pyxis_err #define pyxis$v_err_corr_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_corr_ecc #define pyxis$v_err_unc_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_unc_ecc #define pyxis$v_err_cpu_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_cpu_pe #define pyxis$v_err_mem_nem pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_mem_nem #define pyxis$v_err_pci_serr pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pci_serr #define pyxis$v_err_pci_perr pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pci_perr #define pyxis$v_err_pci_adr_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pci_adr_pe #define pyxis$v_err_m_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_m_abort #define pyxis$v_err_t_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_t_abort #define pyxis$v_err_pa_pte_inv pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pa_pte_inv #define pyxis$v_err_ioa_timeout pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_ioa_timeout #define pyxis$v_err_lost_corr_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_corr_ecc #define pyxis$v_err_lost_unc_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_unc_ecc #define pyxis$v_err_lost_cpu_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_cpu_pe #define pyxis$v_err_lost_mem_nem pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_mem_nem #define pyxis$v_err_lost_pci_perr pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_pci_perr #define pyxis$v_err_lost_pci_adr_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_pci_adr_pe #define pyxis$v_err_lost_m_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_m_abort #define pyxis$v_err_lost_t_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_t_abort #define pyxis$v_err_lost_pa_pte_inv pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_pa_pte_inv #define pyxis$v_err_lost_ioa_timeout pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_ioa_timeout #define pyxis$v_err_valid pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_valid #define pyxis$l_pyxis_stat pyxis$r_pyxis_stat_overlay.pyxis$l_pyxis_stat #define pyxis$v_stat_pci_0 pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_pci_0 #define pyxis$v_stat_pci_1 pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_pci_1 #define pyxis$v_stat_ioa_valid pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_ioa_valid #define pyxis$v_stat_tlb_miss pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_tlb_miss #define pyxis$l_pyxis_error_mask pyxis$r_pyxis_error_mask_overlay.pyxis$l_pyxis_error_mask #define pyxis$v_mask_corr_ecc_err pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_corr_ecc_err #define pyxis$v_mask_unc_ecc_err pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_unc_ecc_err #define pyxis$v_mask_cpu_pe pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_cpu_pe #define pyxis$v_mask_mem_nem pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_mem_nem #define pyxis$v_mask_pci_serr pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pci_serr #define pyxis$v_mask_pci_perr pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pci_perr #define pyxis$v_mask_pci_adr_pe pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pci_adr_pe #define pyxis$v_mask_m_abort pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_m_abort #define pyxis$v_mask_t_abort pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_t_abort #define pyxis$v_mask_pa_pte_inv pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pa_pte_inv #define pyxis$v_mask_ioa_timeout pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_ioa_timeout #define pyxis$l_pyxis_synd pyxis$r_pyxis_syndrome.pyxis$l_pyxis_synd #define pyxis$r_pyxis_synd_bits pyxis$r_pyxis_syndrome.pyxis$r_pyxis_synd_bits #define pyxis$v_pyxis_syndrome0 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_syndrome0 #define pyxis$v_pyxis_syndrome1 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_syndrome1 #define pyxis$v_pyxis_raw_check_bits pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_raw_check_bits #define pyxis$v_pyxis_synd_ce0 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_ce0 #define pyxis$v_pyxis_synd_ce1 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_ce1 #define pyxis$v_pyxis_synd_uce0 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_uce0 #define pyxis$v_pyxis_synd_uce1 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_uce1 #define pyxis$q_pyxis_errdata pyxis$r_pyxis_errdat_overlay.pyxis$q_pyxis_errdata #define pyxis$l_pyxis_mear pyxis$r_pyxis_mear_overlay.pyxis$l_pyxis_mear #define pyxis$v_mear_addr_h pyxis$r_pyxis_mear_overlay.pyxis$r_pyxis_mear_bits.pyxis$v_mear_addr_h #define pyxis$l_pyxis_mesr pyxis$r_pyxis_mesr_overlay.pyxis$l_pyxis_mesr #define pyxis$v_mesr_addr_3932 pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_addr_3932 #define pyxis$v_mesr_dma_rd_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_dma_rd_nxm #define pyxis$v_mesr_dma_wr_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_dma_wr_nxm #define pyxis$v_mesr_cpu_rd_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_cpu_rd_nxm #define pyxis$v_mesr_cpu_wr_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_cpu_wr_nxm #define pyxis$v_mesr_io_rd_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_io_rd_nxm #define pyxis$v_mesr_io_wr_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_io_wr_nxm #define pyxis$v_mesr_victim_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_victim_nxm #define pyxis$v_mesr_tlbfill_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_tlbfill_nxm #define pyxis$v_mesr_oword_index pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_oword_index #define pyxis$v_mesr_data_cycle_typ pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_data_cycle_typ #define pyxis$v_mesr_seq_st pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_seq_st #define pyxis$l_pyxis_pcie0 pyxis$r_pyxis_pcie0_overlay.pyxis$l_pyxis_pcie0 #define pyxis$v_pcie_dma_cmd pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_dma_cmd #define pyxis$v_pcie_dma_dac pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_dma_dac #define pyxis$v_pcie_window pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_window #define pyxis$v_pcie_mstr_state pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_mstr_state #define pyxis$v_pcie_trgt_state pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_trgt_state #define pyxis$v_pcie_pci_cmd pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_pci_cmd #define pyxis$v_pcie_pci_dac pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_pci_dac #define pyxis$l_pcie1_dma_addr_h pyxis$r_pyxis_pcie1_overlay.pyxis$l_pcie1_dma_addr_h #define pyxis$l_pcie2_pci_addr_h pyxis$r_pyxis_pcie2_overlay.pyxis$l_pcie2_pci_addr_h #define pyxis$l_mem_mcr pyxis$r_mem_mcr_overlay.pyxis$l_mem_mcr #define pyxis$v_mcr_mode_req pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_mode_req #define pyxis$v_mcr_server_mode pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_server_mode #define pyxis$v_mcr_bcache_stat pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_bcache_stat #define pyxis$v_mcr_bcache_en pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_bcache_en #define pyxis$v_mcr_pipelined_cache pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_pipelined_cache #define pyxis$v_mcr_overlap_dis pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_overlap_dis #define pyxis$v_mcr_seq_trace pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_seq_trace #define pyxis$v_mcr_cke_auto pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_cke_auto #define pyxis$v_mcr_dram_clk_auto pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_dram_clk_auto #define pyxis$v_mcr_dram_mode pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_dram_mode #define pyxis$l_mem_mcmr pyxis$r_mem_mcmr_overlay.pyxis$l_mem_mcmr #define pyxis$v_mcmr_dram_clock_mask pyxis$r_mem_mcmr_overlay.pyxis$r_mem_mcmr_data.pyxis$v_mcmr_dram_clock_mask #define pyxis$l_mem_mgtr pyxis$r_mem_mgtr_overlay.pyxis$l_mem_mgtr #define pyxis$v_mgtr_min_ras_pre pyxis$r_mem_mgtr_overlay.pyxis$r_mem_mgtr_data.pyxis$v_mgtr_min_ras_pre #define pyxis$v_mgtr_cas_lat pyxis$r_mem_mgtr_overlay.pyxis$r_mem_mgtr_data.pyxis$v_mgtr_cas_lat #define pyxis$v_mgtr_idle_bc_width pyxis$r_mem_mgtr_overlay.pyxis$r_mem_mgtr_data.pyxis$v_mgtr_idle_bc_width #define pyxis$l_mem_mrtr pyxis$r_mem_mrtr_overlay.pyxis$l_mem_mrtr #define pyxis$v_mrtr_ref_width pyxis$r_mem_mrtr_overlay.pyxis$r_mem_mrtr_data.pyxis$v_mrtr_ref_width #define pyxis$v_mrtr_ref_int pyxis$r_mem_mrtr_overlay.pyxis$r_mem_mrtr_data.pyxis$v_mrtr_ref_int #define pyxis$v_mrtr_force_ref pyxis$r_mem_mrtr_overlay.pyxis$r_mem_mrtr_data.pyxis$v_mrtr_force_ref #define pyxis$l_mem_mrphr pyxis$r_mem_mrphr_overlay.pyxis$l_mem_mrphr #define pyxis$v_mrphr_policy_mask pyxis$r_mem_mrphr_overlay.pyxis$r_mem_mrphr_data.pyxis$v_mrphr_policy_mask #define pyxis$l_mem_mdr1 pyxis$r_mem_mdr1_overlay.pyxis$l_mem_mdr1 #define pyxis$v_mdr1_sel0 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel0 #define pyxis$v_mdr1_sel1 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel1 #define pyxis$v_mdr1_sel2 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel2 #define pyxis$v_mdr1_sel3 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel3 #define pyxis$v_mdr1_enable pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_enable #define pyxis$l_mem_mdr2 pyxis$r_mem_mdr2_overlay.pyxis$l_mem_mdr2 #define pyxis$v_mdr2_sel0 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel0 #define pyxis$v_mdr2_sel1 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel1 #define pyxis$v_mdr2_sel2 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel2 #define pyxis$v_mdr2_sel3 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel3 #define pyxis$v_mdr2_enable pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_enable #define pyxis$l_mem_bbar0 pyxis$r_mem_bbar0_overlay.pyxis$l_mem_bbar0 #define pyxis$v_bbar0_base_addr_3324 pyxis$r_mem_bbar0_overlay.pyxis$r_mem_bbar0_data.pyxis$v_bbar0_base_addr_3324 #define pyxis$l_mem_bbar1 pyxis$r_mem_bbar1_overlay.pyxis$l_mem_bbar1 #define pyxis$v_bbar1_base_addr_3324 pyxis$r_mem_bbar1_overlay.pyxis$r_mem_bbar1_data.pyxis$v_bbar1_base_addr_3324 #define pyxis$l_mem_bbar2 pyxis$r_mem_bbar2_overlay.pyxis$l_mem_bbar2 #define pyxis$v_bbar2_base_addr_3324 pyxis$r_mem_bbar2_overlay.pyxis$r_mem_bbar2_data.pyxis$v_bbar2_base_addr_3324 #define pyxis$l_mem_bbar3 pyxis$r_mem_bbar3_overlay.pyxis$l_mem_bbar3 #define pyxis$v_bbar3_base_addr_3324 pyxis$r_mem_bbar3_overlay.pyxis$r_mem_bbar3_data.pyxis$v_bbar3_base_addr_3324 #define pyxis$l_mem_bbar4 pyxis$r_mem_bbar4_overlay.pyxis$l_mem_bbar4 #define pyxis$v_bbar4_base_addr_3324 pyxis$r_mem_bbar4_overlay.pyxis$r_mem_bbar4_data.pyxis$v_bbar4_base_addr_3324 #define pyxis$l_mem_bbar5 pyxis$r_mem_bbar5_overlay.pyxis$l_mem_bbar5 #define pyxis$v_bbar5_base_addr_3324 pyxis$r_mem_bbar5_overlay.pyxis$r_mem_bbar5_data.pyxis$v_bbar5_base_addr_3324 #define pyxis$l_mem_bbar6 pyxis$r_mem_bbar6_overlay.pyxis$l_mem_bbar6 #define pyxis$v_bbar6_base_addr_3324 pyxis$r_mem_bbar6_overlay.pyxis$r_mem_bbar6_data.pyxis$v_bbar6_base_addr_3324 #define pyxis$l_mem_bbar7 pyxis$r_mem_bbar7_overlay.pyxis$l_mem_bbar7 #define pyxis$v_bbar7_base_addr_3324 pyxis$r_mem_bbar7_overlay.pyxis$r_mem_bbar7_data.pyxis$v_bbar7_base_addr_3324 #define pyxis$l_mem_mbcr0 pyxis$r_mem_mbcr0_overlay.pyxis$l_mem_mbcr0 #define pyxis$v_mbcr0_bank_enable pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_bank_enable #define pyxis$v_mbcr0_bank_size pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_bank_size #define pyxis$v_mbcr0_subbank_enable pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_subbank_enable #define pyxis$v_mbcr0_colsel pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_colsel #define pyxis$v_mbcr0_4bank pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_4bank #define pyxis$l_mem_mbcr1 pyxis$r_mem_mbcr1_overlay.pyxis$l_mem_mbcr1 #define pyxis$v_mbcr1_bank_enable pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_bank_enable #define pyxis$v_mbcr1_bank_size pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_bank_size #define pyxis$v_mbcr1_subbank_enable pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_subbank_enable #define pyxis$v_mbcr1_colsel pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_colsel #define pyxis$v_mbcr1_4bank pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_4bank #define pyxis$l_mem_mbcr2 pyxis$r_mem_mbcr2_overlay.pyxis$l_mem_mbcr2 #define pyxis$v_mbcr2_bank_enable pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_bank_enable #define pyxis$v_mbcr2_bank_size pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_bank_size #define pyxis$v_mbcr2_subbank_enable pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_subbank_enable #define pyxis$v_mbcr2_colsel pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_colsel #define pyxis$v_mbcr2_4bank pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_4bank #define pyxis$l_mem_mbcr3 pyxis$r_mem_mbcr3_overlay.pyxis$l_mem_mbcr3 #define pyxis$v_mbcr3_bank_enable pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_bank_enable #define pyxis$v_mbcr3_bank_size pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_bank_size #define pyxis$v_mbcr3_subbank_enable pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_subbank_enable #define pyxis$v_mbcr3_colsel pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_colsel #define pyxis$v_mbcr3_4bank pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_4bank #define pyxis$l_mem_mbcr4 pyxis$r_mem_mbcr4_overlay.pyxis$l_mem_mbcr4 #define pyxis$v_mbcr4_bank_enable pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_bank_enable #define pyxis$v_mbcr4_bank_size pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_bank_size #define pyxis$v_mbcr4_subbank_enable pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_subbank_enable #define pyxis$v_mbcr4_colsel pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_colsel #define pyxis$v_mbcr4_4bank pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_4bank #define pyxis$l_mem_mbcr5 pyxis$r_mem_mbcr5_overlay.pyxis$l_mem_mbcr5 #define pyxis$v_mbcr5_bank_enable pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_bank_enable #define pyxis$v_mbcr5_bank_size pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_bank_size #define pyxis$v_mbcr5_subbank_enable pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_subbank_enable #define pyxis$v_mbcr5_colsel pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_colsel #define pyxis$v_mbcr5_4bank pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_4bank #define pyxis$l_mem_mbcr6 pyxis$r_mem_mbcr6_overlay.pyxis$l_mem_mbcr6 #define pyxis$v_mbcr6_bank_enable pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_bank_enable #define pyxis$v_mbcr6_bank_size pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_bank_size #define pyxis$v_mbcr6_subbank_enable pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_subbank_enable #define pyxis$v_mbcr6_colsel pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_colsel #define pyxis$v_mbcr6_4bank pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_4bank #define pyxis$l_mem_mbcr7 pyxis$r_mem_mbcr7_overlay.pyxis$l_mem_mbcr7 #define pyxis$v_mbcr7_bank_enable pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_bank_enable #define pyxis$v_mbcr7_bank_size pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_bank_size #define pyxis$v_mbcr7_subbank_enable pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_subbank_enable #define pyxis$v_mbcr7_colsel pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_colsel #define pyxis$v_mbcr7_4bank pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_4bank #define pyxis$l_mem_mbtr0 pyxis$r_mem_mbtr0_overlay.pyxis$l_mem_mbtr0 #define pyxis$v_mbtr0_row_addr_hold pyxis$r_mem_mbtr0_overlay.pyxis$r_mem_mbtr0_data.pyxis$v_mbtr0_row_addr_hold #define pyxis$v_mbtr0_toshiba pyxis$r_mem_mbtr0_overlay.pyxis$r_mem_mbtr0_data.pyxis$v_mbtr0_toshiba #define pyxis$v_mbtr0_slow_charge pyxis$r_mem_mbtr0_overlay.pyxis$r_mem_mbtr0_data.pyxis$v_mbtr0_slow_charge #define pyxis$l_mem_mbtr1 pyxis$r_mem_mbtr1_overlay.pyxis$l_mem_mbtr1 #define pyxis$v_mbtr1_row_addr_hold pyxis$r_mem_mbtr1_overlay.pyxis$r_mem_mbtr1_data.pyxis$v_mbtr1_row_addr_hold #define pyxis$v_mbtr1_toshiba pyxis$r_mem_mbtr1_overlay.pyxis$r_mem_mbtr1_data.pyxis$v_mbtr1_toshiba #define pyxis$v_mbtr1_slow_charge pyxis$r_mem_mbtr1_overlay.pyxis$r_mem_mbtr1_data.pyxis$v_mbtr1_slow_charge #define pyxis$l_mem_mbtr2 pyxis$r_mem_mbtr2_overlay.pyxis$l_mem_mbtr2 #define pyxis$v_mbtr2_row_addr_hold pyxis$r_mem_mbtr2_overlay.pyxis$r_mem_mbtr2_data.pyxis$v_mbtr2_row_addr_hold #define pyxis$v_mbtr2_toshiba pyxis$r_mem_mbtr2_overlay.pyxis$r_mem_mbtr2_data.pyxis$v_mbtr2_toshiba #define pyxis$v_mbtr2_slow_charge pyxis$r_mem_mbtr2_overlay.pyxis$r_mem_mbtr2_data.pyxis$v_mbtr2_slow_charge #define pyxis$l_mem_mbtr3 pyxis$r_mem_mbtr3_overlay.pyxis$l_mem_mbtr3 #define pyxis$v_mbtr3_row_addr_hold pyxis$r_mem_mbtr3_overlay.pyxis$r_mem_mbtr3_data.pyxis$v_mbtr3_row_addr_hold #define pyxis$v_mbtr3_toshiba pyxis$r_mem_mbtr3_overlay.pyxis$r_mem_mbtr3_data.pyxis$v_mbtr3_toshiba #define pyxis$v_mbtr3_slow_charge pyxis$r_mem_mbtr3_overlay.pyxis$r_mem_mbtr3_data.pyxis$v_mbtr3_slow_charge #define pyxis$l_mem_mbtr4 pyxis$r_mem_mbtr4_overlay.pyxis$l_mem_mbtr4 #define pyxis$v_mbtr4_row_addr_hold pyxis$r_mem_mbtr4_overlay.pyxis$r_mem_mbtr4_data.pyxis$v_mbtr4_row_addr_hold #define pyxis$v_mbtr4_toshiba pyxis$r_mem_mbtr4_overlay.pyxis$r_mem_mbtr4_data.pyxis$v_mbtr4_toshiba #define pyxis$v_mbtr4_slow_charge pyxis$r_mem_mbtr4_overlay.pyxis$r_mem_mbtr4_data.pyxis$v_mbtr4_slow_charge #define pyxis$l_mem_mbtr5 pyxis$r_mem_mbtr5_overlay.pyxis$l_mem_mbtr5 #define pyxis$v_mbtr5_row_addr_hold pyxis$r_mem_mbtr5_overlay.pyxis$r_mem_mbtr5_data.pyxis$v_mbtr5_row_addr_hold #define pyxis$v_mbtr5_toshiba pyxis$r_mem_mbtr5_overlay.pyxis$r_mem_mbtr5_data.pyxis$v_mbtr5_toshiba #define pyxis$v_mbtr5_slow_charge pyxis$r_mem_mbtr5_overlay.pyxis$r_mem_mbtr5_data.pyxis$v_mbtr5_slow_charge #define pyxis$l_mem_mbtr6 pyxis$r_mem_mbtr6_overlay.pyxis$l_mem_mbtr6 #define pyxis$v_mbtr6_row_addr_hold pyxis$r_mem_mbtr6_overlay.pyxis$r_mem_mbtr6_data.pyxis$v_mbtr6_row_addr_hold #define pyxis$v_mbtr6_toshiba pyxis$r_mem_mbtr6_overlay.pyxis$r_mem_mbtr6_data.pyxis$v_mbtr6_toshiba #define pyxis$v_mbtr6_slow_charge pyxis$r_mem_mbtr6_overlay.pyxis$r_mem_mbtr6_data.pyxis$v_mbtr6_slow_charge #define pyxis$l_mem_mbtr7 pyxis$r_mem_mbtr7_overlay.pyxis$l_mem_mbtr7 #define pyxis$v_mbtr7_row_addr_hold pyxis$r_mem_mbtr7_overlay.pyxis$r_mem_mbtr7_data.pyxis$v_mbtr7_row_addr_hold #define pyxis$v_mbtr7_toshiba pyxis$r_mem_mbtr7_overlay.pyxis$r_mem_mbtr7_data.pyxis$v_mbtr7_toshiba #define pyxis$v_mbtr7_slow_charge pyxis$r_mem_mbtr7_overlay.pyxis$r_mem_mbtr7_data.pyxis$v_mbtr7_slow_charge #define pyxis$l_mem_cvm pyxis$r_mem_cvm_overlay.pyxis$l_mem_cvm #define pyxis$v_cvm_cache_valid_mask pyxis$r_mem_cvm_overlay.pyxis$r_mem_cvm_data.pyxis$v_cvm_cache_valid_mask #define pyxis$l_pci_tbia pyxis$r_pci_tbia_overlay.pyxis$l_pci_tbia #define pyxis$v_tbia_csr_wr_data pyxis$r_pci_tbia_overlay.pyxis$r_pci_tbia_bits.pyxis$v_tbia_csr_wr_data #define pyxis$l_pci_wbase0 pyxis$r_pci_wbase0_overlay.pyxis$l_pci_wbase0 #define pyxis$v_wbase0_w_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_w_en #define pyxis$v_wbase0_sg_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_sg_en #define pyxis$v_wbase0_memcs_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_memcs_en #define pyxis$v_wbase0_dac_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_dac_en #define pyxis$v_wbase0_base pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_base #define pyxis$l_pci_wmask0 pyxis$r_pci_wmask0_overlay.pyxis$l_pci_wmask0 #define pyxis$v_wmask0_mask pyxis$r_pci_wmask0_overlay.pyxis$r_pci_wmask0_bits.pyxis$v_wmask0_mask #define pyxis$l_pci_tbase0 pyxis$r_pci_tbase0_overlay.pyxis$l_pci_tbase0 #define pyxis$v_tbase0_base pyxis$r_pci_tbase0_overlay.pyxis$r_pci_tbase0_bits.pyxis$v_tbase0_base #define pyxis$l_pci_wbase1 pyxis$r_pci_wbase1_overlay.pyxis$l_pci_wbase1 #define pyxis$v_wbase1_w_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_w_en #define pyxis$v_wbase1_sg_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_sg_en #define pyxis$v_wbase1_memcs_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_memcs_en #define pyxis$v_wbase1_dac_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_dac_en #define pyxis$v_wbase1_base pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_base #define pyxis$l_pci_wmask1 pyxis$r_pci_wmask1_overlay.pyxis$l_pci_wmask1 #define pyxis$v_wmask1_mask pyxis$r_pci_wmask1_overlay.pyxis$r_pci_wmask1_bits.pyxis$v_wmask1_mask #define pyxis$l_pci_tbase1 pyxis$r_pci_tbase1_overlay.pyxis$l_pci_tbase1 #define pyxis$v_tbase1_base pyxis$r_pci_tbase1_overlay.pyxis$r_pci_tbase1_bits.pyxis$v_tbase1_base #define pyxis$l_pci_wbase2 pyxis$r_pci_wbase2_overlay.pyxis$l_pci_wbase2 #define pyxis$v_wbase2_w_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_w_en #define pyxis$v_wbase2_sg_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_sg_en #define pyxis$v_wbase2_memcs_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_memcs_en #define pyxis$v_wbase2_dac_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_dac_en #define pyxis$v_wbase2_base pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_base #define pyxis$l_pci_wmask2 pyxis$r_pci_wmask2_overlay.pyxis$l_pci_wmask2 #define pyxis$v_wmask2_mask pyxis$r_pci_wmask2_overlay.pyxis$r_pci_wmask2_bits.pyxis$v_wmask2_mask #define pyxis$l_pci_tbase2 pyxis$r_pci_tbase2_overlay.pyxis$l_pci_tbase2 #define pyxis$v_tbase2_base pyxis$r_pci_tbase2_overlay.pyxis$r_pci_tbase2_bits.pyxis$v_tbase2_base #define pyxis$l_pci_wbase3 pyxis$r_pci_wbase3_overlay.pyxis$l_pci_wbase3 #define pyxis$v_wbase3_w_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_w_en #define pyxis$v_wbase3_sg_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_sg_en #define pyxis$v_wbase3_memcs_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_memcs_en #define pyxis$v_wbase3_dac_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_dac_en #define pyxis$v_wbase3_base pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_base #define pyxis$l_pci_wmask3 pyxis$r_pci_wmask3_overlay.pyxis$l_pci_wmask3 #define pyxis$v_wmask3_mask pyxis$r_pci_wmask3_overlay.pyxis$r_pci_wmask3_bits.pyxis$v_wmask3_mask #define pyxis$l_pci_tbase3 pyxis$r_pci_tbase3_overlay.pyxis$l_pci_tbase3 #define pyxis$v_tbase3_base pyxis$r_pci_tbase3_overlay.pyxis$r_pci_tbase3_bits.pyxis$v_tbase3_base #define pyxis$l_pci_dac pyxis$r_pci_dac_overlay.pyxis$l_pci_dac #define pyxis$v_dac_base pyxis$r_pci_dac_overlay.pyxis$r_pci_dac_bits.pyxis$v_dac_base #define pyxis$l_pci_ltb0 pyxis$r_pci_ltb0_overlay.pyxis$l_pci_ltb0 #define pyxis$v_ltb0_valid pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_valid #define pyxis$v_ltb0_locked pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_locked #define pyxis$v_ltb0_dac pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_dac #define pyxis$v_ltb0_tag pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_tag #define pyxis$l_pci_ltb1 pyxis$r_pci_ltb1_overlay.pyxis$l_pci_ltb1 #define pyxis$v_ltb1_valid pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_valid #define pyxis$v_ltb1_locked pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_locked #define pyxis$v_ltb1_dac pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_dac #define pyxis$v_ltb1_tag pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_tag #define pyxis$l_pci_ltb2 pyxis$r_pci_ltb2_overlay.pyxis$l_pci_ltb2 #define pyxis$v_ltb2_valid pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_valid #define pyxis$v_ltb2_locked pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_locked #define pyxis$v_ltb2_dac pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_dac #define pyxis$v_ltb2_tag pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_tag #define pyxis$l_pci_ltb3 pyxis$r_pci_ltb3_overlay.pyxis$l_pci_ltb3 #define pyxis$v_ltb3_valid pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_valid #define pyxis$v_ltb3_locked pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_locked #define pyxis$v_ltb3_dac pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_dac #define pyxis$v_ltb3_tag pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_tag #define pyxis$l_pci_tb0 pyxis$r_pci_tb0_overlay.pyxis$l_pci_tb0 #define pyxis$v_tb0_valid pyxis$r_pci_tb0_overlay.pyxis$r_pci_tb0_bits.pyxis$v_tb0_valid #define pyxis$v_tb0_dac pyxis$r_pci_tb0_overlay.pyxis$r_pci_tb0_bits.pyxis$v_tb0_dac #define pyxis$v_tb0_tag pyxis$r_pci_tb0_overlay.pyxis$r_pci_tb0_bits.pyxis$v_tb0_tag #define pyxis$l_pci_tb1 pyxis$r_pci_tb1_overlay.pyxis$l_pci_tb1 #define pyxis$v_tb1_valid pyxis$r_pci_tb1_overlay.pyxis$r_pci_tb1_bits.pyxis$v_tb1_valid #define pyxis$v_tb1_dac pyxis$r_pci_tb1_overlay.pyxis$r_pci_tb1_bits.pyxis$v_tb1_dac #define pyxis$v_tb1_tag pyxis$r_pci_tb1_overlay.pyxis$r_pci_tb1_bits.pyxis$v_tb1_tag #define pyxis$l_pci_tb2 pyxis$r_pci_tb2_overlay.pyxis$l_pci_tb2 #define pyxis$v_tb2_valid pyxis$r_pci_tb2_overlay.pyxis$r_pci_tb2_bits.pyxis$v_tb2_valid #define pyxis$v_tb2_dac pyxis$r_pci_tb2_overlay.pyxis$r_pci_tb2_bits.pyxis$v_tb2_dac #define pyxis$v_tb2_tag pyxis$r_pci_tb2_overlay.pyxis$r_pci_tb2_bits.pyxis$v_tb2_tag #define pyxis$l_pci_tb3 pyxis$r_pci_tb3_overlay.pyxis$l_pci_tb3 #define pyxis$v_tb3_valid pyxis$r_pci_tb3_overlay.pyxis$r_pci_tb3_bits.pyxis$v_tb3_valid #define pyxis$v_tb3_dac pyxis$r_pci_tb3_overlay.pyxis$r_pci_tb3_bits.pyxis$v_tb3_dac #define pyxis$v_tb3_tag pyxis$r_pci_tb3_overlay.pyxis$r_pci_tb3_bits.pyxis$v_tb3_tag #define pyxis$l_pci_tb0_page0 pyxis$r_pci_tb0_page0_overlay.pyxis$l_pci_tb0_page0 #define pyxis$v_tb0_page0_valid pyxis$r_pci_tb0_page0_overlay.pyxis$r_pci_tb0_page0_bits.pyxis$v_tb0_page0_valid #define pyxis$v_tb0_page0_addr pyxis$r_pci_tb0_page0_overlay.pyxis$r_pci_tb0_page0_bits.pyxis$v_tb0_page0_addr #define pyxis$l_pci_tb0_page1 pyxis$r_pci_tb0_page1_overlay.pyxis$l_pci_tb0_page1 #define pyxis$v_tb0_page1_valid pyxis$r_pci_tb0_page1_overlay.pyxis$r_pci_tb0_page1_bits.pyxis$v_tb0_page1_valid #define pyxis$v_tb0_page1_addr pyxis$r_pci_tb0_page1_overlay.pyxis$r_pci_tb0_page1_bits.pyxis$v_tb0_page1_addr #define pyxis$l_pci_tb0_page2 pyxis$r_pci_tb0_page2_overlay.pyxis$l_pci_tb0_page2 #define pyxis$v_tb0_page2_valid pyxis$r_pci_tb0_page2_overlay.pyxis$r_pci_tb0_page2_bits.pyxis$v_tb0_page2_valid #define pyxis$v_tb0_page2_addr pyxis$r_pci_tb0_page2_overlay.pyxis$r_pci_tb0_page2_bits.pyxis$v_tb0_page2_addr #define pyxis$l_pci_tb0_page3 pyxis$r_pci_tb0_page3_overlay.pyxis$l_pci_tb0_page3 #define pyxis$v_tb0_page3_valid pyxis$r_pci_tb0_page3_overlay.pyxis$r_pci_tb0_page3_bits.pyxis$v_tb0_page3_valid #define pyxis$v_tb0_page3_addr pyxis$r_pci_tb0_page3_overlay.pyxis$r_pci_tb0_page3_bits.pyxis$v_tb0_page3_addr #define pyxis$l_pci_tb1_page0 pyxis$r_pci_tb1_page0_overlay.pyxis$l_pci_tb1_page0 #define pyxis$v_tb1_page0_valid pyxis$r_pci_tb1_page0_overlay.pyxis$r_pci_tb1_page0_bits.pyxis$v_tb1_page0_valid #define pyxis$v_tb1_page0_addr pyxis$r_pci_tb1_page0_overlay.pyxis$r_pci_tb1_page0_bits.pyxis$v_tb1_page0_addr #define pyxis$l_pci_tb1_page1 pyxis$r_pci_tb1_page1_overlay.pyxis$l_pci_tb1_page1 #define pyxis$v_tb1_page1_valid pyxis$r_pci_tb1_page1_overlay.pyxis$r_pci_tb1_page1_bits.pyxis$v_tb1_page1_valid #define pyxis$v_tb1_page1_addr pyxis$r_pci_tb1_page1_overlay.pyxis$r_pci_tb1_page1_bits.pyxis$v_tb1_page1_addr #define pyxis$l_pci_tb1_page2 pyxis$r_pci_tb1_page2_overlay.pyxis$l_pci_tb1_page2 #define pyxis$v_tb1_page2_valid pyxis$r_pci_tb1_page2_overlay.pyxis$r_pci_tb1_page2_bits.pyxis$v_tb1_page2_valid #define pyxis$v_tb1_page2_addr pyxis$r_pci_tb1_page2_overlay.pyxis$r_pci_tb1_page2_bits.pyxis$v_tb1_page2_addr #define pyxis$l_pci_tb1_page3 pyxis$r_pci_tb1_page3_overlay.pyxis$l_pci_tb1_page3 #define pyxis$v_tb1_page3_valid pyxis$r_pci_tb1_page3_overlay.pyxis$r_pci_tb1_page3_bits.pyxis$v_tb1_page3_valid #define pyxis$v_tb1_page3_addr pyxis$r_pci_tb1_page3_overlay.pyxis$r_pci_tb1_page3_bits.pyxis$v_tb1_page3_addr #define pyxis$l_pci_tb2_page0 pyxis$r_pci_tb2_page0_overlay.pyxis$l_pci_tb2_page0 #define pyxis$v_tb2_page0_valid pyxis$r_pci_tb2_page0_overlay.pyxis$r_pci_tb2_page0_bits.pyxis$v_tb2_page0_valid #define pyxis$v_tb2_page0_addr pyxis$r_pci_tb2_page0_overlay.pyxis$r_pci_tb2_page0_bits.pyxis$v_tb2_page0_addr #define pyxis$l_pci_tb2_page1 pyxis$r_pci_tb2_page1_overlay.pyxis$l_pci_tb2_page1 #define pyxis$v_tb2_page1_valid pyxis$r_pci_tb2_page1_overlay.pyxis$r_pci_tb2_page1_bits.pyxis$v_tb2_page1_valid #define pyxis$v_tb2_page1_addr pyxis$r_pci_tb2_page1_overlay.pyxis$r_pci_tb2_page1_bits.pyxis$v_tb2_page1_addr #define pyxis$l_pci_tb2_page2 pyxis$r_pci_tb2_page2_overlay.pyxis$l_pci_tb2_page2 #define pyxis$v_tb2_page2_valid pyxis$r_pci_tb2_page2_overlay.pyxis$r_pci_tb2_page2_bits.pyxis$v_tb2_page2_valid #define pyxis$v_tb2_page2_addr pyxis$r_pci_tb2_page2_overlay.pyxis$r_pci_tb2_page2_bits.pyxis$v_tb2_page2_addr #define pyxis$l_pci_tb2_page3 pyxis$r_pci_tb2_page3_overlay.pyxis$l_pci_tb2_page3 #define pyxis$v_tb2_page3_valid pyxis$r_pci_tb2_page3_overlay.pyxis$r_pci_tb2_page3_bits.pyxis$v_tb2_page3_valid #define pyxis$v_tb2_page3_addr pyxis$r_pci_tb2_page3_overlay.pyxis$r_pci_tb2_page3_bits.pyxis$v_tb2_page3_addr #define pyxis$l_pci_tb3_page0 pyxis$r_pci_tb3_page0_overlay.pyxis$l_pci_tb3_page0 #define pyxis$v_tb3_page0_valid pyxis$r_pci_tb3_page0_overlay.pyxis$r_pci_tb3_page0_bits.pyxis$v_tb3_page0_valid #define pyxis$v_tb3_page0_addr pyxis$r_pci_tb3_page0_overlay.pyxis$r_pci_tb3_page0_bits.pyxis$v_tb3_page0_addr #define pyxis$l_pci_tb3_page1 pyxis$r_pci_tb3_page1_overlay.pyxis$l_pci_tb3_page1 #define pyxis$v_tb3_page1_valid pyxis$r_pci_tb3_page1_overlay.pyxis$r_pci_tb3_page1_bits.pyxis$v_tb3_page1_valid #define pyxis$v_tb3_page1_addr pyxis$r_pci_tb3_page1_overlay.pyxis$r_pci_tb3_page1_bits.pyxis$v_tb3_page1_addr #define pyxis$l_pci_tb3_page2 pyxis$r_pci_tb3_page2_overlay.pyxis$l_pci_tb3_page2 #define pyxis$v_tb3_page2_valid pyxis$r_pci_tb3_page2_overlay.pyxis$r_pci_tb3_page2_bits.pyxis$v_tb3_page2_valid #define pyxis$v_tb3_page2_addr pyxis$r_pci_tb3_page2_overlay.pyxis$r_pci_tb3_page2_bits.pyxis$v_tb3_page2_addr #define pyxis$l_pci_tb3_page3 pyxis$r_pci_tb3_page3_overlay.pyxis$l_pci_tb3_page3 #define pyxis$v_tb3_page3_valid pyxis$r_pci_tb3_page3_overlay.pyxis$r_pci_tb3_page3_bits.pyxis$v_tb3_page3_valid #define pyxis$v_tb3_page3_addr pyxis$r_pci_tb3_page3_overlay.pyxis$r_pci_tb3_page3_bits.pyxis$v_tb3_page3_addr #define pyxis$l_pci_tb4_page0 pyxis$r_pci_tb4_page0_overlay.pyxis$l_pci_tb4_page0 #define pyxis$v_tb4_page0_valid pyxis$r_pci_tb4_page0_overlay.pyxis$r_pci_tb4_page0_bits.pyxis$v_tb4_page0_valid #define pyxis$v_tb4_page0_addr pyxis$r_pci_tb4_page0_overlay.pyxis$r_pci_tb4_page0_bits.pyxis$v_tb4_page0_addr #define pyxis$l_pci_tb4_page1 pyxis$r_pci_tb4_page1_overlay.pyxis$l_pci_tb4_page1 #define pyxis$v_tb4_page1_valid pyxis$r_pci_tb4_page1_overlay.pyxis$r_pci_tb4_page1_bits.pyxis$v_tb4_page1_valid #define pyxis$v_tb4_page1_addr pyxis$r_pci_tb4_page1_overlay.pyxis$r_pci_tb4_page1_bits.pyxis$v_tb4_page1_addr #define pyxis$l_pci_tb4_page2 pyxis$r_pci_tb4_page2_overlay.pyxis$l_pci_tb4_page2 #define pyxis$v_tb4_page2_valid pyxis$r_pci_tb4_page2_overlay.pyxis$r_pci_tb4_page2_bits.pyxis$v_tb4_page2_valid #define pyxis$v_tb4_page2_addr pyxis$r_pci_tb4_page2_overlay.pyxis$r_pci_tb4_page2_bits.pyxis$v_tb4_page2_addr #define pyxis$l_pci_tb4_page3 pyxis$r_pci_tb4_page3_overlay.pyxis$l_pci_tb4_page3 #define pyxis$v_tb4_page3_valid pyxis$r_pci_tb4_page3_overlay.pyxis$r_pci_tb4_page3_bits.pyxis$v_tb4_page3_valid #define pyxis$v_tb4_page3_addr pyxis$r_pci_tb4_page3_overlay.pyxis$r_pci_tb4_page3_bits.pyxis$v_tb4_page3_addr #define pyxis$l_pci_tb5_page0 pyxis$r_pci_tb5_page0_overlay.pyxis$l_pci_tb5_page0 #define pyxis$v_tb5_page0_valid pyxis$r_pci_tb5_page0_overlay.pyxis$r_pci_tb5_page0_bits.pyxis$v_tb5_page0_valid #define pyxis$v_tb5_page0_addr pyxis$r_pci_tb5_page0_overlay.pyxis$r_pci_tb5_page0_bits.pyxis$v_tb5_page0_addr #define pyxis$l_pci_tb5_page1 pyxis$r_pci_tb5_page1_overlay.pyxis$l_pci_tb5_page1 #define pyxis$v_tb5_page1_valid pyxis$r_pci_tb5_page1_overlay.pyxis$r_pci_tb5_page1_bits.pyxis$v_tb5_page1_valid #define pyxis$v_tb5_page1_addr pyxis$r_pci_tb5_page1_overlay.pyxis$r_pci_tb5_page1_bits.pyxis$v_tb5_page1_addr #define pyxis$l_pci_tb5_page2 pyxis$r_pci_tb5_page2_overlay.pyxis$l_pci_tb5_page2 #define pyxis$v_tb5_page2_valid pyxis$r_pci_tb5_page2_overlay.pyxis$r_pci_tb5_page2_bits.pyxis$v_tb5_page2_valid #define pyxis$v_tb5_page2_addr pyxis$r_pci_tb5_page2_overlay.pyxis$r_pci_tb5_page2_bits.pyxis$v_tb5_page2_addr #define pyxis$l_pci_tb5_page3 pyxis$r_pci_tb5_page3_overlay.pyxis$l_pci_tb5_page3 #define pyxis$v_tb5_page3_valid pyxis$r_pci_tb5_page3_overlay.pyxis$r_pci_tb5_page3_bits.pyxis$v_tb5_page3_valid #define pyxis$v_tb5_page3_addr pyxis$r_pci_tb5_page3_overlay.pyxis$r_pci_tb5_page3_bits.pyxis$v_tb5_page3_addr #define pyxis$l_pci_tb6_page0 pyxis$r_pci_tb6_page0_overlay.pyxis$l_pci_tb6_page0 #define pyxis$v_tb6_page0_valid pyxis$r_pci_tb6_page0_overlay.pyxis$r_pci_tb6_page0_bits.pyxis$v_tb6_page0_valid #define pyxis$v_tb6_page0_addr pyxis$r_pci_tb6_page0_overlay.pyxis$r_pci_tb6_page0_bits.pyxis$v_tb6_page0_addr #define pyxis$l_pci_tb6_page1 pyxis$r_pci_tb6_page1_overlay.pyxis$l_pci_tb6_page1 #define pyxis$v_tb6_page1_valid pyxis$r_pci_tb6_page1_overlay.pyxis$r_pci_tb6_page1_bits.pyxis$v_tb6_page1_valid #define pyxis$v_tb6_page1_addr pyxis$r_pci_tb6_page1_overlay.pyxis$r_pci_tb6_page1_bits.pyxis$v_tb6_page1_addr #define pyxis$l_pci_tb6_page2 pyxis$r_pci_tb6_page2_overlay.pyxis$l_pci_tb6_page2 #define pyxis$v_tb6_page2_valid pyxis$r_pci_tb6_page2_overlay.pyxis$r_pci_tb6_page2_bits.pyxis$v_tb6_page2_valid #define pyxis$v_tb6_page2_addr pyxis$r_pci_tb6_page2_overlay.pyxis$r_pci_tb6_page2_bits.pyxis$v_tb6_page2_addr #define pyxis$l_pci_tb6_page3 pyxis$r_pci_tb6_page3_overlay.pyxis$l_pci_tb6_page3 #define pyxis$v_tb6_page3_valid pyxis$r_pci_tb6_page3_overlay.pyxis$r_pci_tb6_page3_bits.pyxis$v_tb6_page3_valid #define pyxis$v_tb6_page3_addr pyxis$r_pci_tb6_page3_overlay.pyxis$r_pci_tb6_page3_bits.pyxis$v_tb6_page3_addr #define pyxis$l_pci_tb7_page0 pyxis$r_pci_tb7_page0_overlay.pyxis$l_pci_tb7_page0 #define pyxis$v_tb7_page0_valid pyxis$r_pci_tb7_page0_overlay.pyxis$r_pci_tb7_page0_bits.pyxis$v_tb7_page0_valid #define pyxis$v_tb7_page0_addr pyxis$r_pci_tb7_page0_overlay.pyxis$r_pci_tb7_page0_bits.pyxis$v_tb7_page0_addr #define pyxis$l_pci_tb7_page1 pyxis$r_pci_tb7_page1_overlay.pyxis$l_pci_tb7_page1 #define pyxis$v_tb7_page1_valid pyxis$r_pci_tb7_page1_overlay.pyxis$r_pci_tb7_page1_bits.pyxis$v_tb7_page1_valid #define pyxis$v_tb7_page1_addr pyxis$r_pci_tb7_page1_overlay.pyxis$r_pci_tb7_page1_bits.pyxis$v_tb7_page1_addr #define pyxis$l_pci_tb7_page2 pyxis$r_pci_tb7_page2_overlay.pyxis$l_pci_tb7_page2 #define pyxis$v_tb7_page2_valid pyxis$r_pci_tb7_page2_overlay.pyxis$r_pci_tb7_page2_bits.pyxis$v_tb7_page2_valid #define pyxis$v_tb7_page2_addr pyxis$r_pci_tb7_page2_overlay.pyxis$r_pci_tb7_page2_bits.pyxis$v_tb7_page2_addr #define pyxis$l_pci_tb7_page3 pyxis$r_pci_tb7_page3_overlay.pyxis$l_pci_tb7_page3 #define pyxis$v_tb7_page3_valid pyxis$r_pci_tb7_page3_overlay.pyxis$r_pci_tb7_page3_bits.pyxis$v_tb7_page3_valid #define pyxis$v_tb7_page3_addr pyxis$r_pci_tb7_page3_overlay.pyxis$r_pci_tb7_page3_bits.pyxis$v_tb7_page3_addr #define pyxis$l_clock_config pyxis$r_clock_config_overlay.pyxis$l_clock_config #define pyxis$v_ccr_clock_divide pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_clock_divide #define pyxis$v_ccr_pclk_divide pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_pclk_divide #define pyxis$v_ccr_sel_cfg pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_sel_cfg #define pyxis$v_ccr_dclk_inv pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_dclk_inv #define pyxis$v_ccr_dclk_force pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_dclk_force #define pyxis$v_ccr_dclk_delay pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_dclk_delay #define pyxis$l_reset pyxis$r_reset_overlay.pyxis$l_reset #define pyxis$l_far_reg pyxis$r_far_overlay.pyxis$l_far_reg #define pyxis$v_far_heat pyxis$r_far_overlay.pyxis$r_far_bits.pyxis$v_far_heat #define pyxis$l_fcr_reg pyxis$r_fcr_overlay.pyxis$l_fcr_reg #define pyxis$v_fcr_on_heat pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_on_heat #define pyxis$v_fcr_sample pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_sample #define pyxis$v_fcr_off_delay pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_off_delay #define pyxis$v_fcr_force_fan pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_force_fan #define pyxis$v_fcr_force_fan_hi pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_force_fan_hi #define pyxis$v_fcr_fan_on pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_fan_on #define pyxis$v_fcr_fan_on_hi pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_fan_on_hi #define pyxis$l_ftr_reg pyxis$r_ftr_overlay.pyxis$l_ftr_reg #define pyxis$v_ftr_fan_on pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_on #define pyxis$v_ftr_fan_hi pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_hi #define pyxis$v_ftr_fan_hi_lo pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_hi_lo #define pyxis$v_ftr_fan_off pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_off #define pyxis$l_pcr_reg pyxis$r_pcr_overlay.pyxis$l_pcr_reg #define pyxis$v_pcr_power_down pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_power_down #define pyxis$v_pcr_abus_dis pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_abus_dis #define pyxis$v_pcr_iint_dis pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_iint_dis #define pyxis$v_pcr_do_reset pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_do_reset #define pyxis$l_ptr_reg pyxis$r_ptr_overlay.pyxis$l_ptr_reg #define pyxis$v_ptr_pll_delay pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_pll_delay #define pyxis$v_ptr_off_delay pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_off_delay #define pyxis$v_ptr_reset_pulse_width pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_reset_pulse_width #define pyxis$v_ptr_min_off_time pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_min_off_time #define pyxis$l_psr_reg pyxis$r_psr_overlay.pyxis$l_psr_reg #define pyxis$q_int_req pyxis$r_int_req_overlay.pyxis$q_int_req #define pyxis$v_int_req_31_0 pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_31_0 #define pyxis$v_int_req_61_32 pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_61_32 #define pyxis$v_int_req_clk_pend pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_clk_pend #define pyxis$v_int_req_err_int pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_err_int #define pyxis$q_int_mask pyxis$r_int_mask_overlay.pyxis$q_int_mask #define pyxis$v_int_mask_31_0 pyxis$r_int_mask_overlay.pyxis$r_int_mask_bits.pyxis$v_int_mask_31_0 #define pyxis$v_int_mask_61_32 pyxis$r_int_mask_overlay.pyxis$r_int_mask_bits.pyxis$v_int_mask_61_32 #define pyxis$l_int_hilo pyxis$r_int_hilo_overlay.pyxis$l_int_hilo #define pyxis$v_int_hilo_byte pyxis$r_int_hilo_overlay.pyxis$r_int_hilo_bits.pyxis$v_int_hilo_byte #define pyxis$l_int_route pyxis$r_int_route_overlay.pyxis$l_int_route #define pyxis$v_int_rte pyxis$r_int_route_overlay.pyxis$r_int_route_bits.pyxis$v_int_rte #define pyxis$v_int_rte_fill pyxis$r_int_route_overlay.pyxis$r_int_route_bits.pyxis$v_int_rte_fill #define pyxis$q_gpo_register pyxis$r_gpo_overlay.pyxis$q_gpo_register #define pyxis$l_int_config pyxis$r_int_config_overlay.pyxis$l_int_config #define pyxis$v_icnfg_clk_div pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_clk_div #define pyxis$v_icnfg_irq_cnt pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_irq_cnt #define pyxis$v_icnfg_fill1 pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_fill1 #define pyxis$v_icnfg_irq_cfg pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_irq_cfg #define pyxis$v_icnfg_fill2 pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_fill2 #define pyxis$v_icnfg_drive_irq pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_drive_irq #define pyxis$q_real_time_counter pyxis$r_real_time_counter_overlay.pyxis$q_real_time_counter #define pyxis$q_interrupt_timer pyxis$r_int_time_overlay.pyxis$q_interrupt_timer #define pyxis$l_iic_control pyxis$r_iic_control_overlay.pyxis$l_iic_control #define pyxis$v_iic_read_data pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_read_data #define pyxis$v_iic_read_clk pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_read_clk #define pyxis$v_iic_data_en pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_data_en #define pyxis$v_iic_data pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_data #define pyxis$v_iic_clk_en pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_clk_en #define pyxis$v_iic_clk pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_clk #define pyxis$v_iic_fill pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_fill #define pyxis$b_fraction_sec pyxis$r_fraction_sec_overlay.pyxis$b_fraction_sec #define pyxis$v_sec_01 pyxis$r_fraction_sec_overlay.pyxis$r_fraction_sec_bits.pyxis$v_sec_01 #define pyxis$v_sec_1 pyxis$r_fraction_sec_overlay.pyxis$r_fraction_sec_bits.pyxis$v_sec_1 #define pyxis$b_second_byte pyxis$r_second_overlay.pyxis$b_second_byte #define pyxis$v_second pyxis$r_second_overlay.pyxis$r_second_bits.pyxis$v_second #define pyxis$v_sec_10 pyxis$r_second_overlay.pyxis$r_second_bits.pyxis$v_sec_10 #define pyxis$b_minute_byte pyxis$r_minute_overlay.pyxis$b_minute_byte #define pyxis$v_minute pyxis$r_minute_overlay.pyxis$r_minute_bits.pyxis$v_minute #define pyxis$v_min_10 pyxis$r_minute_overlay.pyxis$r_minute_bits.pyxis$v_min_10 #define pyxis$b_min_alarm_byte pyxis$r_min_alarm_overlay.pyxis$b_min_alarm_byte #define pyxis$v_alarm_min pyxis$r_min_alarm_overlay.pyxis$r_min_alarm_bits.pyxis$v_alarm_min #define pyxis$v_alarm_min_10 pyxis$r_min_alarm_overlay.pyxis$r_min_alarm_bits.pyxis$v_alarm_min_10 #define pyxis$v_set_min_alarm pyxis$r_min_alarm_overlay.pyxis$r_min_alarm_bits.pyxis$v_set_min_alarm #define pyxis$b_hour_byte pyxis$r_hour_overlay.pyxis$b_hour_byte #define pyxis$v_hour pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_hour #define pyxis$v_hour_10 pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_hour_10 #define pyxis$v_ap_10hr pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_ap_10hr #define pyxis$v_twelve pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_twelve #define pyxis$b_hour_alarm_byte pyxis$r_hour_alarm_overlay.pyxis$b_hour_alarm_byte #define pyxis$v_alarm_hour pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_hour #define pyxis$v_alarm_hour_10 pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_hour_10 #define pyxis$v_alarm_ap_10hr pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_ap_10hr #define pyxis$v_alarm_twelve pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_twelve #define pyxis$v_set_hour_alarm pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_set_hour_alarm #define pyxis$b_day_byte pyxis$r_day_overlay.pyxis$b_day_byte #define pyxis$v_day pyxis$r_day_overlay.pyxis$r_day_bits.pyxis$v_day #define pyxis$b_day_alarm_byte pyxis$r_day_alarm_overlay.pyxis$b_day_alarm_byte #define pyxis$v_day_alarm pyxis$r_day_alarm_overlay.pyxis$r_day_alarm_bits.pyxis$v_day_alarm #define pyxis$v_day_alarm_mbz pyxis$r_day_alarm_overlay.pyxis$r_day_alarm_bits.pyxis$v_day_alarm_mbz #define pyxis$v_set_day_alarm pyxis$r_day_alarm_overlay.pyxis$r_day_alarm_bits.pyxis$v_set_day_alarm #define pyxis$b_date_byte pyxis$r_date_overlay.pyxis$b_date_byte #define pyxis$v_date pyxis$r_date_overlay.pyxis$r_date_bits.pyxis$v_date #define pyxis$v_date_10 pyxis$r_date_overlay.pyxis$r_date_bits.pyxis$v_date_10 #define pyxis$b_month_byte pyxis$r_month_overlay.pyxis$b_month_byte #define pyxis$v_month pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_month #define pyxis$v_month_10 pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_month_10 #define pyxis$v_month_mbz pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_month_mbz #define pyxis$v_esqw pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_esqw #define pyxis$v_eosc pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_eosc #define pyxis$b_year_byte pyxis$r_year_overlay.pyxis$b_year_byte #define pyxis$v_year pyxis$r_year_overlay.pyxis$r_year_bits.pyxis$v_year #define pyxis$v_year_10 pyxis$r_year_overlay.pyxis$r_year_bits.pyxis$v_year_10 #define pyxis$b_command_1286_byte pyxis$r_command_1286_overlay.pyxis$b_command_1286_byte #define pyxis$v_tdf pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_tdf #define pyxis$v_waf pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_waf #define pyxis$v_tdm pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_tdm #define pyxis$v_wam pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_wam #define pyxis$v_pu_lvl pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_pu_lvl #define pyxis$v_ibh_lo pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_ibh_lo #define pyxis$v_ipsw pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_ipsw #define pyxis$v_te pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_te #define pyxis$b_wdog_c_byte pyxis$r_wdog_1286_c_overlay.pyxis$b_wdog_c_byte #define pyxis$v_wdog_01_sec pyxis$r_wdog_1286_c_overlay.pyxis$r_wdog_c_bits.pyxis$v_wdog_01_sec #define pyxis$v_wdog_1_sec pyxis$r_wdog_1286_c_overlay.pyxis$r_wdog_c_bits.pyxis$v_wdog_1_sec #define pyxis$b_wdog_d_byte pyxis$r_wdog_1286_d_overlay.pyxis$b_wdog_d_byte #define pyxis$v_wdog_sec pyxis$r_wdog_1286_d_overlay.pyxis$r_wdog_d_bits.pyxis$v_wdog_sec #define pyxis$v_wdog_10sec pyxis$r_wdog_1286_d_overlay.pyxis$r_wdog_d_bits.pyxis$v_wdog_10sec #define pyxis$b_vdivr pyxis$r_vdivr_overlay.pyxis$b_vdivr #define pyxis$b_v1isr pyxis$r_v1isr_overlay.pyxis$b_v1isr #define pyxis$b_v2isr pyxis$r_v2isr_overlay.pyxis$b_v2isr #define pyxis$b_v3isr pyxis$r_v3isr_overlay.pyxis$b_v3isr #define pyxis$b_vdier pyxis$r_vdier_overlay.pyxis$b_vdier #define pyxis$b_v1ier pyxis$r_v1ier_overlay.pyxis$b_v1ier #define pyxis$b_v2ier pyxis$r_v2ier_overlay.pyxis$b_v2ier #define pyxis$b_v3ier pyxis$r_v3ier_overlay.pyxis$b_v3ier #define pyxis$b_vmcsr pyxis$r_vmcsr_overlay.pyxis$b_vmcsr #define pyxis$b_vacsr pyxis$r_vacsr_overlay.pyxis$b_vacsr #define pyxis$b_bidr pyxis$r_bidr_overlay.pyxis$b_bidr #define pyxis$b_vsicsr0 pyxis$r_vsicsr0_overlay.pyxis$b_vsicsr0 #define pyxis$b_vsicsr1 pyxis$r_vsicsr1_overlay.pyxis$b_vsicsr1 #define pyxis$b_vsicsr2 pyxis$r_vsicsr2_overlay.pyxis$b_vsicsr2 #define pyxis$b_vsicsr3 pyxis$r_vsicsr3_overlay.pyxis$b_vsicsr3 #define pyxis$b_vsicsr4 pyxis$r_vsicsr4_overlay.pyxis$b_vsicsr4 #define pyxis$b_vsicsr5 pyxis$r_vsicsr5_overlay.pyxis$b_vsicsr5 #define pyxis$b_vsicsr6 pyxis$r_vsicsr6_overlay.pyxis$b_vsicsr6 #define pyxis$b_vsicsr9 pyxis$r_vsicsr9_overlay.pyxis$b_vsicsr9 #define pyxis$b_vsicsra pyxis$r_vsicsra_overlay.pyxis$b_vsicsra #define pyxis$b_vsicsrb pyxis$r_vsicsrb_overlay.pyxis$b_vsicsrb #define pyxis$b_vsicsrc pyxis$r_vsicsrc_overlay.pyxis$b_vsicsrc #define pyxis$b_vsicsr11 pyxis$r_vsicsr11_overlay.pyxis$b_vsicsr11 #define pyxis$b_vsicsr12 pyxis$r_vsicsr12_overlay.pyxis$b_vsicsr12 #define pyxis$b_vsicsr13 pyxis$r_vsicsr13_overlay.pyxis$b_vsicsr13 #define pyxis$b_vsicsr14 pyxis$r_vsicsr14_overlay.pyxis$b_vsicsr14 #define pyxis$b_vsicsr15 pyxis$r_vsicsr15_overlay.pyxis$b_vsicsr15 #define pyxis$b_vsicsr16 pyxis$r_vsicsr16_overlay.pyxis$b_vsicsr16 #define pyxis$b_vsicsr17 pyxis$r_vsicsr17_overlay.pyxis$b_vsicsr17 #endif /* #if !defined(__VAXC) */ /* */ /* DS1287A register definitions */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _pyxis_ds1287a { #pragma __nomember_alignment unsigned char pyxis_ds1287a$b_fill1 [3584]; unsigned int pyxis_ds1287a$l_port_index; unsigned char pyxis_ds1287a$b_fill2 [28]; unsigned int pyxis_ds1287a$l_port_data; char pyxis_ds1287a$b_fill_13_ [4]; } PYXIS_DS1287A; #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __PYXISDEF_LOADED */