/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:39 by OpenVMS SDL EV3-3 */ /* Source: 22-JUN-2006 19:58:04 $1$DGA7274:[LIB_H.SRC]PCIDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $PCIDEF ***/ #ifndef __PCIDEF_LOADED #define __PCIDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* */ /* ============================================================================ */ /* PCI Type-0 Configuration Space */ /* ============================================================================ */ /* */ #define PCI$K_VENDOR_ID 0 #define PCI$K_DEVICE_ID 2 #define PCI$K_COMMAND 4 #define PCI$M_IO_ENABLE 0x1 #define PCI$M_MEM_ENABLE 0x2 #define PCI$M_BUS_MASTER_ENABLE 0x4 #define PCI$M_SPECIAL_CYCLE_ENABLE 0x8 #define PCI$M_INVAL_ENABLE 0x10 #define PCI$M_PALETTE_SNOOP_ENABLE 0x20 #define PCI$M_PARITY_ENABLE 0x40 #define PCI$M_WAIT_CYCLE_ENABLE 0x80 #define PCI$M_SERR_ENABLE 0x100 #define PCI$M_BACK_TO_BACK_ENABLE 0x200 #define PCI$M_INT_DISABLE 0x400 #define PCI$K_STATUS 6 #define PCI$M_INT_STATUS 0x8 #define PCI$M_CAP_LIST 0x10 #define PCI$M_SPEED_66MHZ 0x20 #define PCI$M_RSVD_1 0x40 #define PCI$M_FAST_BB_CAPABLE 0x80 #define PCI$M_DATA_PARITY_DETECT 0x100 #define PCI$M_DEVSEL_TIMING 0x600 #define PCI$M_SIGNAL_TARGET_ABORT 0x800 #define PCI$M_RCV_TARGET_ABORT 0x1000 #define PCI$M_RCV_MASTER_ABORT 0x2000 #define PCI$M_SIGNAL_SERR 0x4000 #define PCI$M_DETECT_PE 0x8000 #define PCI$K_REVISION_ID 8 #define PCI$K_PROGRAMMING_IF 9 #define PCI$K_SUB_CLASS 10 #define PCI$K_BASE_CLASS 11 #define PCI$K_CACHE_LINE_SIZE 12 #define PCI$K_LATENCY_TIMER 13 #define PCI$K_HEADER_TYPE 14 #define PCI$K_BIST 15 #define PCI$K_BASE_ADDRESS_0 16 #define PCI$K_BASE_ADDRESS_1 20 #define PCI$K_BASE_ADDRESS_2 24 #define PCI$K_BASE_ADDRESS_3 28 #define PCI$K_BASE_ADDRESS_4 32 #define PCI$K_BASE_ADDRESS_5 36 #define PCI$K_CARDBUS_CIS 40 #define PCI$K_SUB_VNDR 44 #define PCI$K_SUB_ID 46 #define PCI$K_EXP_ROM_BASE 48 #define PCI$K_CAPABILITIES_POINTER 52 #define PCI$K_INTR_LINE 60 #define PCI$K_INTR_PIN 61 #define PCI$K_MIN_GNT 62 #define PCI$K_MAX_LAT 63 #define PCI$S_PCIDEF 64 /* Old PCI size for compatibility */ /* The following constants apply to the DEVSEL timing field in the STATUS register */ #define PCI$K_DEVSEL_FAST 0 #define PCI$K_DEVSEL_MEDIUM 1 #define PCI$K_DEVSEL_SLOW 2 /* The following constants apply to the BASE_CLASS byte */ #define PCI$K_NOT_IMPLEMENTED 0 #define PCI$K_MASS_STORAGE_CTRLR 1 #define PCI$K_NETWORK_CTRLR 2 #define PCI$K_DISPLAY_CTRLR 3 #define PCI$K_MULTIMEDIA_DEVICE 4 #define PCI$K_MEMORY_CTRLR 5 #define PCI$K_BRIDGE_DEVICE 6 #define PCI$K_UNDEFINED 255 /* The following sub class definitions apply to the Mass Storage Base Class */ #define PCI$K_SCSI_CTRLR 0 #define PCI$K_IDE_CTRLR 1 #define PCI$K_FLOPPY_CTRLR 2 #define PCI$K_IPI_CTRLR 3 #define PCI$K_OTHER_MASS_STORAGE 80 /* The following sub class definitions apply to the Network Controller Base Class */ #define PCI$K_NI_CTRLR 0 #define PCI$K_TOKEN_CTRLR 1 #define PCI$K_FDDI_CTRLR 2 #define PCI$K_OTHER_NETWORK 80 /* The following sub class definitions apply to the Display Controller Base Class */ #define PCI$K_VGA_CTRLR 0 #define PCI$K_XGA_CTRLR 1 #define PCI$K_OTHER_DISPLAY 80 /* The following sub class definitions apply to the Multimedia Device Base Class */ #define PCI$K_VIDEO_CTRLR 0 #define PCI$K_AUDIO_CTRLR 1 #define PCI$K_OTHER_MULTIMEDIA 80 /* The following sub class definitions apply to the Memory Controller Base Class */ #define PCI$K_RAM 0 #define PCI$K_FLASH 1 #define PCI$K_OTHER_MEMORY 80 /* The following sub class definitions apply to the Bridge Device Base Class */ #define PCI$K_HOST_BRIDGE 0 #define PCI$K_ISA_BRIDGE 1 #define PCI$K_EISA_BRIDGE 2 #define PCI$K_MC_BRIDGE 3 #define PCI$K_PCI_PCI_BRIDGE 4 #define PCI$K_PCMCIA_BRIDGE 5 #define PCI$K_OTHER_BRIDGE 80 /* The following constants apply to the Interrupt Pin byte */ #define PCI$K_INTR_PIN_NOT_USED 0 #define PCI$K_INTR_PIN_INTA 1 #define PCI$K_INTR_PIN_INTB 2 #define PCI$K_INTR_PIN_INTC 3 #define PCI$K_INTR_PIN_INTD 4 #define PCI$K_MAX_DEVICES 32 #define PCI$K_LENGTH 64 typedef struct _pci { short int pci$w_vendor_id; short int pci$w_device_id; __union { short int pci$w_command; __struct { unsigned pci$v_io_enable : 1; /* 0 */ unsigned pci$v_mem_enable : 1; /* 1 */ unsigned pci$v_bus_master_enable : 1; /* 2 */ unsigned pci$v_special_cycle_enable : 1; /* 3 */ unsigned pci$v_inval_enable : 1; /* 4 */ unsigned pci$v_palette_snoop_enable : 1; /* 5 */ unsigned pci$v_parity_enable : 1; /* 6 */ unsigned pci$v_wait_cycle_enable : 1; /* 7 */ unsigned pci$v_serr_enable : 1; /* 8 */ unsigned pci$v_back_to_back_enable : 1; /* 9 */ unsigned pci$v_int_disable : 1; /* 10 PCI Spec V2.3 */ unsigned pci$v_command_fill : 5; /* 15:11 */ } pci$r_command_bits; } pci$r_command_overlay; __union { short int pci$w_status; __struct { unsigned pci$v_status_fill : 3; /* 2:0 */ unsigned pci$v_int_status : 1; /* 3 */ unsigned pci$v_cap_list : 1; /* 4 */ unsigned pci$v_speed_66mhz : 1; /* 5 */ unsigned pci$v_rsvd_1 : 1; /* 6 */ unsigned pci$v_fast_bb_capable : 1; /* 7 */ unsigned pci$v_data_parity_detect : 1; /* 8 */ unsigned pci$v_devsel_timing : 2; /* 10:9 */ unsigned pci$v_signal_target_abort : 1; /* 11 */ unsigned pci$v_rcv_target_abort : 1; /* 12 */ unsigned pci$v_rcv_master_abort : 1; /* 13 */ unsigned pci$v_signal_serr : 1; /* 14 */ unsigned pci$v_detect_pe : 1; /* 15 */ } pci$r_status_bits; } pci$r_status_overlay; char pci$b_revision_id; char pci$b_programming_if; char pci$b_sub_class; char pci$b_base_class; char pci$b_cache_line_size; char pci$b_latency_timer; char pci$b_header_type; char pci$b_bist; int pci$l_base_address_0; int pci$l_base_address_1; int pci$l_base_address_2; int pci$l_base_address_3; int pci$l_base_address_4; int pci$l_base_address_5; int pci$l_cardbus_cis; short int pci$w_sub_vndr; short int pci$w_sub_id; int pci$l_exp_rom_base; __union { __struct { char pci$b_capabilities_pointer; } pci$r_lw_0x34_struct; int pci$l_reserved_3; } pci$r_lw_0x34_overlay; int pci$l_reserved_4; char pci$b_intr_line; char pci$b_intr_pin; char pci$b_min_gnt; char pci$b_max_lat; } PCI; #if !defined(__VAXC) #define pci$w_command pci$r_command_overlay.pci$w_command #define pci$v_io_enable pci$r_command_overlay.pci$r_command_bits.pci$v_io_enable #define pci$v_mem_enable pci$r_command_overlay.pci$r_command_bits.pci$v_mem_enable #define pci$v_bus_master_enable pci$r_command_overlay.pci$r_command_bits.pci$v_bus_master_enable #define pci$v_special_cycle_enable pci$r_command_overlay.pci$r_command_bits.pci$v_special_cycle_enable #define pci$v_inval_enable pci$r_command_overlay.pci$r_command_bits.pci$v_inval_enable #define pci$v_palette_snoop_enable pci$r_command_overlay.pci$r_command_bits.pci$v_palette_snoop_enable #define pci$v_parity_enable pci$r_command_overlay.pci$r_command_bits.pci$v_parity_enable #define pci$v_wait_cycle_enable pci$r_command_overlay.pci$r_command_bits.pci$v_wait_cycle_enable #define pci$v_serr_enable pci$r_command_overlay.pci$r_command_bits.pci$v_serr_enable #define pci$v_back_to_back_enable pci$r_command_overlay.pci$r_command_bits.pci$v_back_to_back_enable #define pci$v_int_disable pci$r_command_overlay.pci$r_command_bits.pci$v_int_disable #define pci$w_status pci$r_status_overlay.pci$w_status #define pci$v_int_status pci$r_status_overlay.pci$r_status_bits.pci$v_int_status #define pci$v_cap_list pci$r_status_overlay.pci$r_status_bits.pci$v_cap_list #define pci$v_speed_66mhz pci$r_status_overlay.pci$r_status_bits.pci$v_speed_66mhz #define pci$v_rsvd_1 pci$r_status_overlay.pci$r_status_bits.pci$v_rsvd_1 #define pci$v_fast_bb_capable pci$r_status_overlay.pci$r_status_bits.pci$v_fast_bb_capable #define pci$v_data_parity_detect pci$r_status_overlay.pci$r_status_bits.pci$v_data_parity_detect #define pci$v_devsel_timing pci$r_status_overlay.pci$r_status_bits.pci$v_devsel_timing #define pci$v_signal_target_abort pci$r_status_overlay.pci$r_status_bits.pci$v_signal_target_abort #define pci$v_rcv_target_abort pci$r_status_overlay.pci$r_status_bits.pci$v_rcv_target_abort #define pci$v_rcv_master_abort pci$r_status_overlay.pci$r_status_bits.pci$v_rcv_master_abort #define pci$v_signal_serr pci$r_status_overlay.pci$r_status_bits.pci$v_signal_serr #define pci$v_detect_pe pci$r_status_overlay.pci$r_status_bits.pci$v_detect_pe #define pci$b_capabilities_pointer pci$r_lw_0x34_overlay.pci$r_lw_0x34_struct.pci$b_capabilities_pointer #define pci$l_reserved_3 pci$r_lw_0x34_overlay.pci$l_reserved_3 #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* PCI Capabilities Identifiers */ /* ============================================================================ */ /* These constants apply to the CAPABILITIES field identified by the */ /* CAPABILITIES POINTER. For more details, see Appendix H of the */ /* PCI 3.0 spec. */ /* */ #define PCI$K_PMI_CAP 1 /* 1 Power Management Interface */ #define PCI$K_AGP_CAP 2 /* 2 see http://www.agpforum.org */ #define PCI$K_VPD_CAP 3 /* 3 see sec. 6.4 of PCI 2.3 spec */ #define PCI$K_SID_CAP 4 /* 4 Slot ID, see PPB spec */ #define PCI$K_MSI_CAP 5 /* 5 see sec. 6.8 of PCI 2.3 spec */ #define PCI$K_PHS_CAP 6 /* 6 see http://www.picmg.org */ #define PCI$K_PCIX_CAP 7 /* 7 see PCI-X addendum */ #define PCI$K_AMD_CAP 8 /* 8 reserved for AMD */ #define PCI$K_VSID_CAP 9 /* 9 Vendor-specific */ #define PCI$K_DBG_CAP 10 /* A Debug port */ #define PCI$K_CRC_CAP 11 /* B see http://www.picmg.org */ #define PCI$K_HP_CAP 12 /* C Hot Plug Controller */ #define PCI$K_PPB_VID 13 /* D PCI-PCI Bridge Subsystem Vendor ID */ #define PCI$K_AGP_8X 14 /* E see http://www.agpforum.org */ #define PCI$K_SECURE_CAP 15 /* F secure device */ #define PCI$K_PCIE_CAP 16 /* 10 PCI Express */ #define PCI$K_MSIX_CAP 17 /* 11 MSI-X Capability */ /* */ /* */ /* ============================================================================ */ /* Base Address Register */ /* ============================================================================ */ /* */ #define PCI$M_BASE_ADDRESS_MEM_IO 0x1 #define PCI$M_BASE_ADDRESS_TYPE 0x6 #define PCI$M_BASE_ADDRESS_PREFETCHABLE 0x8 #define PCI$M_BASE_ADDRESS_BITS_31_4 0xFFFFFFF0 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _base_address { #pragma __nomember_alignment __union { int pci$l_base_address; __struct { unsigned pci$v_base_address_mem_io : 1; unsigned pci$v_base_address_type : 2; unsigned pci$v_base_address_prefetchable : 1; unsigned pci$v_base_address_bits_31_4 : 28; } pci$r_base_address_bits; } pci$r_base_address_overlay; } BASE_ADDRESS; #if !defined(__VAXC) #define pci$l_base_address pci$r_base_address_overlay.pci$l_base_address #define pci$v_base_address_mem_io pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_mem_io #define pci$v_base_address_type pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_type #define pci$v_base_address_prefetchable pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_prefetchable #define pci$v_base_address_bits_31_4 pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_bits_31_4 #endif /* #if !defined(__VAXC) */ #define BASE_ADDR_32 0 #define BASE_ADDR_BELOW_1MB 1 #define BASE_ADDR_64 2 #define BASE_ADDR_RESERVED 3 /* */ /* */ /* ============================================================================ */ /* PCI_NODE_NUMBER */ /* ============================================================================ */ /* */ #define PCI$M_PCI_NODE_NUMBER_FUNCTION 0x7 #define PCI$M_PCI_NODE_NUMBER_DEVICE 0xF8 #define PCI$M_PCI_NODE_NUMBER_BUS 0xFF00 #define PCI$M_PCI_NODE_NUMBER_OFFSET 0xFFFF0000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _pci_node_number { #pragma __nomember_alignment __union { int pci$l_pci_node_number; __struct { unsigned pci$v_pci_node_number_function : 3; unsigned pci$v_pci_node_number_device : 5; unsigned pci$v_pci_node_number_bus : 8; unsigned pci$v_pci_node_number_offset : 16; } pci$r_pci_node_number_bits; } pci$r_pci_node_number_overlay; } PCI_NODE_NUMBER; #if !defined(__VAXC) #define pci$l_pci_node_number pci$r_pci_node_number_overlay.pci$l_pci_node_number #define pci$v_pci_node_number_function pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_function #define pci$v_pci_node_number_device pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_device #define pci$v_pci_node_number_bus pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_bus #define pci$v_pci_node_number_offset pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_offset #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* Hardware ID field */ /* ============================================================================ */ /* */ typedef struct _pci_busarray_hardware_id { __union { __int64 pci$q_pci_hardware_id; __struct { short int pci$w_pci_hardware_id_vendor; short int pci$w_pci_hardware_id_device; __union { int pci$l_pci_hardware_id_fill; __struct { short int pci$w_pci_hardware_id_sub_vndr; short int pci$w_pci_hardware_id_sub_id; } pci$r_pci_hardware_id_fill_names; } pci$r_pci_hardware_v21; } pci$r_pci_hardware_id_bits; } pci$r_pci_hardware_id_overlay; } PCI_BUSARRAY_HARDWARE_ID; #if !defined(__VAXC) #define pci$q_pci_hardware_id pci$r_pci_hardware_id_overlay.pci$q_pci_hardware_id #define pci$w_pci_hardware_id_vendor pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$w_pci_hardware_id_vendor #define pci$w_pci_hardware_id_device pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$w_pci_hardware_id_device #define pci$w_pci_hardware_id_sub_vndr pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$r_pci_hardware_v21.pci$r_pci_ha\ rdware_id_fill_names.pci$w_pci_hardware_id_sub_vndr #define pci$w_pci_hardware_id_sub_id pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$r_pci_hardware_v21.pci$r_pci_hard\ ware_id_fill_names.pci$w_pci_hardware_id_sub_id #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* PCIERR Structure */ /* ============================================================================ */ /* */ #define PCIERR$K_LENGTH 72 typedef struct _pcierr { unsigned pcierr$v_fill1 : 11; unsigned pcierr$v_device_number : 5; unsigned char pcierr$b_bus_number; unsigned char pcierr$b_fill2; unsigned int pcierr$l_frame_size; PCI pcierr$r_pci; } PCIERR; /* */ /* */ /* ============================================================================ */ /* PCIFLAGS structure */ /* ============================================================================ */ /* */ #define PCIFLAGS$M_FILL1 0xFFFFFF00 #define PCIFLAGS$M_DATA_PARITY_DETECT 0x1 #define PCIFLAGS$M_SIGNAL_TARGET_ABORT 0x2 #define PCIFLAGS$M_RCV_TARGET_ABORT 0x4 #define PCIFLAGS$M_RCV_MASTER_ABORT 0x8 #define PCIFLAGS$M_SIGNAL_SERR 0x10 #define PCIFLAGS$M_DETECT_PE 0x20 #define PCIFLAGS$M_FILL2 0xC0 #define PCIFLAGS$M_FILL3 0xFFFFFF00 typedef struct _pciflags { __union { __struct { unsigned char pciflags$b_pciflags; unsigned pciflags$v_fill1 : 24; } pciflags$r_pci_bits1; __struct { unsigned pciflags$v_data_parity_detect : 1; /* From PCI stat<8> */ unsigned pciflags$v_signal_target_abort : 1; /* Same as stat<11:15> */ unsigned pciflags$v_rcv_target_abort : 1; unsigned pciflags$v_rcv_master_abort : 1; unsigned pciflags$v_signal_serr : 1; unsigned pciflags$v_detect_pe : 1; unsigned pciflags$v_fill2 : 2; unsigned pciflags$v_fill3 : 24; } pciflags$r_pci_bits2; } pciflags$r_pciflags_ov; } PCIFLAGS; #if !defined(__VAXC) #define pciflags$b_pciflags pciflags$r_pciflags_ov.pciflags$r_pci_bits1.pciflags$b_pciflags #define pciflags$v_data_parity_detect pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_data_parity_detect #define pciflags$v_signal_target_abort pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_signal_target_abort #define pciflags$v_rcv_target_abort pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_rcv_target_abort #define pciflags$v_rcv_master_abort pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_rcv_master_abort #define pciflags$v_signal_serr pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_signal_serr #define pciflags$v_detect_pe pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_detect_pe #endif /* #if !defined(__VAXC) */ #define ERRTAG$K_PCIERR 16 /* */ /* */ /* ============================================================================ */ /* Generic PCI capabilities header fields */ /* ============================================================================ */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8 */ /* */ /* This definition creates constants that are offsets into a PCI Capabiltiy */ /* block for a given device. These offsets are the same for any Capability */ /* block. */ /* */ /* PCICAP$K_ID - offset to the field containing the ID of this */ /* capability. */ /* */ /* PCICAP$K_NEXT - offset to field contianing the offset into the device's */ /* PCI Config Space of the next Capability Block. Contains */ /* zero if this is the last block. */ /* */ /* PCICAP$K_CONTROL - offset to the field containing the control word for */ /* this capability */ /* */ #define PCICAP$K_ID 0 #define PCICAP$K_NEXT 1 #define PCICAP$K_CONTROL 2 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif struct pcicap { #pragma __nomember_alignment unsigned char pcicap$b_id; unsigned char pcicap$b_next; unsigned short int pcicap$w_control; } ; /* */ /* */ /* ============================================================================ */ /* MSI Control Register definition */ /* ============================================================================ */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /* msi$v_enable - RW if set, the device will deliver interrupts as MSI. */ /* */ /* msi$v_multi_cap - RO encodes the number of vectors requested by this */ /* device. */ /* */ /* msi$v_multi_ena - RW encodes the number of vectors assigned to this */ /* device by configuration code. */ /* */ /* msi$v_addr64_cap - RO if set, the device writes its message to a 64-bit */ /* physical address. */ /* */ /* msi$v_per_vec_cap - RO if set, this device supports per-vector MSI masking */ /* capability. */ /* */ #define MSI$M_ENABLE 0x1 #define MSI$M_MULTI_CAP 0xE #define MSI$M_MULTI_ENA 0x70 #define MSI$M_ADDR64_CAP 0x80 #define MSI$M_PER_VEC_CAP 0x100 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __word #else #pragma __nomember_alignment #endif typedef struct _msi_control { #pragma __nomember_alignment __union { unsigned short int msi$w_control; __struct { unsigned msi$v_enable : 1; unsigned msi$v_multi_cap : 3; unsigned msi$v_multi_ena : 3; unsigned msi$v_addr64_cap : 1; unsigned msi$v_per_vec_cap : 1; unsigned msi$v_fill_0_ : 7; } msi$r_control_bits; } msi$r_control_overlay; } MSI_CONTROL; #if !defined(__VAXC) #define msi$w_control msi$r_control_overlay.msi$w_control #define msi$v_enable msi$r_control_overlay.msi$r_control_bits.msi$v_enable #define msi$v_multi_cap msi$r_control_overlay.msi$r_control_bits.msi$v_multi_cap #define msi$v_multi_ena msi$r_control_overlay.msi$r_control_bits.msi$v_multi_ena #define msi$v_addr64_cap msi$r_control_overlay.msi$r_control_bits.msi$v_addr64_cap #define msi$v_per_vec_cap msi$r_control_overlay.msi$r_control_bits.msi$v_per_vec_cap #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* Generic MSI */ /* ============================================================================ */ /* */ /* This definition creates constants that are offsets into the MSI PCI */ /* Capabiltiy block for a given device. */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /*************** */ /** IMPORTANT ** */ /*************** */ /* */ /* 1. If the ADDR64_CAP bit is set, you must use the MSI64 structure to */ /* access the following fields: */ /* . upper 32 bits of address */ /* . MESSAGE */ /* . VEC_MASK */ /* . VEC_PENDING */ /* */ /* 2. VEC_MASK and VEC_PENDING are only valid for access if the PER_VEC_CAP */ /* bit is set. */ /* */ #define MSICAP$K_CAP_ID 0 #define MSICAP$K_NEXT_CAP 1 #define MSICAP$K_CONTROL 2 #define MSICAP$K_ADDRESS 4 #define MSICAP$K_MESSAGE 8 #define MSICAP$K_RESERVED 10 #define MSICAP$K_BASIC_LENGTH 12 #define MSICAP$K_VEC_MASK 12 #define MSICAP$K_VEC_PENDING 16 #define MSICAP$K_VEC_LENGTH 20 #define MSICAP$K_VEC_AREA 8 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif struct msicap { #pragma __nomember_alignment unsigned char msicap$b_cap_id; unsigned char msicap$b_next_cap; MSI_CONTROL msicap$r_control; unsigned int msicap$l_address; unsigned short int msicap$w_message; unsigned short int msicap$w_reserved; unsigned int msicap$l_vec_mask; unsigned int msicap$l_vec_pending; } ; /* */ /* */ /* ============================================================================ */ /* MSI64 - MSI with 64 bit message address */ /* ============================================================================ */ /* */ /* This definition creates constants that are offsets into the MSI PCI */ /* Capabiltiy block for a given device. */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /*************** */ /** IMPORTANT ** */ /*************** */ /* */ /* 1. This structure is valid ONLY if the ADDR64_CAP bit is set. */ /* */ /* 2. VEC_MASK and VEC_PENDING are only valid for access if the PER_VEC_CAP */ /* bit is set. */ /* */ #define MSI64CAP$K_CAP_ID 0 #define MSI64CAP$K_NEXT_CAP 1 #define MSI64CAP$K_CONTROL 2 #define MSI64CAP$K_ADDRESS_LO 4 #define MSI64CAP$K_ADDRESS_HI 8 #define MSI64CAP$K_MESSAGE 12 #define MSI64CAP$K_RESERVED 14 #define MSI64CAP$K_BASIC_LENGTH 16 #define MSI64CAP$K_VEC_MASK 16 #define MSI64CAP$K_VEC_PENDING 20 #define MSI64CAP$K_VEC_LENGTH 24 #define MSI64CAP$K_VEC_AREA 8 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif struct msi64cap { #pragma __nomember_alignment unsigned char msi64cap$b_cap_id; unsigned char msi64cap$b_next_cap; MSI_CONTROL msi64cap$r_control; unsigned int msi64cap$l_address_lo; unsigned int msi64cap$l_address_hi; unsigned short int msi64cap$w_message; unsigned short int msi64cap$w_reserved; unsigned int msi64cap$l_vec_mask; unsigned int msi64cap$l_vec_pending; } ; /* */ /* */ /* ============================================================================ */ /* MSI 32-Bit Address Format */ /* ============================================================================ */ /* */ /* This definition of the Message Interrupt Message Address was obtained from */ /* The Intel IA64 Software Developers Manual, Volume 2, Figure 5-16 and Table */ /* 5-15. */ /* */ #define MSIADDR$M_RESERVED 0x7 #define MSIADDR$M_IR 0x8 #define MSIADDR$M_EID 0xFF0 #define MSIADDR$M_ID 0xFF000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _msiaddr { #pragma __nomember_alignment __union { unsigned int msiaddr$l_address; __struct { unsigned msiaddr$v_reserved : 3; unsigned msiaddr$v_ir : 1; unsigned msiaddr$v_eid : 8; unsigned msiaddr$v_id : 8; unsigned msiaddr$v_fill_1_ : 4; } msiaddr$r_bits; } msiaddr$r_addr_overlay; } MSIADDR; #if !defined(__VAXC) #define msiaddr$l_address msiaddr$r_addr_overlay.msiaddr$l_address #define msiaddr$v_reserved msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_reserved #define msiaddr$v_ir msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_ir #define msiaddr$v_eid msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_eid #define msiaddr$v_id msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_id #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* MSI 64-Bit Address Format */ /* ============================================================================ */ /* */ /* This definition of the Message Interrupt Message Address was obtained from */ /* The Intel IA64 Software Developers Manual, Volume 2, Figure 5-16 and Table */ /* 5-15. */ /* */ #define MSIADDR64$M_RESERVED 0x7 #define MSIADDR64$M_IR 0x8 #define MSIADDR64$M_EID 0xFF0 #define MSIADDR64$M_ID 0xFF000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _msiaddr64 { #pragma __nomember_alignment __union { unsigned __int64 msiaddr64$q_address; __struct { __union { int msiaddr64$l_address_lo; __struct { unsigned msiaddr64$v_reserved : 3; unsigned msiaddr64$v_ir : 1; unsigned msiaddr64$v_eid : 8; unsigned msiaddr64$v_id : 8; unsigned msiaddr64$v_fill_2_ : 4; } msiaddr64$r_lo_bits; } msiaddr64$r_lo_addr_ovly; int msiaddr64$l_address_hi; } msiaddr64$r_addr_ovly; } msiaddr64$r_addr_overlay; } MSIADDR64; #if !defined(__VAXC) #define msiaddr64$q_address msiaddr64$r_addr_overlay.msiaddr64$q_address #define msiaddr64$l_address_lo msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$l_address_lo #define msiaddr64$v_reserved msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$\ v_reserved #define msiaddr64$v_ir msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v_ir #define msiaddr64$v_eid msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v_eid #define msiaddr64$v_id msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v_id #define msiaddr64$l_address_hi msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$l_address_hi #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* MSI Message Format */ /* ============================================================================ */ /* */ /* This definition of the Interrupt Message format was obtained from the */ /* Intel IA64 Software Developers Manual, Volume 2, Figure 5-17 and Table */ /* 5-16. */ /* */ #define MSIMSG$M_VECTOR 0xFF #define MSIMSG$M_DELMODE 0x700 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _msimsg { #pragma __nomember_alignment __union { unsigned int msimsg$l_msg; unsigned short int msimsg$w_msg; __struct { unsigned msimsg$v_vector : 8; unsigned msimsg$v_delmode : 3; unsigned msimsg$v_fill_3_ : 5; } msimsg$r_bits; } msimsg$r_msg_overlay; } MSIMSG; #if !defined(__VAXC) #define msimsg$l_msg msimsg$r_msg_overlay.msimsg$l_msg #define msimsg$w_msg msimsg$r_msg_overlay.msimsg$w_msg #define msimsg$v_vector msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_vector #define msimsg$v_delmode msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_delmode #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* MSI-X Control Register Format */ /* ============================================================================ */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /* msix$v_table_size - number of entries in the Vector Table, which is */ /* also the number of bits in the Pending Bit Array, */ /* maximum 2048. */ /* */ /* msix$v_function_mask - Masks all messages from this device */ /* */ /* msix$v_enable - Enables MSI-X interrupt delivery for this device. */ /* */ #define MSIX$M_TABLE_SIZE 0x7FF #define MSIX$M_RESERVED 0x3800 #define MSIX$M_FUNCTION_MASK 0x4000 #define MSIX$M_ENABLE 0x8000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __word #else #pragma __nomember_alignment #endif typedef struct _msix_control { #pragma __nomember_alignment __union { unsigned short int msix$w_control; __struct { unsigned msix$v_table_size : 11; /* 10:0 */ unsigned msix$v_reserved : 3; /* 13:11 */ unsigned msix$v_function_mask : 1; /* 14 */ unsigned msix$v_enable : 1; /* 15 */ } msix$r_control_bits; } msix$r_control_ovly; } MSIX_CONTROL; #if !defined(__VAXC) #define msix$w_control msix$r_control_ovly.msix$w_control #define msix$v_table_size msix$r_control_ovly.msix$r_control_bits.msix$v_table_size #define msix$v_reserved msix$r_control_ovly.msix$r_control_bits.msix$v_reserved #define msix$v_function_mask msix$r_control_ovly.msix$r_control_bits.msix$v_function_mask #define msix$v_enable msix$r_control_ovly.msix$r_control_bits.msix$v_enable #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* MSI-X Offset Register Format */ /* ============================================================================ */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /* msix$v_bir - Three-bit field that encodes the offset into the device's */ /* PCI config space of the BAR that has the base address in */ /* of the Vector Table or Pending Bit Array, as the case may */ /* be. */ /* */ /* msix$v_offset - The 29-bit field containing the offset into the base */ /* address identified by the BAR of the Table or PBA. */ /* */ #define MSIX$M_BIR 0x7 #define MSIX$M_OFFSET 0xFFFFFFF8 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _msix_offset_reg { #pragma __nomember_alignment __union { unsigned int msix$l_offset; __struct { unsigned msix$v_bir : 3; /* 2:0 */ unsigned msix$v_offset : 29; /* 31:3 */ } msix$r_offset_bits; } msix$r_offset_ovly; } MSIX_OFFSET_REG; #if !defined(__VAXC) #define msix$l_offset msix$r_offset_ovly.msix$l_offset #define msix$v_bir msix$r_offset_ovly.msix$r_offset_bits.msix$v_bir #define msix$v_offset msix$r_offset_ovly.msix$r_offset_bits.msix$v_offset #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* MSI-X Capability Format */ /* ============================================================================ */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /* The constants generated by this definition are byte offsets into the */ /* MSI-X Capability Block in PCI Config space. */ /* */ /* MSIXCAP$K_CAP_ID - Offset to field contianing the ID of this */ /* Capability, for MSI-X, 0x11. */ /* */ /* MSIXCAP$K_NEXT_CAP - Offset to field containing the offset from the */ /* base of PCI config space fof the device to the */ /* next Capability block of the device. Contains */ /* zero if no more Capability blocks. */ /* */ /* MSIXCAP$K_CONTROL - Offset to field containing the MSI-X Capability */ /* control bits. */ /* */ /* MSIXCAP$K_TABLE_OFFSET - Offset to field whose low three bits encode the */ /* offset into PCI Config space of the BAR that has */ /* the base address of the Vector Table, and whose */ /* upper 29 bits contain the offset of the Vector */ /* Table into the space identified by the BAR. */ /* */ /* MSIXCAP$K_PBA_OFFSET - Offset to field whose low three bits encode the */ /* offset into PCI Config space of the BAR that has */ /* the base address of the Pending Bit Array, and */ /* whose upper 29 bits contain the offset of the */ /* Pending Bit Array into the space identified by */ /* the BAR. */ /* */ #define MSIXCAP$K_CAP_ID 0 #define MSIXCAP$K_NEXT_CAP 1 #define MSIXCAP$K_CONTROL 2 #define MSIXCAP$K_TABLE_OFFSET 4 #define MSIXCAP$K_PBA_OFFSET 8 #define MSIXCAP$K_LENGTH 12 #define MSIXCAP$K_SIZE 12 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif struct msixcap { #pragma __nomember_alignment unsigned char msixcap$b_cap_id; unsigned char msixcap$b_next_cap; MSIX_CONTROL msixcap$r_control; MSIX_OFFSET_REG msixcap$r_table_offset; MSIX_OFFSET_REG msixcap$r_pba_offset; } ; /* */ /* */ /* ============================================================================ */ /* MSI-X Table Entry Control Register */ /* ============================================================================ */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /* msix_entry$v_mask - masks the vector of the corresponding Vector Table */ /* MSIX_ENTRY$M_MASK Entry */ /* */ #define MSIX_ENTRY$M_MASK 0x1 #define MSIX_ENTRY$M_RESERVED 0xFFFFFFFE #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __longword #else #pragma __nomember_alignment #endif typedef struct _msix_entry_control { #pragma __nomember_alignment __union { unsigned int msix_entry$l_control; __struct { unsigned msix_entry$v_mask : 1; unsigned msix_entry$v_reserved : 31; } msix_entry$r_control_bits; } msix_entry$r_control_ovly; } MSIX_ENTRY_CONTROL; #if !defined(__VAXC) #define msix_entry$l_control msix_entry$r_control_ovly.msix_entry$l_control #define msix_entry$v_mask msix_entry$r_control_ovly.msix_entry$r_control_bits.msix_entry$v_mask #define msix_entry$v_reserved msix_entry$r_control_ovly.msix_entry$r_control_bits.msix_entry$v_reserved #endif /* #if !defined(__VAXC) */ /* */ /* */ /* ============================================================================ */ /* MSI-X Table Entry */ /* ============================================================================ */ /* */ /* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */ /* */ /* This definition generates constants that are offsets into the MSI-X */ /* Vector Table. */ /* */ /* MSIX_ENTRY$K_ADDRESS - offset of the MSI-X Address field in the MSI-X */ /* Table Entry */ /* msix_entry$q_address - quadword displacement to next field in Table Entry */ /* */ /* */ /* MSIX_ENTRY$K_DATA - offset of the MSI-X Data field in the MSI-X Table */ /* Entry. */ /* msix_entry$l_data - longword displacement to next field in Table Entry */ /* */ /* */ /* MSIX_ENTRY$K_CONTROL - offset of the MSI-X Control field in the MSI-X */ /* Table Entry. */ /* msix_entry$r_control - displacement of the MSI-X Control field formatted */ /* as MSIX_ENTRY_CONTROL (see above). */ /* */ #define MSIX_ENTRY$K_ADDRESS 0 #define MSIX_ENTRY$K_DATA 8 #define MSIX_ENTRY$K_CONTROL 12 #define MSIX_ENTRY$K_LENGTH 16 #define MSIX_ENTRY$K_SIZE 16 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _msix_entry { #pragma __nomember_alignment unsigned __int64 msix_entry$q_address; unsigned int msix_entry$l_data; MSIX_ENTRY_CONTROL msix_entry$r_control; } MSIX_ENTRY; /* */ /* */ /* ================================================================== */ /* MSI and MSI-X Abstracted Data Structures for System Use */ /* ================================================================== */ /* */ /* These abstracted data areas are used to store the information */ /* obtained from the PCI Config Header MSI and MSI-X capability */ /* blocks, making it unnecessary to spin any more PCI config access */ /* cycles to obtain it again. For drivers, this information will */ /* be made available through ioc$node_data() calls. */ /* */ /*------------------------------------------------------------------- */ /* MSI Abstracted Data Area */ /*------------------------------------------------------------------- */ /* */ /* msi$r_address - Target Physical Address for the MSI Message */ /* formatted as MSIADDR64 (see above). */ /* */ /* msi$r_message - Message sent to Target Address formatted as */ /* MSIMSG (see above). */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _msi { /* */ /* Target Physical Address */ /* */ #pragma __nomember_alignment MSIADDR64 msi$r_address; /* */ /* The Message */ /* */ MSIMSG msi$r_message; char msi$b_fill_4_ [4]; } MSI; /* */ /* */ /*-------------------------------------------------------------------- */ /* MSIX Abstracted Data Area */ /*-------------------------------------------------------------------- */ /* */ /* The MSIX area, because it is a system level data area, is */ /* permanently, mapped and the IOHANDLEs for it are stored here. */ /* */ /* msix$q_table_iohandle - IO Handle for access to the MSIX */ /* Vector Table. */ /* */ /* msix$q_pba_iohandle - IO Handle for access to the Pending */ /* Bit Array. */ /* */ /* msix$w_entry_count - number of entries in the Vector Table */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _msix { /* */ /* IOHANDLE of the MSI-X Vector Table */ /* */ #pragma __nomember_alignment unsigned __int64 msix$q_table_iohandle; /* */ /* IOHANDLE of the Pending Bit Array */ /* */ unsigned __int64 msix$q_pba_iohandle; unsigned short int msix$w_entry_count; char msix$b_fill_5_ [6]; } MSIX; /* */ /* */ /*-------------------------------------------------------------------- */ /* MSIDATA Abstracted MSI Union */ /*-------------------------------------------------------------------- */ /* */ /* msidata$r_msi - space required for MSI data block format */ /* msidata$r_msix - space required for MSI-X data block format */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef union _msidata { #pragma __nomember_alignment MSI msidata$r_msi; MSIX msidata$r_msix; } MSIDATA; /* */ /* */ /*-------------------------------------------------------------------- */ /* MSIABS Abstracted MSI Data Block */ /*-------------------------------------------------------------------- */ /* */ /* This structure abstracts the fields of the MSI or MSI-X Capabilty. */ /* Only one of these capabilities will be enabled. OpenVMS will enable */ /* the MSI-X capability of a device if it supports both MSI and MSI-X. */ /* */ /* The salient information about the MSI or MSI-X capability is */ /* stored and updated in this structure for the system-level interface */ /* to driver code provided by ioc$node_data() and ioc$node_function */ /* routines. */ /* */ /* msiabs$l_cfg_offset - Offset into the device's PCI Config space */ /* of its MSI or MSI-X Capabilitly Block. */ /* */ /* msiabs$w_control - Copy of the most recent write to the control */ /* register of the MSI or MSI-X capability. */ /* */ /* msiabs$w_type - contains one of: */ /* IOC$K_INTDEL_IOSAPIC - not MSI or MSI-X capable */ /* IOC$K_INTDEL_MSI - MSI enabled */ /* IOC$K_INTDEL_MSIX - MSI-X enabled */ /* The contents of this field tell the user how */ /* to format the data areas of this structure, */ /* whetehr for MSI or MSI-X. */ /* */ /* msiabs$r_data - MSI or MSI-X specific data area formatted */ /* according to the contents of msiabs$w_type */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _msiabs { #pragma __nomember_alignment unsigned int msiabs$l_cfg_offset; /* PCI Config Offset of MSI Cap Block */ unsigned short int msiabs$w_control; /* Copy of the MSI* Control Register */ /* */ /* The msiabs$w_type field indicates how to format the msiabs$r_data */ /* field, in C terms, whether to cast it as MSI or MSIX. */ /* */ unsigned short int msiabs$w_type; MSIDATA msiabs$r_data; } MSIABS; #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __PCIDEF_LOADED */