/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:08 by OpenVMS SDL EV3-3 */ /* Source: 11-MAY-1993 15:50:20 $1$DGA7274:[LIB_H.SRC]KFE52DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $KFE52DEF ***/ #ifndef __KFE52DEF_LOADED #define __KFE52DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* CIRRUS CIO module related definitions */ /* */ #define KFE52RAM$M_REV 0x7FF #define KFE52RAM$M_SERIALNO 0x3FF800 #define KFE52RAM$M_MODULEID 0x3C00000 #define KFE52RAM$S_RAMDEF 8 /* Old size name - synonym */ typedef struct _cirram { __union { /* Module data */ unsigned int kfe52ram$l_moddata; /* */ __struct { /* */ unsigned kfe52ram$v_rev : 11; /* Module revision filed */ unsigned kfe52ram$v_serialno : 11; /* Module serial number */ unsigned kfe52ram$v_moduleid : 4; /* Module id type */ unsigned kfe52ram$v_fill_0_ : 6; } kfe52ram$r_moddate_bits; } kfe52ram$r_moddate_overlay; unsigned int kfe52ram$l_modstatus; /* Module status */ } CIRRAM; #if !defined(__VAXC) #define kfe52ram$l_moddata kfe52ram$r_moddate_overlay.kfe52ram$l_moddata #define kfe52ram$v_rev kfe52ram$r_moddate_overlay.kfe52ram$r_moddate_bits.kfe52ram$v_rev #define kfe52ram$v_serialno kfe52ram$r_moddate_overlay.kfe52ram$r_moddate_bits.kfe52ram$v_serialno #define kfe52ram$v_moduleid kfe52ram$r_moddate_overlay.kfe52ram$r_moddate_bits.kfe52ram$v_moduleid #endif /* #if !defined(__VAXC) */ #define KFE52RAM$K_MOD_GOOD 179 /* Good module status */ #define KFE52RAM$K_MOD_BAD 76 /* Bad module status */ #define KFE52RAM$L_TRDB 13312 /* Trace RAM data block */ /* SLIM offsets and definitions */ #define SLI520$M_TCA 0x7C #define SLI520$M_TESTPTRS 0x80 #define SLI520$M_DIAGMODE 0x100 #define SLI520$M_DMASEL 0x400 #define SLI520$M_DISARB 0x800 #define SLI520$S_SLIMDEF 4 /* Old size name - synonym */ typedef struct _cirslim { __union { unsigned int sli520$l_icsr0; /* II32 Control register */ __struct { unsigned sli520$v_fill_3 : 2; unsigned sli520$v_tca : 5; /* Trace RAM number */ unsigned sli520$v_testptrs : 1; /* Test pointers */ unsigned sli520$v_diagmode : 1; /* Diagnostic mode */ unsigned sli520$v_fill_2 : 1; unsigned sli520$v_dmasel : 1; /* DMA select */ unsigned sli520$v_disarb : 1; /* Disable arbitration */ unsigned sli520$v_fill_1_ : 4; } sli520$r_icsr0_bits; } sli520$r_icsr0_overlay; } CIRSLIM; #if !defined(__VAXC) #define sli520$l_icsr0 sli520$r_icsr0_overlay.sli520$l_icsr0 #define sli520$v_tca sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_tca #define sli520$v_testptrs sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_testptrs #define sli520$v_diagmode sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_diagmode #define sli520$v_dmasel sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_dmasel #define sli520$v_disarb sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_disarb #endif /* #if !defined(__VAXC) */ /* FIREWALL offsets */ #define FIR520$S_FIRDEF 48 /* Old size name - synonym */ typedef struct _cirfir { unsigned int fir520$l_intvec0; /* SWIFT */ unsigned int fir520$l_intvec1; /* LANCE */ unsigned int fir520$l_intvec2; /* Not used */ unsigned int fir520$l_intvec3; /* PCM */ unsigned int fir520$l_uccrvec; /* UCCR (read only) */ unsigned int fir520$l_dccrvec; /* DCCR (read only) */ unsigned int fir520$l_fill_1; unsigned int fir520$l_winvec; /* Vector that has won interrupt arbitration */ unsigned int fir520$l_ipl; /* IPL settings for INTVEC0 - INTVEC3 (Interrupt Level) */ unsigned int fir520$l_imr; /* Interrupt Mask Register */ unsigned int fir520$l_ics; /* Interrupt Control/Status register. */ unsigned int fir520$l_pcmvec; /* PCM */ } CIRFIR; /* SCB offsets per section of the second page of the SCB. The second page */ /* of the SCB is divided into 16 sections each of which correspond to */ /* a slot (TR) number. */ #define KA520SCB$S_CIRCSCBDEF 20 /* Old size name - synonym */ typedef struct _cirscb { unsigned int ka520scb$l_coni; /* Console input */ unsigned int ka520scb$l_cono; /* Console output */ unsigned int ka520scb$l_lance; /* LANCE */ unsigned int ka520scb$l_swift; /* SWIFT */ unsigned int ka520scb$l_pcm; /* PCM */ } CIRSCB; /* The physical byte offsets of various register from the beginning of a CIO */ /* module. */ #define KFE52$K_COMM_RAM 0 /* COMM RAM */ #define KFE52$K_COMM_SIZE 65536 /* COMM RAM size */ #define KFE52$K_SL_RAM 65536 /* SWIFT/LANCE RAM */ #define KFE52$K_SL_SIZE 196608 /* SWIFT/LANCE RAM size */ #define KFE52$K_LANCE_RAM 65536 /* LANCE RAM */ #define KFE52$K_LANCE_SIZE 65536 /* LANCE RAM size */ #define KFE52$K_SWIFT_RAM 131072 /* SWIFT RAM */ #define KFE52$K_SWIFT_SIZE 131072 /* SWIFT RAM size */ #define KFE52$K_ETH_ADR_ROM 9043968 /* Ethernet address ROM */ #define KFE52$K_SSC_CSR 9699328 /* SSC CSR and RAM */ #define KFE52$K_SSC_TOY_CLOCK 9699436 /* SSC TOY clock */ #define KFE52$K_FIREWALL 10485760 /* Firewall registers */ #define KFE52$K_DMA_BCNT 10489856 /* DMA byte count */ #define KFE52$K_DMA_STL 10489860 /* DMA sub transfer length */ #define KFE52$K_DMA_STS 10489864 /* DMA status */ #define KFE52$K_PCM_CSR 10498048 /* PCM CSR */ #define KFE52$K_FW_CSR 10502144 /* Firewall CSR */ #define KFE52$K_CONS_CSR 10510336 /* Console registers */ #define KFE52$K_SLIM_CSR 12582912 /* SLIM CSR */ #define KFE52$K_SWIFT_CSR 12582976 /* SWIFT CSR */ #define KFE52$K_LANCE_CSR 12583040 /* LANCE CSR */ /* CONSOLE REGISTER offsets and definitions */ #define CON520$M_UTYP 0x100 #define CON520$M_UID 0xE00 #define CON520$M_UBRK 0x1000 #define CON520$M_UEIE 0x2000 #define CON520$M_UFIE 0x4000 #define CON520$M_UBSY 0x8000 #define CON520$M_DTYP 0x100 #define CON520$M_DID 0xE00 #define CON520$M_DEIE 0x2000 #define CON520$M_DFIE 0x4000 #define CON520$M_DBSY 0x8000 #define CON520$S_CONDEF 8 /* Old size name - synonym */ typedef struct _circon { __union { unsigned int con520$l_uccr; /* UPWARD Console Communication Register */ __struct { unsigned con520$v_udata : 8; /* Data */ unsigned con520$v_utyp : 1; /* Type */ unsigned con520$v_uid : 3; /* ID */ unsigned con520$v_ubrk : 1; /* CIO module Broken */ unsigned con520$v_ueie : 1; /* Empty Interrupt enable */ unsigned con520$v_ufie : 1; /* Full Interrupt enable */ unsigned con520$v_ubsy : 1; /* Busy */ } con520$r_uccr_bits; } con520$r_uccr_overlay; __union { unsigned int con520$l_dccr; /* DOWNWARD Console Communication Register */ __struct { unsigned con520$v_ddata : 8; /* Data */ unsigned con520$v_dtyp : 1; /* Type */ unsigned con520$v_did : 3; /* ID */ unsigned con520$v_dfill : 1; /* MBZ */ unsigned con520$v_deie : 1; /* Empty interrupt enable */ unsigned con520$v_dfie : 1; /* Full Interrupt enable */ unsigned con520$v_dbsy : 1; /* Busy */ } con520$r_dccr_bits; } con520$r_dccr_overlay; } CIRCON; #if !defined(__VAXC) #define con520$l_uccr con520$r_uccr_overlay.con520$l_uccr #define con520$v_udata con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_udata #define con520$v_utyp con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_utyp #define con520$v_uid con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_uid #define con520$v_ubrk con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ubrk #define con520$v_ueie con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ueie #define con520$v_ufie con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ufie #define con520$v_ubsy con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ubsy #define con520$l_dccr con520$r_dccr_overlay.con520$l_dccr #define con520$v_ddata con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_ddata #define con520$v_dtyp con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_dtyp #define con520$v_did con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_did #define con520$v_deie con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_deie #define con520$v_dfie con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_dfie #define con520$v_dbsy con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_dbsy #endif /* #if !defined(__VAXC) */ #define FWCSR520$M_TRACE_READ 0x1 #define FWCSR520$M_CPU_WRITE 0x2 #define FWCSR520$M_CPU_READ 0x4 #define FWCSR520$M_CPU_XCHK_ENA 0x8 #define FWCSR520$M_FW_LOCK 0x10 #define FWCSR520$M_II32_DRV 0x20 #define FWCSR520$M_DMR_ENA 0x40 #define FWCSR520$M_DIAG_MODE 0x80 #define FWCSR520$M_IO_XCHK_ERR 0x100 #define FWCSR520$M_DIAG_XCHK 0x200 #define FWCSR520$M_IO_XCHK_ENA 0x400 #define FWCSR520$M_MBZ 0x800 #define FWCSR520$M_RAIL_ID 0x1000 #define FWCSR520$M_SLOT_ID 0xE000 #define FWCSR520$S_FWCSRDEF 4 /* Old size name - synonym */ typedef struct _cirfwcsr { __union { unsigned int fwcsr520$l_fwcsr; /* Firewall Control register */ __struct { unsigned fwcsr520$v_trace_read : 1; /* Read Trace RAMs */ unsigned fwcsr520$v_cpu_write : 1; /* CVAX write downward console */ unsigned fwcsr520$v_cpu_read : 1; /* CVAX read upward console */ unsigned fwcsr520$v_cpu_xchk_ena : 1; /* CVAX crosscheck enable */ unsigned fwcsr520$v_fw_lock : 1; /* Firewall lock */ unsigned fwcsr520$v_ii32_drv : 1; /* 1132(T) drive */ unsigned fwcsr520$v_dmr_ena : 1; /* DMR enable */ unsigned fwcsr520$v_diag_mode : 1; /* Diagnostic mode */ unsigned fwcsr520$v_io_xchk_err : 1; /* UVAX crosscheck error */ unsigned fwcsr520$v_diag_xchk : 1; /* Diagnostic crosscheck bit */ unsigned fwcsr520$v_io_xchk_ena : 1; /* UVAX crosscheck enable */ unsigned fwcsr520$v_mbz : 1; /* Must be zero */ unsigned fwcsr520$v_rail_id : 1; /* Rail ID */ unsigned fwcsr520$v_slot_id : 3; /* Slot ID */ unsigned fwcsr520$v_unused : 16; /* Unused */ } fwcsr520$r_fwcsr_bits; } fwcsr520$r_fwcsr_overlay; } CIRFWCSR; #if !defined(__VAXC) #define fwcsr520$l_fwcsr fwcsr520$r_fwcsr_overlay.fwcsr520$l_fwcsr #define fwcsr520$v_trace_read fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_trace_read #define fwcsr520$v_cpu_write fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_cpu_write #define fwcsr520$v_cpu_read fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_cpu_read #define fwcsr520$v_cpu_xchk_ena fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_cpu_xchk_ena #define fwcsr520$v_fw_lock fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_fw_lock #define fwcsr520$v_ii32_drv fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_ii32_drv #define fwcsr520$v_dmr_ena fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_dmr_ena #define fwcsr520$v_diag_mode fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_diag_mode #define fwcsr520$v_io_xchk_err fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_io_xchk_err #define fwcsr520$v_diag_xchk fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_diag_xchk #define fwcsr520$v_io_xchk_ena fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_io_xchk_ena #define fwcsr520$v_mbz fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_mbz #define fwcsr520$v_rail_id fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_rail_id #define fwcsr520$v_slot_id fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_slot_id #define fwcsr520$v_unused fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_unused #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __KFE52DEF_LOADED */