/******************************************************************************* * * * Copyright Digital Equipment Corporation 1995, 1996 All rights reserved. * * * * Restricted Rights: Use, duplication, or disclosure by the U.S. Government * * is subject to restrictions as set forth * * in subparagraph (c) (1) (ii) of * * DFARS 252.227-7013, or in FAR 52.227-19, or in FAR 52.227-14 Alt. III, as * * applicable. * * * * This software is proprietary to and embodies the confidential technology of * * Digital Equipment Corporation. Possession, use, or copying of this software * * and media is authorized only pursuant to a valid written license from * * Digital or an authorized sublicensor. * * * *******************************************************************************/ /*++ * FACILITY: CPU1605 * * ABSTRACT: * * This module contains structure definitions for the different types of * rawhide addresses and for the individual bits in the MC-PCI bridge CSRs. * This .h file is not generated by SDL. The structures here are not * defined with SDL in order to keep their field names simple (i.e. in * order to have the same field name in multiple structures). * * AUTHORS: * * Walter D. Arbo CREATION DATE: 23-May-1995 * * REVISION HISTORY: * * X-2 WDA W.D. Arbo 05-Feb-1996 * Add bits for I2C bus to RH_INT_MASK * X-1 WDA W.D. Arbo 23-May-1995 * Initial version. *-- */ #include #pragma __member_alignment save #pragma __nomember_alignment quadword /* * Rawhide Sparse Memory Space CPU Address * * 63 40 39 38-36 35-33 32 31 7 6 5 4-3 2-0 * +------------+---+-----+-----+---+----------------+--------+-----+---+ * | 0 | 1 | GID | MID | 0 | address info. | offset | len | 0 | * +------------+---+-----+-----+---+----------------+--------+-----+---+ */ typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned addr : 27; unsigned type : 1; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits; } RH_SPARSE_MEM_ADDR; #define RH_SPARSE_MEM_ADDR_T 0 /* * Rawhide Dense Memory Space CPU Address * * 63 40 39 38-36 35-33 32-31 30 0 * +------------+---+-----+-----+-----+-------------------------------+ * | 0 | 1 | GID | MID | 10 | address info. | * +------------+---+-----+-----+-----+-------------------------------+ */ typedef union { uint64 q; struct { unsigned addr : 31; unsigned type : 2; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits; } RH_DENSE_MEM_ADDR; #define RH_DENSE_MEM_ADDR_T 2 /* * Rawhide Sparse I/O Space CPU Address * * 63 40 39 38-36 35-33 32-30 29 7 6 5 4-3 2-0 * +------------+---+-----+-----+-----+----------------+--------+-----+---+ * | 0 | 1 | GID | MID | 110 | address info. | offset | len | 0 | * +------------+---+-----+-----+-----+----------------+--------+-----+---+ */ typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned addr : 25; unsigned type : 3; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits; } RH_SPARSE_IO_ADDR; #define RH_SPARSE_IO_ADDR_T 6 /* * Rawhide Sparse Config Space CPU Address (Sparse Space) * * 63 40 39 38-36 35-33 32 29 28 21 20 16 15 13 12 7 6 5 4-3 2-0 * +------------+---+-----+-----+-------+-------+---------+------+-------+--------+-----+---+ * | 0 | 1 | GID | MID | 1110 | bus | device | func | reg | offset | len | 0 | * +------------+---+-----+-----+-------+-------+---------+------+-------+--------+-----+---+ */ typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned offset : 2; unsigned reg : 6; unsigned func : 3; unsigned device : 5; unsigned bus : 8; unsigned type : 4; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits; } RH_PCI_CONFIG_ADDR; #define RH_PCI_CONFIG_ADDR_T 0x0E /* * Rawhide PCI CSR Space CPU Address Format (Pseudo-Sparse space) * * 63 40 39 38-36 35-33 32 28 27 7 6 5 4-3 2-0 * +------------+---+-----+-----+-------+----------------+--------+-----+---+ * | 0 | 1 | GID | MID | 11110 | address info. | offset | len | 0 | * +------------+---+-----+-----+-------+----------------+--------+-----+---+ */ typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned addr : 23; unsigned type : 5; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits; } RH_PCI_CSR_ADDR; #define RH_PCI_CSR_ADDR_T 0x01E /* Definitions for bits in the bridge CSRs. */ #pragma __nomember_alignment longword typedef union { uint32 l; struct { unsigned int0_mid : 3; unsigned int0_gid : 3; unsigned int1_mid : 3; unsigned int1_gid : 3; unsigned mbz : 20; } bits0; struct { unsigned int0_targ_dev_id : 6; unsigned int1_targ_dev_id : 6; unsigned mbz : 20; } bits1; } RH_INT_TARG; typedef union { uint32 l; struct { unsigned mbz_2 : 2; unsigned pci_offset : 4; unsigned mbz : 6; unsigned int_adr_lo : 20; } bits; } RH_INT_ADR; typedef union { uint32 l; struct { unsigned int_adr_ext : 7; unsigned mbz : 25; } bits; } RH_INT_ADR_EXT; typedef union { uint32 l; struct { unsigned intr : 16; unsigned eisa_intr : 1; unsigned i2c_ctrl : 1; unsigned i2c : 1; unsigned mbz : 2; unsigned eisa_nmi : 1; unsigned soft_error : 1; unsigned hard_error : 1; unsigned mbzz : 8; } bits; } RH_INT_MASK; typedef union { uint32 l; struct { unsigned cap_rev : 4; unsigned horse_rev : 4; unsigned saddle_rev : 4; unsigned saddle_type : 3; unsigned eisa_present : 1; unsigned pci_cc : 16; } bits; } RH_PCI_REV; typedef union { uint32 l; struct { unsigned mid : 3; unsigned gid : 3; unsigned cpu : 8; unsigned mbz : 18; } bits; } RH_WHOAMI; typedef union { uint32 l; struct { unsigned enable : 1; unsigned scatter_gather : 1; unsigned mbz : 18; unsigned base : 12; } bits; } RH_W_BASE; typedef union { uint32 l; struct { unsigned mbz : 20; unsigned mask : 12; } bits; } RH_W_MASK; typedef union { uint32 l; struct { unsigned mbz : 2; unsigned base : 30; } bits; } RH_T_BASE; typedef union { uint32 l; struct { unsigned h_bound : 9; unsigned mbz_0 : 4; unsigned pc_he1 : 1; unsigned pc_he2 : 1; unsigned h_base : 9; unsigned mbz_1 : 8; } bits; } RH_HBASE; #pragma __member_alignment restore