/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:07 by OpenVMS SDL EV3-3 */ /* Source: 07-MAR-1997 16:36:13 $1$DGA7274:[LIB_H.SRC]KA0F05DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $KA0F05DEF IDENT X-5 ***/ #ifndef __KA0F05DEF_LOADED #define __KA0F05DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* GRU space */ /* */ #define GRU$M_INT_CLR 0x1 #define GRU$M_CNFG_CLK_DIV 0xF0 #define GRU$M_CNFG_CACHE_SP 0x1800 #define GRU$M_CNFG_CACHE_SZ 0xE000 #define GRU$M_CNFG_MMB0_CFG 0xF0000 #define GRU$M_CNFG_MMB1_CFG 0xF000000 #define GRU$M_CNFG_SS7_MMB0 0x3 #define GRU$M_CNFG_SS6_MMB0 0xC #define GRU$M_CNFG_SS5_MMB0 0x30 #define GRU$M_CNFG_SS4_MMB0 0xC0 #define GRU$M_CNFG_SS3_MMB0 0x300 #define GRU$M_CNFG_SS2_MMB0 0xC00 #define GRU$M_CNFG_SS1_MMB0 0x3000 #define GRU$M_CNFG_SS0_MMB0 0xC000 #define GRU$M_CNFG_SS7_MMB1 0x30000 #define GRU$M_CNFG_SS6_MMB1 0xC0000 #define GRU$M_CNFG_SS5_MMB1 0x300000 #define GRU$M_CNFG_SS4_MMB1 0xC00000 #define GRU$M_CNFG_SS3_MMB1 0x3000000 #define GRU$M_CNFG_SS2_MMB1 0xC000000 #define GRU$M_CNFG_SS1_MMB1 0x30000000 #define GRU$M_CNFG_SS0_MMB1 0xC0000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _gru { /* */ /* The following element is the displacement in the virtual io table from */ /* the cia structure to the gru structure (see map_local_io_0f05() in */ /* io_support_0f05.c). */ /* */ #pragma __nomember_alignment unsigned char gru$b_displacement [57344]; /* */ /* GRU Interrupt request register - 0x8780000000 */ /* */ __union { int gru$l_int_req; unsigned char int_req$b_displacement [64]; } gru$r_int_req_overlay; /* */ /* GRU Interrupt mask register - 0x8780000040 */ /* */ __union { int gru$l_int_mask; unsigned char int_mask$b_displacement [64]; } gru$r_int_mask_overlay; /* */ /* GRU Interrupt Level/edge select register - 0x8780000080 */ /* */ __union { int gru$l_int_edge; unsigned char int_edge$b_displacement [64]; } gru$r_int_edge_overlay; /* */ /* GRU Interrupt High/Low select register - 0x87800000C0 */ /* */ __union { int gru$l_int_hilo; unsigned char int_hilo$b_displacement [64]; } gru$r_int_hilo_overlay; /* */ /* GRU Interrupt clear register - 0x8780000100 */ /* */ __union { int gru$l_int_clear; __struct { unsigned gru$v_int_clr : 1; /* */ unsigned gru$v_iclr_fill : 31; } gru$r_int_clear_bits; unsigned char int_clr$b_displacement [256]; } gru$r_int_clr_overlay; /* */ /* GRU Cache and Memory Config register - 0x8780000200 */ /* */ __union { int gru$l_cache_config; __struct { unsigned gru$v_cc_fill : 4; /* */ unsigned gru$v_cnfg_clk_div : 4; /* */ unsigned gru$v_cc_fill1 : 3; /* */ unsigned gru$v_cnfg_cache_sp : 2; /* */ unsigned gru$v_cnfg_cache_sz : 3; /* */ unsigned gru$v_cnfg_mmb0_cfg : 4; /* */ unsigned gru$v_cc_fill2 : 4; /* */ unsigned gru$v_cnfg_mmb1_cfg : 4; /* */ unsigned gru$v_cc_fill3 : 4; } gru$r_cache_config_bits; unsigned char cache_cnfg$b_displacement [256]; } gru$r_cache_cnfg_overlay; /* */ /* GRU SET Memory Config register - 0x8780000300 */ /* */ __union { int gru$l_set_config; __struct { unsigned gru$v_cnfg_ss7_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss6_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss5_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss4_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss3_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss2_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss1_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss0_mmb0 : 2; /* */ unsigned gru$v_cnfg_ss7_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss6_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss5_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss4_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss3_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss2_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss1_mmb1 : 2; /* */ unsigned gru$v_cnfg_ss0_mmb1 : 2; /* */ } gru$r_set_config_bits; unsigned char set_cnfg$b_displacement [1280]; } gru$r_set_cnfg_overlay; /* */ /* GRU LED register - 0x8780000800 */ /* */ __union { int gru$l_led; unsigned char led$b_displacement [256]; } gru$r_led_overlay; /* */ /* GRU RESET register - 0x8780000900 */ /* */ __union { int gru$l_reset; unsigned char reset$b_displacement [256]; } gru$r_reset_overlay; } GRU; #if !defined(__VAXC) #define gru$l_int_req gru$r_int_req_overlay.gru$l_int_req #define gru$l_int_mask gru$r_int_mask_overlay.gru$l_int_mask #define gru$l_int_edge gru$r_int_edge_overlay.gru$l_int_edge #define gru$l_int_hilo gru$r_int_hilo_overlay.gru$l_int_hilo #define gru$l_int_clear gru$r_int_clr_overlay.gru$l_int_clear #define gru$v_int_clr gru$r_int_clr_overlay.gru$r_int_clear_bits.gru$v_int_clr #define gru$v_iclr_fill gru$r_int_clr_overlay.gru$r_int_clear_bits.gru$v_iclr_fill #define gru$l_cache_config gru$r_cache_cnfg_overlay.gru$l_cache_config #define gru$v_cnfg_clk_div gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_clk_div #define gru$v_cnfg_cache_sp gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_cache_sp #define gru$v_cnfg_cache_sz gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_cache_sz #define gru$v_cnfg_mmb0_cfg gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_mmb0_cfg #define gru$v_cnfg_mmb1_cfg gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_mmb1_cfg #define gru$l_set_config gru$r_set_cnfg_overlay.gru$l_set_config #define gru$v_cnfg_ss7_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss7_mmb0 #define gru$v_cnfg_ss6_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss6_mmb0 #define gru$v_cnfg_ss5_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss5_mmb0 #define gru$v_cnfg_ss4_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss4_mmb0 #define gru$v_cnfg_ss3_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss3_mmb0 #define gru$v_cnfg_ss2_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss2_mmb0 #define gru$v_cnfg_ss1_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss1_mmb0 #define gru$v_cnfg_ss0_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss0_mmb0 #define gru$v_cnfg_ss7_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss7_mmb1 #define gru$v_cnfg_ss6_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss6_mmb1 #define gru$v_cnfg_ss5_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss5_mmb1 #define gru$v_cnfg_ss4_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss4_mmb1 #define gru$v_cnfg_ss3_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss3_mmb1 #define gru$v_cnfg_ss2_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss2_mmb1 #define gru$v_cnfg_ss1_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss1_mmb1 #define gru$v_cnfg_ss0_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss0_mmb1 #define gru$l_led gru$r_led_overlay.gru$l_led #define gru$l_reset gru$r_reset_overlay.gru$l_reset #endif /* #if !defined(__VAXC) */ /* */ /* DS1287A register definitions */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0f05_ds1287a { #pragma __nomember_alignment unsigned char ka0f05_ds1287a$b_fill1 [3584]; unsigned int ka0f05_ds1287a$l_port_index; unsigned char ka0f05_ds1287a$b_fill2 [28]; unsigned int ka0f05_ds1287a$l_port_data; char ka0f05_ds1287a$b_fill_0_ [4]; } KA0F05_DS1287A; #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __KA0F05DEF_LOADED */