/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:06 by OpenVMS SDL EV3-3 */ /* Source: 21-JAN-1994 16:46:22 $1$DGA7274:[LIB_H.SRC]KA0E04DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $KA0E04DEF ***/ #ifndef __KA0E04DEF_LOADED #define __KA0E04DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define KA0E04$M_IOC_PCI_CFG_CYC 0x3 #define KA0E04$M_IOC_CERR 0x10 #define KA0E04$M_IOC_CLOST 0x20 #define KA0E04$M_IOC_PCI_SOFT_RST 0x40 #define KA0E04$M_IOC_TLB_EN 0x80 #define KA0E04$M_IOC_HAE 0xF8000000 #define KA0E04$M_STAT0_CMD 0xF #define KA0E04$M_STAT0_ERR 0x10 #define KA0E04$M_STAT0_LOST 0x20 #define KA0E04$M_STAT0_T_HIT 0x40 #define KA0E04$M_STAT0_T_REF 0x80 #define KA0E04$M_STAT0_CODE 0x700 #define KA0E04$M_STAT0_P_NBR 0xFFFFE000 #define KA0E04$M_WBASE0_WBASE 0xFFF00000 #define KA0E04$M_WBASE0_SG 0x100000000 #define KA0E04$M_WBASE0_WEN 0x200000000 #define KA0E04$M_WBASE1_WBASE 0xFFF00000 #define KA0E04$M_WBASE1_SG 0x100000000 #define KA0E04$M_WBASE1_WEN 0x200000000 #define KA0E04$M_WMASK0_WMASK 0xFFF00000 #define KA0E04$M_WMASK1_WMASK 0xFFF00000 #define KA0E04$M_TBASE0_TBASE 0xFFF00000 #define KA0E04$M_TBASE1_TBASE 0xFFFFFC00 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0e04 { #pragma __nomember_alignment __union { unsigned __int64 ka0e04$q_ioc; __struct { unsigned ka0e04$v_ioc_pci_cfg_cyc : 2; unsigned ka0e04$v_ioc_fill2 : 2; unsigned ka0e04$v_ioc_cerr : 1; unsigned ka0e04$v_ioc_clost : 1; unsigned ka0e04$v_ioc_pci_soft_rst : 1; unsigned ka0e04$v_ioc_tlb_en : 1; unsigned ka0e04$v_ioc_fill3 : 19; unsigned ka0e04$v_ioc_hae : 5; unsigned ka0e04$v_ioc_fill4 : 32; } ka0e04$r_ioc_bits; } ka0e04$r_ioc_u; char ka0e04$b_fill1 [56]; /* this should pad from PA 180000008 to 180000040 */ __union { unsigned __int64 ka0e04$q_ioc_stat0; __struct { unsigned ka0e04$v_stat0_cmd : 4; unsigned ka0e04$v_stat0_err : 1; unsigned ka0e04$v_stat0_lost : 1; unsigned ka0e04$v_stat0_t_hit : 1; unsigned ka0e04$v_stat0_t_ref : 1; unsigned ka0e04$v_stat0_code : 3; unsigned ka0e04$v_stat0_fill : 2; unsigned ka0e04$v_stat0_p_nbr : 19; unsigned ka0e04$v_stat0_fill1 : 32; } ka0e04$r_ioc_stat0_bits; } ka0e04$r_ioc_stat0; char ka0e04$b_fill2 [24]; /* pad from PA 1.8000.0048 to 1.8000.0060 */ __union { unsigned __int64 ka0e04$q_ioc_stat1; } ka0e04$r_ioc_stat1; char ka0e04$b_fill3 [24]; /* pad from PA 1.8000.0068 to 1.8000.0080 */ __union { unsigned __int64 ka0e04$q_ioc_tbia; } ka0e04$r_ioc_tbia; char ka0e04$b_fill4 [120]; /* pad from PA 1.8000.0088 to 1.8000.0100 */ __union { unsigned __int64 ka0e04$q_ioc_wbase0; __struct { unsigned ka0e04$v_wbase0_fill : 20; unsigned ka0e04$v_wbase0_wbase : 12; unsigned ka0e04$v_wbase0_sg : 1; unsigned ka0e04$v_wbase0_wen : 1; unsigned ka0e04$v_wbase0_fill1 : 30; } ka0e04$r_ioc_wbase0_bits; } ka0e04$r_ioc_wbase0; char ka0e04$b_fill5 [24]; /* pad from PA 1.8000.0108 to 1.8000.0120 */ __union { unsigned __int64 ka0e04$q_ioc_wbase1; __struct { unsigned ka0e04$v_wbase1_fill : 20; unsigned ka0e04$v_wbase1_wbase : 12; unsigned ka0e04$v_wbase1_sg : 1; unsigned ka0e04$v_wbase1_wen : 1; unsigned ka0e04$v_wbase1_fill2 : 30; } ka0e04$r_ioc_wbase1_bits; } ka0e04$r_ioc_wbase1; char ka0e04$b_fill6 [24]; /* pad from PA 1.8000.0128 to 1.8000.0140 */ __union { unsigned __int64 ka0e04$q_ioc_wmask0; __struct { unsigned ka0e04$v_wmask0_fill : 20; unsigned ka0e04$v_wmask0_wmask : 12; unsigned ka0e04$v_wmask0_fill1 : 32; } ka0e04$r_ioc_wmask0_bits; } ka0e04$r_ioc_wmask0; char ka0e04$b_fill7 [24]; /* pad from PA 1.8000.0148 to 1.8000.0160 */ __union { unsigned __int64 ka0e04$q_ioc_wmask1; __struct { unsigned ka0e04$v_wmask1_fill : 20; unsigned ka0e04$v_wmask1_wmask : 12; unsigned ka0e04$v_wmask1_fill1 : 32; } ka0e04$r_ioc_wmask1_bits; } ka0e04$r_ioc_wmask1; char ka0e04$b_fill8 [24]; /* pad from PA 1.8000.0168 to 1.8000.0180 */ __union { unsigned __int64 ka0e04$q_ioc_tbase0; __struct { unsigned ka0e04$v_tbase0_fill : 20; unsigned ka0e04$v_tbase0_tbase : 12; unsigned ka0e04$v_tbase0_fill1 : 32; } ka0e04$r_ioc_tbase0_bits; } ka0e04$r_ioc_tbase0; char ka0e04$b_fill9 [24]; /* pad from PA 1.8000.0188 to 1.8000.01A0 */ __union { unsigned __int64 ka0e04$q_ioc_tbase1; __struct { unsigned ka0e04$v_tbase1_fill : 10; unsigned ka0e04$v_tbase1_tbase : 22; unsigned ka0e04$v_tbase1_fill1 : 32; } ka0e04$r_ioc_tbase1_bits; } ka0e04$r_ioc_tbase1; } KA0E04; #if !defined(__VAXC) #define ka0e04$q_ioc ka0e04$r_ioc_u.ka0e04$q_ioc #define ka0e04$v_ioc_pci_cfg_cyc ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_pci_cfg_cyc #define ka0e04$v_ioc_cerr ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_cerr #define ka0e04$v_ioc_clost ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_clost #define ka0e04$v_ioc_pci_soft_rst ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_pci_soft_rst #define ka0e04$v_ioc_tlb_en ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_tlb_en #define ka0e04$v_ioc_hae ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_hae #define ka0e04$q_ioc_stat0 ka0e04$r_ioc_stat0.ka0e04$q_ioc_stat0 #define ka0e04$v_stat0_cmd ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_cmd #define ka0e04$v_stat0_err ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_err #define ka0e04$v_stat0_lost ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_lost #define ka0e04$v_stat0_t_hit ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_t_hit #define ka0e04$v_stat0_t_ref ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_t_ref #define ka0e04$v_stat0_code ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_code #define ka0e04$v_stat0_p_nbr ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_p_nbr #define ka0e04$q_ioc_stat1 ka0e04$r_ioc_stat1.ka0e04$q_ioc_stat1 #define ka0e04$q_ioc_tbia ka0e04$r_ioc_tbia.ka0e04$q_ioc_tbia #define ka0e04$q_ioc_wbase0 ka0e04$r_ioc_wbase0.ka0e04$q_ioc_wbase0 #define ka0e04$v_wbase0_wbase ka0e04$r_ioc_wbase0.ka0e04$r_ioc_wbase0_bits.ka0e04$v_wbase0_wbase #define ka0e04$v_wbase0_sg ka0e04$r_ioc_wbase0.ka0e04$r_ioc_wbase0_bits.ka0e04$v_wbase0_sg #define ka0e04$v_wbase0_wen ka0e04$r_ioc_wbase0.ka0e04$r_ioc_wbase0_bits.ka0e04$v_wbase0_wen #define ka0e04$q_ioc_wbase1 ka0e04$r_ioc_wbase1.ka0e04$q_ioc_wbase1 #define ka0e04$v_wbase1_wbase ka0e04$r_ioc_wbase1.ka0e04$r_ioc_wbase1_bits.ka0e04$v_wbase1_wbase #define ka0e04$v_wbase1_sg ka0e04$r_ioc_wbase1.ka0e04$r_ioc_wbase1_bits.ka0e04$v_wbase1_sg #define ka0e04$v_wbase1_wen ka0e04$r_ioc_wbase1.ka0e04$r_ioc_wbase1_bits.ka0e04$v_wbase1_wen #define ka0e04$q_ioc_wmask0 ka0e04$r_ioc_wmask0.ka0e04$q_ioc_wmask0 #define ka0e04$v_wmask0_wmask ka0e04$r_ioc_wmask0.ka0e04$r_ioc_wmask0_bits.ka0e04$v_wmask0_wmask #define ka0e04$q_ioc_wmask1 ka0e04$r_ioc_wmask1.ka0e04$q_ioc_wmask1 #define ka0e04$v_wmask1_wmask ka0e04$r_ioc_wmask1.ka0e04$r_ioc_wmask1_bits.ka0e04$v_wmask1_wmask #define ka0e04$q_ioc_tbase0 ka0e04$r_ioc_tbase0.ka0e04$q_ioc_tbase0 #define ka0e04$v_tbase0_tbase ka0e04$r_ioc_tbase0.ka0e04$r_ioc_tbase0_bits.ka0e04$v_tbase0_tbase #define ka0e04$q_ioc_tbase1 ka0e04$r_ioc_tbase1.ka0e04$q_ioc_tbase1 #define ka0e04$v_tbase1_tbase ka0e04$r_ioc_tbase1.ka0e04$r_ioc_tbase1_bits.ka0e04$v_tbase1_tbase #endif /* #if !defined(__VAXC) */ #define KA0E04$K_OPDRIVER_XMT_ISR 1 #define KA0E04$K_OPDRIVER_RCV_ISR 12 #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __KA0E04DEF_LOADED */