/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:06 by OpenVMS SDL EV3-3 */ /* Source: 20-JAN-1998 11:03:32 $1$DGA7274:[LIB_H.SRC]KA0C05DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $KA0C05DEF ***/ #ifndef __KA0C05DEF_LOADED #define __KA0C05DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define KA0C05_BSB$M_TLIPINT_MASK 0xFFFF #define KA0C05_BSB$M_TLIOINT4_MASK 0xFFFF #define KA0C05_BSB$M_TLIOINT4_IPL14 0x10000 #define KA0C05_BSB$M_TLIOINT4_IPL15 0x20000 #define KA0C05_BSB$M_TLIOINT4_IPL16 0x40000 #define KA0C05_BSB$M_TLIOINT4_IPL17 0x80000 #define KA0C05_BSB$M_TLIOINT5_MASK 0xFFFF #define KA0C05_BSB$M_TLIOINT5_IPL14 0x10000 #define KA0C05_BSB$M_TLIOINT5_IPL15 0x20000 #define KA0C05_BSB$M_TLIOINT5_IPL16 0x40000 #define KA0C05_BSB$M_TLIOINT5_IPL17 0x80000 #define KA0C05_BSB$M_TLIOINT6_MASK 0xFFFF #define KA0C05_BSB$M_TLIOINT6_IPL14 0x10000 #define KA0C05_BSB$M_TLIOINT6_IPL15 0x20000 #define KA0C05_BSB$M_TLIOINT6_IPL16 0x40000 #define KA0C05_BSB$M_TLIOINT6_IPL17 0x80000 #define KA0C05_BSB$M_TLIOINT7_MASK 0xFFFF #define KA0C05_BSB$M_TLIOINT7_IPL14 0x10000 #define KA0C05_BSB$M_TLIOINT7_IPL15 0x20000 #define KA0C05_BSB$M_TLIOINT7_IPL16 0x40000 #define KA0C05_BSB$M_TLIOINT7_IPL17 0x80000 #define KA0C05_BSB$M_TLIOINT8_MASK 0xFFFF #define KA0C05_BSB$M_TLIOINT8_IPL14 0x10000 #define KA0C05_BSB$M_TLIOINT8_IPL15 0x20000 #define KA0C05_BSB$M_TLIOINT8_IPL16 0x40000 #define KA0C05_BSB$M_TLIOINT8_IPL17 0x80000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_bsb { #pragma __nomember_alignment __union { unsigned int ka0c05_bsb$l_tlprivate; __struct { unsigned ka0c05_bsb$v_tlprivate_f1 : 32; } ka0c05_bsb$r_tlprivate_bits; } ka0c05_bsb$r_tlprivate_overlay; unsigned char ka0c05_bsb$b_f10 [60]; __union { unsigned int ka0c05_bsb$l_tlipint; __struct { unsigned ka0c05_bsb$v_tlipint_mask : 16; unsigned ka0c05_bsb$v_tlipint_f1 : 16; } ka0c05_bsb$r_tlipint_bits; } ka0c05_bsb$r_tlipint_overlay; unsigned char ka0c05_bsb$b_f20 [188]; __union { unsigned int ka0c05_bsb$l_tlioint4; __struct { unsigned ka0c05_bsb$v_tlioint4_mask : 16; unsigned ka0c05_bsb$v_tlioint4_ipl14 : 1; unsigned ka0c05_bsb$v_tlioint4_ipl15 : 1; unsigned ka0c05_bsb$v_tlioint4_ipl16 : 1; unsigned ka0c05_bsb$v_tlioint4_ipl17 : 1; unsigned ka0c05_bsb$v_tlioint4_f1 : 12; } ka0c05_bsb$r_tlioint4_bits; } ka0c05_bsb$r_tlioint4_overlay; unsigned char ka0c05_bsb$b_fill30 [60]; __union { unsigned int ka0c05_bsb$l_tlioint5; __struct { unsigned ka0c05_bsb$v_tlioint5_mask : 16; unsigned ka0c05_bsb$v_tlioint5_ipl14 : 1; unsigned ka0c05_bsb$v_tlioint5_ipl15 : 1; unsigned ka0c05_bsb$v_tlioint5_ipl16 : 1; unsigned ka0c05_bsb$v_tlioint5_ipl17 : 1; unsigned ka0c05_bsb$v_tlioint5_f1 : 12; } ka0c05_bsb$r_tlioint5_bits; } ka0c05_bsb$r_tlioint5_overlay; unsigned char ka0c05_bsb$b_fill40 [60]; __union { unsigned int ka0c05_bsb$l_tlioint6; __struct { unsigned ka0c05_bsb$v_tlioint6_mask : 16; unsigned ka0c05_bsb$v_tlioint6_ipl14 : 1; unsigned ka0c05_bsb$v_tlioint6_ipl15 : 1; unsigned ka0c05_bsb$v_tlioint6_ipl16 : 1; unsigned ka0c05_bsb$v_tlioint6_ipl17 : 1; unsigned ka0c05_bsb$v_tlioint6_f1 : 12; } ka0c05_bsb$r_tlioint6_bits; } ka0c05_bsb$r_tlioint6_overlay; unsigned char ka0c05_bsb$b_fill50 [60]; __union { unsigned int ka0c05_bsb$l_tlioint7; __struct { unsigned ka0c05_bsb$v_tlioint7_mask : 16; unsigned ka0c05_bsb$v_tlioint7_ipl14 : 1; unsigned ka0c05_bsb$v_tlioint7_ipl15 : 1; unsigned ka0c05_bsb$v_tlioint7_ipl16 : 1; unsigned ka0c05_bsb$v_tlioint7_ipl17 : 1; unsigned ka0c05_bsb$v_tlioint7_f1 : 12; } ka0c05_bsb$r_tlioint7_bits; } ka0c05_bsb$r_tlioint7_overlay; unsigned char ka0c05_bsb$b_fill60 [60]; __union { unsigned int ka0c05_bsb$l_tlioint8; __struct { unsigned ka0c05_bsb$v_tlioint8_mask : 16; unsigned ka0c05_bsb$v_tlioint8_ipl14 : 1; unsigned ka0c05_bsb$v_tlioint8_ipl15 : 1; unsigned ka0c05_bsb$v_tlioint8_ipl16 : 1; unsigned ka0c05_bsb$v_tlioint8_ipl17 : 1; unsigned ka0c05_bsb$v_tlioint8_f1 : 12; } ka0c05_bsb$r_tlioint8_bits; } ka0c05_bsb$r_tlioint8_overlay; unsigned char ka0c05_bsb$b_fill70 [508]; __union { unsigned int ka0c05_bsb$l_tlwsdqr4; __struct { unsigned ka0c05_bsb$v_tlwsdqr4_f1 : 32; } ka0c05_bsb$r_tlwsdqr4_bits; } ka0c05_bsb$r_tlwsdqr4_overlay; unsigned char ka0c05_bsb$b_fill80 [60]; __union { unsigned int ka0c05_bsb$l_tlwsdqr5; __struct { unsigned ka0c05_bsb$v_tlwsdqr5_f1 : 32; } ka0c05_bsb$r_tlwsdqr5_bits; } ka0c05_bsb$r_tlwsdqr5_overlay; unsigned char ka0c05_bsb$b_fill90 [60]; __union { unsigned int ka0c05_bsb$l_tlwsdqr6; __struct { unsigned ka0c05_bsb$v_tlwsdqr6_f1 : 32; } ka0c05_bsb$r_tlwsdqr6_bits; } ka0c05_bsb$r_tlwsdqr6_overlay; unsigned char ka0c05_bsb$b_f100 [60]; __union { unsigned int ka0c05_bsb$l_tlwsdqr7; __struct { unsigned ka0c05_bsb$v_tlwsdqr7_f1 : 32; } ka0c05_bsb$r_tlwsdqr7_bits; } ka0c05_bsb$r_tlwsdqr7_overlay; unsigned char ka0c05_bsb$b_f110 [60]; __union { unsigned int ka0c05_bsb$l_tlwsdqr8; __struct { unsigned ka0c05_bsb$v_tlwsdqr8_f1 : 32; } ka0c05_bsb$r_tlwsdqr8_bits; } ka0c05_bsb$r_tlwsdqr8_overlay; unsigned char ka0c05_bsb$b_f120 [252]; __union { unsigned int ka0c05_bsb$l_tlrmdqrx; __struct { unsigned ka0c05_bsb$v_tlrmdqrx_f1 : 32; } ka0c05_bsb$r_tlrmdqrx_bits; } ka0c05_bsb$r_tlrmdqrx_overlay; unsigned char ka0c05_bsb$b_f130 [60]; __union { unsigned int ka0c05_bsb$l_tlrmdqr8; __struct { unsigned ka0c05_bsb$v_tlrmdqr8_f1 : 32; } ka0c05_bsb$r_tlrmdqr8_bits; } ka0c05_bsb$r_tlrmdqr8_overlay; unsigned char ka0c05_bsb$b_f140 [444]; __union { __int64 ka0c05_bsb$q_tlrdrd; } ka0c05_bsb$r_tlrdrd_overlay; unsigned char ka0c05_bsb$b_f150 [60]; __union { unsigned int ka0c05_bsb$l_tlrdre; __struct { unsigned ka0c05_bsb$v_tlrdre_f1 : 32; } ka0c05_bsb$r_tlrdre_bits; } ka0c05_bsb$r_tlrdre_overlay; unsigned char ka0c05_bsb$b_f160 [4156]; __union { unsigned int ka0c05_bsb$l_tlmcr; __struct { unsigned ka0c05_bsb$v_tlmcr_f1 : 32; } ka0c05_bsb$r_tlmcr_bits; } ka0c05_bsb$r_tlmcr_overlay; unsigned char ka0c05_bsb$b_f170 [1916]; char ka0c05_bsb$b_fill_0_ [4]; } KA0C05_BSB; #if !defined(__VAXC) #define ka0c05_bsb$l_tlprivate ka0c05_bsb$r_tlprivate_overlay.ka0c05_bsb$l_tlprivate #define ka0c05_bsb$l_tlipint ka0c05_bsb$r_tlipint_overlay.ka0c05_bsb$l_tlipint #define ka0c05_bsb$v_tlipint_mask ka0c05_bsb$r_tlipint_overlay.ka0c05_bsb$r_tlipint_bits.ka0c05_bsb$v_tlipint_mask #define ka0c05_bsb$l_tlioint4 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$l_tlioint4 #define ka0c05_bsb$v_tlioint4_mask ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_mask #define ka0c05_bsb$v_tlioint4_ipl14 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl14 #define ka0c05_bsb$v_tlioint4_ipl15 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl15 #define ka0c05_bsb$v_tlioint4_ipl16 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl16 #define ka0c05_bsb$v_tlioint4_ipl17 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl17 #define ka0c05_bsb$l_tlioint5 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$l_tlioint5 #define ka0c05_bsb$v_tlioint5_mask ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_mask #define ka0c05_bsb$v_tlioint5_ipl14 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl14 #define ka0c05_bsb$v_tlioint5_ipl15 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl15 #define ka0c05_bsb$v_tlioint5_ipl16 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl16 #define ka0c05_bsb$v_tlioint5_ipl17 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl17 #define ka0c05_bsb$l_tlioint6 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$l_tlioint6 #define ka0c05_bsb$v_tlioint6_mask ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_mask #define ka0c05_bsb$v_tlioint6_ipl14 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl14 #define ka0c05_bsb$v_tlioint6_ipl15 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl15 #define ka0c05_bsb$v_tlioint6_ipl16 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl16 #define ka0c05_bsb$v_tlioint6_ipl17 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl17 #define ka0c05_bsb$l_tlioint7 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$l_tlioint7 #define ka0c05_bsb$v_tlioint7_mask ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_mask #define ka0c05_bsb$v_tlioint7_ipl14 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl14 #define ka0c05_bsb$v_tlioint7_ipl15 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl15 #define ka0c05_bsb$v_tlioint7_ipl16 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl16 #define ka0c05_bsb$v_tlioint7_ipl17 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl17 #define ka0c05_bsb$l_tlioint8 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$l_tlioint8 #define ka0c05_bsb$v_tlioint8_mask ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_mask #define ka0c05_bsb$v_tlioint8_ipl14 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl14 #define ka0c05_bsb$v_tlioint8_ipl15 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl15 #define ka0c05_bsb$v_tlioint8_ipl16 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl16 #define ka0c05_bsb$v_tlioint8_ipl17 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl17 #define ka0c05_bsb$l_tlwsdqr4 ka0c05_bsb$r_tlwsdqr4_overlay.ka0c05_bsb$l_tlwsdqr4 #define ka0c05_bsb$l_tlwsdqr5 ka0c05_bsb$r_tlwsdqr5_overlay.ka0c05_bsb$l_tlwsdqr5 #define ka0c05_bsb$l_tlwsdqr6 ka0c05_bsb$r_tlwsdqr6_overlay.ka0c05_bsb$l_tlwsdqr6 #define ka0c05_bsb$l_tlwsdqr7 ka0c05_bsb$r_tlwsdqr7_overlay.ka0c05_bsb$l_tlwsdqr7 #define ka0c05_bsb$l_tlwsdqr8 ka0c05_bsb$r_tlwsdqr8_overlay.ka0c05_bsb$l_tlwsdqr8 #define ka0c05_bsb$l_tlrmdqrx ka0c05_bsb$r_tlrmdqrx_overlay.ka0c05_bsb$l_tlrmdqrx #define ka0c05_bsb$l_tlrmdqr8 ka0c05_bsb$r_tlrmdqr8_overlay.ka0c05_bsb$l_tlrmdqr8 #define ka0c05_bsb$q_tlrdrd ka0c05_bsb$r_tlrdrd_overlay.ka0c05_bsb$q_tlrdrd #define ka0c05_bsb$l_tlrdre ka0c05_bsb$r_tlrdre_overlay.ka0c05_bsb$l_tlrdre #define ka0c05_bsb$l_tlmcr ka0c05_bsb$r_tlmcr_overlay.ka0c05_bsb$l_tlmcr #endif /* #if !defined(__VAXC) */ #define KA0C05_TLEP$M_TLDEV_DTYPE 0xFFFF #define KA0C05_TLEP$M_TLDEV_SWREV 0xFF0000 #define KA0C05_TLEP$M_TLDEV_HWREV 0xFF000000 #define KA0C05_TLEP$M_TLBER_ATCE 0x1 #define KA0C05_TLEP$M_TLBER_APE 0x2 #define KA0C05_TLEP$M_TLBER_BBE 0x4 #define KA0C05_TLEP$M_TLBER_LKTO 0x8 #define KA0C05_TLEP$M_TLBER_NAE 0x10 #define KA0C05_TLEP$M_TLBER_RTCE 0x20 #define KA0C05_TLEP$M_TLBER_ACKTCE 0x40 #define KA0C05_TLEP$M_TLBER_MMRE 0x80 #define KA0C05_TLEP$M_TLBER_FNAE 0x100 #define KA0C05_TLEP$M_TLBER_REQDE 0x200 #define KA0C05_TLEP$M_TLBER_ATDE 0x400 #define KA0C05_TLEP$M_TLBER_UDE 0x10000 #define KA0C05_TLEP$M_TLBER_CWDE 0x20000 #define KA0C05_TLEP$M_TLBER_CRDE 0x40000 #define KA0C05_TLEP$M_TLBER_DS0 0x100000 #define KA0C05_TLEP$M_TLBER_DS1 0x200000 #define KA0C05_TLEP$M_TLBER_DS2 0x400000 #define KA0C05_TLEP$M_TLBER_DS3 0x800000 #define KA0C05_TLEP$M_TLBER_DTDE 0x1000000 #define KA0C05_TLEP$M_TLBER_FDTCE 0x2000000 #define KA0C05_TLEP$M_TLBER_UACKE 0x4000000 #define KA0C05_TLEP$M_TLBER_ABTCE 0x8000000 #define KA0C05_TLEP$M_TLBER_DCTCE 0x10000000 #define KA0C05_TLEP$M_TLBER_SEQE 0x20000000 #define KA0C05_TLEP$M_TLBER_DSE 0x40000000 #define KA0C05_TLEP$M_TLBER_DTO 0x80000000 #define KA0C05_TLEP$M_TLCNR_CWDD 0x1 #define KA0C05_TLEP$M_TLCNR_CRDD 0x2 #define KA0C05_TLEP$M_TLCNR_DTOD 0x8 #define KA0C05_TLEP$M_TLCNR_NODE_ID 0xF0 #define KA0C05_TLEP$M_TLCNR_VCNT 0xF00 #define KA0C05_TLEP$M_TLCNR_STF_A 0x1000 #define KA0C05_TLEP$M_TLCNR_STF_B 0x2000 #define KA0C05_TLEP$M_TLCNR_HALT_A 0x100000 #define KA0C05_TLEP$M_TLCNR_HALT_B 0x200000 #define KA0C05_TLEP$M_TLCNR_NRST 0x40000000 #define KA0C05_TLEP$M_TLCNR_LOFE 0x80000000 #define KA0C05_TLEP$M_VID_A 0xF #define KA0C05_TLEP$M_VID_B 0xF0 #define KA0C05_TLEP$M_TLMMR0_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR0_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR0_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR0_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR0_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR0_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR1_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR1_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR1_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR1_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR1_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR1_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR2_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR2_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR2_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR2_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR2_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR2_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR3_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR3_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR3_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR3_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR3_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR3_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR4_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR4_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR4_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR4_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR4_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR4_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR5_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR5_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR5_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR5_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR5_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR5_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR6_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR6_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR6_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR6_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR6_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR6_VALID 0x80000000 #define KA0C05_TLEP$M_TLMMR7_INTMASK 0x3 #define KA0C05_TLEP$M_TLMMR7_ADRMASK 0xF0 #define KA0C05_TLEP$M_TLMMR7_INTLV 0x700 #define KA0C05_TLEP$M_TLMMR7_SBANK 0x800 #define KA0C05_TLEP$M_TLMMR7_ADDRESS 0x3FFF000 #define KA0C05_TLEP$M_TLMMR7_VALID 0x80000000 #define KA0C05_TLEP$M_TLESR0_SYND0 0xFF #define KA0C05_TLEP$M_TLESR0_SYND1 0xFF00 #define KA0C05_TLEP$M_TLESR0_TDE 0x10000 #define KA0C05_TLEP$M_TLESR0_TCE 0x20000 #define KA0C05_TLEP$M_TLESR0_DVTCE 0x40000 #define KA0C05_TLEP$M_TLESR0_UECC 0x80000 #define KA0C05_TLEP$M_TLESR0_CWECC 0x100000 #define KA0C05_TLEP$M_TLESR0_CRECC 0x200000 #define KA0C05_TLEP$M_TLESR0_CPU0 0x400000 #define KA0C05_TLEP$M_TLESR0_CPU1 0x800000 #define KA0C05_TLEP$M_TLESR0_LOFSYN 0x80000000 #define KA0C05_TLEP$M_TLESR1_SYND0 0xFF #define KA0C05_TLEP$M_TLESR1_SYND1 0xFF00 #define KA0C05_TLEP$M_TLESR1_TDE 0x10000 #define KA0C05_TLEP$M_TLESR1_TCE 0x20000 #define KA0C05_TLEP$M_TLESR1_DVTCE 0x40000 #define KA0C05_TLEP$M_TLESR1_UECC 0x80000 #define KA0C05_TLEP$M_TLESR1_CWECC 0x100000 #define KA0C05_TLEP$M_TLESR1_CRECC 0x200000 #define KA0C05_TLEP$M_TLESR1_CPU0 0x400000 #define KA0C05_TLEP$M_TLESR1_CPU1 0x800000 #define KA0C05_TLEP$M_TLESR1_LOFSYN 0x80000000 #define KA0C05_TLEP$M_TLESR2_SYND0 0xFF #define KA0C05_TLEP$M_TLESR2_SYND1 0xFF00 #define KA0C05_TLEP$M_TLESR2_TDE 0x10000 #define KA0C05_TLEP$M_TLESR2_TCE 0x20000 #define KA0C05_TLEP$M_TLESR2_DVTCE 0x40000 #define KA0C05_TLEP$M_TLESR2_UECC 0x80000 #define KA0C05_TLEP$M_TLESR2_CWECC 0x100000 #define KA0C05_TLEP$M_TLESR2_CRECC 0x200000 #define KA0C05_TLEP$M_TLESR2_CPU0 0x400000 #define KA0C05_TLEP$M_TLESR2_CPU1 0x800000 #define KA0C05_TLEP$M_TLESR2_LOFSYN 0x80000000 #define KA0C05_TLEP$M_TLESR3_SYND0 0xFF #define KA0C05_TLEP$M_TLESR3_SYND1 0xFF00 #define KA0C05_TLEP$M_TLESR3_TDE 0x10000 #define KA0C05_TLEP$M_TLESR3_TCE 0x20000 #define KA0C05_TLEP$M_TLESR3_DVTCE 0x40000 #define KA0C05_TLEP$M_TLESR3_UECC 0x80000 #define KA0C05_TLEP$M_TLESR3_CWECC 0x100000 #define KA0C05_TLEP$M_TLESR3_CRECC 0x200000 #define KA0C05_TLEP$M_TLESR3_CPU0 0x400000 #define KA0C05_TLEP$M_TLESR3_CPU1 0x800000 #define KA0C05_TLEP$M_TLESR3_LOFSYN 0x80000000 #define KA0C05_TLEP$M_TLDIAG_FRIGN 0x1 #define KA0C05_TLEP$M_TLDIAG_DTWR 0x2 #define KA0C05_TLEP$M_TLDIAG_DTRD 0x4 #define KA0C05_TLEP$M_TLDIAG_DTCP 0x8 #define KA0C05_TLEP$M_TLDIAG_FVW 0x10 #define KA0C05_TLEP$M_TLDIAG_FAE 0x20 #define KA0C05_TLEP$M_TLDIAG_FCBE 0x40 #define KA0C05_TLEP$M_TLDIAG_FDBE 0x80 #define KA0C05_TLEP$M_TLDIAG_FDE 0xF00 #define KA0C05_TLEP$M_TLDIAG_FTW 0x1000 #define KA0C05_TLEP$M_TLDIAG_ASRT_FLT 0x2000 #define KA0C05_TLEP$M_TLDIAG_QWVAL_EN 0x4000 #define KA0C05_TLEP$M_TLDIAG_GSLOW 0x8000 #define KA0C05_TLEP$M_TLDTAGD_DTAG_PAR 0x1 #define KA0C05_TLEP$M_TLDTAGD_DTAG_DATA 0xFFFFE #define KA0C05_TLEP$M_TLDTAGS_STATPAR 0x1 #define KA0C05_TLEP$M_TLDTAGS_STATD 0x2 #define KA0C05_TLEP$M_TLDTAGS_STATS 0x4 #define KA0C05_TLEP$M_TLDTAGS_STATV 0x8 #define KA0C05_TLEP$M_TLMCFG_CPU0DSBL 0x1 #define KA0C05_TLEP$M_TLMCFG_CPU1DSBL 0x2 #define KA0C05_TLEP$M_TLMCFG_BC_SIZE 0xC #define KA0C05_TLEP$M_TLMCFG_LO_EN 0x10 #define KA0C05_TLEP$M_TLMCFG_RM_SIZE 0x20 #define KA0C05_TLEP$M_TLMCFG_BCIDLE 0x3C0 #define KA0C05_TLEP$M_TLMCFG_CQ_ENTRY 0x1C00 #define KA0C05_TLEP$M_TLMCFG_BQ_ENTRY 0xE000 #define KA0C05_TLEP$M_TLMCFG_SYS_DSBL 0x10000 #define KA0C05_TLEP$M_TLMCFG_EV5_DSBL 0x20000 #define KA0C05_TLEP$M_TLMCFG_FLT_DSBL 0x40000 #define KA0C05_TLEP$M_TLIMASK0_DUART0EN 0x1 #define KA0C05_TLEP$M_TLIMASK0_IPL14_EN 0x2 #define KA0C05_TLEP$M_TLIMASK0_IPL15_EN 0x4 #define KA0C05_TLEP$M_TLIMASK0_IPL16_EN 0x8 #define KA0C05_TLEP$M_TLIMASK0_IPL17_EN 0x10 #define KA0C05_TLEP$M_TLIMASK0_IP_EN 0x20 #define KA0C05_TLEP$M_TLIMASK0_INTIM_EN 0x40 #define KA0C05_TLEP$M_TLIMASK0_HALT_EN 0x80 #define KA0C05_TLEP$M_TLIMASK0_CP_EN 0x100 #define KA0C05_TLEP$M_TLIMASK1_DUART0EN 0x1 #define KA0C05_TLEP$M_TLIMASK1_IPL14_EN 0x2 #define KA0C05_TLEP$M_TLIMASK1_IPL15_EN 0x4 #define KA0C05_TLEP$M_TLIMASK1_IPL16_EN 0x8 #define KA0C05_TLEP$M_TLIMASK1_IPL17_EN 0x10 #define KA0C05_TLEP$M_TLIMASK1_IP_EN 0x20 #define KA0C05_TLEP$M_TLIMASK1_INTIM_EN 0x40 #define KA0C05_TLEP$M_TLIMASK1_HALT_EN 0x80 #define KA0C05_TLEP$M_TLIMASK1_CP_EN 0x100 #define KA0C05_TLEP$M_TLISUM0_DUART0INT 0x1 #define KA0C05_TLEP$M_TLISUM0_IPL14_INT 0x2 #define KA0C05_TLEP$M_TLISUM0_IPL15_INT 0x4 #define KA0C05_TLEP$M_TLISUM0_IPL16_INT 0x8 #define KA0C05_TLEP$M_TLISUM0_IPL17_INT 0x10 #define KA0C05_TLEP$M_TLISUM0_IP_INT 0x20 #define KA0C05_TLEP$M_TLISUM0_INTIM_INT 0x40 #define KA0C05_TLEP$M_TLISUM0_IPL14 0xF80 #define KA0C05_TLEP$M_TLISUM0_IPL15 0x1F000 #define KA0C05_TLEP$M_TLISUM0_IPL16 0x3E0000 #define KA0C05_TLEP$M_TLISUM0_IPL17 0x7C00000 #define KA0C05_TLEP$M_TLISUM0_CP_HALT 0x8000000 #define KA0C05_TLEP$M_TLISUM0_HALT 0x10000000 #define KA0C05_TLEP$M_TLISUM1_DUART0INT 0x1 #define KA0C05_TLEP$M_TLISUM1_IPL14_INT 0x2 #define KA0C05_TLEP$M_TLISUM1_IPL15_INT 0x4 #define KA0C05_TLEP$M_TLISUM1_IPL16_INT 0x8 #define KA0C05_TLEP$M_TLISUM1_IPL17_INT 0x10 #define KA0C05_TLEP$M_TLISUM1_IP_INT 0x20 #define KA0C05_TLEP$M_TLISUM1_INTIM_INT 0x40 #define KA0C05_TLEP$M_TLISUM1_IPL14 0xF80 #define KA0C05_TLEP$M_TLISUM1_IPL15 0x1F000 #define KA0C05_TLEP$M_TLISUM1_IPL16 0x3E0000 #define KA0C05_TLEP$M_TLISUM1_IPL17 0x7C00000 #define KA0C05_TLEP$M_TLISUM1_CP_HALT 0x8000000 #define KA0C05_TLEP$M_TLISUM1_HALT 0x10000000 #define KA0C05_TLEP$M_TLEPAERR_E2MAPE0 0x1 #define KA0C05_TLEP$M_TLEPAERR_E2MAPE1 0x2 #define KA0C05_TLEP$M_TLEPAERR_M2AAPE0 0x4 #define KA0C05_TLEP$M_TLEPAERR_M2AAPE1 0x8 #define KA0C05_TLEP$M_TLEPAERR_DTDPE 0x10 #define KA0C05_TLEP$M_TLEPAERR_DTSPE 0x20 #define KA0C05_TLEP$M_TLEPAERR_D2ACPE 0x40 #define KA0C05_TLEP$M_TLEPAERR_SYSDERR 0x80 #define KA0C05_TLEP$M_TLEPAERR_SYSFLT 0x100 #define KA0C05_TLEP$M_TLEPAERR_RD_ERR 0x600 #define KA0C05_TLEP$M_TLEPAERR_IBOXTO 0x1800 #define KA0C05_TLEP$M_TLEPAERR_RD_PEND 0x6000 #define KA0C05_TLEP$M_TLEPAERR_NXM 0x8000 #define KA0C05_TLEP$M_TLEPAERR_NO_ACK 0x30000 #define KA0C05_TLEP$M_TLEPDERR_A2DCPE 0x1 #define KA0C05_TLEP$M_TLEPDERR_D2DCPE0 0x2 #define KA0C05_TLEP$M_TLEPDERR_GBTO 0x4 #define KA0C05_TLEP$M_TLEPMERR_A2MAPE0 0x1 #define KA0C05_TLEP$M_TLEPMERR_A2MAPE1 0x2 #define KA0C05_TLEP$M_TLEPMERR_D2MCPE 0x4 #define KA0C05_TLEP$M_TLEPMERR_D2DCPE1 0x8 #define KA0C05_TLEP$M_TLEPMERR_D2DCPE2 0x10 #define KA0C05_TLEP$M_TLEPMERR_D2DCPE3 0x20 #define KA0C05_TLEP$M_TLEPMERR_RSTSTAT 0x40 #define KA0C05_TLEP$M_TLEP_VMG_5P 0x1 #define KA0C05_TLEP$M_TLEP_VMG_5M 0x2 #define KA0C05_TLEP$M_TLEP_VMG_3P 0x4 #define KA0C05_TLEP$M_TLEP_VMG_3M 0x8 #define KA0C05_TLEP$M_TLDMCMD_SIZE_512 0x1 #define KA0C05_TLEP$M_TLDMCMD_SIZE_1K 0x2 #define KA0C05_TLEP$M_TLDMCMD_SIZE_2K 0x4 #define KA0C05_TLEP$M_TLDMCMD_SIZE_4K 0x8 #define KA0C05_TLEP$M_TLDMCMD_SIZE_8K 0x10 #define KA0C05_TLEP$M_TLDMCMD_CMD 0x300 #define KA0C05_TLEP$M_TLDMCMD_VALID 0x800 #define KA0C05_TLEP$M_TLDMCMD_RM_3 0x1000 #define KA0C05_TLEP$M_TLDMCMD_RM_4 0x2000 #define KA0C05_TLEP$M_TLDMCMD_RM_INLV 0x4000 #define KA0C05_TLEP$M_TLDMCMD_CPU_ID 0x10000 #define KA0C05_TLEP$M_TLDMCMD_IN_PROG 0x100000 #define KA0C05_TLEP$M_TLDMCMD_DONE 0x200000 #define KA0C05_TLEP$M_TLDMADRA_ADDR 0x3FFFFFFF #define KA0C05_TLEP$M_TLDMADRB_ADDR 0x3FFFFFFF #define KA0C05_TLEP$M_TLPM_CMD_CPUNUM 0x1 #define KA0C05_TLEP$M_TLPM_CMD_SET_SEL 0x6 #define KA0C05_TLEP$M_TLPM_CMD_VALID 0x8 #define KA0C05_TLEP$M_TLPM_CMD_READ_SET 0x10 #define KA0C05_TLEP$M_TLPM_CMD_OVRF_EN 0x800 #define KA0C05_TLEP$M_TLPM_CMD_TOT_CYC 0x1000 #define KA0C05_TLEP$M_TLPM_CMD_EV5_LAT 0x2000 #define KA0C05_TLEP$M_TLPM_CMD_RD_LAT 0x4000 #define KA0C05_TLEP$M_TLPM_CMD_SYS_OWN 0x8000 #define KA0C05_TLEP$M_TLPM_CMD_F2 0x10000 #define KA0C05_TLEP$M_TLPM_CMD_LOCK 0x20000 #define KA0C05_TLEP$M_TLPM_CMD_MB 0x40000 #define KA0C05_TLEP$M_TLPM_CMD_SD_TOT 0x80000 #define KA0C05_TLEP$M_TLPM_CMD_SD_ACK 0x100000 #define KA0C05_TLEP$M_TLPM_CMD_RD_CSR 0x200000 #define KA0C05_TLEP$M_TLPM_CMD_RD 0x400000 #define KA0C05_TLEP$M_TLPM_CMD_RD_MOD 0x800000 #define KA0C05_TLEP$M_TLPM_CMD_RD_STC 0x1000000 #define KA0C05_TLEP$M_TLPM_CMD_VIC 0x2000000 #define KA0C05_TLEP$M_TLPM_CMD_WR_CSR 0x4000000 #define KA0C05_TLEP$M_TLPM_CMD_WR 0x8000000 #define KA0C05_TLEP$M_TLPM_CMD_WR_LOCK 0x10000000 #define KA0C05_TLEP$M_TLPM_CMD_INVAL 0x20000000 #define KA0C05_TLEP$M_TLPM_CMD_SET_SHR 0x40000000 #define KA0C05_TLEP$M_TLPM_CMD_RD_DIRT 0x80000000 #define KA0C05_TLEP$M_RM_REG0A_AEXT 0xF #define KA0C05_TLEP$M_RM_REG0A_BADDR 0xFFFFF00 #define KA0C05_TLEP$M_RM_REG0A_VALID 0x80000000 #define KA0C05_TLEP$M_RM_REG0B_AEXT 0xF #define KA0C05_TLEP$M_RM_REG0B_BADDR 0xFFFFF00 #define KA0C05_TLEP$M_RM_REG0B_VALID 0x80000000 #define KA0C05_TLEP$M_RM_REG1A_AEXT 0xF #define KA0C05_TLEP$M_RM_REG1A_BADDR 0xFFFFF00 #define KA0C05_TLEP$M_RM_REG1A_VALID 0x80000000 #define KA0C05_TLEP$M_RM_REG1B_AEXT 0xF #define KA0C05_TLEP$M_RM_REG1B_BADDR 0xFFFFF00 #define KA0C05_TLEP$M_RM_REG1B_VALID 0x80000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_tlep { #pragma __nomember_alignment __union { unsigned int ka0c05_tlep$l_tldev; __struct { unsigned ka0c05_tlep$v_tldev_dtype : 16; unsigned ka0c05_tlep$v_tldev_swrev : 8; unsigned ka0c05_tlep$v_tldev_hwrev : 8; } ka0c05_tlep$r_tldev_bits; } ka0c05_tlep$r_tldev_overlay; unsigned char ka0c05_tlep$b_f200 [60]; __union { unsigned int ka0c05_tlep$l_tlber; __struct { unsigned ka0c05_tlep$v_tlber_atce : 1; unsigned ka0c05_tlep$v_tlber_ape : 1; unsigned ka0c05_tlep$v_tlber_bbe : 1; unsigned ka0c05_tlep$v_tlber_lkto : 1; unsigned ka0c05_tlep$v_tlber_nae : 1; unsigned ka0c05_tlep$v_tlber_rtce : 1; unsigned ka0c05_tlep$v_tlber_acktce : 1; unsigned ka0c05_tlep$v_tlber_mmre : 1; unsigned ka0c05_tlep$v_tlber_fnae : 1; unsigned ka0c05_tlep$v_tlber_reqde : 1; unsigned ka0c05_tlep$v_tlber_atde : 1; unsigned ka0c05_tlep$v_tlber_f1 : 5; unsigned ka0c05_tlep$v_tlber_ude : 1; unsigned ka0c05_tlep$v_tlber_cwde : 1; unsigned ka0c05_tlep$v_tlber_crde : 1; unsigned ka0c05_tlep$v_tlber_cwde2 : 1; unsigned ka0c05_tlep$v_tlber_ds0 : 1; unsigned ka0c05_tlep$v_tlber_ds1 : 1; unsigned ka0c05_tlep$v_tlber_ds2 : 1; unsigned ka0c05_tlep$v_tlber_ds3 : 1; unsigned ka0c05_tlep$v_tlber_dtde : 1; unsigned ka0c05_tlep$v_tlber_fdtce : 1; unsigned ka0c05_tlep$v_tlber_uacke : 1; unsigned ka0c05_tlep$v_tlber_abtce : 1; unsigned ka0c05_tlep$v_tlber_dctce : 1; unsigned ka0c05_tlep$v_tlber_seqe : 1; unsigned ka0c05_tlep$v_tlber_dse : 1; unsigned ka0c05_tlep$v_tlber_dto : 1; } ka0c05_tlep$r_tlber_bits; } ka0c05_tlep$r_tlber_overlay; unsigned char ka0c05_tlep$b_f210 [60]; __union { unsigned int ka0c05_tlep$l_tlcnr; __struct { unsigned ka0c05_tlep$v_tlcnr_cwdd : 1; unsigned ka0c05_tlep$v_tlcnr_crdd : 1; unsigned ka0c05_tlep$v_tlcnr_f1 : 1; unsigned ka0c05_tlep$v_tlcnr_dtod : 1; unsigned ka0c05_tlep$v_tlcnr_node_id : 4; unsigned ka0c05_tlep$v_tlcnr_vcnt : 4; unsigned ka0c05_tlep$v_tlcnr_stf_a : 1; unsigned ka0c05_tlep$v_tlcnr_stf_b : 1; unsigned ka0c05_tlep$v_tlcnr_f2 : 6; unsigned ka0c05_tlep$v_tlcnr_halt_a : 1; unsigned ka0c05_tlep$v_tlcnr_halt_b : 1; unsigned ka0c05_tlep$v_tlcnr_fill3 : 8; unsigned ka0c05_tlep$v_tlcnr_nrst : 1; unsigned ka0c05_tlep$v_tlcnr_lofe : 1; } ka0c05_tlep$r_tlcnr_bits; } ka0c05_tlep$r_tlcnr_overlay; unsigned char ka0c05_tlep$b_f220 [60]; __union { unsigned int ka0c05_tlep$l_tlvid; __struct { unsigned ka0c05_tlep$v_vid_a : 4; unsigned ka0c05_tlep$v_vid_b : 4; unsigned ka0c05_tlep$v_vid_f1 : 24; } ka0c05_tlep$r_tlvid_bits; } ka0c05_tlep$r_tlvid_overlay; unsigned char ka0c05_tlep$b_f230 [316]; __union { unsigned int ka0c05_tlep$l_tlmmr0; __struct { unsigned ka0c05_tlep$v_tlmmr0_intmask : 2; unsigned ka0c05_tlep$v_tlmmr0_f1 : 2; unsigned ka0c05_tlep$v_tlmmr0_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr0_intlv : 3; unsigned ka0c05_tlep$v_tlmmr0_sbank : 1; unsigned ka0c05_tlep$v_tlmmr0_address : 14; unsigned ka0c05_tlep$v_tlmmr0_f2 : 5; unsigned ka0c05_tlep$v_tlmmr0_valid : 1; } ka0c05_tlep$r_tlmmr0_bits; } ka0c05_tlep$r_tlmmr0_overlay; unsigned char ka0c05_tlep$b_f240 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr1; __struct { unsigned ka0c05_tlep$v_tlmmr1_intmask : 2; unsigned ka0c05_tlep$v_tlmmr1_f1 : 2; unsigned ka0c05_tlep$v_tlmmr1_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr1_intlv : 3; unsigned ka0c05_tlep$v_tlmmr1_sbank : 1; unsigned ka0c05_tlep$v_tlmmr1_address : 14; unsigned ka0c05_tlep$v_tlmmr1_f2 : 5; unsigned ka0c05_tlep$v_tlmmr1_valid : 1; } ka0c05_tlep$r_tlmmr1_bits; } ka0c05_tlep$r_tlmmr1_overlay; unsigned char ka0c05_tlep$b_f250 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr2; __struct { unsigned ka0c05_tlep$v_tlmmr2_intmask : 2; unsigned ka0c05_tlep$v_tlmmr2_f1 : 2; unsigned ka0c05_tlep$v_tlmmr2_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr2_intlv : 3; unsigned ka0c05_tlep$v_tlmmr2_sbank : 1; unsigned ka0c05_tlep$v_tlmmr2_address : 14; unsigned ka0c05_tlep$v_tlmmr2_f2 : 5; unsigned ka0c05_tlep$v_tlmmr2_valid : 1; } ka0c05_tlep$r_tlmmr2_bits; } ka0c05_tlep$r_tlmmr2_overlay; unsigned char ka0c05_tlep$b_f260 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr3; __struct { unsigned ka0c05_tlep$v_tlmmr3_intmask : 2; unsigned ka0c05_tlep$v_tlmmr3_f1 : 2; unsigned ka0c05_tlep$v_tlmmr3_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr3_intlv : 3; unsigned ka0c05_tlep$v_tlmmr3_sbank : 1; unsigned ka0c05_tlep$v_tlmmr3_address : 14; unsigned ka0c05_tlep$v_tlmmr3_f2 : 5; unsigned ka0c05_tlep$v_tlmmr3_valid : 1; } ka0c05_tlep$r_tlmmr3_bits; } ka0c05_tlep$r_tlmmr3_overlay; unsigned char ka0c05_tlep$b_f270 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr4; __struct { unsigned ka0c05_tlep$v_tlmmr4_intmask : 2; unsigned ka0c05_tlep$v_tlmmr4_f1 : 2; unsigned ka0c05_tlep$v_tlmmr4_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr4_intlv : 3; unsigned ka0c05_tlep$v_tlmmr4_sbank : 1; unsigned ka0c05_tlep$v_tlmmr4_address : 14; unsigned ka0c05_tlep$v_tlmmr4_f2 : 5; unsigned ka0c05_tlep$v_tlmmr4_valid : 1; } ka0c05_tlep$r_tlmmr4_bits; } ka0c05_tlep$r_tlmmr4_overlay; unsigned char ka0c05_tlep$b_f280 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr5; __struct { unsigned ka0c05_tlep$v_tlmmr5_intmask : 2; unsigned ka0c05_tlep$v_tlmmr5_f1 : 2; unsigned ka0c05_tlep$v_tlmmr5_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr5_intlv : 3; unsigned ka0c05_tlep$v_tlmmr5_sbank : 1; unsigned ka0c05_tlep$v_tlmmr5_address : 14; unsigned ka0c05_tlep$v_tlmmr5_f2 : 5; unsigned ka0c05_tlep$v_tlmmr5_valid : 1; } ka0c05_tlep$r_tlmmr5_bits; } ka0c05_tlep$r_tlmmr5_overlay; unsigned char ka0c05_tlep$b_f290 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr6; __struct { unsigned ka0c05_tlep$v_tlmmr6_intmask : 2; unsigned ka0c05_tlep$v_tlmmr6_f1 : 2; unsigned ka0c05_tlep$v_tlmmr6_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr6_intlv : 3; unsigned ka0c05_tlep$v_tlmmr6_sbank : 1; unsigned ka0c05_tlep$v_tlmmr6_address : 14; unsigned ka0c05_tlep$v_tlmmr6_f2 : 5; unsigned ka0c05_tlep$v_tlmmr6_valid : 1; } ka0c05_tlep$r_tlmmr6_bits; } ka0c05_tlep$r_tlmmr6_overlay; unsigned char ka0c05_tlep$b_fill300 [60]; __union { unsigned int ka0c05_tlep$l_tlmmr7; __struct { unsigned ka0c05_tlep$v_tlmmr7_intmask : 2; unsigned ka0c05_tlep$v_tlmmr7_f1 : 2; unsigned ka0c05_tlep$v_tlmmr7_adrmask : 4; unsigned ka0c05_tlep$v_tlmmr7_intlv : 3; unsigned ka0c05_tlep$v_tlmmr7_sbank : 1; unsigned ka0c05_tlep$v_tlmmr7_address : 14; unsigned ka0c05_tlep$v_tlmmr7_f2 : 5; unsigned ka0c05_tlep$v_tlmmr7_valid : 1; } ka0c05_tlep$r_tlmmr7_bits; } ka0c05_tlep$r_tlmmr7_overlay; unsigned char ka0c05_tlep$b_fill310 [700]; __union { unsigned int ka0c05_tlep$l_tlesr0; __struct { unsigned ka0c05_tlep$v_tlesr0_synd0 : 8; unsigned ka0c05_tlep$v_tlesr0_synd1 : 8; unsigned ka0c05_tlep$v_tlesr0_tde : 1; unsigned ka0c05_tlep$v_tlesr0_tce : 1; unsigned ka0c05_tlep$v_tlesr0_dvtce : 1; unsigned ka0c05_tlep$v_tlesr0_uecc : 1; unsigned ka0c05_tlep$v_tlesr0_cwecc : 1; unsigned ka0c05_tlep$v_tlesr0_crecc : 1; unsigned ka0c05_tlep$v_tlesr0_cpu0 : 1; unsigned ka0c05_tlep$v_tlesr0_cpu1 : 1; unsigned ka0c05_tlep$v_tlesr0_f1 : 7; unsigned ka0c05_tlep$v_tlesr0_lofsyn : 1; } ka0c05_tlep$r_tlesr0_bits; } ka0c05_tlep$r_tlesr0_overlay; unsigned char ka0c05_tlep$b_fill320 [60]; __union { unsigned int ka0c05_tlep$l_tlesr1; __struct { unsigned ka0c05_tlep$v_tlesr1_synd0 : 8; unsigned ka0c05_tlep$v_tlesr1_synd1 : 8; unsigned ka0c05_tlep$v_tlesr1_tde : 1; unsigned ka0c05_tlep$v_tlesr1_tce : 1; unsigned ka0c05_tlep$v_tlesr1_dvtce : 1; unsigned ka0c05_tlep$v_tlesr1_uecc : 1; unsigned ka0c05_tlep$v_tlesr1_cwecc : 1; unsigned ka0c05_tlep$v_tlesr1_crecc : 1; unsigned ka0c05_tlep$v_tlesr1_cpu0 : 1; unsigned ka0c05_tlep$v_tlesr1_cpu1 : 1; unsigned ka0c05_tlep$v_tlesr1_f1 : 7; unsigned ka0c05_tlep$v_tlesr1_lofsyn : 1; } ka0c05_tlep$r_tlesr1_bits; } ka0c05_tlep$r_tlesr1_overlay; unsigned char ka0c05_tlep$b_fill330 [60]; __union { unsigned int ka0c05_tlep$l_tlesr2; __struct { unsigned ka0c05_tlep$v_tlesr2_synd0 : 8; unsigned ka0c05_tlep$v_tlesr2_synd1 : 8; unsigned ka0c05_tlep$v_tlesr2_tde : 1; unsigned ka0c05_tlep$v_tlesr2_tce : 1; unsigned ka0c05_tlep$v_tlesr2_dvtce : 1; unsigned ka0c05_tlep$v_tlesr2_uecc : 1; unsigned ka0c05_tlep$v_tlesr2_cwecc : 1; unsigned ka0c05_tlep$v_tlesr2_crecc : 1; unsigned ka0c05_tlep$v_tlesr2_cpu0 : 1; unsigned ka0c05_tlep$v_tlesr2_cpu1 : 1; unsigned ka0c05_tlep$v_tlesr2_f1 : 7; unsigned ka0c05_tlep$v_tlesr2_lofsyn : 1; } ka0c05_tlep$r_tlesr2_bits; } ka0c05_tlep$r_tlesr2_overlay; unsigned char ka0c05_tlep$b_fill340 [60]; __union { unsigned int ka0c05_tlep$l_tlesr3; __struct { unsigned ka0c05_tlep$v_tlesr3_synd0 : 8; unsigned ka0c05_tlep$v_tlesr3_synd1 : 8; unsigned ka0c05_tlep$v_tlesr3_tde : 1; unsigned ka0c05_tlep$v_tlesr3_tce : 1; unsigned ka0c05_tlep$v_tlesr3_dvtce : 1; unsigned ka0c05_tlep$v_tlesr3_uecc : 1; unsigned ka0c05_tlep$v_tlesr3_cwecc : 1; unsigned ka0c05_tlep$v_tlesr3_crecc : 1; unsigned ka0c05_tlep$v_tlesr3_cpu0 : 1; unsigned ka0c05_tlep$v_tlesr3_cpu1 : 1; unsigned ka0c05_tlep$v_tlesr3_f1 : 7; unsigned ka0c05_tlep$v_tlesr3_lofsyn : 1; } ka0c05_tlep$r_tlesr3_bits; } ka0c05_tlep$r_tlesr3_overlay; unsigned char ka0c05_tlep$b_fill350 [2236]; __union { unsigned int ka0c05_tlep$l_tldiag; __struct { unsigned ka0c05_tlep$v_tldiag_frign : 1; unsigned ka0c05_tlep$v_tldiag_dtwr : 1; unsigned ka0c05_tlep$v_tldiag_dtrd : 1; unsigned ka0c05_tlep$v_tldiag_dtcp : 1; unsigned ka0c05_tlep$v_tldiag_fvw : 1; unsigned ka0c05_tlep$v_tldiag_fae : 1; unsigned ka0c05_tlep$v_tldiag_fcbe : 1; unsigned ka0c05_tlep$v_tldiag_fdbe : 1; unsigned ka0c05_tlep$v_tldiag_fde : 4; unsigned ka0c05_tlep$v_tldiag_ftw : 1; unsigned ka0c05_tlep$v_tldiag_asrt_flt : 1; unsigned ka0c05_tlep$v_tldiag_qwval_en : 1; unsigned ka0c05_tlep$v_tldiag_gslow : 1; unsigned ka0c05_tlep$v_tldiag_f1 : 16; } ka0c05_tlep$r_tldiag_bits; } ka0c05_tlep$r_tldiag_overlay; unsigned char ka0c05_tlep$b_fill360 [60]; __union { unsigned int ka0c05_tlep$l_tldtagd; __struct { unsigned ka0c05_tlep$v_tldtagd_dtag_par : 1; unsigned ka0c05_tlep$v_tldtagd_dtag_data : 19; unsigned ka0c05_tlep$v_tldtagd_f1 : 12; } ka0c05_tlep$r_tldtagd_bits; } ka0c05_tlep$r_tldtagd_overlay; unsigned char ka0c05_tlep$b_fill370 [60]; __union { unsigned int ka0c05_tlep$l_tldtags; __struct { unsigned ka0c05_tlep$v_tldtags_statpar : 1; unsigned ka0c05_tlep$v_tldtags_statd : 1; unsigned ka0c05_tlep$v_tldtags_stats : 1; unsigned ka0c05_tlep$v_tldtags_statv : 1; unsigned ka0c05_tlep$v_tldtags_f1 : 28; } ka0c05_tlep$r_tldtags_bits; } ka0c05_tlep$r_tldtags_overlay; unsigned char ka0c05_tlep$b_fill380 [60]; __union { unsigned int ka0c05_tlep$l_tlmcfg; __struct { unsigned ka0c05_tlep$v_tlmcfg_cpu0dsbl : 1; unsigned ka0c05_tlep$v_tlmcfg_cpu1dsbl : 1; unsigned ka0c05_tlep$v_tlmcfg_bc_size : 2; unsigned ka0c05_tlep$v_tlmcfg_lo_en : 1; unsigned ka0c05_tlep$v_tlmcfg_rm_size : 1; unsigned ka0c05_tlep$v_tlmcfg_bcidle : 4; unsigned ka0c05_tlep$v_tlmcfg_cq_entry : 3; unsigned ka0c05_tlep$v_tlmcfg_bq_entry : 3; unsigned ka0c05_tlep$v_tlmcfg_sys_dsbl : 1; unsigned ka0c05_tlep$v_tlmcfg_ev5_dsbl : 1; unsigned ka0c05_tlep$v_tlmcfg_flt_dsbl : 1; unsigned ka0c05_tlep$v_tlmcfg_f1 : 13; } ka0c05_tlep$r_tlmcfg_bits; } ka0c05_tlep$r_tlmcfg_overlay; unsigned char ka0c05_tlep$b_fill390 [60]; __union { unsigned int ka0c05_tlep$l_tlimask0; __struct { unsigned ka0c05_tlep$v_tlimask0_duart0en : 1; unsigned ka0c05_tlep$v_tlimask0_ipl14_en : 1; unsigned ka0c05_tlep$v_tlimask0_ipl15_en : 1; unsigned ka0c05_tlep$v_tlimask0_ipl16_en : 1; unsigned ka0c05_tlep$v_tlimask0_ipl17_en : 1; unsigned ka0c05_tlep$v_tlimask0_ip_en : 1; unsigned ka0c05_tlep$v_tlimask0_intim_en : 1; unsigned ka0c05_tlep$v_tlimask0_halt_en : 1; unsigned ka0c05_tlep$v_tlimask0_cp_en : 1; unsigned ka0c05_tlep$v_tlimask0_f1 : 23; } ka0c05_tlep$r_tlimask0_bits; } ka0c05_tlep$r_tlimask0_overlay; unsigned char ka0c05_tlep$b_fill400 [60]; __union { unsigned int ka0c05_tlep$l_tlimask1; __struct { unsigned ka0c05_tlep$v_tlimask1_duart0en : 1; unsigned ka0c05_tlep$v_tlimask1_ipl14_en : 1; unsigned ka0c05_tlep$v_tlimask1_ipl15_en : 1; unsigned ka0c05_tlep$v_tlimask1_ipl16_en : 1; unsigned ka0c05_tlep$v_tlimask1_ipl17_en : 1; unsigned ka0c05_tlep$v_tlimask1_ip_en : 1; unsigned ka0c05_tlep$v_tlimask1_intim_en : 1; unsigned ka0c05_tlep$v_tlimask1_halt_en : 1; unsigned ka0c05_tlep$v_tlimask1_cp_en : 1; unsigned ka0c05_tlep$v_tlimask1_f1 : 23; } ka0c05_tlep$r_tlimask1_bits; } ka0c05_tlep$r_tlimask1_overlay; unsigned char ka0c05_tlep$b_fill410 [60]; __union { unsigned int ka0c05_tlep$l_tlisum0; __struct { unsigned ka0c05_tlep$v_tlisum0_duart0int : 1; unsigned ka0c05_tlep$v_tlisum0_ipl14_int : 1; unsigned ka0c05_tlep$v_tlisum0_ipl15_int : 1; unsigned ka0c05_tlep$v_tlisum0_ipl16_int : 1; unsigned ka0c05_tlep$v_tlisum0_ipl17_int : 1; unsigned ka0c05_tlep$v_tlisum0_ip_int : 1; unsigned ka0c05_tlep$v_tlisum0_intim_int : 1; unsigned ka0c05_tlep$v_tlisum0_ipl14 : 5; unsigned ka0c05_tlep$v_tlisum0_ipl15 : 5; unsigned ka0c05_tlep$v_tlisum0_ipl16 : 5; unsigned ka0c05_tlep$v_tlisum0_ipl17 : 5; unsigned ka0c05_tlep$v_tlisum0_cp_halt : 1; unsigned ka0c05_tlep$v_tlisum0_halt : 1; unsigned ka0c05_tlep$v_tlisum0_f1 : 3; } ka0c05_tlep$r_tlisum0_bits; } ka0c05_tlep$r_tlisum0_overlay; unsigned char ka0c05_tlep$b_fill420 [60]; __union { unsigned int ka0c05_tlep$l_tlisum1; __struct { unsigned ka0c05_tlep$v_tlisum1_duart0int : 1; unsigned ka0c05_tlep$v_tlisum1_ipl14_int : 1; unsigned ka0c05_tlep$v_tlisum1_ipl15_int : 1; unsigned ka0c05_tlep$v_tlisum1_ipl16_int : 1; unsigned ka0c05_tlep$v_tlisum1_ipl17_int : 1; unsigned ka0c05_tlep$v_tlisum1_ip_int : 1; unsigned ka0c05_tlep$v_tlisum1_intim_int : 1; unsigned ka0c05_tlep$v_tlisum1_ipl14 : 5; unsigned ka0c05_tlep$v_tlisum1_ipl15 : 5; unsigned ka0c05_tlep$v_tlisum1_ipl16 : 5; unsigned ka0c05_tlep$v_tlisum1_ipl17 : 5; unsigned ka0c05_tlep$v_tlisum1_cp_halt : 1; unsigned ka0c05_tlep$v_tlisum1_halt : 1; unsigned ka0c05_tlep$v_tlisum1_f1 : 3; } ka0c05_tlep$r_tlisum1_bits; } ka0c05_tlep$r_tlisum1_overlay; unsigned char ka0c05_tlep$b_fill430 [60]; __union { unsigned int ka0c05_tlep$l_tlcon00; __struct { unsigned ka0c05_tlep$v_tlcon00_f1 : 32; } ka0c05_tlep$r_tlcon00_bits; } ka0c05_tlep$r_tlcon00_overlay; unsigned char ka0c05_tlep$b_fill440 [60]; __union { unsigned int ka0c05_tlep$l_tlcon00a; __struct { unsigned ka0c05_tlep$v_tlcon00a_f1 : 32; } ka0c05_tlep$r_tlcon00a_bits; } ka0c05_tlep$r_tlcon00a_overlay; unsigned char ka0c05_tlep$b_fill450 [60]; __union { unsigned int ka0c05_tlep$l_tlcon00b; __struct { unsigned ka0c05_tlep$v_tlcon00b_f1 : 32; } ka0c05_tlep$r_tlcon00b_bits; } ka0c05_tlep$r_tlcon00b_overlay; unsigned char ka0c05_tlep$b_fill460 [60]; __union { unsigned int ka0c05_tlep$l_tlcon00c; __struct { unsigned ka0c05_tlep$v_tlcon00c_f1 : 32; } ka0c05_tlep$r_tlcon00c_bits; } ka0c05_tlep$r_tlcon00c_overlay; unsigned char ka0c05_tlep$b_fill470 [60]; __union { unsigned int ka0c05_tlep$l_tlcon10; __struct { unsigned ka0c05_tlep$v_tlcon10_f1 : 32; } ka0c05_tlep$r_tlcon10_bits; } ka0c05_tlep$r_tlcon10_overlay; unsigned char ka0c05_tlep$b_fill480 [60]; __union { unsigned int ka0c05_tlep$l_tlcon10a; __struct { unsigned ka0c05_tlep$v_tlcon10a_f1 : 32; } ka0c05_tlep$r_tlcon10a_bits; } ka0c05_tlep$r_tlcon10a_overlay; unsigned char ka0c05_tlep$b_fill490 [60]; __union { unsigned int ka0c05_tlep$l_tlcon10b; __struct { unsigned ka0c05_tlep$v_tlcon10b_f1 : 32; } ka0c05_tlep$r_tlcon10b_bits; } ka0c05_tlep$r_tlcon10b_overlay; unsigned char ka0c05_tlep$b_fill500 [60]; __union { unsigned int ka0c05_tlep$l_tlcon10c; __struct { unsigned ka0c05_tlep$v_tlcon10c_f1 : 32; } ka0c05_tlep$r_tlcon10c_bits; } ka0c05_tlep$r_tlcon10c_overlay; unsigned char ka0c05_tlep$b_fill510 [60]; __union { unsigned int ka0c05_tlep$l_tlcon01; __struct { unsigned ka0c05_tlep$v_tlcon01_f1 : 32; } ka0c05_tlep$r_tlcon01_bits; } ka0c05_tlep$r_tlcon01_overlay; unsigned char ka0c05_tlep$b_fill520 [60]; __union { unsigned int ka0c05_tlep$l_tlcon11; __struct { unsigned ka0c05_tlep$v_tlcon11_f1 : 32; } ka0c05_tlep$r_tlcon11_bits; } ka0c05_tlep$r_tlcon11_overlay; unsigned char ka0c05_tlep$b_fill530 [188]; __union { unsigned int ka0c05_tlep$l_tlepaerr; __struct { unsigned ka0c05_tlep$v_tlepaerr_e2mape0 : 1; unsigned ka0c05_tlep$v_tlepaerr_e2mape1 : 1; unsigned ka0c05_tlep$v_tlepaerr_m2aape0 : 1; unsigned ka0c05_tlep$v_tlepaerr_m2aape1 : 1; unsigned ka0c05_tlep$v_tlepaerr_dtdpe : 1; unsigned ka0c05_tlep$v_tlepaerr_dtspe : 1; unsigned ka0c05_tlep$v_tlepaerr_d2acpe : 1; unsigned ka0c05_tlep$v_tlepaerr_sysderr : 1; unsigned ka0c05_tlep$v_tlepaerr_sysflt : 1; unsigned ka0c05_tlep$v_tlepaerr_rd_err : 2; unsigned ka0c05_tlep$v_tlepaerr_iboxto : 2; unsigned ka0c05_tlep$v_tlepaerr_rd_pend : 2; unsigned ka0c05_tlep$v_tlepaerr_nxm : 1; unsigned ka0c05_tlep$v_tlepaerr_no_ack : 2; unsigned ka0c05_tlep$v_tlepaerr_f1 : 14; } ka0c05_tlep$r_tlepaerr_bits; } ka0c05_tlep$r_tlepaerr_overlay; unsigned char ka0c05_tlep$b_fill540 [60]; __union { unsigned int ka0c05_tlep$l_tlepderr; __struct { unsigned ka0c05_tlep$v_tlepderr_a2dcpe : 1; unsigned ka0c05_tlep$v_tlepderr_d2dcpe0 : 1; unsigned ka0c05_tlep$v_tlepderr_gbto : 1; unsigned ka0c05_tlep$v_tlepderr_f1 : 29; } ka0c05_tlep$r_tlepderr_bits; } ka0c05_tlep$r_tlepderr_overlay; unsigned char ka0c05_tlep$b_fill550 [60]; __union { unsigned int ka0c05_tlep$l_tlepmerr; __struct { unsigned ka0c05_tlep$v_tlepmerr_a2mape0 : 1; unsigned ka0c05_tlep$v_tlepmerr_a2mape1 : 1; unsigned ka0c05_tlep$v_tlepmerr_d2mcpe : 1; unsigned ka0c05_tlep$v_tlepmerr_d2dcpe1 : 1; unsigned ka0c05_tlep$v_tlepmerr_d2dcpe2 : 1; unsigned ka0c05_tlep$v_tlepmerr_d2dcpe3 : 1; unsigned ka0c05_tlep$v_tlepmerr_rststat : 1; unsigned ka0c05_tlep$v_tlepmerr_f1 : 25; } ka0c05_tlep$r_tlepmerr_bits; } ka0c05_tlep$r_tlepmerr_overlay; unsigned char ka0c05_tlep$b_fill560 [60]; __union { unsigned int ka0c05_tlep$l_tlep_vmg; __struct { unsigned ka0c05_tlep$v_tlep_vmg_5p : 1; unsigned ka0c05_tlep$v_tlep_vmg_5m : 1; unsigned ka0c05_tlep$v_tlep_vmg_3p : 1; unsigned ka0c05_tlep$v_tlep_vmg_3m : 1; unsigned ka0c05_tlep$v_tlep_vmg_f1 : 28; } ka0c05_tlep$r_tlep_vmg_bits; } ka0c05_tlep$r_tlep_vmg_overlay; unsigned char ka0c05_tlep$b_fill570 [60]; __union { unsigned int ka0c05_tlep$l_tldmcmd; __struct { unsigned ka0c05_tlep$v_tldmcmd_size_512 : 1; unsigned ka0c05_tlep$v_tldmcmd_size_1k : 1; unsigned ka0c05_tlep$v_tldmcmd_size_2k : 1; unsigned ka0c05_tlep$v_tldmcmd_size_4k : 1; unsigned ka0c05_tlep$v_tldmcmd_size_8k : 1; unsigned ka0c05_tlep$v_tldmcmd_f1 : 3; unsigned ka0c05_tlep$v_tldmcmd_cmd : 2; unsigned ka0c05_tlep$v_tldmcmd_f2 : 1; unsigned ka0c05_tlep$v_tldmcmd_valid : 1; unsigned ka0c05_tlep$v_tldmcmd_rm_3 : 1; unsigned ka0c05_tlep$v_tldmcmd_rm_4 : 1; unsigned ka0c05_tlep$v_tldmcmd_rm_inlv : 1; unsigned ka0c05_tlep$v_tldmcmd_fill3 : 1; unsigned ka0c05_tlep$v_tldmcmd_cpu_id : 1; unsigned ka0c05_tlep$v_tldmcmd_fill4 : 3; unsigned ka0c05_tlep$v_tldmcmd_in_prog : 1; unsigned ka0c05_tlep$v_tldmcmd_done : 1; unsigned ka0c05_tlep$v_tldmcmd_fill5 : 10; } ka0c05_tlep$r_tldmcmd_bits; } ka0c05_tlep$r_tldmcmd_overlay; unsigned char ka0c05_tlep$b_fill580 [124]; __union { unsigned int ka0c05_tlep$l_tldmadra; __struct { unsigned ka0c05_tlep$v_tldmadra_addr : 30; unsigned ka0c05_tlep$v_tldmadra_f1 : 2; } ka0c05_tlep$r_tldmadra_bits; } ka0c05_tlep$r_tldmadra_overlay; unsigned char ka0c05_tlep$b_fill590 [60]; __union { unsigned int ka0c05_tlep$l_tldmadrb; __struct { unsigned ka0c05_tlep$v_tldmadrb_addr : 30; unsigned ka0c05_tlep$v_tldmadrb_f1 : 2; } ka0c05_tlep$r_tldmadrb_bits; } ka0c05_tlep$r_tldmadrb_overlay; unsigned char ka0c05_tlep$b_fill600 [316]; __union { unsigned int ka0c05_tlep$l_tlpm_cmd; __struct { unsigned ka0c05_tlep$v_tlpm_cmd_cpunum : 1; unsigned ka0c05_tlep$v_tlpm_cmd_set_sel : 2; unsigned ka0c05_tlep$v_tlpm_cmd_valid : 1; unsigned ka0c05_tlep$v_tlpm_cmd_read_set : 1; unsigned ka0c05_tlep$v_tlpm_cmd_f1 : 6; unsigned ka0c05_tlep$v_tlpm_cmd_ovrf_en : 1; unsigned ka0c05_tlep$v_tlpm_cmd_tot_cyc : 1; unsigned ka0c05_tlep$v_tlpm_cmd_ev5_lat : 1; unsigned ka0c05_tlep$v_tlpm_cmd_rd_lat : 1; unsigned ka0c05_tlep$v_tlpm_cmd_sys_own : 1; unsigned ka0c05_tlep$v_tlpm_cmd_f2 : 1; unsigned ka0c05_tlep$v_tlpm_cmd_lock : 1; unsigned ka0c05_tlep$v_tlpm_cmd_mb : 1; unsigned ka0c05_tlep$v_tlpm_cmd_sd_tot : 1; unsigned ka0c05_tlep$v_tlpm_cmd_sd_ack : 1; unsigned ka0c05_tlep$v_tlpm_cmd_rd_csr : 1; unsigned ka0c05_tlep$v_tlpm_cmd_rd : 1; unsigned ka0c05_tlep$v_tlpm_cmd_rd_mod : 1; unsigned ka0c05_tlep$v_tlpm_cmd_rd_stc : 1; unsigned ka0c05_tlep$v_tlpm_cmd_vic : 1; unsigned ka0c05_tlep$v_tlpm_cmd_wr_csr : 1; unsigned ka0c05_tlep$v_tlpm_cmd_wr : 1; unsigned ka0c05_tlep$v_tlpm_cmd_wr_lock : 1; unsigned ka0c05_tlep$v_tlpm_cmd_inval : 1; unsigned ka0c05_tlep$v_tlpm_cmd_set_shr : 1; unsigned ka0c05_tlep$v_tlpm_cmd_rd_dirt : 1; } ka0c05_tlep$r_tlpm_cmd_bits; } ka0c05_tlep$r_tlpm_cmd_overlay; unsigned char ka0c05_tlep$b_fill610 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_tot_cycles; __struct { unsigned ka0c05_tlep$v_tlpm_tot_cycles_f1 : 32; } ka0c05_tlep$r_tlpm_tot_cycles_bits; } ka0c05_tlep$r_tlpm_tot_cycles_over; unsigned char ka0c05_tlep$b_fill620 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_ev5_lat; __struct { unsigned ka0c05_tlep$v_tlpm_ev5_lat_f1 : 32; } ka0c05_tlep$r_tlpm_ev5_lat_bits; } ka0c05_tlep$r_tlpm_ev5_lat_overlay; unsigned char ka0c05_tlep$b_fill630 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_read_lat; __struct { unsigned ka0c05_tlep$v_tlpm_read_lat_f1 : 32; } ka0c05_tlep$r_tlpm_read_lat_bits; } ka0c05_tlep$r_tlpm_read_lat_overla; unsigned char ka0c05_tlep$b_fill640 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_owner; __struct { unsigned ka0c05_tlep$v_tlpm_owner_f1 : 32; } ka0c05_tlep$r_tlpm_owner_bits; } ka0c05_tlep$r_tlpm_owner_overlay; unsigned char ka0c05_tlep$b_fill650 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_silo; __struct { unsigned ka0c05_tlep$v_tlpm_silo_f1 : 32; } ka0c05_tlep$r_tlpm_silo_bits; } ka0c05_tlep$r_tlpm_silo_overlay; unsigned char ka0c05_tlep$b_fill660 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_lock; __struct { unsigned ka0c05_tlep$v_tlpm_lock_f1 : 32; } ka0c05_tlep$r_tlpm_lock_bits; } ka0c05_tlep$r_tlpm_lock_overlay; unsigned char ka0c05_tlep$b_fill670 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_mb; __struct { unsigned ka0c05_tlep$v_tlpm_mb_f1 : 32; } ka0c05_tlep$r_tlpm_mb_bits; } ka0c05_tlep$r_tlpm_mb_overlay; unsigned char ka0c05_tlep$b_fill680 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_sd; __struct { unsigned ka0c05_tlep$v_tlpm_sd_f1 : 32; } ka0c05_tlep$r_tlpm_sd_bits; } ka0c05_tlep$r_tlpm_sd_overlay; unsigned char ka0c05_tlep$b_fill690 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_sd_ack; __struct { unsigned ka0c05_tlep$v_tlpm_sd_ack_f1 : 32; } ka0c05_tlep$r_tlpm_sd_ack_bits; } ka0c05_tlep$r_tlpm_sd_ack_overlay; unsigned char ka0c05_tlep$b_fill700 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_rd_csr; __struct { unsigned ka0c05_tlep$v_tlpm_rd_csr_f1 : 32; } ka0c05_tlep$r_tlpm_rd_csr_bits; } ka0c05_tlep$r_tlpm_rd_csr_overlay; unsigned char ka0c05_tlep$b_fill710 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_rd_miss; __struct { unsigned ka0c05_tlep$v_tlpm_rd_miss_f1 : 32; } ka0c05_tlep$r_tlpm_rd_miss_bits; } ka0c05_tlep$r_tlpm_rd_miss_overlay; unsigned char ka0c05_tlep$b_fill720 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_rd_mod; __struct { unsigned ka0c05_tlep$v_tlpm_rd_mod_f1 : 32; } ka0c05_tlep$r_tlpm_rd_mod_bits; } ka0c05_tlep$r_tlpm_rd_mod_overlay; unsigned char ka0c05_tlep$b_fill730 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_rd_stc; __struct { unsigned ka0c05_tlep$v_tlpm_rd_stc_f1 : 32; } ka0c05_tlep$r_tlpm_rd_stc_bits; } ka0c05_tlep$r_tlpm_rd_stc_overlay; unsigned char ka0c05_tlep$b_fill740 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_victim; __struct { unsigned ka0c05_tlep$v_tlpm_victim_f1 : 32; } ka0c05_tlep$r_tlpm_victim_bits; } ka0c05_tlep$r_tlpm_victim_overlay; unsigned char ka0c05_tlep$b_fill750 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_wr_csr; __struct { unsigned ka0c05_tlep$v_tlpm_wr_csr_f1 : 32; } ka0c05_tlep$r_tlpm_wr_csr_bits; } ka0c05_tlep$r_tlpm_wr_csr_overlay; unsigned char ka0c05_tlep$b_fill760 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_wr; __struct { unsigned ka0c05_tlep$v_tlpm_wr_f1 : 32; } ka0c05_tlep$r_tlpm_wr_bits; } ka0c05_tlep$r_tlpm_wr_overlay; unsigned char ka0c05_tlep$b_fill770 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_wr_lock; __struct { unsigned ka0c05_tlep$v_tlpm_wr_lock_f1 : 32; } ka0c05_tlep$r_tlpm_wr_lock_bits; } ka0c05_tlep$r_tlpm_wr_lock_overlay; unsigned char ka0c05_tlep$b_fill780 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_inval; __struct { unsigned ka0c05_tlep$v_tlpm_inval_f1 : 32; } ka0c05_tlep$r_tlpm_inval_bits; } ka0c05_tlep$r_tlpm_inval_overlay; unsigned char ka0c05_tlep$b_fill790 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_s_shrd; __struct { unsigned ka0c05_tlep$v_tlpm_s_shrd_f1 : 32; } ka0c05_tlep$r_tlpm_s_shrd_bits; } ka0c05_tlep$r_tlpm_s_shrd_overlay; unsigned char ka0c05_tlep$b_fill800 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_rd; __struct { unsigned ka0c05_tlep$v_tlpm_rd_f1 : 32; } ka0c05_tlep$r_tlpm_rd_bits; } ka0c05_tlep$r_tlpm_rd_overlay; unsigned char ka0c05_tlep$b_fill810 [60]; __union { unsigned int ka0c05_tlep$l_tlpm_asilo; __struct { unsigned ka0c05_tlep$v_tlpm_asilo_f1 : 32; } ka0c05_tlep$r_tlpm_asilo_bits; } ka0c05_tlep$r_tlpm_asilo_overlay; unsigned char ka0c05_tlep$b_fill820 [60]; __union { unsigned int ka0c05_tlep$l_rm_reg0a; __struct { unsigned ka0c05_tlep$v_rm_reg0a_aext : 4; unsigned ka0c05_tlep$v_rm_reg0a_f1 : 4; unsigned ka0c05_tlep$v_rm_reg0a_baddr : 20; unsigned ka0c05_tlep$v_rm_reg0a_f2 : 3; unsigned ka0c05_tlep$v_rm_reg0a_valid : 1; } ka0c05_tlep$r_rm_reg0a_bits; } ka0c05_tlep$r_rm_reg0a_overlay; unsigned char ka0c05_tlep$b_fill830 [60]; __union { unsigned int ka0c05_tlep$l_rm_reg0b; __struct { unsigned ka0c05_tlep$v_rm_reg0b_aext : 4; unsigned ka0c05_tlep$v_rm_reg0b_f1 : 4; unsigned ka0c05_tlep$v_rm_reg0b_baddr : 20; unsigned ka0c05_tlep$v_rm_reg0b_f2 : 3; unsigned ka0c05_tlep$v_rm_reg0b_valid : 1; } ka0c05_tlep$r_rm_reg0b_bits; } ka0c05_tlep$r_rm_reg0b_overlay; unsigned char ka0c05_tlep$b_fill840 [60]; __union { unsigned int ka0c05_tlep$l_rm_reg1a; __struct { unsigned ka0c05_tlep$v_rm_reg1a_aext : 4; unsigned ka0c05_tlep$v_rm_reg1a_f1 : 4; unsigned ka0c05_tlep$v_rm_reg1a_baddr : 20; unsigned ka0c05_tlep$v_rm_reg1a_f2 : 3; unsigned ka0c05_tlep$v_rm_reg1a_valid : 1; } ka0c05_tlep$r_rm_reg1a_bits; } ka0c05_tlep$r_rm_reg1a_overlay; unsigned char ka0c05_tlep$b_fill850 [60]; __union { unsigned int ka0c05_tlep$l_rm_reg1b; __struct { unsigned ka0c05_tlep$v_rm_reg1b_aext : 4; unsigned ka0c05_tlep$v_rm_reg1b_f1 : 4; unsigned ka0c05_tlep$v_rm_reg1b_baddr : 20; unsigned ka0c05_tlep$v_rm_reg1b_f2 : 3; unsigned ka0c05_tlep$v_rm_reg1b_valid : 1; } ka0c05_tlep$r_rm_reg1b_bits; } ka0c05_tlep$r_rm_reg1b_overlay; unsigned char ka0c05_tlep$b_fill860 [316]; } KA0C05_TLEP; #if !defined(__VAXC) #define ka0c05_tlep$l_tldev ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$l_tldev #define ka0c05_tlep$v_tldev_dtype ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$r_tldev_bits.ka0c05_tlep$v_tldev_dtype #define ka0c05_tlep$v_tldev_swrev ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$r_tldev_bits.ka0c05_tlep$v_tldev_swrev #define ka0c05_tlep$v_tldev_hwrev ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$r_tldev_bits.ka0c05_tlep$v_tldev_hwrev #define ka0c05_tlep$l_tlber ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$l_tlber #define ka0c05_tlep$v_tlber_atce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_atce #define ka0c05_tlep$v_tlber_ape ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ape #define ka0c05_tlep$v_tlber_bbe ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_bbe #define ka0c05_tlep$v_tlber_lkto ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_lkto #define ka0c05_tlep$v_tlber_nae ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_nae #define ka0c05_tlep$v_tlber_rtce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_rtce #define ka0c05_tlep$v_tlber_acktce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_acktce #define ka0c05_tlep$v_tlber_mmre ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_mmre #define ka0c05_tlep$v_tlber_fnae ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_fnae #define ka0c05_tlep$v_tlber_reqde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_reqde #define ka0c05_tlep$v_tlber_atde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_atde #define ka0c05_tlep$v_tlber_ude ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ude #define ka0c05_tlep$v_tlber_cwde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_cwde #define ka0c05_tlep$v_tlber_crde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_crde #define ka0c05_tlep$v_tlber_ds0 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds0 #define ka0c05_tlep$v_tlber_ds1 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds1 #define ka0c05_tlep$v_tlber_ds2 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds2 #define ka0c05_tlep$v_tlber_ds3 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds3 #define ka0c05_tlep$v_tlber_dtde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dtde #define ka0c05_tlep$v_tlber_fdtce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_fdtce #define ka0c05_tlep$v_tlber_uacke ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_uacke #define ka0c05_tlep$v_tlber_abtce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_abtce #define ka0c05_tlep$v_tlber_dctce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dctce #define ka0c05_tlep$v_tlber_seqe ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_seqe #define ka0c05_tlep$v_tlber_dse ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dse #define ka0c05_tlep$v_tlber_dto ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dto #define ka0c05_tlep$l_tlcnr ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$l_tlcnr #define ka0c05_tlep$v_tlcnr_cwdd ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_cwdd #define ka0c05_tlep$v_tlcnr_crdd ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_crdd #define ka0c05_tlep$v_tlcnr_dtod ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_dtod #define ka0c05_tlep$v_tlcnr_node_id ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_node_id #define ka0c05_tlep$v_tlcnr_vcnt ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_vcnt #define ka0c05_tlep$v_tlcnr_stf_a ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_stf_a #define ka0c05_tlep$v_tlcnr_stf_b ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_stf_b #define ka0c05_tlep$v_tlcnr_halt_a ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_halt_a #define ka0c05_tlep$v_tlcnr_halt_b ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_halt_b #define ka0c05_tlep$v_tlcnr_nrst ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_nrst #define ka0c05_tlep$v_tlcnr_lofe ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_lofe #define ka0c05_tlep$l_tlvid ka0c05_tlep$r_tlvid_overlay.ka0c05_tlep$l_tlvid #define ka0c05_tlep$v_vid_a ka0c05_tlep$r_tlvid_overlay.ka0c05_tlep$r_tlvid_bits.ka0c05_tlep$v_vid_a #define ka0c05_tlep$v_vid_b ka0c05_tlep$r_tlvid_overlay.ka0c05_tlep$r_tlvid_bits.ka0c05_tlep$v_vid_b #define ka0c05_tlep$l_tlmmr0 ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$l_tlmmr0 #define ka0c05_tlep$v_tlmmr0_intmask ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_intmask #define ka0c05_tlep$v_tlmmr0_adrmask ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_adrmask #define ka0c05_tlep$v_tlmmr0_intlv ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_intlv #define ka0c05_tlep$v_tlmmr0_sbank ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_sbank #define ka0c05_tlep$v_tlmmr0_address ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_address #define ka0c05_tlep$v_tlmmr0_valid ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_valid #define ka0c05_tlep$l_tlmmr1 ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$l_tlmmr1 #define ka0c05_tlep$v_tlmmr1_intmask ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_intmask #define ka0c05_tlep$v_tlmmr1_adrmask ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_adrmask #define ka0c05_tlep$v_tlmmr1_intlv ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_intlv #define ka0c05_tlep$v_tlmmr1_sbank ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_sbank #define ka0c05_tlep$v_tlmmr1_address ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_address #define ka0c05_tlep$v_tlmmr1_valid ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_valid #define ka0c05_tlep$l_tlmmr2 ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$l_tlmmr2 #define ka0c05_tlep$v_tlmmr2_intmask ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_intmask #define ka0c05_tlep$v_tlmmr2_adrmask ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_adrmask #define ka0c05_tlep$v_tlmmr2_intlv ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_intlv #define ka0c05_tlep$v_tlmmr2_sbank ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_sbank #define ka0c05_tlep$v_tlmmr2_address ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_address #define ka0c05_tlep$v_tlmmr2_valid ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_valid #define ka0c05_tlep$l_tlmmr3 ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$l_tlmmr3 #define ka0c05_tlep$v_tlmmr3_intmask ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_intmask #define ka0c05_tlep$v_tlmmr3_adrmask ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_adrmask #define ka0c05_tlep$v_tlmmr3_intlv ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_intlv #define ka0c05_tlep$v_tlmmr3_sbank ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_sbank #define ka0c05_tlep$v_tlmmr3_address ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_address #define ka0c05_tlep$v_tlmmr3_valid ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_valid #define ka0c05_tlep$l_tlmmr4 ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$l_tlmmr4 #define ka0c05_tlep$v_tlmmr4_intmask ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_intmask #define ka0c05_tlep$v_tlmmr4_adrmask ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_adrmask #define ka0c05_tlep$v_tlmmr4_intlv ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_intlv #define ka0c05_tlep$v_tlmmr4_sbank ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_sbank #define ka0c05_tlep$v_tlmmr4_address ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_address #define ka0c05_tlep$v_tlmmr4_valid ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_valid #define ka0c05_tlep$l_tlmmr5 ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$l_tlmmr5 #define ka0c05_tlep$v_tlmmr5_intmask ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_intmask #define ka0c05_tlep$v_tlmmr5_adrmask ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_adrmask #define ka0c05_tlep$v_tlmmr5_intlv ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_intlv #define ka0c05_tlep$v_tlmmr5_sbank ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_sbank #define ka0c05_tlep$v_tlmmr5_address ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_address #define ka0c05_tlep$v_tlmmr5_valid ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_valid #define ka0c05_tlep$l_tlmmr6 ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$l_tlmmr6 #define ka0c05_tlep$v_tlmmr6_intmask ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_intmask #define ka0c05_tlep$v_tlmmr6_adrmask ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_adrmask #define ka0c05_tlep$v_tlmmr6_intlv ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_intlv #define ka0c05_tlep$v_tlmmr6_sbank ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_sbank #define ka0c05_tlep$v_tlmmr6_address ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_address #define ka0c05_tlep$v_tlmmr6_valid ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_valid #define ka0c05_tlep$l_tlmmr7 ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$l_tlmmr7 #define ka0c05_tlep$v_tlmmr7_intmask ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_intmask #define ka0c05_tlep$v_tlmmr7_adrmask ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_adrmask #define ka0c05_tlep$v_tlmmr7_intlv ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_intlv #define ka0c05_tlep$v_tlmmr7_sbank ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_sbank #define ka0c05_tlep$v_tlmmr7_address ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_address #define ka0c05_tlep$v_tlmmr7_valid ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_valid #define ka0c05_tlep$l_tlesr0 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$l_tlesr0 #define ka0c05_tlep$v_tlesr0_synd0 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_synd0 #define ka0c05_tlep$v_tlesr0_synd1 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_synd1 #define ka0c05_tlep$v_tlesr0_tde ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_tde #define ka0c05_tlep$v_tlesr0_tce ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_tce #define ka0c05_tlep$v_tlesr0_dvtce ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_dvtce #define ka0c05_tlep$v_tlesr0_uecc ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_uecc #define ka0c05_tlep$v_tlesr0_cwecc ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_cwecc #define ka0c05_tlep$v_tlesr0_crecc ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_crecc #define ka0c05_tlep$v_tlesr0_cpu0 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_cpu0 #define ka0c05_tlep$v_tlesr0_cpu1 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_cpu1 #define ka0c05_tlep$v_tlesr0_lofsyn ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_lofsyn #define ka0c05_tlep$l_tlesr1 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$l_tlesr1 #define ka0c05_tlep$v_tlesr1_synd0 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_synd0 #define ka0c05_tlep$v_tlesr1_synd1 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_synd1 #define ka0c05_tlep$v_tlesr1_tde ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_tde #define ka0c05_tlep$v_tlesr1_tce ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_tce #define ka0c05_tlep$v_tlesr1_dvtce ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_dvtce #define ka0c05_tlep$v_tlesr1_uecc ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_uecc #define ka0c05_tlep$v_tlesr1_cwecc ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_cwecc #define ka0c05_tlep$v_tlesr1_crecc ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_crecc #define ka0c05_tlep$v_tlesr1_cpu0 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_cpu0 #define ka0c05_tlep$v_tlesr1_cpu1 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_cpu1 #define ka0c05_tlep$v_tlesr1_lofsyn ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_lofsyn #define ka0c05_tlep$l_tlesr2 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$l_tlesr2 #define ka0c05_tlep$v_tlesr2_synd0 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_synd0 #define ka0c05_tlep$v_tlesr2_synd1 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_synd1 #define ka0c05_tlep$v_tlesr2_tde ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_tde #define ka0c05_tlep$v_tlesr2_tce ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_tce #define ka0c05_tlep$v_tlesr2_dvtce ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_dvtce #define ka0c05_tlep$v_tlesr2_uecc ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_uecc #define ka0c05_tlep$v_tlesr2_cwecc ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_cwecc #define ka0c05_tlep$v_tlesr2_crecc ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_crecc #define ka0c05_tlep$v_tlesr2_cpu0 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_cpu0 #define ka0c05_tlep$v_tlesr2_cpu1 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_cpu1 #define ka0c05_tlep$v_tlesr2_lofsyn ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_lofsyn #define ka0c05_tlep$l_tlesr3 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$l_tlesr3 #define ka0c05_tlep$v_tlesr3_synd0 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_synd0 #define ka0c05_tlep$v_tlesr3_synd1 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_synd1 #define ka0c05_tlep$v_tlesr3_tde ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_tde #define ka0c05_tlep$v_tlesr3_tce ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_tce #define ka0c05_tlep$v_tlesr3_dvtce ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_dvtce #define ka0c05_tlep$v_tlesr3_uecc ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_uecc #define ka0c05_tlep$v_tlesr3_cwecc ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_cwecc #define ka0c05_tlep$v_tlesr3_crecc ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_crecc #define ka0c05_tlep$v_tlesr3_cpu0 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_cpu0 #define ka0c05_tlep$v_tlesr3_cpu1 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_cpu1 #define ka0c05_tlep$v_tlesr3_lofsyn ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_lofsyn #define ka0c05_tlep$l_tldiag ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$l_tldiag #define ka0c05_tlep$v_tldiag_frign ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_frign #define ka0c05_tlep$v_tldiag_dtwr ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_dtwr #define ka0c05_tlep$v_tldiag_dtrd ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_dtrd #define ka0c05_tlep$v_tldiag_dtcp ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_dtcp #define ka0c05_tlep$v_tldiag_fvw ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fvw #define ka0c05_tlep$v_tldiag_fae ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fae #define ka0c05_tlep$v_tldiag_fcbe ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fcbe #define ka0c05_tlep$v_tldiag_fdbe ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fdbe #define ka0c05_tlep$v_tldiag_fde ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fde #define ka0c05_tlep$v_tldiag_ftw ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_ftw #define ka0c05_tlep$v_tldiag_asrt_flt ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_asrt_flt #define ka0c05_tlep$v_tldiag_qwval_en ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_qwval_en #define ka0c05_tlep$v_tldiag_gslow ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_gslow #define ka0c05_tlep$l_tldtagd ka0c05_tlep$r_tldtagd_overlay.ka0c05_tlep$l_tldtagd #define ka0c05_tlep$v_tldtagd_dtag_par ka0c05_tlep$r_tldtagd_overlay.ka0c05_tlep$r_tldtagd_bits.ka0c05_tlep$v_tldtagd_dtag_par #define ka0c05_tlep$v_tldtagd_dtag_data ka0c05_tlep$r_tldtagd_overlay.ka0c05_tlep$r_tldtagd_bits.ka0c05_tlep$v_tldtagd_dtag_data #define ka0c05_tlep$l_tldtags ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$l_tldtags #define ka0c05_tlep$v_tldtags_statpar ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statpar #define ka0c05_tlep$v_tldtags_statd ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statd #define ka0c05_tlep$v_tldtags_stats ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_stats #define ka0c05_tlep$v_tldtags_statv ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statv #define ka0c05_tlep$l_tlmcfg ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$l_tlmcfg #define ka0c05_tlep$v_tlmcfg_cpu0dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_cpu0dsbl #define ka0c05_tlep$v_tlmcfg_cpu1dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_cpu1dsbl #define ka0c05_tlep$v_tlmcfg_bc_size ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_bc_size #define ka0c05_tlep$v_tlmcfg_lo_en ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_lo_en #define ka0c05_tlep$v_tlmcfg_rm_size ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_rm_size #define ka0c05_tlep$v_tlmcfg_bcidle ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_bcidle #define ka0c05_tlep$v_tlmcfg_cq_entry ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_cq_entry #define ka0c05_tlep$v_tlmcfg_bq_entry ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_bq_entry #define ka0c05_tlep$v_tlmcfg_sys_dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_sys_dsbl #define ka0c05_tlep$v_tlmcfg_ev5_dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_ev5_dsbl #define ka0c05_tlep$v_tlmcfg_flt_dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_flt_dsbl #define ka0c05_tlep$l_tlimask0 ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$l_tlimask0 #define ka0c05_tlep$v_tlimask0_duart0en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_duart0en #define ka0c05_tlep$v_tlimask0_ipl14_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl14_en #define ka0c05_tlep$v_tlimask0_ipl15_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl15_en #define ka0c05_tlep$v_tlimask0_ipl16_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl16_en #define ka0c05_tlep$v_tlimask0_ipl17_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl17_en #define ka0c05_tlep$v_tlimask0_ip_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ip_en #define ka0c05_tlep$v_tlimask0_intim_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_intim_en #define ka0c05_tlep$v_tlimask0_halt_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_halt_en #define ka0c05_tlep$v_tlimask0_cp_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_cp_en #define ka0c05_tlep$l_tlimask1 ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$l_tlimask1 #define ka0c05_tlep$v_tlimask1_duart0en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_duart0en #define ka0c05_tlep$v_tlimask1_ipl14_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl14_en #define ka0c05_tlep$v_tlimask1_ipl15_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl15_en #define ka0c05_tlep$v_tlimask1_ipl16_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl16_en #define ka0c05_tlep$v_tlimask1_ipl17_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl17_en #define ka0c05_tlep$v_tlimask1_ip_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ip_en #define ka0c05_tlep$v_tlimask1_intim_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_intim_en #define ka0c05_tlep$v_tlimask1_halt_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_halt_en #define ka0c05_tlep$v_tlimask1_cp_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_cp_en #define ka0c05_tlep$l_tlisum0 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$l_tlisum0 #define ka0c05_tlep$v_tlisum0_duart0int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_duart0int #define ka0c05_tlep$v_tlisum0_ipl14_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl14_int #define ka0c05_tlep$v_tlisum0_ipl15_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl15_int #define ka0c05_tlep$v_tlisum0_ipl16_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl16_int #define ka0c05_tlep$v_tlisum0_ipl17_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl17_int #define ka0c05_tlep$v_tlisum0_ip_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ip_int #define ka0c05_tlep$v_tlisum0_intim_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_intim_int #define ka0c05_tlep$v_tlisum0_ipl14 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl14 #define ka0c05_tlep$v_tlisum0_ipl15 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl15 #define ka0c05_tlep$v_tlisum0_ipl16 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl16 #define ka0c05_tlep$v_tlisum0_ipl17 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl17 #define ka0c05_tlep$v_tlisum0_cp_halt ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_cp_halt #define ka0c05_tlep$v_tlisum0_halt ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_halt #define ka0c05_tlep$l_tlisum1 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$l_tlisum1 #define ka0c05_tlep$v_tlisum1_duart0int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_duart0int #define ka0c05_tlep$v_tlisum1_ipl14_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl14_int #define ka0c05_tlep$v_tlisum1_ipl15_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl15_int #define ka0c05_tlep$v_tlisum1_ipl16_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl16_int #define ka0c05_tlep$v_tlisum1_ipl17_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl17_int #define ka0c05_tlep$v_tlisum1_ip_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ip_int #define ka0c05_tlep$v_tlisum1_intim_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_intim_int #define ka0c05_tlep$v_tlisum1_ipl14 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl14 #define ka0c05_tlep$v_tlisum1_ipl15 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl15 #define ka0c05_tlep$v_tlisum1_ipl16 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl16 #define ka0c05_tlep$v_tlisum1_ipl17 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl17 #define ka0c05_tlep$v_tlisum1_cp_halt ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_cp_halt #define ka0c05_tlep$v_tlisum1_halt ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_halt #define ka0c05_tlep$l_tlcon00 ka0c05_tlep$r_tlcon00_overlay.ka0c05_tlep$l_tlcon00 #define ka0c05_tlep$l_tlcon00a ka0c05_tlep$r_tlcon00a_overlay.ka0c05_tlep$l_tlcon00a #define ka0c05_tlep$l_tlcon00b ka0c05_tlep$r_tlcon00b_overlay.ka0c05_tlep$l_tlcon00b #define ka0c05_tlep$l_tlcon00c ka0c05_tlep$r_tlcon00c_overlay.ka0c05_tlep$l_tlcon00c #define ka0c05_tlep$l_tlcon10 ka0c05_tlep$r_tlcon10_overlay.ka0c05_tlep$l_tlcon10 #define ka0c05_tlep$l_tlcon10a ka0c05_tlep$r_tlcon10a_overlay.ka0c05_tlep$l_tlcon10a #define ka0c05_tlep$l_tlcon10b ka0c05_tlep$r_tlcon10b_overlay.ka0c05_tlep$l_tlcon10b #define ka0c05_tlep$l_tlcon10c ka0c05_tlep$r_tlcon10c_overlay.ka0c05_tlep$l_tlcon10c #define ka0c05_tlep$l_tlcon01 ka0c05_tlep$r_tlcon01_overlay.ka0c05_tlep$l_tlcon01 #define ka0c05_tlep$l_tlcon11 ka0c05_tlep$r_tlcon11_overlay.ka0c05_tlep$l_tlcon11 #define ka0c05_tlep$l_tlepaerr ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$l_tlepaerr #define ka0c05_tlep$v_tlepaerr_e2mape0 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_e2mape0 #define ka0c05_tlep$v_tlepaerr_e2mape1 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_e2mape1 #define ka0c05_tlep$v_tlepaerr_m2aape0 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_m2aape0 #define ka0c05_tlep$v_tlepaerr_m2aape1 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_m2aape1 #define ka0c05_tlep$v_tlepaerr_dtdpe ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_dtdpe #define ka0c05_tlep$v_tlepaerr_dtspe ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_dtspe #define ka0c05_tlep$v_tlepaerr_d2acpe ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_d2acpe #define ka0c05_tlep$v_tlepaerr_sysderr ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_sysderr #define ka0c05_tlep$v_tlepaerr_sysflt ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_sysflt #define ka0c05_tlep$v_tlepaerr_rd_err ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_rd_err #define ka0c05_tlep$v_tlepaerr_iboxto ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_iboxto #define ka0c05_tlep$v_tlepaerr_rd_pend ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_rd_pend #define ka0c05_tlep$v_tlepaerr_nxm ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_nxm #define ka0c05_tlep$v_tlepaerr_no_ack ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_no_ack #define ka0c05_tlep$l_tlepderr ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$l_tlepderr #define ka0c05_tlep$v_tlepderr_a2dcpe ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$r_tlepderr_bits.ka0c05_tlep$v_tlepderr_a2dcpe #define ka0c05_tlep$v_tlepderr_d2dcpe0 ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$r_tlepderr_bits.ka0c05_tlep$v_tlepderr_d2dcpe0 #define ka0c05_tlep$v_tlepderr_gbto ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$r_tlepderr_bits.ka0c05_tlep$v_tlepderr_gbto #define ka0c05_tlep$l_tlepmerr ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$l_tlepmerr #define ka0c05_tlep$v_tlepmerr_a2mape0 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_a2mape0 #define ka0c05_tlep$v_tlepmerr_a2mape1 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_a2mape1 #define ka0c05_tlep$v_tlepmerr_d2mcpe ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2mcpe #define ka0c05_tlep$v_tlepmerr_d2dcpe1 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2dcpe1 #define ka0c05_tlep$v_tlepmerr_d2dcpe2 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2dcpe2 #define ka0c05_tlep$v_tlepmerr_d2dcpe3 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2dcpe3 #define ka0c05_tlep$v_tlepmerr_rststat ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_rststat #define ka0c05_tlep$l_tlep_vmg ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$l_tlep_vmg #define ka0c05_tlep$v_tlep_vmg_5p ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_5p #define ka0c05_tlep$v_tlep_vmg_5m ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_5m #define ka0c05_tlep$v_tlep_vmg_3p ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_3p #define ka0c05_tlep$v_tlep_vmg_3m ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_3m #define ka0c05_tlep$l_tldmcmd ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$l_tldmcmd #define ka0c05_tlep$v_tldmcmd_size_512 ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_512 #define ka0c05_tlep$v_tldmcmd_size_1k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_1k #define ka0c05_tlep$v_tldmcmd_size_2k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_2k #define ka0c05_tlep$v_tldmcmd_size_4k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_4k #define ka0c05_tlep$v_tldmcmd_size_8k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_8k #define ka0c05_tlep$v_tldmcmd_cmd ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_cmd #define ka0c05_tlep$v_tldmcmd_valid ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_valid #define ka0c05_tlep$v_tldmcmd_rm_3 ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_rm_3 #define ka0c05_tlep$v_tldmcmd_rm_4 ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_rm_4 #define ka0c05_tlep$v_tldmcmd_rm_inlv ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_rm_inlv #define ka0c05_tlep$v_tldmcmd_cpu_id ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_cpu_id #define ka0c05_tlep$v_tldmcmd_in_prog ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_in_prog #define ka0c05_tlep$v_tldmcmd_done ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_done #define ka0c05_tlep$l_tldmadra ka0c05_tlep$r_tldmadra_overlay.ka0c05_tlep$l_tldmadra #define ka0c05_tlep$v_tldmadra_addr ka0c05_tlep$r_tldmadra_overlay.ka0c05_tlep$r_tldmadra_bits.ka0c05_tlep$v_tldmadra_addr #define ka0c05_tlep$l_tldmadrb ka0c05_tlep$r_tldmadrb_overlay.ka0c05_tlep$l_tldmadrb #define ka0c05_tlep$v_tldmadrb_addr ka0c05_tlep$r_tldmadrb_overlay.ka0c05_tlep$r_tldmadrb_bits.ka0c05_tlep$v_tldmadrb_addr #define ka0c05_tlep$l_tlpm_cmd ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$l_tlpm_cmd #define ka0c05_tlep$v_tlpm_cmd_cpunum ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_cpunum #define ka0c05_tlep$v_tlpm_cmd_set_sel ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_set_sel #define ka0c05_tlep$v_tlpm_cmd_valid ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_valid #define ka0c05_tlep$v_tlpm_cmd_read_set ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_read_set #define ka0c05_tlep$v_tlpm_cmd_ovrf_en ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_ovrf_en #define ka0c05_tlep$v_tlpm_cmd_tot_cyc ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_tot_cyc #define ka0c05_tlep$v_tlpm_cmd_ev5_lat ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_ev5_lat #define ka0c05_tlep$v_tlpm_cmd_rd_lat ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_lat #define ka0c05_tlep$v_tlpm_cmd_sys_own ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_sys_own #define ka0c05_tlep$v_tlpm_cmd_f2 ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_f2 #define ka0c05_tlep$v_tlpm_cmd_lock ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_lock #define ka0c05_tlep$v_tlpm_cmd_mb ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_mb #define ka0c05_tlep$v_tlpm_cmd_sd_tot ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_sd_tot #define ka0c05_tlep$v_tlpm_cmd_sd_ack ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_sd_ack #define ka0c05_tlep$v_tlpm_cmd_rd_csr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_csr #define ka0c05_tlep$v_tlpm_cmd_rd ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd #define ka0c05_tlep$v_tlpm_cmd_rd_mod ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_mod #define ka0c05_tlep$v_tlpm_cmd_rd_stc ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_stc #define ka0c05_tlep$v_tlpm_cmd_vic ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_vic #define ka0c05_tlep$v_tlpm_cmd_wr_csr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_wr_csr #define ka0c05_tlep$v_tlpm_cmd_wr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_wr #define ka0c05_tlep$v_tlpm_cmd_wr_lock ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_wr_lock #define ka0c05_tlep$v_tlpm_cmd_inval ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_inval #define ka0c05_tlep$v_tlpm_cmd_set_shr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_set_shr #define ka0c05_tlep$v_tlpm_cmd_rd_dirt ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_dirt #define ka0c05_tlep$l_tlpm_tot_cycles ka0c05_tlep$r_tlpm_tot_cycles_over.ka0c05_tlep$l_tlpm_tot_cycles #define ka0c05_tlep$l_tlpm_ev5_lat ka0c05_tlep$r_tlpm_ev5_lat_overlay.ka0c05_tlep$l_tlpm_ev5_lat #define ka0c05_tlep$l_tlpm_read_lat ka0c05_tlep$r_tlpm_read_lat_overla.ka0c05_tlep$l_tlpm_read_lat #define ka0c05_tlep$l_tlpm_owner ka0c05_tlep$r_tlpm_owner_overlay.ka0c05_tlep$l_tlpm_owner #define ka0c05_tlep$l_tlpm_silo ka0c05_tlep$r_tlpm_silo_overlay.ka0c05_tlep$l_tlpm_silo #define ka0c05_tlep$l_tlpm_lock ka0c05_tlep$r_tlpm_lock_overlay.ka0c05_tlep$l_tlpm_lock #define ka0c05_tlep$l_tlpm_mb ka0c05_tlep$r_tlpm_mb_overlay.ka0c05_tlep$l_tlpm_mb #define ka0c05_tlep$l_tlpm_sd ka0c05_tlep$r_tlpm_sd_overlay.ka0c05_tlep$l_tlpm_sd #define ka0c05_tlep$l_tlpm_sd_ack ka0c05_tlep$r_tlpm_sd_ack_overlay.ka0c05_tlep$l_tlpm_sd_ack #define ka0c05_tlep$l_tlpm_rd_csr ka0c05_tlep$r_tlpm_rd_csr_overlay.ka0c05_tlep$l_tlpm_rd_csr #define ka0c05_tlep$l_tlpm_rd_miss ka0c05_tlep$r_tlpm_rd_miss_overlay.ka0c05_tlep$l_tlpm_rd_miss #define ka0c05_tlep$l_tlpm_rd_mod ka0c05_tlep$r_tlpm_rd_mod_overlay.ka0c05_tlep$l_tlpm_rd_mod #define ka0c05_tlep$l_tlpm_rd_stc ka0c05_tlep$r_tlpm_rd_stc_overlay.ka0c05_tlep$l_tlpm_rd_stc #define ka0c05_tlep$l_tlpm_victim ka0c05_tlep$r_tlpm_victim_overlay.ka0c05_tlep$l_tlpm_victim #define ka0c05_tlep$l_tlpm_wr_csr ka0c05_tlep$r_tlpm_wr_csr_overlay.ka0c05_tlep$l_tlpm_wr_csr #define ka0c05_tlep$l_tlpm_wr ka0c05_tlep$r_tlpm_wr_overlay.ka0c05_tlep$l_tlpm_wr #define ka0c05_tlep$l_tlpm_wr_lock ka0c05_tlep$r_tlpm_wr_lock_overlay.ka0c05_tlep$l_tlpm_wr_lock #define ka0c05_tlep$l_tlpm_inval ka0c05_tlep$r_tlpm_inval_overlay.ka0c05_tlep$l_tlpm_inval #define ka0c05_tlep$l_tlpm_s_shrd ka0c05_tlep$r_tlpm_s_shrd_overlay.ka0c05_tlep$l_tlpm_s_shrd #define ka0c05_tlep$l_tlpm_rd ka0c05_tlep$r_tlpm_rd_overlay.ka0c05_tlep$l_tlpm_rd #define ka0c05_tlep$l_tlpm_asilo ka0c05_tlep$r_tlpm_asilo_overlay.ka0c05_tlep$l_tlpm_asilo #define ka0c05_tlep$l_rm_reg0a ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$l_rm_reg0a #define ka0c05_tlep$v_rm_reg0a_aext ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$r_rm_reg0a_bits.ka0c05_tlep$v_rm_reg0a_aext #define ka0c05_tlep$v_rm_reg0a_baddr ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$r_rm_reg0a_bits.ka0c05_tlep$v_rm_reg0a_baddr #define ka0c05_tlep$v_rm_reg0a_valid ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$r_rm_reg0a_bits.ka0c05_tlep$v_rm_reg0a_valid #define ka0c05_tlep$l_rm_reg0b ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$l_rm_reg0b #define ka0c05_tlep$v_rm_reg0b_aext ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$r_rm_reg0b_bits.ka0c05_tlep$v_rm_reg0b_aext #define ka0c05_tlep$v_rm_reg0b_baddr ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$r_rm_reg0b_bits.ka0c05_tlep$v_rm_reg0b_baddr #define ka0c05_tlep$v_rm_reg0b_valid ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$r_rm_reg0b_bits.ka0c05_tlep$v_rm_reg0b_valid #define ka0c05_tlep$l_rm_reg1a ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$l_rm_reg1a #define ka0c05_tlep$v_rm_reg1a_aext ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$r_rm_reg1a_bits.ka0c05_tlep$v_rm_reg1a_aext #define ka0c05_tlep$v_rm_reg1a_baddr ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$r_rm_reg1a_bits.ka0c05_tlep$v_rm_reg1a_baddr #define ka0c05_tlep$v_rm_reg1a_valid ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$r_rm_reg1a_bits.ka0c05_tlep$v_rm_reg1a_valid #define ka0c05_tlep$l_rm_reg1b ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$l_rm_reg1b #define ka0c05_tlep$v_rm_reg1b_aext ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$r_rm_reg1b_bits.ka0c05_tlep$v_rm_reg1b_aext #define ka0c05_tlep$v_rm_reg1b_baddr ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$r_rm_reg1b_bits.ka0c05_tlep$v_rm_reg1b_baddr #define ka0c05_tlep$v_rm_reg1b_valid ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$r_rm_reg1b_bits.ka0c05_tlep$v_rm_reg1b_valid #endif /* #if !defined(__VAXC) */ #define KA0C08_TLEP$M_TLDEV_DTYPE 0xFFFF #define KA0C08_TLEP$M_TLDEV_SWREV 0xFF0000 #define KA0C08_TLEP$M_TLDEV_HWREV 0xFF000000 #define KA0C08_TLEP$M_TLBER_ATCE 0x1 #define KA0C08_TLEP$M_TLBER_APE 0x2 #define KA0C08_TLEP$M_TLBER_BBE 0x4 #define KA0C08_TLEP$M_TLBER_LKTO 0x8 #define KA0C08_TLEP$M_TLBER_NAE 0x10 #define KA0C08_TLEP$M_TLBER_RTCE 0x20 #define KA0C08_TLEP$M_TLBER_ACKTCE 0x40 #define KA0C08_TLEP$M_TLBER_MMRE 0x80 #define KA0C08_TLEP$M_TLBER_FNAE 0x100 #define KA0C08_TLEP$M_TLBER_REQDE 0x200 #define KA0C08_TLEP$M_TLBER_ATDE 0x400 #define KA0C08_TLEP$M_TLBER_UDE 0x10000 #define KA0C08_TLEP$M_TLBER_CWDE 0x20000 #define KA0C08_TLEP$M_TLBER_CRDE 0x40000 #define KA0C08_TLEP$M_TLBER_DS0 0x100000 #define KA0C08_TLEP$M_TLBER_DS1 0x200000 #define KA0C08_TLEP$M_TLBER_DS2 0x400000 #define KA0C08_TLEP$M_TLBER_DS3 0x800000 #define KA0C08_TLEP$M_TLBER_DTDE 0x1000000 #define KA0C08_TLEP$M_TLBER_FDTCE 0x2000000 #define KA0C08_TLEP$M_TLBER_UACKE 0x4000000 #define KA0C08_TLEP$M_TLBER_ABTCE 0x8000000 #define KA0C08_TLEP$M_TLBER_DCTCE 0x10000000 #define KA0C08_TLEP$M_TLBER_SEQE 0x20000000 #define KA0C08_TLEP$M_TLBER_DSE 0x40000000 #define KA0C08_TLEP$M_TLBER_DTO 0x80000000 #define KA0C08_TLEP$M_TLCNR_CWDD 0x1 #define KA0C08_TLEP$M_TLCNR_CRDD 0x2 #define KA0C08_TLEP$M_TLCNR_DTOD 0x8 #define KA0C08_TLEP$M_TLCNR_NODE_ID 0xF0 #define KA0C08_TLEP$M_TLCNR_VCNT 0xF00 #define KA0C08_TLEP$M_TLCNR_STF_A 0x1000 #define KA0C08_TLEP$M_TLCNR_STF_B 0x2000 #define KA0C08_TLEP$M_TLCNR_HALT_A 0x100000 #define KA0C08_TLEP$M_TLCNR_HALT_B 0x200000 #define KA0C08_TLEP$M_TLCNR_NRST 0x40000000 #define KA0C08_TLEP$M_TLCNR_LOFE 0x80000000 #define KA0C08_TLEP$M_VID_A 0xF #define KA0C08_TLEP$M_VID_B 0xF0 #define KA0C08_TLEP$M_TLMMR0_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR0_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR0_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR0_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR0_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR0_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR1_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR1_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR1_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR1_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR1_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR1_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR2_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR2_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR2_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR2_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR2_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR2_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR3_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR3_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR3_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR3_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR3_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR3_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR4_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR4_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR4_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR4_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR4_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR4_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR5_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR5_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR5_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR5_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR5_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR5_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR6_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR6_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR6_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR6_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR6_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR6_VALID 0x80000000 #define KA0C08_TLEP$M_TLMMR7_INTMASK 0x3 #define KA0C08_TLEP$M_TLMMR7_ADRMASK 0xF0 #define KA0C08_TLEP$M_TLMMR7_INTLV 0x700 #define KA0C08_TLEP$M_TLMMR7_SBANK 0x800 #define KA0C08_TLEP$M_TLMMR7_ADDRESS 0x3FFF000 #define KA0C08_TLEP$M_TLMMR7_VALID 0x80000000 #define KA0C08_TLEP$M_TLESR0_SYND0 0xFF #define KA0C08_TLEP$M_TLESR0_SYND1 0xFF00 #define KA0C08_TLEP$M_TLESR0_TDE 0x10000 #define KA0C08_TLEP$M_TLESR0_TCE 0x20000 #define KA0C08_TLEP$M_TLESR0_DVTCE 0x40000 #define KA0C08_TLEP$M_TLESR0_UECC 0x80000 #define KA0C08_TLEP$M_TLESR0_CWECC 0x100000 #define KA0C08_TLEP$M_TLESR0_CRECC 0x200000 #define KA0C08_TLEP$M_TLESR0_CPU0 0x400000 #define KA0C08_TLEP$M_TLESR0_CPU1 0x800000 #define KA0C08_TLEP$M_TLESR0_LOFSYN 0x80000000 #define KA0C08_TLEP$M_TLESR1_SYND0 0xFF #define KA0C08_TLEP$M_TLESR1_SYND1 0xFF00 #define KA0C08_TLEP$M_TLESR1_TDE 0x10000 #define KA0C08_TLEP$M_TLESR1_TCE 0x20000 #define KA0C08_TLEP$M_TLESR1_DVTCE 0x40000 #define KA0C08_TLEP$M_TLESR1_UECC 0x80000 #define KA0C08_TLEP$M_TLESR1_CWECC 0x100000 #define KA0C08_TLEP$M_TLESR1_CRECC 0x200000 #define KA0C08_TLEP$M_TLESR1_CPU0 0x400000 #define KA0C08_TLEP$M_TLESR1_CPU1 0x800000 #define KA0C08_TLEP$M_TLESR1_LOFSYN 0x80000000 #define KA0C08_TLEP$M_TLESR2_SYND0 0xFF #define KA0C08_TLEP$M_TLESR2_SYND1 0xFF00 #define KA0C08_TLEP$M_TLESR2_TDE 0x10000 #define KA0C08_TLEP$M_TLESR2_TCE 0x20000 #define KA0C08_TLEP$M_TLESR2_DVTCE 0x40000 #define KA0C08_TLEP$M_TLESR2_UECC 0x80000 #define KA0C08_TLEP$M_TLESR2_CWECC 0x100000 #define KA0C08_TLEP$M_TLESR2_CRECC 0x200000 #define KA0C08_TLEP$M_TLESR2_CPU0 0x400000 #define KA0C08_TLEP$M_TLESR2_CPU1 0x800000 #define KA0C08_TLEP$M_TLESR2_LOFSYN 0x80000000 #define KA0C08_TLEP$M_TLESR3_SYND0 0xFF #define KA0C08_TLEP$M_TLESR3_SYND1 0xFF00 #define KA0C08_TLEP$M_TLESR3_TDE 0x10000 #define KA0C08_TLEP$M_TLESR3_TCE 0x20000 #define KA0C08_TLEP$M_TLESR3_DVTCE 0x40000 #define KA0C08_TLEP$M_TLESR3_UECC 0x80000 #define KA0C08_TLEP$M_TLESR3_CWECC 0x100000 #define KA0C08_TLEP$M_TLESR3_CRECC 0x200000 #define KA0C08_TLEP$M_TLESR3_CPU0 0x400000 #define KA0C08_TLEP$M_TLESR3_CPU1 0x800000 #define KA0C08_TLEP$M_TLESR3_LOFSYN 0x80000000 #define KA0C08_TLEP$M_TLMODCFG0_FRIGN 0x1 #define KA0C08_TLEP$M_TLMODCFG0_FDE0 0x2 #define KA0C08_TLEP$M_TLMODCFG0_FDE1 0x4 #define KA0C08_TLEP$M_TLMODCFG0_P1_UDE 0x8 #define KA0C08_TLEP$M_TLMODCFG0_P1_CRDE 0x10 #define KA0C08_TLEP$M_TLMODCFG0_DLY_IN 0x20 #define KA0C08_TLEP$M_TLMODCFG0_DLY_OUT 0x40 #define KA0C08_TLEP$M_TLMODCFG0_DPQ_MAX 0x380 #define KA0C08_TLEP$M_TLMODCFG0_MMRE_DS 0x400 #define KA0C08_TLEP$M_TLMODCFG0_FASTFLS 0x800 #define KA0C08_TLEP$M_TLMODCFG0_DELAY_A 0x1000 #define KA0C08_TLEP$M_TLMODCFG0_ILGLCSR 0x2000 #define KA0C08_TLEP$M_TLMODCFG0_E_SLOWR 0x4000 #define KA0C08_TLEP$M_TLMODCFG0_ASRT_FT 0x8000 #define KA0C08_TLEP$M_TLMODCFG0_DTAG_PE 0x10000 #define KA0C08_TLEP$M_TLMODCFG0_DTAG0_D 0x20000 #define KA0C08_TLEP$M_TLMODCFG0_DTAG1_D 0x40000 #define KA0C08_TLEP$M_TLMODCFG0_D_WRAP 0x80000 #define KA0C08_TLEP$M_TLMODCFG0_BQ_MAX 0x700000 #define KA0C08_TLEP$M_TLMODCFG0_BC_SIZE 0x1800000 #define KA0C08_TLEP$M_TLMODCFG0_FDE_CMD 0x1E000000 #define KA0C08_TLEP$M_TLMODCFG0_FSBE 0x20000000 #define KA0C08_TLEP$M_TLMODCFG0_FDE2 0x40000000 #define KA0C08_TLEP$M_TLMODCFG0_FDE3 0x80000000 #define KA0C08_TLEP$M_TLDTAGDATA_PAR 0x1 #define KA0C08_TLEP$M_TLDTAGDATA_DATA 0x3FFFE #define KA0C08_TLEP$M_TLDTAGADDR_ADDR 0x3FFFF #define KA0C08_TLEP$M_TLDTAGADDR_CPU_SL 0x1000000 #define KA0C08_TLEP$M_TLMODCFG1_OVRTK_E 0x1 #define KA0C08_TLEP$M_TLMODCFG1_P0_RID 0xE #define KA0C08_TLEP$M_TLMODCFG1_P1_RID 0x70 #define KA0C08_TLEP$M_TLMODCFG1_MBPR_RY 0x180 #define KA0C08_TLEP$M_TLMODCFG1_FAULT_D 0x200 #define KA0C08_TLEP$M_TLMODCFG1_FSTRQ_D 0x400 #define KA0C08_TLEP$M_TLMODCFG1_P0_RQ_D 0x800 #define KA0C08_TLEP$M_TLMODCFG1_P1_RQ_D 0x1000 #define KA0C08_TLEP$M_TLMODCFG1_D_PROBE 0x6000 #define KA0C08_TLEP$M_TLMODCFG1_FSTPTH 0x8000 #define KA0C08_TLEP$M_TLMODCFG1_DLSB_PR 0x10000 #define KA0C08_TLEP$M_TLMODCFG1_VIC_SKP 0x20000 #define KA0C08_TLEP$M_TLMODCFG1_FRCE_SQ 0x40000 #define KA0C08_TLEP$M_TLMODCFG1_DB_BUB 0x80000 #define KA0C08_TLEP$M_TLMODCFG1_FST_VQ 0x100000 #define KA0C08_TLEP$M_TLMODCFG1_FST_PRQ 0x200000 #define KA0C08_TLEP$M_TLMODCFG1_BUSWRTE 0x400000 #define KA0C08_TLEP$M_TLMODCFG1_FST_WRT 0x800000 #define KA0C08_TLEP$M_TLMODCFG1_FRC_SHR 0x1000000 #define KA0C08_TLEP$M_TLMODCFG1_VQRBCTL 0x2000000 #define KA0C08_TLEP$M_TLMODCFG1_CSR_SIZ 0x4000000 #define KA0C08_TLEP$M_TLIMASK0_DUART0EN 0x1 #define KA0C08_TLEP$M_TLIMASK0_IPL14_EN 0x2 #define KA0C08_TLEP$M_TLIMASK0_IPL15_EN 0x4 #define KA0C08_TLEP$M_TLIMASK0_IPL16_EN 0x8 #define KA0C08_TLEP$M_TLIMASK0_IPL17_EN 0x10 #define KA0C08_TLEP$M_TLIMASK0_IP_EN 0x20 #define KA0C08_TLEP$M_TLIMASK0_INTIM_EN 0x40 #define KA0C08_TLEP$M_TLIMASK0_HALT_EN 0x80 #define KA0C08_TLEP$M_TLIMASK0_CP_EN 0x100 #define KA0C08_TLEP$M_TLIMASK1_DUART0EN 0x1 #define KA0C08_TLEP$M_TLIMASK1_IPL14_EN 0x2 #define KA0C08_TLEP$M_TLIMASK1_IPL15_EN 0x4 #define KA0C08_TLEP$M_TLIMASK1_IPL16_EN 0x8 #define KA0C08_TLEP$M_TLIMASK1_IPL17_EN 0x10 #define KA0C08_TLEP$M_TLIMASK1_IP_EN 0x20 #define KA0C08_TLEP$M_TLIMASK1_INTIM_EN 0x40 #define KA0C08_TLEP$M_TLIMASK1_HALT_EN 0x80 #define KA0C08_TLEP$M_TLIMASK1_CP_EN 0x100 #define KA0C08_TLEP$M_TLISUM0_DUART0INT 0x1 #define KA0C08_TLEP$M_TLISUM0_IPL14_INT 0x2 #define KA0C08_TLEP$M_TLISUM0_IPL15_INT 0x4 #define KA0C08_TLEP$M_TLISUM0_IPL16_INT 0x8 #define KA0C08_TLEP$M_TLISUM0_IPL17_INT 0x10 #define KA0C08_TLEP$M_TLISUM0_IP_INT 0x20 #define KA0C08_TLEP$M_TLISUM0_INTIM_INT 0x40 #define KA0C08_TLEP$M_TLISUM0_IPL14 0xF80 #define KA0C08_TLEP$M_TLISUM0_IPL15 0x1F000 #define KA0C08_TLEP$M_TLISUM0_IPL16 0x3E0000 #define KA0C08_TLEP$M_TLISUM0_IPL17 0x7C00000 #define KA0C08_TLEP$M_TLISUM0_CP_HALT 0x8000000 #define KA0C08_TLEP$M_TLISUM0_HALT 0x10000000 #define KA0C08_TLEP$M_TLISUM1_DUART0INT 0x1 #define KA0C08_TLEP$M_TLISUM1_IPL14_INT 0x2 #define KA0C08_TLEP$M_TLISUM1_IPL15_INT 0x4 #define KA0C08_TLEP$M_TLISUM1_IPL16_INT 0x8 #define KA0C08_TLEP$M_TLISUM1_IPL17_INT 0x10 #define KA0C08_TLEP$M_TLISUM1_IP_INT 0x20 #define KA0C08_TLEP$M_TLISUM1_INTIM_INT 0x40 #define KA0C08_TLEP$M_TLISUM1_IPL14 0xF80 #define KA0C08_TLEP$M_TLISUM1_IPL15 0x1F000 #define KA0C08_TLEP$M_TLISUM1_IPL16 0x3E0000 #define KA0C08_TLEP$M_TLISUM1_IPL17 0x7C00000 #define KA0C08_TLEP$M_TLISUM1_CP_HALT 0x8000000 #define KA0C08_TLEP$M_TLISUM1_HALT 0x10000000 #define KA0C08_TLEP$M_TCCERR_P0_MBPR_TO 0x1 #define KA0C08_TLEP$M_TCCERR_P1_MBPR_TO 0x2 #define KA0C08_TLEP$M_TCCERR_DTPE0 0x4 #define KA0C08_TLEP$M_TCCERR_DTPE1 0x8 #define KA0C08_TLEP$M_TCCERR_SYSDERR 0x10 #define KA0C08_TLEP$M_TCCERR_WSPC_RD_ER 0x20 #define KA0C08_TLEP$M_TCCERR_SYSFAULT 0xC0 #define KA0C08_TLEP$M_TCCERR_FAULT_ASRT 0x100 #define KA0C08_TLEP$M_TCCERR_P0_FTLMMRE 0x200 #define KA0C08_TLEP$M_TCCERR_P1_FTLMMRE 0x400 #define KA0C08_TLEP$M_TCCERR_P0_MMRE 0x800 #define KA0C08_TLEP$M_TCCERR_P1_MMRE 0x1000 #define KA0C08_TLEP$M_TCCERR_CSR_WR_NXM 0x2000 #define KA0C08_TLEP$M_TCCERR_CSR_XACTN 0x4000 #define KA0C08_TLEP$M_TCCERR_TCC_REV 0xF0000 #define KA0C08_TLEP$M_TCCERR_P0_ILGLCSR 0x100000 #define KA0C08_TLEP$M_TCCERR_P1_ILGLCSR 0x200000 #define KA0C08_TLEP$M_TDIERR_GBTO 0x4 #define KA0C08_TLEP$M_TL6_VMG_5P 0x1 #define KA0C08_TLEP$M_TL6_VMG_5M 0x2 #define KA0C08_TLEP$M_TL6_VMG_3P 0x4 #define KA0C08_TLEP$M_TL6_VMG_3M 0x8 #define KA0C08_TLEP$M_TL6WERR_SELECT 0x3 #define KA0C08_TLEP$M_TL6WERR_R0_RD_PND 0x1 #define KA0C08_TLEP$M_TL6WERR_R0_ADDR 0xFFFF8 #define KA0C08_TLEP$M_TL6WERR_R1_ADDR 0x7FFFF #define KA0C08_TLEP$M_TL6WERR_R2_RD_PND 0x1 #define KA0C08_TLEP$M_TL6WERR_R2_ADDR 0xFFFF8 #define KA0C08_TLEP$M_TL6WERR_R3_ADDR 0x7FFFF #define KA0C08_TLEP$M_TLDTAGEX_F1 0xFFFFFFFF #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c08_tlep { #pragma __nomember_alignment __union { unsigned int ka0c08_tlep$l_tldev; __struct { unsigned ka0c08_tlep$v_tldev_dtype : 16; unsigned ka0c08_tlep$v_tldev_swrev : 8; unsigned ka0c08_tlep$v_tldev_hwrev : 8; } ka0c08_tlep$r_tldev_bits; } ka0c08_tlep$r_tldev_overlay; unsigned char ka0c08_tlep$b_f200 [60]; __union { unsigned int ka0c08_tlep$l_tlber; __struct { unsigned ka0c08_tlep$v_tlber_atce : 1; unsigned ka0c08_tlep$v_tlber_ape : 1; unsigned ka0c08_tlep$v_tlber_bbe : 1; unsigned ka0c08_tlep$v_tlber_lkto : 1; unsigned ka0c08_tlep$v_tlber_nae : 1; unsigned ka0c08_tlep$v_tlber_rtce : 1; unsigned ka0c08_tlep$v_tlber_acktce : 1; unsigned ka0c08_tlep$v_tlber_mmre : 1; unsigned ka0c08_tlep$v_tlber_fnae : 1; unsigned ka0c08_tlep$v_tlber_reqde : 1; unsigned ka0c08_tlep$v_tlber_atde : 1; unsigned ka0c08_tlep$v_tlber_f1 : 5; unsigned ka0c08_tlep$v_tlber_ude : 1; unsigned ka0c08_tlep$v_tlber_cwde : 1; unsigned ka0c08_tlep$v_tlber_crde : 1; unsigned ka0c08_tlep$v_tlber_cwde2 : 1; unsigned ka0c08_tlep$v_tlber_ds0 : 1; unsigned ka0c08_tlep$v_tlber_ds1 : 1; unsigned ka0c08_tlep$v_tlber_ds2 : 1; unsigned ka0c08_tlep$v_tlber_ds3 : 1; unsigned ka0c08_tlep$v_tlber_dtde : 1; unsigned ka0c08_tlep$v_tlber_fdtce : 1; unsigned ka0c08_tlep$v_tlber_uacke : 1; unsigned ka0c08_tlep$v_tlber_abtce : 1; unsigned ka0c08_tlep$v_tlber_dctce : 1; unsigned ka0c08_tlep$v_tlber_seqe : 1; unsigned ka0c08_tlep$v_tlber_dse : 1; unsigned ka0c08_tlep$v_tlber_dto : 1; } ka0c08_tlep$r_tlber_bits; } ka0c08_tlep$r_tlber_overlay; unsigned char ka0c08_tlep$b_f210 [60]; __union { unsigned int ka0c08_tlep$l_tlcnr; __struct { unsigned ka0c08_tlep$v_tlcnr_cwdd : 1; unsigned ka0c08_tlep$v_tlcnr_crdd : 1; unsigned ka0c08_tlep$v_tlcnr_f1 : 1; unsigned ka0c08_tlep$v_tlcnr_dtod : 1; unsigned ka0c08_tlep$v_tlcnr_node_id : 4; unsigned ka0c08_tlep$v_tlcnr_vcnt : 4; unsigned ka0c08_tlep$v_tlcnr_stf_a : 1; unsigned ka0c08_tlep$v_tlcnr_stf_b : 1; unsigned ka0c08_tlep$v_tlcnr_f2 : 6; unsigned ka0c08_tlep$v_tlcnr_halt_a : 1; unsigned ka0c08_tlep$v_tlcnr_halt_b : 1; unsigned ka0c08_tlep$v_tlcnr_fill3 : 8; unsigned ka0c08_tlep$v_tlcnr_nrst : 1; unsigned ka0c08_tlep$v_tlcnr_lofe : 1; } ka0c08_tlep$r_tlcnr_bits; } ka0c08_tlep$r_tlcnr_overlay; unsigned char ka0c08_tlep$b_f220 [60]; __union { unsigned int ka0c08_tlep$l_tlvid; __struct { unsigned ka0c08_tlep$v_vid_a : 4; unsigned ka0c08_tlep$v_vid_b : 4; unsigned ka0c08_tlep$v_vid_f1 : 24; } ka0c08_tlep$r_tlvid_bits; } ka0c08_tlep$r_tlvid_overlay; unsigned char ka0c08_tlep$b_f230 [316]; __union { unsigned int ka0c08_tlep$l_tlmmr0; __struct { unsigned ka0c08_tlep$v_tlmmr0_intmask : 2; unsigned ka0c08_tlep$v_tlmmr0_f1 : 2; unsigned ka0c08_tlep$v_tlmmr0_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr0_intlv : 3; unsigned ka0c08_tlep$v_tlmmr0_sbank : 1; unsigned ka0c08_tlep$v_tlmmr0_address : 14; unsigned ka0c08_tlep$v_tlmmr0_f2 : 5; unsigned ka0c08_tlep$v_tlmmr0_valid : 1; } ka0c08_tlep$r_tlmmr0_bits; } ka0c08_tlep$r_tlmmr0_overlay; unsigned char ka0c08_tlep$b_f240 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr1; __struct { unsigned ka0c08_tlep$v_tlmmr1_intmask : 2; unsigned ka0c08_tlep$v_tlmmr1_f1 : 2; unsigned ka0c08_tlep$v_tlmmr1_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr1_intlv : 3; unsigned ka0c08_tlep$v_tlmmr1_sbank : 1; unsigned ka0c08_tlep$v_tlmmr1_address : 14; unsigned ka0c08_tlep$v_tlmmr1_f2 : 5; unsigned ka0c08_tlep$v_tlmmr1_valid : 1; } ka0c08_tlep$r_tlmmr1_bits; } ka0c08_tlep$r_tlmmr1_overlay; unsigned char ka0c08_tlep$b_f250 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr2; __struct { unsigned ka0c08_tlep$v_tlmmr2_intmask : 2; unsigned ka0c08_tlep$v_tlmmr2_f1 : 2; unsigned ka0c08_tlep$v_tlmmr2_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr2_intlv : 3; unsigned ka0c08_tlep$v_tlmmr2_sbank : 1; unsigned ka0c08_tlep$v_tlmmr2_address : 14; unsigned ka0c08_tlep$v_tlmmr2_f2 : 5; unsigned ka0c08_tlep$v_tlmmr2_valid : 1; } ka0c08_tlep$r_tlmmr2_bits; } ka0c08_tlep$r_tlmmr2_overlay; unsigned char ka0c08_tlep$b_f260 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr3; __struct { unsigned ka0c08_tlep$v_tlmmr3_intmask : 2; unsigned ka0c08_tlep$v_tlmmr3_f1 : 2; unsigned ka0c08_tlep$v_tlmmr3_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr3_intlv : 3; unsigned ka0c08_tlep$v_tlmmr3_sbank : 1; unsigned ka0c08_tlep$v_tlmmr3_address : 14; unsigned ka0c08_tlep$v_tlmmr3_f2 : 5; unsigned ka0c08_tlep$v_tlmmr3_valid : 1; } ka0c08_tlep$r_tlmmr3_bits; } ka0c08_tlep$r_tlmmr3_overlay; unsigned char ka0c08_tlep$b_f270 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr4; __struct { unsigned ka0c08_tlep$v_tlmmr4_intmask : 2; unsigned ka0c08_tlep$v_tlmmr4_f1 : 2; unsigned ka0c08_tlep$v_tlmmr4_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr4_intlv : 3; unsigned ka0c08_tlep$v_tlmmr4_sbank : 1; unsigned ka0c08_tlep$v_tlmmr4_address : 14; unsigned ka0c08_tlep$v_tlmmr4_f2 : 5; unsigned ka0c08_tlep$v_tlmmr4_valid : 1; } ka0c08_tlep$r_tlmmr4_bits; } ka0c08_tlep$r_tlmmr4_overlay; unsigned char ka0c08_tlep$b_f280 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr5; __struct { unsigned ka0c08_tlep$v_tlmmr5_intmask : 2; unsigned ka0c08_tlep$v_tlmmr5_f1 : 2; unsigned ka0c08_tlep$v_tlmmr5_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr5_intlv : 3; unsigned ka0c08_tlep$v_tlmmr5_sbank : 1; unsigned ka0c08_tlep$v_tlmmr5_address : 14; unsigned ka0c08_tlep$v_tlmmr5_f2 : 5; unsigned ka0c08_tlep$v_tlmmr5_valid : 1; } ka0c08_tlep$r_tlmmr5_bits; } ka0c08_tlep$r_tlmmr5_overlay; unsigned char ka0c08_tlep$b_f290 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr6; __struct { unsigned ka0c08_tlep$v_tlmmr6_intmask : 2; unsigned ka0c08_tlep$v_tlmmr6_f1 : 2; unsigned ka0c08_tlep$v_tlmmr6_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr6_intlv : 3; unsigned ka0c08_tlep$v_tlmmr6_sbank : 1; unsigned ka0c08_tlep$v_tlmmr6_address : 14; unsigned ka0c08_tlep$v_tlmmr6_f2 : 5; unsigned ka0c08_tlep$v_tlmmr6_valid : 1; } ka0c08_tlep$r_tlmmr6_bits; } ka0c08_tlep$r_tlmmr6_overlay; unsigned char ka0c08_tlep$b_fill300 [60]; __union { unsigned int ka0c08_tlep$l_tlmmr7; __struct { unsigned ka0c08_tlep$v_tlmmr7_intmask : 2; unsigned ka0c08_tlep$v_tlmmr7_f1 : 2; unsigned ka0c08_tlep$v_tlmmr7_adrmask : 4; unsigned ka0c08_tlep$v_tlmmr7_intlv : 3; unsigned ka0c08_tlep$v_tlmmr7_sbank : 1; unsigned ka0c08_tlep$v_tlmmr7_address : 14; unsigned ka0c08_tlep$v_tlmmr7_f2 : 5; unsigned ka0c08_tlep$v_tlmmr7_valid : 1; } ka0c08_tlep$r_tlmmr7_bits; } ka0c08_tlep$r_tlmmr7_overlay; unsigned char ka0c08_tlep$b_fill310 [700]; __union { unsigned int ka0c08_tlep$l_tlesr0; __struct { unsigned ka0c08_tlep$v_tlesr0_synd0 : 8; unsigned ka0c08_tlep$v_tlesr0_synd1 : 8; unsigned ka0c08_tlep$v_tlesr0_tde : 1; unsigned ka0c08_tlep$v_tlesr0_tce : 1; unsigned ka0c08_tlep$v_tlesr0_dvtce : 1; unsigned ka0c08_tlep$v_tlesr0_uecc : 1; unsigned ka0c08_tlep$v_tlesr0_cwecc : 1; unsigned ka0c08_tlep$v_tlesr0_crecc : 1; unsigned ka0c08_tlep$v_tlesr0_cpu0 : 1; unsigned ka0c08_tlep$v_tlesr0_cpu1 : 1; unsigned ka0c08_tlep$v_tlesr0_f1 : 7; unsigned ka0c08_tlep$v_tlesr0_lofsyn : 1; } ka0c08_tlep$r_tlesr0_bits; } ka0c08_tlep$r_tlesr0_overlay; unsigned char ka0c08_tlep$b_fill320 [60]; __union { unsigned int ka0c08_tlep$l_tlesr1; __struct { unsigned ka0c08_tlep$v_tlesr1_synd0 : 8; unsigned ka0c08_tlep$v_tlesr1_synd1 : 8; unsigned ka0c08_tlep$v_tlesr1_tde : 1; unsigned ka0c08_tlep$v_tlesr1_tce : 1; unsigned ka0c08_tlep$v_tlesr1_dvtce : 1; unsigned ka0c08_tlep$v_tlesr1_uecc : 1; unsigned ka0c08_tlep$v_tlesr1_cwecc : 1; unsigned ka0c08_tlep$v_tlesr1_crecc : 1; unsigned ka0c08_tlep$v_tlesr1_cpu0 : 1; unsigned ka0c08_tlep$v_tlesr1_cpu1 : 1; unsigned ka0c08_tlep$v_tlesr1_f1 : 7; unsigned ka0c08_tlep$v_tlesr1_lofsyn : 1; } ka0c08_tlep$r_tlesr1_bits; } ka0c08_tlep$r_tlesr1_overlay; unsigned char ka0c08_tlep$b_fill330 [60]; __union { unsigned int ka0c08_tlep$l_tlesr2; __struct { unsigned ka0c08_tlep$v_tlesr2_synd0 : 8; unsigned ka0c08_tlep$v_tlesr2_synd1 : 8; unsigned ka0c08_tlep$v_tlesr2_tde : 1; unsigned ka0c08_tlep$v_tlesr2_tce : 1; unsigned ka0c08_tlep$v_tlesr2_dvtce : 1; unsigned ka0c08_tlep$v_tlesr2_uecc : 1; unsigned ka0c08_tlep$v_tlesr2_cwecc : 1; unsigned ka0c08_tlep$v_tlesr2_crecc : 1; unsigned ka0c08_tlep$v_tlesr2_cpu0 : 1; unsigned ka0c08_tlep$v_tlesr2_cpu1 : 1; unsigned ka0c08_tlep$v_tlesr2_f1 : 7; unsigned ka0c08_tlep$v_tlesr2_lofsyn : 1; } ka0c08_tlep$r_tlesr2_bits; } ka0c08_tlep$r_tlesr2_overlay; unsigned char ka0c08_tlep$b_fill340 [60]; __union { unsigned int ka0c08_tlep$l_tlesr3; __struct { unsigned ka0c08_tlep$v_tlesr3_synd0 : 8; unsigned ka0c08_tlep$v_tlesr3_synd1 : 8; unsigned ka0c08_tlep$v_tlesr3_tde : 1; unsigned ka0c08_tlep$v_tlesr3_tce : 1; unsigned ka0c08_tlep$v_tlesr3_dvtce : 1; unsigned ka0c08_tlep$v_tlesr3_uecc : 1; unsigned ka0c08_tlep$v_tlesr3_cwecc : 1; unsigned ka0c08_tlep$v_tlesr3_crecc : 1; unsigned ka0c08_tlep$v_tlesr3_cpu0 : 1; unsigned ka0c08_tlep$v_tlesr3_cpu1 : 1; unsigned ka0c08_tlep$v_tlesr3_f1 : 7; unsigned ka0c08_tlep$v_tlesr3_lofsyn : 1; } ka0c08_tlep$r_tlesr3_bits; } ka0c08_tlep$r_tlesr3_overlay; unsigned char ka0c08_tlep$b_fill350 [2236]; __union { unsigned int ka0c08_tlep$l_tlmodcfg0; __struct { unsigned ka0c08_tlep$v_tlmodcfg0_frign : 1; unsigned ka0c08_tlep$v_tlmodcfg0_fde0 : 1; unsigned ka0c08_tlep$v_tlmodcfg0_fde1 : 1; unsigned ka0c08_tlep$v_tlmodcfg0_p1_ude : 1; unsigned ka0c08_tlep$v_tlmodcfg0_p1_crde : 1; unsigned ka0c08_tlep$v_tlmodcfg0_dly_in : 1; unsigned ka0c08_tlep$v_tlmodcfg0_dly_out : 1; unsigned ka0c08_tlep$v_tlmodcfg0_dpq_max : 3; unsigned ka0c08_tlep$v_tlmodcfg0_mmre_ds : 1; unsigned ka0c08_tlep$v_tlmodcfg0_fastfls : 1; unsigned ka0c08_tlep$v_tlmodcfg0_delay_a : 1; unsigned ka0c08_tlep$v_tlmodcfg0_ilglcsr : 1; unsigned ka0c08_tlep$v_tlmodcfg0_e_slowr : 1; unsigned ka0c08_tlep$v_tlmodcfg0_asrt_ft : 1; unsigned ka0c08_tlep$v_tlmodcfg0_dtag_pe : 1; unsigned ka0c08_tlep$v_tlmodcfg0_dtag0_d : 1; unsigned ka0c08_tlep$v_tlmodcfg0_dtag1_d : 1; unsigned ka0c08_tlep$v_tlmodcfg0_d_wrap : 1; unsigned ka0c08_tlep$v_tlmodcfg0_bq_max : 3; unsigned ka0c08_tlep$v_tlmodcfg0_bc_size : 2; unsigned ka0c08_tlep$v_tlmodcfg0_fde_cmd : 4; unsigned ka0c08_tlep$v_tlmodcfg0_fsbe : 1; unsigned ka0c08_tlep$v_tlmodcfg0_fde2 : 1; unsigned ka0c08_tlep$v_tlmodcfg0_fde3 : 1; } ka0c08_tlep$r_tlmodcfg0_bits; } ka0c08_tlep$r_tlmodcfg0_overlay; unsigned char ka0c08_tlep$b_fill360 [60]; __union { unsigned int ka0c08_tlep$l_tldtagdata; __struct { unsigned ka0c08_tlep$v_tldtagdata_par : 1; unsigned ka0c08_tlep$v_tldtagdata_data : 17; unsigned ka0c08_tlep$v_tldtagdata_f1 : 14; } ka0c08_tlep$r_tldtagdata_bits; } ka0c08_tlep$r_tldtagdata_overlay; unsigned char ka0c08_tlep$b_fill370 [60]; __union { unsigned int ka0c08_tlep$l_tldtagaddr; __struct { unsigned ka0c08_tlep$v_tldtagaddr_addr : 18; unsigned ka0c08_tlep$v_tldtagaddr_f1 : 6; unsigned ka0c08_tlep$v_tldtagaddr_cpu_sl : 1; unsigned ka0c08_tlep$v_tldtagaddr_f2 : 7; } ka0c08_tlep$r_tldtagaddr_bits; } ka0c08_tlep$r_tldtagaddr_overlay; unsigned char ka0c08_tlep$b_fill380 [60]; __union { unsigned int ka0c08_tlep$l_tlmodcfg1; __struct { unsigned ka0c08_tlep$v_tlmodcfg1_ovrtk_e : 1; unsigned ka0c08_tlep$v_tlmodcfg1_p0_rid : 3; unsigned ka0c08_tlep$v_tlmodcfg1_p1_rid : 3; unsigned ka0c08_tlep$v_tlmodcfg1_mbpr_ry : 2; unsigned ka0c08_tlep$v_tlmodcfg1_fault_d : 1; unsigned ka0c08_tlep$v_tlmodcfg1_fstrq_d : 1; unsigned ka0c08_tlep$v_tlmodcfg1_p0_rq_d : 1; unsigned ka0c08_tlep$v_tlmodcfg1_p1_rq_d : 1; unsigned ka0c08_tlep$v_tlmodcfg1_d_probe : 2; unsigned ka0c08_tlep$v_tlmodcfg1_fstpth : 1; unsigned ka0c08_tlep$v_tlmodcfg1_dlsb_pr : 1; unsigned ka0c08_tlep$v_tlmodcfg1_vic_skp : 1; unsigned ka0c08_tlep$v_tlmodcfg1_frce_sq : 1; unsigned ka0c08_tlep$v_tlmodcfg1_db_bub : 1; unsigned ka0c08_tlep$v_tlmodcfg1_fst_vq : 1; unsigned ka0c08_tlep$v_tlmodcfg1_fst_prq : 1; unsigned ka0c08_tlep$v_tlmodcfg1_buswrte : 1; unsigned ka0c08_tlep$v_tlmodcfg1_fst_wrt : 1; unsigned ka0c08_tlep$v_tlmodcfg1_frc_shr : 1; unsigned ka0c08_tlep$v_tlmodcfg1_vqrbctl : 1; unsigned ka0c08_tlep$v_tlmodcfg1_csr_siz : 1; unsigned ka0c08_tlep$v_tlmodcfg1_f1 : 5; } ka0c08_tlep$r_tlmodcfg1_bits; } ka0c08_tlep$r_tlmodcfg1_overlay; unsigned char ka0c08_tlep$b_fill390 [60]; __union { unsigned int ka0c08_tlep$l_tlimask0; __struct { unsigned ka0c08_tlep$v_tlimask0_duart0en : 1; unsigned ka0c08_tlep$v_tlimask0_ipl14_en : 1; unsigned ka0c08_tlep$v_tlimask0_ipl15_en : 1; unsigned ka0c08_tlep$v_tlimask0_ipl16_en : 1; unsigned ka0c08_tlep$v_tlimask0_ipl17_en : 1; unsigned ka0c08_tlep$v_tlimask0_ip_en : 1; unsigned ka0c08_tlep$v_tlimask0_intim_en : 1; unsigned ka0c08_tlep$v_tlimask0_halt_en : 1; unsigned ka0c08_tlep$v_tlimask0_cp_en : 1; unsigned ka0c08_tlep$v_tlimask0_f1 : 23; } ka0c08_tlep$r_tlimask0_bits; } ka0c08_tlep$r_tlimask0_overlay; unsigned char ka0c08_tlep$b_fill400 [60]; __union { unsigned int ka0c08_tlep$l_tlimask1; __struct { unsigned ka0c08_tlep$v_tlimask1_duart0en : 1; unsigned ka0c08_tlep$v_tlimask1_ipl14_en : 1; unsigned ka0c08_tlep$v_tlimask1_ipl15_en : 1; unsigned ka0c08_tlep$v_tlimask1_ipl16_en : 1; unsigned ka0c08_tlep$v_tlimask1_ipl17_en : 1; unsigned ka0c08_tlep$v_tlimask1_ip_en : 1; unsigned ka0c08_tlep$v_tlimask1_intim_en : 1; unsigned ka0c08_tlep$v_tlimask1_halt_en : 1; unsigned ka0c08_tlep$v_tlimask1_cp_en : 1; unsigned ka0c08_tlep$v_tlimask1_f1 : 23; } ka0c08_tlep$r_tlimask1_bits; } ka0c08_tlep$r_tlimask1_overlay; unsigned char ka0c08_tlep$b_fill410 [60]; __union { unsigned int ka0c08_tlep$l_tlisum0; __struct { unsigned ka0c08_tlep$v_tlisum0_duart0int : 1; unsigned ka0c08_tlep$v_tlisum0_ipl14_int : 1; unsigned ka0c08_tlep$v_tlisum0_ipl15_int : 1; unsigned ka0c08_tlep$v_tlisum0_ipl16_int : 1; unsigned ka0c08_tlep$v_tlisum0_ipl17_int : 1; unsigned ka0c08_tlep$v_tlisum0_ip_int : 1; unsigned ka0c08_tlep$v_tlisum0_intim_int : 1; unsigned ka0c08_tlep$v_tlisum0_ipl14 : 5; unsigned ka0c08_tlep$v_tlisum0_ipl15 : 5; unsigned ka0c08_tlep$v_tlisum0_ipl16 : 5; unsigned ka0c08_tlep$v_tlisum0_ipl17 : 5; unsigned ka0c08_tlep$v_tlisum0_cp_halt : 1; unsigned ka0c08_tlep$v_tlisum0_halt : 1; unsigned ka0c08_tlep$v_tlisum0_f1 : 3; } ka0c08_tlep$r_tlisum0_bits; } ka0c08_tlep$r_tlisum0_overlay; unsigned char ka0c08_tlep$b_fill420 [60]; __union { unsigned int ka0c08_tlep$l_tlisum1; __struct { unsigned ka0c08_tlep$v_tlisum1_duart0int : 1; unsigned ka0c08_tlep$v_tlisum1_ipl14_int : 1; unsigned ka0c08_tlep$v_tlisum1_ipl15_int : 1; unsigned ka0c08_tlep$v_tlisum1_ipl16_int : 1; unsigned ka0c08_tlep$v_tlisum1_ipl17_int : 1; unsigned ka0c08_tlep$v_tlisum1_ip_int : 1; unsigned ka0c08_tlep$v_tlisum1_intim_int : 1; unsigned ka0c08_tlep$v_tlisum1_ipl14 : 5; unsigned ka0c08_tlep$v_tlisum1_ipl15 : 5; unsigned ka0c08_tlep$v_tlisum1_ipl16 : 5; unsigned ka0c08_tlep$v_tlisum1_ipl17 : 5; unsigned ka0c08_tlep$v_tlisum1_cp_halt : 1; unsigned ka0c08_tlep$v_tlisum1_halt : 1; unsigned ka0c08_tlep$v_tlisum1_f1 : 3; } ka0c08_tlep$r_tlisum1_bits; } ka0c08_tlep$r_tlisum1_overlay; unsigned char ka0c08_tlep$b_fill430 [60]; __union { unsigned int ka0c08_tlep$l_tlcon00; __struct { unsigned ka0c08_tlep$v_tlcon00_f1 : 32; } ka0c08_tlep$r_tlcon00_bits; } ka0c08_tlep$r_tlcon00_overlay; unsigned char ka0c08_tlep$b_fill440 [60]; __union { unsigned int ka0c08_tlep$l_tlcon00a; __struct { unsigned ka0c08_tlep$v_tlcon00a_f1 : 32; } ka0c08_tlep$r_tlcon00a_bits; } ka0c08_tlep$r_tlcon00a_overlay; unsigned char ka0c08_tlep$b_fill450 [60]; __union { unsigned int ka0c08_tlep$l_tlcon00b; __struct { unsigned ka0c08_tlep$v_tlcon00b_f1 : 32; } ka0c08_tlep$r_tlcon00b_bits; } ka0c08_tlep$r_tlcon00b_overlay; unsigned char ka0c08_tlep$b_fill460 [60]; __union { unsigned int ka0c08_tlep$l_tlcon00c; __struct { unsigned ka0c08_tlep$v_tlcon00c_f1 : 32; } ka0c08_tlep$r_tlcon00c_bits; } ka0c08_tlep$r_tlcon00c_overlay; unsigned char ka0c08_tlep$b_fill470 [60]; __union { unsigned int ka0c08_tlep$l_tlcon10; __struct { unsigned ka0c08_tlep$v_tlcon10_f1 : 32; } ka0c08_tlep$r_tlcon10_bits; } ka0c08_tlep$r_tlcon10_overlay; unsigned char ka0c08_tlep$b_fill480 [60]; __union { unsigned int ka0c08_tlep$l_tlcon10a; __struct { unsigned ka0c08_tlep$v_tlcon10a_f1 : 32; } ka0c08_tlep$r_tlcon10a_bits; } ka0c08_tlep$r_tlcon10a_overlay; unsigned char ka0c08_tlep$b_fill490 [60]; __union { unsigned int ka0c08_tlep$l_tlcon10b; __struct { unsigned ka0c08_tlep$v_tlcon10b_f1 : 32; } ka0c08_tlep$r_tlcon10b_bits; } ka0c08_tlep$r_tlcon10b_overlay; unsigned char ka0c08_tlep$b_fill500 [60]; __union { unsigned int ka0c08_tlep$l_tlcon10c; __struct { unsigned ka0c08_tlep$v_tlcon10c_f1 : 32; } ka0c08_tlep$r_tlcon10c_bits; } ka0c08_tlep$r_tlcon10c_overlay; unsigned char ka0c08_tlep$b_fill510 [60]; __union { unsigned int ka0c08_tlep$l_tlcon01; __struct { unsigned ka0c08_tlep$v_tlcon01_f1 : 32; } ka0c08_tlep$r_tlcon01_bits; } ka0c08_tlep$r_tlcon01_overlay; unsigned char ka0c08_tlep$b_fill520 [60]; __union { unsigned int ka0c08_tlep$l_tlcon11; __struct { unsigned ka0c08_tlep$v_tlcon11_f1 : 32; } ka0c08_tlep$r_tlcon11_bits; } ka0c08_tlep$r_tlcon11_overlay; unsigned char ka0c08_tlep$b_fill530 [188]; __union { unsigned int ka0c08_tlep$l_tccerr; __struct { unsigned ka0c08_tlep$v_tccerr_p0_mbpr_to : 1; unsigned ka0c08_tlep$v_tccerr_p1_mbpr_to : 1; unsigned ka0c08_tlep$v_tccerr_dtpe0 : 1; unsigned ka0c08_tlep$v_tccerr_dtpe1 : 1; unsigned ka0c08_tlep$v_tccerr_sysderr : 1; unsigned ka0c08_tlep$v_tccerr_wspc_rd_er : 1; unsigned ka0c08_tlep$v_tccerr_sysfault : 2; unsigned ka0c08_tlep$v_tccerr_fault_asrt : 1; unsigned ka0c08_tlep$v_tccerr_p0_ftlmmre : 1; unsigned ka0c08_tlep$v_tccerr_p1_ftlmmre : 1; unsigned ka0c08_tlep$v_tccerr_p0_mmre : 1; unsigned ka0c08_tlep$v_tccerr_p1_mmre : 1; unsigned ka0c08_tlep$v_tccerr_csr_wr_nxm : 1; unsigned ka0c08_tlep$v_tccerr_csr_xactn : 1; unsigned ka0c08_tlep$v_tccerr_f1 : 1; unsigned ka0c08_tlep$v_tccerr_tcc_rev : 4; unsigned ka0c08_tlep$v_tccerr_p0_ilglcsr : 1; unsigned ka0c08_tlep$v_tccerr_p1_ilglcsr : 1; unsigned ka0c08_tlep$v_tccerr_f2 : 10; } ka0c08_tlep$r_tccerr_bits; } ka0c08_tlep$r_tccerr_overlay; unsigned char ka0c08_tlep$b_fill540 [60]; __union { unsigned int ka0c08_tlep$l_tdierr; __struct { unsigned ka0c08_tlep$v_tdierr_f1 : 2; unsigned ka0c08_tlep$v_tdierr_gbto : 1; unsigned ka0c08_tlep$v_tdierr_f2 : 29; } ka0c08_tlep$r_tdierr_bits; } ka0c08_tlep$r_tdierr_overlay; unsigned char ka0c08_tlep$b_fill550 [124]; __union { unsigned int ka0c08_tlep$l_tl6_vmg; __struct { unsigned ka0c08_tlep$v_tl6_vmg_5p : 1; unsigned ka0c08_tlep$v_tl6_vmg_5m : 1; unsigned ka0c08_tlep$v_tl6_vmg_3p : 1; unsigned ka0c08_tlep$v_tl6_vmg_3m : 1; unsigned ka0c08_tlep$v_tl6_vmg_f1 : 28; } ka0c08_tlep$r_tl6_vmg_bits; } ka0c08_tlep$r_tl6_vmg_overlay; unsigned char ka0c08_tlep$b_fill570 [60]; __union { unsigned int ka0c08_tlep$l_tl6werr; __struct { unsigned ka0c08_tlep$v_tl6werr_select : 2; unsigned ka0c08_tlep$v_tl6werr_f1 : 30; } ka0c08_tlep$r_tl6werr_select_bits; __struct { unsigned ka0c08_tlep$v_tl6werr_r0_rd_pnd : 1; unsigned ka0c08_tlep$v_tl6werr_r0_f1 : 2; unsigned ka0c08_tlep$v_tl6werr_r0_addr : 17; unsigned ka0c08_tlep$v_tl6werr_r0_f2 : 12; } ka0c08_tlep$r_tl6werr_register0_bi; __struct { unsigned ka0c08_tlep$v_tl6werr_r1_addr : 19; unsigned ka0c08_tlep$v_tl6werr_r1_f1 : 13; } ka0c08_tlep$r_tl6werr_register1_bi; __struct { unsigned ka0c08_tlep$v_tl6werr_r2_rd_pnd : 1; unsigned ka0c08_tlep$v_tl6werr_r2_f1 : 2; unsigned ka0c08_tlep$v_tl6werr_r2_addr : 17; unsigned ka0c08_tlep$v_tl6werr_r2_f2 : 12; } ka0c08_tlep$r_tl6werr_register2_bi; __struct { unsigned ka0c08_tlep$v_tl6werr_r3_addr : 19; unsigned ka0c08_tlep$v_tl6werr_r3_f1 : 13; } ka0c08_tlep$r_tl6werr_register3_bi; } ka0c08_tlep$r_tl6werr_overlay; unsigned char ka0c08_tlep$b_fill580 [508]; __union { unsigned int ka0c08_tlep$l_tldtagex; __struct { unsigned ka0c08_tlep$v_tldtagex_f1 : 32; } ka0c08_tlep$r_tldtagex_bits; } ka0c08_tlep$r_tldtagex_overlay; unsigned char ka0c08_tlep$b_fill610 [60]; __union { unsigned int ka0c08_tlep$l_tlloopbck; __struct { unsigned ka0c08_tlep$v_tlloopbck_f1 : 32; } ka0c08_tlep$r_tlloopbck_bits; } ka0c08_tlep$r_tlloopbck_overlay; unsigned char ka0c08_tlep$b_fill620 [60]; } KA0C08_TLEP; #if !defined(__VAXC) #define ka0c08_tlep$l_tldev ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$l_tldev #define ka0c08_tlep$v_tldev_dtype ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$r_tldev_bits.ka0c08_tlep$v_tldev_dtype #define ka0c08_tlep$v_tldev_swrev ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$r_tldev_bits.ka0c08_tlep$v_tldev_swrev #define ka0c08_tlep$v_tldev_hwrev ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$r_tldev_bits.ka0c08_tlep$v_tldev_hwrev #define ka0c08_tlep$l_tlber ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$l_tlber #define ka0c08_tlep$v_tlber_atce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_atce #define ka0c08_tlep$v_tlber_ape ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ape #define ka0c08_tlep$v_tlber_bbe ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_bbe #define ka0c08_tlep$v_tlber_lkto ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_lkto #define ka0c08_tlep$v_tlber_nae ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_nae #define ka0c08_tlep$v_tlber_rtce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_rtce #define ka0c08_tlep$v_tlber_acktce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_acktce #define ka0c08_tlep$v_tlber_mmre ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_mmre #define ka0c08_tlep$v_tlber_fnae ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_fnae #define ka0c08_tlep$v_tlber_reqde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_reqde #define ka0c08_tlep$v_tlber_atde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_atde #define ka0c08_tlep$v_tlber_ude ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ude #define ka0c08_tlep$v_tlber_cwde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_cwde #define ka0c08_tlep$v_tlber_crde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_crde #define ka0c08_tlep$v_tlber_ds0 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds0 #define ka0c08_tlep$v_tlber_ds1 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds1 #define ka0c08_tlep$v_tlber_ds2 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds2 #define ka0c08_tlep$v_tlber_ds3 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds3 #define ka0c08_tlep$v_tlber_dtde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dtde #define ka0c08_tlep$v_tlber_fdtce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_fdtce #define ka0c08_tlep$v_tlber_uacke ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_uacke #define ka0c08_tlep$v_tlber_abtce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_abtce #define ka0c08_tlep$v_tlber_dctce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dctce #define ka0c08_tlep$v_tlber_seqe ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_seqe #define ka0c08_tlep$v_tlber_dse ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dse #define ka0c08_tlep$v_tlber_dto ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dto #define ka0c08_tlep$l_tlcnr ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$l_tlcnr #define ka0c08_tlep$v_tlcnr_cwdd ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_cwdd #define ka0c08_tlep$v_tlcnr_crdd ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_crdd #define ka0c08_tlep$v_tlcnr_dtod ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_dtod #define ka0c08_tlep$v_tlcnr_node_id ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_node_id #define ka0c08_tlep$v_tlcnr_vcnt ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_vcnt #define ka0c08_tlep$v_tlcnr_stf_a ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_stf_a #define ka0c08_tlep$v_tlcnr_stf_b ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_stf_b #define ka0c08_tlep$v_tlcnr_halt_a ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_halt_a #define ka0c08_tlep$v_tlcnr_halt_b ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_halt_b #define ka0c08_tlep$v_tlcnr_nrst ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_nrst #define ka0c08_tlep$v_tlcnr_lofe ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_lofe #define ka0c08_tlep$l_tlvid ka0c08_tlep$r_tlvid_overlay.ka0c08_tlep$l_tlvid #define ka0c08_tlep$v_vid_a ka0c08_tlep$r_tlvid_overlay.ka0c08_tlep$r_tlvid_bits.ka0c08_tlep$v_vid_a #define ka0c08_tlep$v_vid_b ka0c08_tlep$r_tlvid_overlay.ka0c08_tlep$r_tlvid_bits.ka0c08_tlep$v_vid_b #define ka0c08_tlep$l_tlmmr0 ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$l_tlmmr0 #define ka0c08_tlep$v_tlmmr0_intmask ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_intmask #define ka0c08_tlep$v_tlmmr0_adrmask ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_adrmask #define ka0c08_tlep$v_tlmmr0_intlv ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_intlv #define ka0c08_tlep$v_tlmmr0_sbank ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_sbank #define ka0c08_tlep$v_tlmmr0_address ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_address #define ka0c08_tlep$v_tlmmr0_valid ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_valid #define ka0c08_tlep$l_tlmmr1 ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$l_tlmmr1 #define ka0c08_tlep$v_tlmmr1_intmask ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_intmask #define ka0c08_tlep$v_tlmmr1_adrmask ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_adrmask #define ka0c08_tlep$v_tlmmr1_intlv ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_intlv #define ka0c08_tlep$v_tlmmr1_sbank ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_sbank #define ka0c08_tlep$v_tlmmr1_address ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_address #define ka0c08_tlep$v_tlmmr1_valid ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_valid #define ka0c08_tlep$l_tlmmr2 ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$l_tlmmr2 #define ka0c08_tlep$v_tlmmr2_intmask ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_intmask #define ka0c08_tlep$v_tlmmr2_adrmask ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_adrmask #define ka0c08_tlep$v_tlmmr2_intlv ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_intlv #define ka0c08_tlep$v_tlmmr2_sbank ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_sbank #define ka0c08_tlep$v_tlmmr2_address ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_address #define ka0c08_tlep$v_tlmmr2_valid ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_valid #define ka0c08_tlep$l_tlmmr3 ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$l_tlmmr3 #define ka0c08_tlep$v_tlmmr3_intmask ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_intmask #define ka0c08_tlep$v_tlmmr3_adrmask ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_adrmask #define ka0c08_tlep$v_tlmmr3_intlv ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_intlv #define ka0c08_tlep$v_tlmmr3_sbank ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_sbank #define ka0c08_tlep$v_tlmmr3_address ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_address #define ka0c08_tlep$v_tlmmr3_valid ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_valid #define ka0c08_tlep$l_tlmmr4 ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$l_tlmmr4 #define ka0c08_tlep$v_tlmmr4_intmask ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_intmask #define ka0c08_tlep$v_tlmmr4_adrmask ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_adrmask #define ka0c08_tlep$v_tlmmr4_intlv ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_intlv #define ka0c08_tlep$v_tlmmr4_sbank ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_sbank #define ka0c08_tlep$v_tlmmr4_address ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_address #define ka0c08_tlep$v_tlmmr4_valid ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_valid #define ka0c08_tlep$l_tlmmr5 ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$l_tlmmr5 #define ka0c08_tlep$v_tlmmr5_intmask ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_intmask #define ka0c08_tlep$v_tlmmr5_adrmask ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_adrmask #define ka0c08_tlep$v_tlmmr5_intlv ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_intlv #define ka0c08_tlep$v_tlmmr5_sbank ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_sbank #define ka0c08_tlep$v_tlmmr5_address ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_address #define ka0c08_tlep$v_tlmmr5_valid ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_valid #define ka0c08_tlep$l_tlmmr6 ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$l_tlmmr6 #define ka0c08_tlep$v_tlmmr6_intmask ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_intmask #define ka0c08_tlep$v_tlmmr6_adrmask ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_adrmask #define ka0c08_tlep$v_tlmmr6_intlv ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_intlv #define ka0c08_tlep$v_tlmmr6_sbank ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_sbank #define ka0c08_tlep$v_tlmmr6_address ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_address #define ka0c08_tlep$v_tlmmr6_valid ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_valid #define ka0c08_tlep$l_tlmmr7 ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$l_tlmmr7 #define ka0c08_tlep$v_tlmmr7_intmask ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_intmask #define ka0c08_tlep$v_tlmmr7_adrmask ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_adrmask #define ka0c08_tlep$v_tlmmr7_intlv ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_intlv #define ka0c08_tlep$v_tlmmr7_sbank ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_sbank #define ka0c08_tlep$v_tlmmr7_address ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_address #define ka0c08_tlep$v_tlmmr7_valid ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_valid #define ka0c08_tlep$l_tlesr0 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$l_tlesr0 #define ka0c08_tlep$v_tlesr0_synd0 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_synd0 #define ka0c08_tlep$v_tlesr0_synd1 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_synd1 #define ka0c08_tlep$v_tlesr0_tde ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_tde #define ka0c08_tlep$v_tlesr0_tce ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_tce #define ka0c08_tlep$v_tlesr0_dvtce ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_dvtce #define ka0c08_tlep$v_tlesr0_uecc ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_uecc #define ka0c08_tlep$v_tlesr0_cwecc ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_cwecc #define ka0c08_tlep$v_tlesr0_crecc ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_crecc #define ka0c08_tlep$v_tlesr0_cpu0 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_cpu0 #define ka0c08_tlep$v_tlesr0_cpu1 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_cpu1 #define ka0c08_tlep$v_tlesr0_lofsyn ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_lofsyn #define ka0c08_tlep$l_tlesr1 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$l_tlesr1 #define ka0c08_tlep$v_tlesr1_synd0 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_synd0 #define ka0c08_tlep$v_tlesr1_synd1 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_synd1 #define ka0c08_tlep$v_tlesr1_tde ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_tde #define ka0c08_tlep$v_tlesr1_tce ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_tce #define ka0c08_tlep$v_tlesr1_dvtce ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_dvtce #define ka0c08_tlep$v_tlesr1_uecc ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_uecc #define ka0c08_tlep$v_tlesr1_cwecc ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_cwecc #define ka0c08_tlep$v_tlesr1_crecc ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_crecc #define ka0c08_tlep$v_tlesr1_cpu0 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_cpu0 #define ka0c08_tlep$v_tlesr1_cpu1 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_cpu1 #define ka0c08_tlep$v_tlesr1_lofsyn ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_lofsyn #define ka0c08_tlep$l_tlesr2 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$l_tlesr2 #define ka0c08_tlep$v_tlesr2_synd0 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_synd0 #define ka0c08_tlep$v_tlesr2_synd1 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_synd1 #define ka0c08_tlep$v_tlesr2_tde ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_tde #define ka0c08_tlep$v_tlesr2_tce ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_tce #define ka0c08_tlep$v_tlesr2_dvtce ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_dvtce #define ka0c08_tlep$v_tlesr2_uecc ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_uecc #define ka0c08_tlep$v_tlesr2_cwecc ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_cwecc #define ka0c08_tlep$v_tlesr2_crecc ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_crecc #define ka0c08_tlep$v_tlesr2_cpu0 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_cpu0 #define ka0c08_tlep$v_tlesr2_cpu1 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_cpu1 #define ka0c08_tlep$v_tlesr2_lofsyn ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_lofsyn #define ka0c08_tlep$l_tlesr3 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$l_tlesr3 #define ka0c08_tlep$v_tlesr3_synd0 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_synd0 #define ka0c08_tlep$v_tlesr3_synd1 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_synd1 #define ka0c08_tlep$v_tlesr3_tde ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_tde #define ka0c08_tlep$v_tlesr3_tce ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_tce #define ka0c08_tlep$v_tlesr3_dvtce ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_dvtce #define ka0c08_tlep$v_tlesr3_uecc ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_uecc #define ka0c08_tlep$v_tlesr3_cwecc ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_cwecc #define ka0c08_tlep$v_tlesr3_crecc ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_crecc #define ka0c08_tlep$v_tlesr3_cpu0 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_cpu0 #define ka0c08_tlep$v_tlesr3_cpu1 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_cpu1 #define ka0c08_tlep$v_tlesr3_lofsyn ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_lofsyn #define ka0c08_tlep$l_tlmodcfg0 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$l_tlmodcfg0 #define ka0c08_tlep$v_tlmodcfg0_frign ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_frign #define ka0c08_tlep$v_tlmodcfg0_fde0 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde0 #define ka0c08_tlep$v_tlmodcfg0_fde1 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde1 #define ka0c08_tlep$v_tlmodcfg0_p1_ude ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_p1_ude #define ka0c08_tlep$v_tlmodcfg0_p1_crde ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_p1_crde #define ka0c08_tlep$v_tlmodcfg0_dly_in ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dly_in #define ka0c08_tlep$v_tlmodcfg0_dly_out ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dly_out #define ka0c08_tlep$v_tlmodcfg0_dpq_max ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dpq_max #define ka0c08_tlep$v_tlmodcfg0_mmre_ds ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_mmre_ds #define ka0c08_tlep$v_tlmodcfg0_fastfls ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fastfls #define ka0c08_tlep$v_tlmodcfg0_delay_a ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_delay_a #define ka0c08_tlep$v_tlmodcfg0_ilglcsr ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_ilglcsr #define ka0c08_tlep$v_tlmodcfg0_e_slowr ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_e_slowr #define ka0c08_tlep$v_tlmodcfg0_asrt_ft ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_asrt_ft #define ka0c08_tlep$v_tlmodcfg0_dtag_pe ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dtag_pe #define ka0c08_tlep$v_tlmodcfg0_dtag0_d ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dtag0_d #define ka0c08_tlep$v_tlmodcfg0_dtag1_d ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dtag1_d #define ka0c08_tlep$v_tlmodcfg0_d_wrap ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_d_wrap #define ka0c08_tlep$v_tlmodcfg0_bq_max ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_bq_max #define ka0c08_tlep$v_tlmodcfg0_bc_size ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_bc_size #define ka0c08_tlep$v_tlmodcfg0_fde_cmd ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde_cmd #define ka0c08_tlep$v_tlmodcfg0_fsbe ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fsbe #define ka0c08_tlep$v_tlmodcfg0_fde2 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde2 #define ka0c08_tlep$v_tlmodcfg0_fde3 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde3 #define ka0c08_tlep$l_tldtagdata ka0c08_tlep$r_tldtagdata_overlay.ka0c08_tlep$l_tldtagdata #define ka0c08_tlep$v_tldtagdata_par ka0c08_tlep$r_tldtagdata_overlay.ka0c08_tlep$r_tldtagdata_bits.ka0c08_tlep$v_tldtagdata_par #define ka0c08_tlep$v_tldtagdata_data ka0c08_tlep$r_tldtagdata_overlay.ka0c08_tlep$r_tldtagdata_bits.ka0c08_tlep$v_tldtagdata_data #define ka0c08_tlep$l_tldtagaddr ka0c08_tlep$r_tldtagaddr_overlay.ka0c08_tlep$l_tldtagaddr #define ka0c08_tlep$v_tldtagaddr_addr ka0c08_tlep$r_tldtagaddr_overlay.ka0c08_tlep$r_tldtagaddr_bits.ka0c08_tlep$v_tldtagaddr_addr #define ka0c08_tlep$v_tldtagaddr_cpu_sl ka0c08_tlep$r_tldtagaddr_overlay.ka0c08_tlep$r_tldtagaddr_bits.ka0c08_tlep$v_tldtagaddr_cpu\ _sl #define ka0c08_tlep$l_tlmodcfg1 ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$l_tlmodcfg1 #define ka0c08_tlep$v_tlmodcfg1_ovrtk_e ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_ovrtk_e #define ka0c08_tlep$v_tlmodcfg1_p0_rid ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p0_rid #define ka0c08_tlep$v_tlmodcfg1_p1_rid ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p1_rid #define ka0c08_tlep$v_tlmodcfg1_mbpr_ry ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_mbpr_ry #define ka0c08_tlep$v_tlmodcfg1_fault_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fault_d #define ka0c08_tlep$v_tlmodcfg1_fstrq_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fstrq_d #define ka0c08_tlep$v_tlmodcfg1_p0_rq_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p0_rq_d #define ka0c08_tlep$v_tlmodcfg1_p1_rq_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p1_rq_d #define ka0c08_tlep$v_tlmodcfg1_d_probe ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_d_probe #define ka0c08_tlep$v_tlmodcfg1_fstpth ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fstpth #define ka0c08_tlep$v_tlmodcfg1_dlsb_pr ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_dlsb_pr #define ka0c08_tlep$v_tlmodcfg1_vic_skp ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_vic_skp #define ka0c08_tlep$v_tlmodcfg1_frce_sq ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_frce_sq #define ka0c08_tlep$v_tlmodcfg1_db_bub ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_db_bub #define ka0c08_tlep$v_tlmodcfg1_fst_vq ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fst_vq #define ka0c08_tlep$v_tlmodcfg1_fst_prq ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fst_prq #define ka0c08_tlep$v_tlmodcfg1_buswrte ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_buswrte #define ka0c08_tlep$v_tlmodcfg1_fst_wrt ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fst_wrt #define ka0c08_tlep$v_tlmodcfg1_frc_shr ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_frc_shr #define ka0c08_tlep$v_tlmodcfg1_vqrbctl ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_vqrbctl #define ka0c08_tlep$v_tlmodcfg1_csr_siz ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_csr_siz #define ka0c08_tlep$l_tlimask0 ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$l_tlimask0 #define ka0c08_tlep$v_tlimask0_duart0en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_duart0en #define ka0c08_tlep$v_tlimask0_ipl14_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl14_en #define ka0c08_tlep$v_tlimask0_ipl15_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl15_en #define ka0c08_tlep$v_tlimask0_ipl16_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl16_en #define ka0c08_tlep$v_tlimask0_ipl17_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl17_en #define ka0c08_tlep$v_tlimask0_ip_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ip_en #define ka0c08_tlep$v_tlimask0_intim_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_intim_en #define ka0c08_tlep$v_tlimask0_halt_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_halt_en #define ka0c08_tlep$v_tlimask0_cp_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_cp_en #define ka0c08_tlep$l_tlimask1 ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$l_tlimask1 #define ka0c08_tlep$v_tlimask1_duart0en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_duart0en #define ka0c08_tlep$v_tlimask1_ipl14_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl14_en #define ka0c08_tlep$v_tlimask1_ipl15_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl15_en #define ka0c08_tlep$v_tlimask1_ipl16_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl16_en #define ka0c08_tlep$v_tlimask1_ipl17_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl17_en #define ka0c08_tlep$v_tlimask1_ip_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ip_en #define ka0c08_tlep$v_tlimask1_intim_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_intim_en #define ka0c08_tlep$v_tlimask1_halt_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_halt_en #define ka0c08_tlep$v_tlimask1_cp_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_cp_en #define ka0c08_tlep$l_tlisum0 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$l_tlisum0 #define ka0c08_tlep$v_tlisum0_duart0int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_duart0int #define ka0c08_tlep$v_tlisum0_ipl14_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl14_int #define ka0c08_tlep$v_tlisum0_ipl15_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl15_int #define ka0c08_tlep$v_tlisum0_ipl16_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl16_int #define ka0c08_tlep$v_tlisum0_ipl17_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl17_int #define ka0c08_tlep$v_tlisum0_ip_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ip_int #define ka0c08_tlep$v_tlisum0_intim_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_intim_int #define ka0c08_tlep$v_tlisum0_ipl14 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl14 #define ka0c08_tlep$v_tlisum0_ipl15 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl15 #define ka0c08_tlep$v_tlisum0_ipl16 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl16 #define ka0c08_tlep$v_tlisum0_ipl17 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl17 #define ka0c08_tlep$v_tlisum0_cp_halt ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_cp_halt #define ka0c08_tlep$v_tlisum0_halt ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_halt #define ka0c08_tlep$l_tlisum1 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$l_tlisum1 #define ka0c08_tlep$v_tlisum1_duart0int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_duart0int #define ka0c08_tlep$v_tlisum1_ipl14_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl14_int #define ka0c08_tlep$v_tlisum1_ipl15_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl15_int #define ka0c08_tlep$v_tlisum1_ipl16_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl16_int #define ka0c08_tlep$v_tlisum1_ipl17_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl17_int #define ka0c08_tlep$v_tlisum1_ip_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ip_int #define ka0c08_tlep$v_tlisum1_intim_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_intim_int #define ka0c08_tlep$v_tlisum1_ipl14 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl14 #define ka0c08_tlep$v_tlisum1_ipl15 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl15 #define ka0c08_tlep$v_tlisum1_ipl16 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl16 #define ka0c08_tlep$v_tlisum1_ipl17 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl17 #define ka0c08_tlep$v_tlisum1_cp_halt ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_cp_halt #define ka0c08_tlep$v_tlisum1_halt ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_halt #define ka0c08_tlep$l_tlcon00 ka0c08_tlep$r_tlcon00_overlay.ka0c08_tlep$l_tlcon00 #define ka0c08_tlep$l_tlcon00a ka0c08_tlep$r_tlcon00a_overlay.ka0c08_tlep$l_tlcon00a #define ka0c08_tlep$l_tlcon00b ka0c08_tlep$r_tlcon00b_overlay.ka0c08_tlep$l_tlcon00b #define ka0c08_tlep$l_tlcon00c ka0c08_tlep$r_tlcon00c_overlay.ka0c08_tlep$l_tlcon00c #define ka0c08_tlep$l_tlcon10 ka0c08_tlep$r_tlcon10_overlay.ka0c08_tlep$l_tlcon10 #define ka0c08_tlep$l_tlcon10a ka0c08_tlep$r_tlcon10a_overlay.ka0c08_tlep$l_tlcon10a #define ka0c08_tlep$l_tlcon10b ka0c08_tlep$r_tlcon10b_overlay.ka0c08_tlep$l_tlcon10b #define ka0c08_tlep$l_tlcon10c ka0c08_tlep$r_tlcon10c_overlay.ka0c08_tlep$l_tlcon10c #define ka0c08_tlep$l_tlcon01 ka0c08_tlep$r_tlcon01_overlay.ka0c08_tlep$l_tlcon01 #define ka0c08_tlep$l_tlcon11 ka0c08_tlep$r_tlcon11_overlay.ka0c08_tlep$l_tlcon11 #define ka0c08_tlep$l_tccerr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$l_tccerr #define ka0c08_tlep$v_tccerr_p0_mbpr_to ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_mbpr_to #define ka0c08_tlep$v_tccerr_p1_mbpr_to ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_mbpr_to #define ka0c08_tlep$v_tccerr_dtpe0 ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_dtpe0 #define ka0c08_tlep$v_tccerr_dtpe1 ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_dtpe1 #define ka0c08_tlep$v_tccerr_sysderr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_sysderr #define ka0c08_tlep$v_tccerr_wspc_rd_er ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_wspc_rd_er #define ka0c08_tlep$v_tccerr_sysfault ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_sysfault #define ka0c08_tlep$v_tccerr_fault_asrt ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_fault_asrt #define ka0c08_tlep$v_tccerr_p0_ftlmmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_ftlmmre #define ka0c08_tlep$v_tccerr_p1_ftlmmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_ftlmmre #define ka0c08_tlep$v_tccerr_p0_mmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_mmre #define ka0c08_tlep$v_tccerr_p1_mmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_mmre #define ka0c08_tlep$v_tccerr_csr_wr_nxm ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_csr_wr_nxm #define ka0c08_tlep$v_tccerr_csr_xactn ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_csr_xactn #define ka0c08_tlep$v_tccerr_tcc_rev ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_tcc_rev #define ka0c08_tlep$v_tccerr_p0_ilglcsr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_ilglcsr #define ka0c08_tlep$v_tccerr_p1_ilglcsr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_ilglcsr #define ka0c08_tlep$l_tdierr ka0c08_tlep$r_tdierr_overlay.ka0c08_tlep$l_tdierr #define ka0c08_tlep$v_tdierr_gbto ka0c08_tlep$r_tdierr_overlay.ka0c08_tlep$r_tdierr_bits.ka0c08_tlep$v_tdierr_gbto #define ka0c08_tlep$l_tl6_vmg ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$l_tl6_vmg #define ka0c08_tlep$v_tl6_vmg_5p ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_5p #define ka0c08_tlep$v_tl6_vmg_5m ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_5m #define ka0c08_tlep$v_tl6_vmg_3p ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_3p #define ka0c08_tlep$v_tl6_vmg_3m ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_3m #define ka0c08_tlep$l_tl6werr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$l_tl6werr #define ka0c08_tlep$v_tl6werr_select ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_select_bits.ka0c08_tlep$v_tl6werr_select #define ka0c08_tlep$v_tl6werr_r0_rd_pnd ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register0_bi.ka0c08_tlep$v_tl6werr_r0_r\ d_pnd #define ka0c08_tlep$v_tl6werr_r0_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register0_bi.ka0c08_tlep$v_tl6werr_r0_addr #define ka0c08_tlep$v_tl6werr_r1_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register1_bi.ka0c08_tlep$v_tl6werr_r1_addr #define ka0c08_tlep$v_tl6werr_r2_rd_pnd ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register2_bi.ka0c08_tlep$v_tl6werr_r2_r\ d_pnd #define ka0c08_tlep$v_tl6werr_r2_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register2_bi.ka0c08_tlep$v_tl6werr_r2_addr #define ka0c08_tlep$v_tl6werr_r3_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register3_bi.ka0c08_tlep$v_tl6werr_r3_addr #define ka0c08_tlep$l_tldtagex ka0c08_tlep$r_tldtagex_overlay.ka0c08_tlep$l_tldtagex #define ka0c08_tlep$v_tldtagex_f1 ka0c08_tlep$r_tldtagex_overlay.ka0c08_tlep$r_tldtagex_bits.ka0c08_tlep$v_tldtagex_f1 #define ka0c08_tlep$l_tlloopbck ka0c08_tlep$r_tlloopbck_overlay.ka0c08_tlep$l_tlloopbck #endif /* #if !defined(__VAXC) */ #define KA0C05_TLMEM$M_TLDEV_DTYPE 0xFFFF #define KA0C05_TLMEM$M_TLDEV_SWREV 0xFF0000 #define KA0C05_TLMEM$M_TLDEV_HWREV 0xFF000000 #define KA0C05_TLMEM$M_TLBER_ATCE 0x1 #define KA0C05_TLMEM$M_TLBER_APE 0x2 #define KA0C05_TLMEM$M_TLBER_BBE 0x4 #define KA0C05_TLMEM$M_TLBER_LKTO 0x8 #define KA0C05_TLMEM$M_TLBER_NAE 0x10 #define KA0C05_TLMEM$M_TLBER_RTCE 0x20 #define KA0C05_TLMEM$M_TLBER_ACKTCE 0x40 #define KA0C05_TLMEM$M_TLBER_MMRE 0x80 #define KA0C05_TLMEM$M_TLBER_FNAE 0x100 #define KA0C05_TLMEM$M_TLBER_REQDE 0x200 #define KA0C05_TLMEM$M_TLBER_ATDE 0x400 #define KA0C05_TLMEM$M_TLBER_UDE 0x10000 #define KA0C05_TLMEM$M_TLBER_CWDE 0x20000 #define KA0C05_TLMEM$M_TLBER_CRDE 0x40000 #define KA0C05_TLMEM$M_TLBER_DS0 0x100000 #define KA0C05_TLMEM$M_TLBER_DS1 0x200000 #define KA0C05_TLMEM$M_TLBER_DS2 0x400000 #define KA0C05_TLMEM$M_TLBER_DS3 0x800000 #define KA0C05_TLMEM$M_TLBER_DTDE 0x1000000 #define KA0C05_TLMEM$M_TLBER_FDTCE 0x2000000 #define KA0C05_TLMEM$M_TLBER_UACKE 0x4000000 #define KA0C05_TLMEM$M_TLBER_ABTCE 0x8000000 #define KA0C05_TLMEM$M_TLBER_DCTCE 0x10000000 #define KA0C05_TLMEM$M_TLBER_SEQE 0x20000000 #define KA0C05_TLMEM$M_TLBER_DSE 0x40000000 #define KA0C05_TLMEM$M_TLBER_DTO 0x80000000 #define KA0C05_TLMEM$M_TLCNR_CWDD 0x1 #define KA0C05_TLMEM$M_TLCNR_CRDD 0x2 #define KA0C05_TLMEM$M_TLCNR_LKTOD 0x4 #define KA0C05_TLMEM$M_TLCNR_DTOD 0x8 #define KA0C05_TLMEM$M_TLCNR_NODE_ID 0xF0 #define KA0C05_TLMEM$M_TLCNR_VCNT 0xF00 #define KA0C05_TLMEM$M_TLCNR_STF_A 0x1000 #define KA0C05_TLMEM$M_TLCNR_STF_B 0x2000 #define KA0C05_TLMEM$M_TLCNR_STF_C 0x4000 #define KA0C05_TLMEM$M_TLCNR_STF_D 0x8000 #define KA0C05_TLMEM$M_TLCNR_STF_E 0x10000 #define KA0C05_TLMEM$M_TLCNR_STF_F 0x20000 #define KA0C05_TLMEM$M_TLCNR_STF_G 0x40000 #define KA0C05_TLMEM$M_TLCNR_STF_H 0x80000 #define KA0C05_TLMEM$M_TLCNR_HALT_A 0x100000 #define KA0C05_TLMEM$M_TLCNR_HALT_B 0x200000 #define KA0C05_TLMEM$M_TLCNR_HALT_C 0x400000 #define KA0C05_TLMEM$M_TLCNR_HALT_D 0x800000 #define KA0C05_TLMEM$M_TLCNR_HALT_E 0x1000000 #define KA0C05_TLMEM$M_TLCNR_HALT_F 0x2000000 #define KA0C05_TLMEM$M_TLCNR_HALT_G 0x4000000 #define KA0C05_TLMEM$M_TLCNR_HALT_H 0x8000000 #define KA0C05_TLMEM$M_TLCNR_RSTSTAT 0x10000000 #define KA0C05_TLMEM$M_TLCNR_NRST 0x40000000 #define KA0C05_TLMEM$M_TLCNR_LOFE 0x80000000 #define KA0C05_TLMEM$M_VID_A 0xF #define KA0C05_TLMEM$M_VID_B 0xF0 #define KA0C05_TLMEM$M_VID_C 0xF00 #define KA0C05_TLMEM$M_VID_D 0xF000 #define KA0C05_TLMEM$M_VID_E 0xF0000 #define KA0C05_TLMEM$M_VID_F 0xF00000 #define KA0C05_TLMEM$M_VID_G 0xF000000 #define KA0C05_TLMEM$M_VID_H 0xF0000000 #define KA0C05_TLMEM$M_TLFADR0_FADR 0xFFFFFFF8 #define KA0C05_TLMEM$M_TLFADR1_FADR 0xFF #define KA0C05_TLMEM$M_TLFADR1_FCMD 0x70000 #define KA0C05_TLMEM$M_TLFADR1_FBANK 0xF00000 #define KA0C05_TLMEM$M_TLFADR1_ADRV 0x1000000 #define KA0C05_TLMEM$M_TLFADR1_CMDV 0x2000000 #define KA0C05_TLMEM$M_TLFADR1_BANKV 0x4000000 #define KA0C05_TLMEM$K_VICTIM 65536 #define KA0C05_TLMEM$K_BUS_READ 131072 #define KA0C05_TLMEM$K_BUS_WRITE 196608 #define KA0C05_TLMEM$K_READ_BANK_LOCK 262144 #define KA0C05_TLMEM$K_WRITE_BANK_UNLCK 327680 #define KA0C05_TLMEM$K_CSR_READ 393216 #define KA0C05_TLMEM$K_CSR_WRITE 458752 #define KA0C05_TLMEM$M_TLESR0_SYND0 0xFF #define KA0C05_TLMEM$M_TLESR0_SYND1 0xFF00 #define KA0C05_TLMEM$M_TLESR0_TDE 0x10000 #define KA0C05_TLMEM$M_TLESR0_TCE 0x20000 #define KA0C05_TLMEM$M_TLESR0_DVTCE 0x40000 #define KA0C05_TLMEM$M_TLESR0_UECC 0x80000 #define KA0C05_TLMEM$M_TLESR0_CWECC 0x100000 #define KA0C05_TLMEM$M_TLESR0_CRECC 0x200000 #define KA0C05_TLMEM$M_TLESR0_LOFSYN 0x80000000 #define KA0C05_TLMEM$M_TLESR1_SYND0 0xFF #define KA0C05_TLMEM$M_TLESR1_SYND1 0xFF00 #define KA0C05_TLMEM$M_TLESR1_TDE 0x10000 #define KA0C05_TLMEM$M_TLESR1_TCE 0x20000 #define KA0C05_TLMEM$M_TLESR1_DVTCE 0x40000 #define KA0C05_TLMEM$M_TLESR1_UECC 0x80000 #define KA0C05_TLMEM$M_TLESR1_CWECC 0x100000 #define KA0C05_TLMEM$M_TLESR1_CRECC 0x200000 #define KA0C05_TLMEM$M_TLESR1_LOFSYN 0x80000000 #define KA0C05_TLMEM$M_TLESR2_SYND0 0xFF #define KA0C05_TLMEM$M_TLESR2_SYND1 0xFF00 #define KA0C05_TLMEM$M_TLESR2_TDE 0x10000 #define KA0C05_TLMEM$M_TLESR2_TCE 0x20000 #define KA0C05_TLMEM$M_TLESR2_DVTCE 0x40000 #define KA0C05_TLMEM$M_TLESR2_UECC 0x80000 #define KA0C05_TLMEM$M_TLESR2_CWECC 0x100000 #define KA0C05_TLMEM$M_TLESR2_CRECC 0x200000 #define KA0C05_TLMEM$M_TLESR2_LOFSYN 0x80000000 #define KA0C05_TLMEM$M_TLESR3_SYND0 0xFF #define KA0C05_TLMEM$M_TLESR3_SYND1 0xFF00 #define KA0C05_TLMEM$M_TLESR3_TDE 0x10000 #define KA0C05_TLMEM$M_TLESR3_TCE 0x20000 #define KA0C05_TLMEM$M_TLESR3_DVTCE 0x40000 #define KA0C05_TLMEM$M_TLESR3_UECC 0x80000 #define KA0C05_TLMEM$M_TLESR3_CWECC 0x100000 #define KA0C05_TLMEM$M_TLESR3_CRECC 0x200000 #define KA0C05_TLMEM$M_TLESR3_LOFSYN 0x80000000 #define KA0C05_TLMEM$M_TLSECR_RCV_SDAT 0x1 #define KA0C05_TLMEM$M_TLSECR_XMT_SDAT 0x2 #define KA0C05_TLMEM$M_TLSECR_SCLK 0x4 #define KA0C05_TLMEM$M_TLMIR_INT 0x7 #define KA0C05_TLMEM$M_TLMIR_V 0x80000000 #define KA0C05_TLMEM$M_TLMCR_DTYP 0x1 #define KA0C05_TLMEM$M_TLMCR_STRN 0xC #define KA0C05_TLMEM$M_TLMCR_DTR 0x30 #define KA0C05_TLMEM$M_TLMCR_DEFLT 0x40 #define KA0C05_TLMEM$M_TLMCR_SHRD 0x100 #define KA0C05_TLMEM$M_TLMCR_OPTION 0x200 #define KA0C05_TLMEM$M_TLMCR_BDC 0x10000000 #define KA0C05_TLMEM$M_TLMCR_BREN 0x20000000 #define KA0C05_TLMEM$M_TLMCR_BDIS 0x40000000 #define KA0C05_TLMEM$M_TLMCR_BAT 0x80000000 #define KA0C05_TLMEM$M_TLSTER_FSTR 0x7 #define KA0C05_TLMEM$M_TLSTER_STE0 0x10 #define KA0C05_TLMEM$M_TLSTER_STE1 0x20 #define KA0C05_TLMEM$M_TLSTER_STE2 0x40 #define KA0C05_TLMEM$M_TLSTER_STE3 0x80 #define KA0C05_TLMEM$M_TLMER_FSTR 0x7 #define KA0C05_TLMEM$M_TLMDRA_AMEN 0x1 #define KA0C05_TLMEM$M_TLMDRA_FRAPE 0x2 #define KA0C05_TLMEM$M_TLMDRA_FCAPE 0x4 #define KA0C05_TLMEM$M_TLMDRA_MMPS 0x8 #define KA0C05_TLMEM$M_TLMDRA_EXST 0x10 #define KA0C05_TLMEM$M_TLMDRA_FRUN 0x20 #define KA0C05_TLMEM$M_TLMDRA_POEM 0x40 #define KA0C05_TLMEM$M_TLMDRA_POEMC 0x80 #define KA0C05_TLMEM$M_TLMDRA_DEDA 0x100 #define KA0C05_TLMEM$M_TLMDRA_RFR 0x30000000 #define KA0C05_TLMEM$M_TLMDRA_BRFSH 0x40000000 #define KA0C05_TLMEM$M_TLMDRA_DRFSH 0x80000000 #define KA0C05_TLMEM$M_TLMDRB_MADR 0xFFFFFFFF #define KA0C05_TLMEM$M_TLSTDERE_0_STE 0xFFFF #define KA0C05_TLMEM$M_TLSTDERE_0_VRC 0x70000 #define KA0C05_TLMEM$M_TLDDR0_LOE 0x1 #define KA0C05_TLMEM$M_TLDDR0_CDER 0x2 #define KA0C05_TLMEM$M_TLDDR0_ICFR 0x4 #define KA0C05_TLMEM$M_TLDDR0_PAT 0x8 #define KA0C05_TLMEM$M_TLDDR0_CFLP 0x70 #define KA0C05_TLMEM$M_TLDDR0_DFLP 0x3F00 #define KA0C05_TLMEM$M_TLDDR0_EFLPC 0x4000 #define KA0C05_TLMEM$M_TLDDR0_EFLPD 0x8000 #define KA0C05_TLMEM$M_TLDDR0_MARG 0x80000000 #define KA0C05_TLMEM$M_TLSTDERE_1_STE 0xFFFF #define KA0C05_TLMEM$M_TLSTDERE_1_VRC 0x70000 #define KA0C05_TLMEM$M_TLDDR1_LOE 0x1 #define KA0C05_TLMEM$M_TLDDR1_CDER 0x2 #define KA0C05_TLMEM$M_TLDDR1_ICFR 0x4 #define KA0C05_TLMEM$M_TLDDR1_PAT 0x8 #define KA0C05_TLMEM$M_TLDDR1_CFLP 0x70 #define KA0C05_TLMEM$M_TLDDR1_DFLP 0x3F00 #define KA0C05_TLMEM$M_TLDDR1_EFLPC 0x4000 #define KA0C05_TLMEM$M_TLDDR1_EFLPD 0x8000 #define KA0C05_TLMEM$M_TLDDR1_MARG 0x80000000 #define KA0C05_TLMEM$M_TLSTDERE_2_STE 0xFFFF #define KA0C05_TLMEM$M_TLSTDERE_2_VRC 0x70000 #define KA0C05_TLMEM$M_TLDDR2_LOE 0x1 #define KA0C05_TLMEM$M_TLDDR2_CDER 0x2 #define KA0C05_TLMEM$M_TLDDR2_ICFR 0x4 #define KA0C05_TLMEM$M_TLDDR2_PAT 0x8 #define KA0C05_TLMEM$M_TLDDR2_CFLP 0x70 #define KA0C05_TLMEM$M_TLDDR2_DFLP 0x3F00 #define KA0C05_TLMEM$M_TLDDR2_EFLPC 0x4000 #define KA0C05_TLMEM$M_TLDDR2_EFLPD 0x8000 #define KA0C05_TLMEM$M_TLDDR2_MARG 0x80000000 #define KA0C05_TLMEM$M_TLSTDERE_3_STE 0xFFFF #define KA0C05_TLMEM$M_TLSTDERE_3_VRC 0x70000 #define KA0C05_TLMEM$M_TLDDR3_LOE 0x1 #define KA0C05_TLMEM$M_TLDDR3_CDER 0x2 #define KA0C05_TLMEM$M_TLDDR3_ICFR 0x4 #define KA0C05_TLMEM$M_TLDDR3_PAT 0x8 #define KA0C05_TLMEM$M_TLDDR3_CFLP 0x70 #define KA0C05_TLMEM$M_TLDDR3_DFLP 0x3F00 #define KA0C05_TLMEM$M_TLDDR3_EFLPC 0x4000 #define KA0C05_TLMEM$M_TLDDR3_EFLPD 0x8000 #define KA0C05_TLMEM$M_TLDDR3_MARG 0x80000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_tlmem { #pragma __nomember_alignment __union { unsigned int ka0c05_tlmem$l_tldev; __struct { unsigned ka0c05_tlmem$v_tldev_dtype : 16; unsigned ka0c05_tlmem$v_tldev_swrev : 8; unsigned ka0c05_tlmem$v_tldev_hwrev : 8; } ka0c05_tlmem$r_tldev_bits; } ka0c05_tlmem$r_tldev_overlay; unsigned char ka0c05_tlmem$b_fill900 [60]; __union { unsigned int ka0c05_tlmem$l_tlber; __struct { unsigned ka0c05_tlmem$v_tlber_atce : 1; unsigned ka0c05_tlmem$v_tlber_ape : 1; unsigned ka0c05_tlmem$v_tlber_bbe : 1; unsigned ka0c05_tlmem$v_tlber_lkto : 1; unsigned ka0c05_tlmem$v_tlber_nae : 1; unsigned ka0c05_tlmem$v_tlber_rtce : 1; unsigned ka0c05_tlmem$v_tlber_acktce : 1; unsigned ka0c05_tlmem$v_tlber_mmre : 1; unsigned ka0c05_tlmem$v_tlber_fnae : 1; unsigned ka0c05_tlmem$v_tlber_reqde : 1; unsigned ka0c05_tlmem$v_tlber_atde : 1; unsigned ka0c05_tlmem$v_tlber_f1 : 5; unsigned ka0c05_tlmem$v_tlber_ude : 1; unsigned ka0c05_tlmem$v_tlber_cwde : 1; unsigned ka0c05_tlmem$v_tlber_crde : 1; unsigned ka0c05_tlmem$v_tlber_cwde2 : 1; unsigned ka0c05_tlmem$v_tlber_ds0 : 1; unsigned ka0c05_tlmem$v_tlber_ds1 : 1; unsigned ka0c05_tlmem$v_tlber_ds2 : 1; unsigned ka0c05_tlmem$v_tlber_ds3 : 1; unsigned ka0c05_tlmem$v_tlber_dtde : 1; unsigned ka0c05_tlmem$v_tlber_fdtce : 1; unsigned ka0c05_tlmem$v_tlber_uacke : 1; unsigned ka0c05_tlmem$v_tlber_abtce : 1; unsigned ka0c05_tlmem$v_tlber_dctce : 1; unsigned ka0c05_tlmem$v_tlber_seqe : 1; unsigned ka0c05_tlmem$v_tlber_dse : 1; unsigned ka0c05_tlmem$v_tlber_dto : 1; } ka0c05_tlmem$r_tlber_bits; } ka0c05_tlmem$r_tlber_overlay; unsigned char ka0c05_tlmem$b_fill910 [60]; __union { unsigned int ka0c05_tlmem$l_tlcnr; __struct { unsigned ka0c05_tlmem$v_tlcnr_cwdd : 1; unsigned ka0c05_tlmem$v_tlcnr_crdd : 1; unsigned ka0c05_tlmem$v_tlcnr_lktod : 1; unsigned ka0c05_tlmem$v_tlcnr_dtod : 1; unsigned ka0c05_tlmem$v_tlcnr_node_id : 4; unsigned ka0c05_tlmem$v_tlcnr_vcnt : 4; unsigned ka0c05_tlmem$v_tlcnr_stf_a : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_b : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_c : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_d : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_e : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_f : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_g : 1; unsigned ka0c05_tlmem$v_tlcnr_stf_h : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_a : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_b : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_c : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_d : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_e : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_f : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_g : 1; unsigned ka0c05_tlmem$v_tlcnr_halt_h : 1; unsigned ka0c05_tlmem$v_tlcnr_rststat : 1; unsigned ka0c05_tlmem$v_tlcnr_f1 : 1; unsigned ka0c05_tlmem$v_tlcnr_nrst : 1; unsigned ka0c05_tlmem$v_tlcnr_lofe : 1; } ka0c05_tlmem$r_tlcnr_bits; } ka0c05_tlmem$r_tlcnr_overlay; unsigned char ka0c05_tlmem$b_fill920 [60]; __union { unsigned int ka0c05_tlmem$l_tlvid; __struct { unsigned ka0c05_tlmem$v_vid_a : 4; unsigned ka0c05_tlmem$v_vid_b : 4; unsigned ka0c05_tlmem$v_vid_c : 4; unsigned ka0c05_tlmem$v_vid_d : 4; unsigned ka0c05_tlmem$v_vid_e : 4; unsigned ka0c05_tlmem$v_vid_f : 4; unsigned ka0c05_tlmem$v_vid_g : 4; unsigned ka0c05_tlmem$v_vid_h : 4; } ka0c05_tlmem$r_tlvid_bits; } ka0c05_tlmem$r_tlvid_overlay; unsigned char ka0c05_tlmem$b_fill930 [1340]; __union { unsigned int ka0c05_tlmem$l_tlfadr0; __struct { unsigned ka0c05_tlmem$v_tlfadr0_f1 : 3; unsigned ka0c05_tlmem$v_tlfadr0_fadr : 29; } ka0c05_tlmem$r_tlfadr0_bits; } ka0c05_tlmem$r_tlfadr0_overlay; unsigned char ka0c05_tlmem$b_fill940 [60]; __union { unsigned int ka0c05_tlmem$l_tlfadr1; __struct { unsigned ka0c05_tlmem$v_tlfadr1_fadr : 8; unsigned ka0c05_tlmem$v_tlfadr1_f1 : 8; unsigned ka0c05_tlmem$v_tlfadr1_fcmd : 3; unsigned ka0c05_tlmem$v_tlfadr1_f2 : 1; unsigned ka0c05_tlmem$v_tlfadr1_fbank : 4; unsigned ka0c05_tlmem$v_tlfadr1_adrv : 1; unsigned ka0c05_tlmem$v_tlfadr1_cmdv : 1; unsigned ka0c05_tlmem$v_tlfadr1_bankv : 1; unsigned ka0c05_tlmem$v_tlfadr1_fill3 : 5; } ka0c05_tlmem$r_tlfadr1_bits; } ka0c05_tlmem$r_tlfadr1_overlay; unsigned char ka0c05_tlmem$b_fill950 [60]; __union { unsigned int ka0c05_tlmem$l_tlesr0; __struct { unsigned ka0c05_tlmem$v_tlesr0_synd0 : 8; unsigned ka0c05_tlmem$v_tlesr0_synd1 : 8; unsigned ka0c05_tlmem$v_tlesr0_tde : 1; unsigned ka0c05_tlmem$v_tlesr0_tce : 1; unsigned ka0c05_tlmem$v_tlesr0_dvtce : 1; unsigned ka0c05_tlmem$v_tlesr0_uecc : 1; unsigned ka0c05_tlmem$v_tlesr0_cwecc : 1; unsigned ka0c05_tlmem$v_tlesr0_crecc : 1; unsigned ka0c05_tlmem$v_tlesr0_f1 : 9; unsigned ka0c05_tlmem$v_tlesr0_lofsyn : 1; } ka0c05_tlmem$r_tlesr0_bits; } ka0c05_tlmem$r_tlesr0_overlay; unsigned char ka0c05_tlmem$b_fill960 [60]; __union { unsigned int ka0c05_tlmem$l_tlesr1; __struct { unsigned ka0c05_tlmem$v_tlesr1_synd0 : 8; unsigned ka0c05_tlmem$v_tlesr1_synd1 : 8; unsigned ka0c05_tlmem$v_tlesr1_tde : 1; unsigned ka0c05_tlmem$v_tlesr1_tce : 1; unsigned ka0c05_tlmem$v_tlesr1_dvtce : 1; unsigned ka0c05_tlmem$v_tlesr1_uecc : 1; unsigned ka0c05_tlmem$v_tlesr1_cwecc : 1; unsigned ka0c05_tlmem$v_tlesr1_crecc : 1; unsigned ka0c05_tlmem$v_tlesr1_f1 : 9; unsigned ka0c05_tlmem$v_tlesr1_lofsyn : 1; } ka0c05_tlmem$r_tlesr1_bits; } ka0c05_tlmem$r_tlesr1_overlay; unsigned char ka0c05_tlmem$b_fill970 [60]; __union { unsigned int ka0c05_tlmem$l_tlesr2; __struct { unsigned ka0c05_tlmem$v_tlesr2_synd0 : 8; unsigned ka0c05_tlmem$v_tlesr2_synd1 : 8; unsigned ka0c05_tlmem$v_tlesr2_tde : 1; unsigned ka0c05_tlmem$v_tlesr2_tce : 1; unsigned ka0c05_tlmem$v_tlesr2_dvtce : 1; unsigned ka0c05_tlmem$v_tlesr2_uecc : 1; unsigned ka0c05_tlmem$v_tlesr2_cwecc : 1; unsigned ka0c05_tlmem$v_tlesr2_crecc : 1; unsigned ka0c05_tlmem$v_tlesr2_f1 : 9; unsigned ka0c05_tlmem$v_tlesr2_lofsyn : 1; } ka0c05_tlmem$r_tlesr2_bits; } ka0c05_tlmem$r_tlesr2_overlay; unsigned char ka0c05_tlmem$b_fill980 [60]; __union { unsigned int ka0c05_tlmem$l_tlesr3; __struct { unsigned ka0c05_tlmem$v_tlesr3_synd0 : 8; unsigned ka0c05_tlmem$v_tlesr3_synd1 : 8; unsigned ka0c05_tlmem$v_tlesr3_tde : 1; unsigned ka0c05_tlmem$v_tlesr3_tce : 1; unsigned ka0c05_tlmem$v_tlesr3_dvtce : 1; unsigned ka0c05_tlmem$v_tlesr3_uecc : 1; unsigned ka0c05_tlmem$v_tlesr3_cwecc : 1; unsigned ka0c05_tlmem$v_tlesr3_crecc : 1; unsigned ka0c05_tlmem$v_tlesr3_f1 : 9; unsigned ka0c05_tlmem$v_tlesr3_lofsyn : 1; } ka0c05_tlmem$r_tlesr3_bits; } ka0c05_tlmem$r_tlesr3_overlay; unsigned char ka0c05_tlmem$b_fill990 [4284]; __union { unsigned int ka0c05_tlmem$l_tlsecr; __struct { unsigned ka0c05_tlmem$v_tlsecr_rcv_sdat : 1; unsigned ka0c05_tlmem$v_tlsecr_xmt_sdat : 1; unsigned ka0c05_tlmem$v_tlsecr_sclk : 1; unsigned ka0c05_tlmem$v_tlsecr_f1 : 29; } ka0c05_tlmem$r_tlsecr_bits; } ka0c05_tlmem$r_tlsecr_overlay; unsigned char ka0c05_tlmem$b_f1000 [60]; __union { unsigned int ka0c05_tlmem$l_tlmir; __struct { unsigned ka0c05_tlmem$v_tlmir_int : 3; unsigned ka0c05_tlmem$v_tlmir_f1 : 28; unsigned ka0c05_tlmem$v_tlmir_v : 1; } ka0c05_tlmem$r_tlmir_bits; } ka0c05_tlmem$r_tlmir_overlay; unsigned char ka0c05_tlmem$b_f1010 [60]; __union { unsigned int ka0c05_tlmem$l_tlmcr; __struct { unsigned ka0c05_tlmem$v_tlmcr_dtyp : 1; unsigned ka0c05_tlmem$v_tlmcr_f1 : 1; unsigned ka0c05_tlmem$v_tlmcr_strn : 2; unsigned ka0c05_tlmem$v_tlmcr_dtr : 2; unsigned ka0c05_tlmem$v_tlmcr_deflt : 1; unsigned ka0c05_tlmem$v_tlmcr_f2 : 1; unsigned ka0c05_tlmem$v_tlmcr_shrd : 1; unsigned ka0c05_tlmem$v_tlmcr_option : 1; unsigned ka0c05_tlmem$v_tlmcr_fill3 : 18; unsigned ka0c05_tlmem$v_tlmcr_bdc : 1; unsigned ka0c05_tlmem$v_tlmcr_bren : 1; unsigned ka0c05_tlmem$v_tlmcr_bdis : 1; unsigned ka0c05_tlmem$v_tlmcr_bat : 1; } ka0c05_tlmem$r_tlmcr_bits; } ka0c05_tlmem$r_tlmcr_overlay; unsigned char ka0c05_tlmem$b_f1020 [60]; __union { unsigned int ka0c05_tlmem$l_tlstair; __struct { unsigned ka0c05_tlmem$v_tlstair_f1 : 32; } ka0c05_tlmem$r_tlstair_bits; } ka0c05_tlmem$r_tlstair_overlay; unsigned char ka0c05_tlmem$b_f1030 [60]; __union { unsigned int ka0c05_tlmem$l_tlster; __struct { unsigned ka0c05_tlmem$v_tlster_fstr : 3; unsigned ka0c05_tlmem$v_tlster_f1 : 1; unsigned ka0c05_tlmem$v_tlster_ste0 : 1; unsigned ka0c05_tlmem$v_tlster_ste1 : 1; unsigned ka0c05_tlmem$v_tlster_ste2 : 1; unsigned ka0c05_tlmem$v_tlster_ste3 : 1; unsigned ka0c05_tlmem$v_tlster_f2 : 24; } ka0c05_tlmem$r_tlster_bits; } ka0c05_tlmem$r_tlster_overlay; unsigned char ka0c05_tlmem$b_f1040 [60]; __union { unsigned int ka0c05_tlmem$l_tlmer; __struct { unsigned ka0c05_tlmem$v_tlmer_fstr : 3; unsigned ka0c05_tlmem$v_tlmer_f1 : 29; } ka0c05_tlmem$r_tlmer_bits; } ka0c05_tlmem$r_tlmer_overlay; unsigned char ka0c05_tlmem$b_f1050 [60]; __union { unsigned int ka0c05_tlmem$l_tlmdra; __struct { unsigned ka0c05_tlmem$v_tlmdra_amen : 1; unsigned ka0c05_tlmem$v_tlmdra_frape : 1; unsigned ka0c05_tlmem$v_tlmdra_fcape : 1; unsigned ka0c05_tlmem$v_tlmdra_mmps : 1; unsigned ka0c05_tlmem$v_tlmdra_exst : 1; unsigned ka0c05_tlmem$v_tlmdra_frun : 1; unsigned ka0c05_tlmem$v_tlmdra_poem : 1; unsigned ka0c05_tlmem$v_tlmdra_poemc : 1; unsigned ka0c05_tlmem$v_tlmdra_deda : 1; unsigned ka0c05_tlmem$v_tlmdra_f1 : 19; unsigned ka0c05_tlmem$v_tlmdra_rfr : 2; unsigned ka0c05_tlmem$v_tlmdra_brfsh : 1; unsigned ka0c05_tlmem$v_tlmdra_drfsh : 1; } ka0c05_tlmem$r_tlmdra_bits; } ka0c05_tlmem$r_tlmdra_overlay; unsigned char ka0c05_tlmem$b_f1060 [60]; __union { unsigned int ka0c05_tlmem$l_tlmdrb; __struct { unsigned ka0c05_tlmem$v_tlmdrb_madr : 32; } ka0c05_tlmem$r_tlmdrb_bits; } ka0c05_tlmem$r_tlmdrb_overlay; unsigned char ka0c05_tlmem$b_f1070 [1596]; __union { unsigned int ka0c05_tlmem$l_tlstdera_0; __struct { unsigned ka0c05_tlmem$v_tlstdera_0_f1 : 32; } ka0c05_tlmem$r_tlstdera_0_bits; } ka0c05_tlmem$r_tlstdera_0_overlay; unsigned char ka0c05_tlmem$b_f1080 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderb_0; __struct { unsigned ka0c05_tlmem$v_tlstderb_0_f1 : 32; } ka0c05_tlmem$r_tlstderb_0_bits; } ka0c05_tlmem$r_tlstderb_0_overlay; unsigned char ka0c05_tlmem$b_f1090 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderc_0; __struct { unsigned ka0c05_tlmem$v_tlstderc_0_f1 : 32; } ka0c05_tlmem$r_tlstderc_0_bits; } ka0c05_tlmem$r_tlstderc_0_overlay; unsigned char ka0c05_tlmem$b_f1100 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderd_0; __struct { unsigned ka0c05_tlmem$v_tlstderd_0_f1 : 32; } ka0c05_tlmem$r_tlstderd_0_bits; } ka0c05_tlmem$r_tlstderd_0_overlay; unsigned char ka0c05_tlmem$b_f1110 [60]; __union { unsigned int ka0c05_tlmem$l_tlstdere_0; __struct { unsigned ka0c05_tlmem$v_tlstdere_0_ste : 16; unsigned ka0c05_tlmem$v_tlstdere_0_vrc : 3; unsigned ka0c05_tlmem$v_tlstdere_0_f1 : 13; } ka0c05_tlmem$r_tlstdere_0_bits; } ka0c05_tlmem$r_tlstdere_0_overlay; unsigned char ka0c05_tlmem$b_f1120 [60]; __union { unsigned int ka0c05_tlmem$l_tlddr0; __struct { unsigned ka0c05_tlmem$v_tlddr0_loe : 1; unsigned ka0c05_tlmem$v_tlddr0_cder : 1; unsigned ka0c05_tlmem$v_tlddr0_icfr : 1; unsigned ka0c05_tlmem$v_tlddr0_pat : 1; unsigned ka0c05_tlmem$v_tlddr0_cflp : 3; unsigned ka0c05_tlmem$v_tlddr0_f1 : 1; unsigned ka0c05_tlmem$v_tlddr0_dflp : 6; unsigned ka0c05_tlmem$v_tlddr0_eflpc : 1; unsigned ka0c05_tlmem$v_tlddr0_eflpd : 1; unsigned ka0c05_tlmem$v_tlddr0_f2 : 15; unsigned ka0c05_tlmem$v_tlddr0_marg : 1; } ka0c05_tlmem$r_tlddr0_bits; } ka0c05_tlmem$r_tlddr0_overlay; unsigned char ka0c05_tlmem$b_f1130 [7868]; __union { unsigned int ka0c05_tlmem$l_tlstdera_1; __struct { unsigned ka0c05_tlmem$v_tlstdera_1_f1 : 32; } ka0c05_tlmem$r_tlstdera_1_bits; } ka0c05_tlmem$r_tlstdera_1_overlay; unsigned char ka0c05_tlmem$b_f1140 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderb_1; __struct { unsigned ka0c05_tlmem$v_tlstderb_1_f1 : 32; } ka0c05_tlmem$r_tlstderb_1_bits; } ka0c05_tlmem$r_tlstderb_1_overlay; unsigned char ka0c05_tlmem$b_f1150 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderc_1; __struct { unsigned ka0c05_tlmem$v_tlstderc_1_f1 : 32; } ka0c05_tlmem$r_tlstderc_1_bits; } ka0c05_tlmem$r_tlstderc_1_overlay; unsigned char ka0c05_tlmem$b_f1160 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderd_1; __struct { unsigned ka0c05_tlmem$v_tlstderd_1_f1 : 32; } ka0c05_tlmem$r_tlstderd_1_bits; } ka0c05_tlmem$r_tlstderd_1_overlay; unsigned char ka0c05_tlmem$b_f1170 [60]; __union { unsigned int ka0c05_tlmem$l_tlstdere_1; __struct { unsigned ka0c05_tlmem$v_tlstdere_1_ste : 16; unsigned ka0c05_tlmem$v_tlstdere_1_vrc : 3; unsigned ka0c05_tlmem$v_tlstdere_1_f1 : 13; } ka0c05_tlmem$r_tlstdere_1_bits; } ka0c05_tlmem$r_tlstdere_1_overlay; unsigned char ka0c05_tlmem$b_f1180 [60]; __union { unsigned int ka0c05_tlmem$l_tlddr1; __struct { unsigned ka0c05_tlmem$v_tlddr1_loe : 1; unsigned ka0c05_tlmem$v_tlddr1_cder : 1; unsigned ka0c05_tlmem$v_tlddr1_icfr : 1; unsigned ka0c05_tlmem$v_tlddr1_pat : 1; unsigned ka0c05_tlmem$v_tlddr1_cflp : 3; unsigned ka0c05_tlmem$v_tlddr1_f1 : 1; unsigned ka0c05_tlmem$v_tlddr1_dflp : 6; unsigned ka0c05_tlmem$v_tlddr1_eflpc : 1; unsigned ka0c05_tlmem$v_tlddr1_eflpd : 1; unsigned ka0c05_tlmem$v_tlddr1_f2 : 15; unsigned ka0c05_tlmem$v_tlddr1_marg : 1; } ka0c05_tlmem$r_tlddr1_bits; } ka0c05_tlmem$r_tlddr1_overlay; unsigned char ka0c05_tlmem$b_f1190 [7868]; __union { unsigned int ka0c05_tlmem$l_tlstdera_2; __struct { unsigned ka0c05_tlmem$v_tlstdera_2_f1 : 32; } ka0c05_tlmem$r_tlstdera_2_bits; } ka0c05_tlmem$r_tlstdera_2_overlay; unsigned char ka0c05_tlmem$b_f1200 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderb_2; __struct { unsigned ka0c05_tlmem$v_tlstderb_2_f1 : 32; } ka0c05_tlmem$r_tlstderb_2_bits; } ka0c05_tlmem$r_tlstderb_2_overlay; unsigned char ka0c05_tlmem$b_f1210 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderc_2; __struct { unsigned ka0c05_tlmem$v_tlstderc_2_f1 : 32; } ka0c05_tlmem$r_tlstderc_2_bits; } ka0c05_tlmem$r_tlstderc_2_overlay; unsigned char ka0c05_tlmem$b_f1220 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderd_2; __struct { unsigned ka0c05_tlmem$v_tlstderd_2_f1 : 32; } ka0c05_tlmem$r_tlstderd_2_bits; } ka0c05_tlmem$r_tlstderd_2_overlay; unsigned char ka0c05_tlmem$b_f1230 [60]; __union { unsigned int ka0c05_tlmem$l_tlstdere_2; __struct { unsigned ka0c05_tlmem$v_tlstdere_2_ste : 16; unsigned ka0c05_tlmem$v_tlstdere_2_vrc : 3; unsigned ka0c05_tlmem$v_tlstdere_2_f1 : 13; } ka0c05_tlmem$r_tlstdere_2_bits; } ka0c05_tlmem$r_tlstdere_2_overlay; unsigned char ka0c05_tlmem$b_f1240 [60]; __union { unsigned int ka0c05_tlmem$l_tlddr2; __struct { unsigned ka0c05_tlmem$v_tlddr2_loe : 1; unsigned ka0c05_tlmem$v_tlddr2_cder : 1; unsigned ka0c05_tlmem$v_tlddr2_icfr : 1; unsigned ka0c05_tlmem$v_tlddr2_pat : 1; unsigned ka0c05_tlmem$v_tlddr2_cflp : 3; unsigned ka0c05_tlmem$v_tlddr2_f1 : 1; unsigned ka0c05_tlmem$v_tlddr2_dflp : 6; unsigned ka0c05_tlmem$v_tlddr2_eflpc : 1; unsigned ka0c05_tlmem$v_tlddr2_eflpd : 1; unsigned ka0c05_tlmem$v_tlddr2_f2 : 15; unsigned ka0c05_tlmem$v_tlddr2_marg : 1; } ka0c05_tlmem$r_tlddr2_bits; } ka0c05_tlmem$r_tlddr2_overlay; unsigned char ka0c05_tlmem$b_f1250 [7868]; __union { unsigned int ka0c05_tlmem$l_tlstdera_3; __struct { unsigned ka0c05_tlmem$v_tlstdera_3_f1 : 32; } ka0c05_tlmem$r_tlstdera_3_bits; } ka0c05_tlmem$r_tlstdera_3_overlay; unsigned char ka0c05_tlmem$b_f1260 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderb_3; __struct { unsigned ka0c05_tlmem$v_tlstderb_3_f1 : 32; } ka0c05_tlmem$r_tlstderb_3_bits; } ka0c05_tlmem$r_tlstderb_3_overlay; unsigned char ka0c05_tlmem$b_f1270 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderc_3; __struct { unsigned ka0c05_tlmem$v_tlstderc_3_f1 : 32; } ka0c05_tlmem$r_tlstderc_3_bits; } ka0c05_tlmem$r_tlstderc_3_overlay; unsigned char ka0c05_tlmem$b_f1280 [60]; __union { unsigned int ka0c05_tlmem$l_tlstderd_3; __struct { unsigned ka0c05_tlmem$v_tlstderd_3_f1 : 32; } ka0c05_tlmem$r_tlstderd_3_bits; } ka0c05_tlmem$r_tlstderd_3_overlay; unsigned char ka0c05_tlmem$b_f1290 [60]; __union { unsigned int ka0c05_tlmem$l_tlstdere_3; __struct { unsigned ka0c05_tlmem$v_tlstdere_3_ste : 16; unsigned ka0c05_tlmem$v_tlstdere_3_vrc : 3; unsigned ka0c05_tlmem$v_tlstdere_3_f1 : 13; } ka0c05_tlmem$r_tlstdere_3_bits; } ka0c05_tlmem$r_tlstdere_3_overlay; unsigned char ka0c05_tlmem$b_f1300 [60]; __union { unsigned int ka0c05_tlmem$l_tlddr3; __struct { unsigned ka0c05_tlmem$v_tlddr3_loe : 1; unsigned ka0c05_tlmem$v_tlddr3_cder : 1; unsigned ka0c05_tlmem$v_tlddr3_icfr : 1; unsigned ka0c05_tlmem$v_tlddr3_pat : 1; unsigned ka0c05_tlmem$v_tlddr3_cflp : 3; unsigned ka0c05_tlmem$v_tlddr3_f1 : 1; unsigned ka0c05_tlmem$v_tlddr3_dflp : 6; unsigned ka0c05_tlmem$v_tlddr3_eflpc : 1; unsigned ka0c05_tlmem$v_tlddr3_eflpd : 1; unsigned ka0c05_tlmem$v_tlddr3_f2 : 15; unsigned ka0c05_tlmem$v_tlddr3_marg : 1; } ka0c05_tlmem$r_tlddr3_bits; } ka0c05_tlmem$r_tlddr3_overlay; unsigned char ka0c05_tlmem$b_f1310 [7868]; } KA0C05_TLMEM; #if !defined(__VAXC) #define ka0c05_tlmem$l_tldev ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$l_tldev #define ka0c05_tlmem$v_tldev_dtype ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$r_tldev_bits.ka0c05_tlmem$v_tldev_dtype #define ka0c05_tlmem$v_tldev_swrev ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$r_tldev_bits.ka0c05_tlmem$v_tldev_swrev #define ka0c05_tlmem$v_tldev_hwrev ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$r_tldev_bits.ka0c05_tlmem$v_tldev_hwrev #define ka0c05_tlmem$l_tlber ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$l_tlber #define ka0c05_tlmem$v_tlber_atce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_atce #define ka0c05_tlmem$v_tlber_ape ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ape #define ka0c05_tlmem$v_tlber_bbe ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_bbe #define ka0c05_tlmem$v_tlber_lkto ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_lkto #define ka0c05_tlmem$v_tlber_nae ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_nae #define ka0c05_tlmem$v_tlber_rtce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_rtce #define ka0c05_tlmem$v_tlber_acktce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_acktce #define ka0c05_tlmem$v_tlber_mmre ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_mmre #define ka0c05_tlmem$v_tlber_fnae ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_fnae #define ka0c05_tlmem$v_tlber_reqde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_reqde #define ka0c05_tlmem$v_tlber_atde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_atde #define ka0c05_tlmem$v_tlber_ude ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ude #define ka0c05_tlmem$v_tlber_cwde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_cwde #define ka0c05_tlmem$v_tlber_crde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_crde #define ka0c05_tlmem$v_tlber_ds0 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds0 #define ka0c05_tlmem$v_tlber_ds1 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds1 #define ka0c05_tlmem$v_tlber_ds2 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds2 #define ka0c05_tlmem$v_tlber_ds3 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds3 #define ka0c05_tlmem$v_tlber_dtde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dtde #define ka0c05_tlmem$v_tlber_fdtce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_fdtce #define ka0c05_tlmem$v_tlber_uacke ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_uacke #define ka0c05_tlmem$v_tlber_abtce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_abtce #define ka0c05_tlmem$v_tlber_dctce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dctce #define ka0c05_tlmem$v_tlber_seqe ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_seqe #define ka0c05_tlmem$v_tlber_dse ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dse #define ka0c05_tlmem$v_tlber_dto ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dto #define ka0c05_tlmem$l_tlcnr ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$l_tlcnr #define ka0c05_tlmem$v_tlcnr_cwdd ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_cwdd #define ka0c05_tlmem$v_tlcnr_crdd ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_crdd #define ka0c05_tlmem$v_tlcnr_lktod ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_lktod #define ka0c05_tlmem$v_tlcnr_dtod ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_dtod #define ka0c05_tlmem$v_tlcnr_node_id ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_node_id #define ka0c05_tlmem$v_tlcnr_vcnt ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_vcnt #define ka0c05_tlmem$v_tlcnr_stf_a ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_a #define ka0c05_tlmem$v_tlcnr_stf_b ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_b #define ka0c05_tlmem$v_tlcnr_stf_c ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_c #define ka0c05_tlmem$v_tlcnr_stf_d ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_d #define ka0c05_tlmem$v_tlcnr_stf_e ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_e #define ka0c05_tlmem$v_tlcnr_stf_f ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_f #define ka0c05_tlmem$v_tlcnr_stf_g ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_g #define ka0c05_tlmem$v_tlcnr_stf_h ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_h #define ka0c05_tlmem$v_tlcnr_halt_a ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_a #define ka0c05_tlmem$v_tlcnr_halt_b ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_b #define ka0c05_tlmem$v_tlcnr_halt_c ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_c #define ka0c05_tlmem$v_tlcnr_halt_d ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_d #define ka0c05_tlmem$v_tlcnr_halt_e ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_e #define ka0c05_tlmem$v_tlcnr_halt_f ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_f #define ka0c05_tlmem$v_tlcnr_halt_g ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_g #define ka0c05_tlmem$v_tlcnr_halt_h ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_h #define ka0c05_tlmem$v_tlcnr_rststat ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_rststat #define ka0c05_tlmem$v_tlcnr_nrst ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_nrst #define ka0c05_tlmem$v_tlcnr_lofe ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_lofe #define ka0c05_tlmem$l_tlvid ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$l_tlvid #define ka0c05_tlmem$v_vid_a ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_a #define ka0c05_tlmem$v_vid_b ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_b #define ka0c05_tlmem$v_vid_c ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_c #define ka0c05_tlmem$v_vid_d ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_d #define ka0c05_tlmem$v_vid_e ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_e #define ka0c05_tlmem$v_vid_f ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_f #define ka0c05_tlmem$v_vid_g ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_g #define ka0c05_tlmem$v_vid_h ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_h #define ka0c05_tlmem$l_tlfadr0 ka0c05_tlmem$r_tlfadr0_overlay.ka0c05_tlmem$l_tlfadr0 #define ka0c05_tlmem$v_tlfadr0_fadr ka0c05_tlmem$r_tlfadr0_overlay.ka0c05_tlmem$r_tlfadr0_bits.ka0c05_tlmem$v_tlfadr0_fadr #define ka0c05_tlmem$l_tlfadr1 ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$l_tlfadr1 #define ka0c05_tlmem$v_tlfadr1_fadr ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_fadr #define ka0c05_tlmem$v_tlfadr1_fcmd ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_fcmd #define ka0c05_tlmem$v_tlfadr1_fbank ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_fbank #define ka0c05_tlmem$v_tlfadr1_adrv ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_adrv #define ka0c05_tlmem$v_tlfadr1_cmdv ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_cmdv #define ka0c05_tlmem$v_tlfadr1_bankv ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_bankv #define ka0c05_tlmem$l_tlesr0 ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$l_tlesr0 #define ka0c05_tlmem$v_tlesr0_synd0 ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_synd0 #define ka0c05_tlmem$v_tlesr0_synd1 ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_synd1 #define ka0c05_tlmem$v_tlesr0_tde ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_tde #define ka0c05_tlmem$v_tlesr0_tce ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_tce #define ka0c05_tlmem$v_tlesr0_dvtce ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_dvtce #define ka0c05_tlmem$v_tlesr0_uecc ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_uecc #define ka0c05_tlmem$v_tlesr0_cwecc ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_cwecc #define ka0c05_tlmem$v_tlesr0_crecc ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_crecc #define ka0c05_tlmem$v_tlesr0_lofsyn ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_lofsyn #define ka0c05_tlmem$l_tlesr1 ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$l_tlesr1 #define ka0c05_tlmem$v_tlesr1_synd0 ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_synd0 #define ka0c05_tlmem$v_tlesr1_synd1 ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_synd1 #define ka0c05_tlmem$v_tlesr1_tde ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_tde #define ka0c05_tlmem$v_tlesr1_tce ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_tce #define ka0c05_tlmem$v_tlesr1_dvtce ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_dvtce #define ka0c05_tlmem$v_tlesr1_uecc ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_uecc #define ka0c05_tlmem$v_tlesr1_cwecc ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_cwecc #define ka0c05_tlmem$v_tlesr1_crecc ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_crecc #define ka0c05_tlmem$v_tlesr1_lofsyn ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_lofsyn #define ka0c05_tlmem$l_tlesr2 ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$l_tlesr2 #define ka0c05_tlmem$v_tlesr2_synd0 ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_synd0 #define ka0c05_tlmem$v_tlesr2_synd1 ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_synd1 #define ka0c05_tlmem$v_tlesr2_tde ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_tde #define ka0c05_tlmem$v_tlesr2_tce ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_tce #define ka0c05_tlmem$v_tlesr2_dvtce ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_dvtce #define ka0c05_tlmem$v_tlesr2_uecc ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_uecc #define ka0c05_tlmem$v_tlesr2_cwecc ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_cwecc #define ka0c05_tlmem$v_tlesr2_crecc ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_crecc #define ka0c05_tlmem$v_tlesr2_lofsyn ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_lofsyn #define ka0c05_tlmem$l_tlesr3 ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$l_tlesr3 #define ka0c05_tlmem$v_tlesr3_synd0 ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_synd0 #define ka0c05_tlmem$v_tlesr3_synd1 ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_synd1 #define ka0c05_tlmem$v_tlesr3_tde ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_tde #define ka0c05_tlmem$v_tlesr3_tce ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_tce #define ka0c05_tlmem$v_tlesr3_dvtce ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_dvtce #define ka0c05_tlmem$v_tlesr3_uecc ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_uecc #define ka0c05_tlmem$v_tlesr3_cwecc ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_cwecc #define ka0c05_tlmem$v_tlesr3_crecc ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_crecc #define ka0c05_tlmem$v_tlesr3_lofsyn ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_lofsyn #define ka0c05_tlmem$l_tlsecr ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$l_tlsecr #define ka0c05_tlmem$v_tlsecr_rcv_sdat ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$r_tlsecr_bits.ka0c05_tlmem$v_tlsecr_rcv_sdat #define ka0c05_tlmem$v_tlsecr_xmt_sdat ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$r_tlsecr_bits.ka0c05_tlmem$v_tlsecr_xmt_sdat #define ka0c05_tlmem$v_tlsecr_sclk ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$r_tlsecr_bits.ka0c05_tlmem$v_tlsecr_sclk #define ka0c05_tlmem$l_tlmir ka0c05_tlmem$r_tlmir_overlay.ka0c05_tlmem$l_tlmir #define ka0c05_tlmem$v_tlmir_int ka0c05_tlmem$r_tlmir_overlay.ka0c05_tlmem$r_tlmir_bits.ka0c05_tlmem$v_tlmir_int #define ka0c05_tlmem$v_tlmir_v ka0c05_tlmem$r_tlmir_overlay.ka0c05_tlmem$r_tlmir_bits.ka0c05_tlmem$v_tlmir_v #define ka0c05_tlmem$l_tlmcr ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$l_tlmcr #define ka0c05_tlmem$v_tlmcr_dtyp ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_dtyp #define ka0c05_tlmem$v_tlmcr_strn ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_strn #define ka0c05_tlmem$v_tlmcr_dtr ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_dtr #define ka0c05_tlmem$v_tlmcr_deflt ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_deflt #define ka0c05_tlmem$v_tlmcr_shrd ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_shrd #define ka0c05_tlmem$v_tlmcr_option ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_option #define ka0c05_tlmem$v_tlmcr_bdc ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_bdc #define ka0c05_tlmem$v_tlmcr_bren ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_bren #define ka0c05_tlmem$v_tlmcr_bdis ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_bdis #define ka0c05_tlmem$v_tlmcr_bat ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_bat #define ka0c05_tlmem$l_tlstair ka0c05_tlmem$r_tlstair_overlay.ka0c05_tlmem$l_tlstair #define ka0c05_tlmem$l_tlster ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$l_tlster #define ka0c05_tlmem$v_tlster_fstr ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_fstr #define ka0c05_tlmem$v_tlster_ste0 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste0 #define ka0c05_tlmem$v_tlster_ste1 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste1 #define ka0c05_tlmem$v_tlster_ste2 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste2 #define ka0c05_tlmem$v_tlster_ste3 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste3 #define ka0c05_tlmem$l_tlmer ka0c05_tlmem$r_tlmer_overlay.ka0c05_tlmem$l_tlmer #define ka0c05_tlmem$v_tlmer_fstr ka0c05_tlmem$r_tlmer_overlay.ka0c05_tlmem$r_tlmer_bits.ka0c05_tlmem$v_tlmer_fstr #define ka0c05_tlmem$l_tlmdra ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$l_tlmdra #define ka0c05_tlmem$v_tlmdra_amen ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_amen #define ka0c05_tlmem$v_tlmdra_frape ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_frape #define ka0c05_tlmem$v_tlmdra_fcape ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_fcape #define ka0c05_tlmem$v_tlmdra_mmps ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_mmps #define ka0c05_tlmem$v_tlmdra_exst ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_exst #define ka0c05_tlmem$v_tlmdra_frun ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_frun #define ka0c05_tlmem$v_tlmdra_poem ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_poem #define ka0c05_tlmem$v_tlmdra_poemc ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_poemc #define ka0c05_tlmem$v_tlmdra_deda ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_deda #define ka0c05_tlmem$v_tlmdra_rfr ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_rfr #define ka0c05_tlmem$v_tlmdra_brfsh ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_brfsh #define ka0c05_tlmem$v_tlmdra_drfsh ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_drfsh #define ka0c05_tlmem$l_tlmdrb ka0c05_tlmem$r_tlmdrb_overlay.ka0c05_tlmem$l_tlmdrb #define ka0c05_tlmem$v_tlmdrb_madr ka0c05_tlmem$r_tlmdrb_overlay.ka0c05_tlmem$r_tlmdrb_bits.ka0c05_tlmem$v_tlmdrb_madr #define ka0c05_tlmem$l_tlstdera_0 ka0c05_tlmem$r_tlstdera_0_overlay.ka0c05_tlmem$l_tlstdera_0 #define ka0c05_tlmem$l_tlstderb_0 ka0c05_tlmem$r_tlstderb_0_overlay.ka0c05_tlmem$l_tlstderb_0 #define ka0c05_tlmem$l_tlstderc_0 ka0c05_tlmem$r_tlstderc_0_overlay.ka0c05_tlmem$l_tlstderc_0 #define ka0c05_tlmem$l_tlstderd_0 ka0c05_tlmem$r_tlstderd_0_overlay.ka0c05_tlmem$l_tlstderd_0 #define ka0c05_tlmem$l_tlstdere_0 ka0c05_tlmem$r_tlstdere_0_overlay.ka0c05_tlmem$l_tlstdere_0 #define ka0c05_tlmem$v_tlstdere_0_ste ka0c05_tlmem$r_tlstdere_0_overlay.ka0c05_tlmem$r_tlstdere_0_bits.ka0c05_tlmem$v_tlstdere_0_ste #define ka0c05_tlmem$v_tlstdere_0_vrc ka0c05_tlmem$r_tlstdere_0_overlay.ka0c05_tlmem$r_tlstdere_0_bits.ka0c05_tlmem$v_tlstdere_0_vrc #define ka0c05_tlmem$l_tlddr0 ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$l_tlddr0 #define ka0c05_tlmem$v_tlddr0_loe ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_loe #define ka0c05_tlmem$v_tlddr0_cder ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_cder #define ka0c05_tlmem$v_tlddr0_icfr ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_icfr #define ka0c05_tlmem$v_tlddr0_pat ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_pat #define ka0c05_tlmem$v_tlddr0_cflp ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_cflp #define ka0c05_tlmem$v_tlddr0_dflp ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_dflp #define ka0c05_tlmem$v_tlddr0_eflpc ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_eflpc #define ka0c05_tlmem$v_tlddr0_eflpd ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_eflpd #define ka0c05_tlmem$v_tlddr0_marg ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_marg #define ka0c05_tlmem$l_tlstdera_1 ka0c05_tlmem$r_tlstdera_1_overlay.ka0c05_tlmem$l_tlstdera_1 #define ka0c05_tlmem$l_tlstderb_1 ka0c05_tlmem$r_tlstderb_1_overlay.ka0c05_tlmem$l_tlstderb_1 #define ka0c05_tlmem$l_tlstderc_1 ka0c05_tlmem$r_tlstderc_1_overlay.ka0c05_tlmem$l_tlstderc_1 #define ka0c05_tlmem$l_tlstderd_1 ka0c05_tlmem$r_tlstderd_1_overlay.ka0c05_tlmem$l_tlstderd_1 #define ka0c05_tlmem$l_tlstdere_1 ka0c05_tlmem$r_tlstdere_1_overlay.ka0c05_tlmem$l_tlstdere_1 #define ka0c05_tlmem$v_tlstdere_1_ste ka0c05_tlmem$r_tlstdere_1_overlay.ka0c05_tlmem$r_tlstdere_1_bits.ka0c05_tlmem$v_tlstdere_1_ste #define ka0c05_tlmem$v_tlstdere_1_vrc ka0c05_tlmem$r_tlstdere_1_overlay.ka0c05_tlmem$r_tlstdere_1_bits.ka0c05_tlmem$v_tlstdere_1_vrc #define ka0c05_tlmem$l_tlddr1 ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$l_tlddr1 #define ka0c05_tlmem$v_tlddr1_loe ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_loe #define ka0c05_tlmem$v_tlddr1_cder ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_cder #define ka0c05_tlmem$v_tlddr1_icfr ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_icfr #define ka0c05_tlmem$v_tlddr1_pat ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_pat #define ka0c05_tlmem$v_tlddr1_cflp ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_cflp #define ka0c05_tlmem$v_tlddr1_dflp ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_dflp #define ka0c05_tlmem$v_tlddr1_eflpc ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_eflpc #define ka0c05_tlmem$v_tlddr1_eflpd ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_eflpd #define ka0c05_tlmem$v_tlddr1_marg ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_marg #define ka0c05_tlmem$l_tlstdera_2 ka0c05_tlmem$r_tlstdera_2_overlay.ka0c05_tlmem$l_tlstdera_2 #define ka0c05_tlmem$l_tlstderb_2 ka0c05_tlmem$r_tlstderb_2_overlay.ka0c05_tlmem$l_tlstderb_2 #define ka0c05_tlmem$l_tlstderc_2 ka0c05_tlmem$r_tlstderc_2_overlay.ka0c05_tlmem$l_tlstderc_2 #define ka0c05_tlmem$l_tlstderd_2 ka0c05_tlmem$r_tlstderd_2_overlay.ka0c05_tlmem$l_tlstderd_2 #define ka0c05_tlmem$l_tlstdere_2 ka0c05_tlmem$r_tlstdere_2_overlay.ka0c05_tlmem$l_tlstdere_2 #define ka0c05_tlmem$v_tlstdere_2_ste ka0c05_tlmem$r_tlstdere_2_overlay.ka0c05_tlmem$r_tlstdere_2_bits.ka0c05_tlmem$v_tlstdere_2_ste #define ka0c05_tlmem$v_tlstdere_2_vrc ka0c05_tlmem$r_tlstdere_2_overlay.ka0c05_tlmem$r_tlstdere_2_bits.ka0c05_tlmem$v_tlstdere_2_vrc #define ka0c05_tlmem$l_tlddr2 ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$l_tlddr2 #define ka0c05_tlmem$v_tlddr2_loe ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_loe #define ka0c05_tlmem$v_tlddr2_cder ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_cder #define ka0c05_tlmem$v_tlddr2_icfr ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_icfr #define ka0c05_tlmem$v_tlddr2_pat ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_pat #define ka0c05_tlmem$v_tlddr2_cflp ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_cflp #define ka0c05_tlmem$v_tlddr2_dflp ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_dflp #define ka0c05_tlmem$v_tlddr2_eflpc ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_eflpc #define ka0c05_tlmem$v_tlddr2_eflpd ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_eflpd #define ka0c05_tlmem$v_tlddr2_marg ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_marg #define ka0c05_tlmem$l_tlstdera_3 ka0c05_tlmem$r_tlstdera_3_overlay.ka0c05_tlmem$l_tlstdera_3 #define ka0c05_tlmem$l_tlstderb_3 ka0c05_tlmem$r_tlstderb_3_overlay.ka0c05_tlmem$l_tlstderb_3 #define ka0c05_tlmem$l_tlstderc_3 ka0c05_tlmem$r_tlstderc_3_overlay.ka0c05_tlmem$l_tlstderc_3 #define ka0c05_tlmem$l_tlstderd_3 ka0c05_tlmem$r_tlstderd_3_overlay.ka0c05_tlmem$l_tlstderd_3 #define ka0c05_tlmem$l_tlstdere_3 ka0c05_tlmem$r_tlstdere_3_overlay.ka0c05_tlmem$l_tlstdere_3 #define ka0c05_tlmem$v_tlstdere_3_ste ka0c05_tlmem$r_tlstdere_3_overlay.ka0c05_tlmem$r_tlstdere_3_bits.ka0c05_tlmem$v_tlstdere_3_ste #define ka0c05_tlmem$v_tlstdere_3_vrc ka0c05_tlmem$r_tlstdere_3_overlay.ka0c05_tlmem$r_tlstdere_3_bits.ka0c05_tlmem$v_tlstdere_3_vrc #define ka0c05_tlmem$l_tlddr3 ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$l_tlddr3 #define ka0c05_tlmem$v_tlddr3_loe ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_loe #define ka0c05_tlmem$v_tlddr3_cder ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_cder #define ka0c05_tlmem$v_tlddr3_icfr ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_icfr #define ka0c05_tlmem$v_tlddr3_pat ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_pat #define ka0c05_tlmem$v_tlddr3_cflp ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_cflp #define ka0c05_tlmem$v_tlddr3_dflp ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_dflp #define ka0c05_tlmem$v_tlddr3_eflpc ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_eflpc #define ka0c05_tlmem$v_tlddr3_eflpd ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_eflpd #define ka0c05_tlmem$v_tlddr3_marg ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_marg #endif /* #if !defined(__VAXC) */ #define KA0C05_CMD$K_NOP 0 #define KA0C05_CMD$K_VICTIM 1 #define KA0C05_CMD$K_BUS_READ 2 #define KA0C05_CMD$K_BUS_WRITE 3 #define KA0C05_CMD$K_READ_BANK_LOCK 4 #define KA0C05_CMD$K_WRITE_BANK_UNLOCK 5 #define KA0C05_CMD$K_CSR_READ 6 #define KA0C05_CMD$K_CSR_WRITE 7 #define KA0C05_TIOP$M_TLDEV_DTYPE 0xFFFF #define KA0C05_TIOP$M_TLDEV_SWREV 0xFF0000 #define KA0C05_TIOP$M_TLDEV_HWREV 0xFF000000 #define KA0C05_TIOP$M_TLBER_ATCE 0x1 #define KA0C05_TIOP$M_TLBER_APE 0x2 #define KA0C05_TIOP$M_TLBER_BBE 0x4 #define KA0C05_TIOP$M_TLBER_LKTO 0x8 #define KA0C05_TIOP$M_TLBER_NAE 0x10 #define KA0C05_TIOP$M_TLBER_RTCE 0x20 #define KA0C05_TIOP$M_TLBER_ACKTCE 0x40 #define KA0C05_TIOP$M_TLBER_MMRE 0x80 #define KA0C05_TIOP$M_TLBER_FNAE 0x100 #define KA0C05_TIOP$M_TLBER_REQDE 0x200 #define KA0C05_TIOP$M_TLBER_ATDE 0x400 #define KA0C05_TIOP$M_TLBER_UDE 0x10000 #define KA0C05_TIOP$M_TLBER_CWDE 0x20000 #define KA0C05_TIOP$M_TLBER_CRDE 0x40000 #define KA0C05_TIOP$M_TLBER_DS0 0x100000 #define KA0C05_TIOP$M_TLBER_DS1 0x200000 #define KA0C05_TIOP$M_TLBER_DS2 0x400000 #define KA0C05_TIOP$M_TLBER_DS3 0x800000 #define KA0C05_TIOP$M_TLBER_DTDE 0x1000000 #define KA0C05_TIOP$M_TLBER_FDTCE 0x2000000 #define KA0C05_TIOP$M_TLBER_UACKE 0x4000000 #define KA0C05_TIOP$M_TLBER_ABTCE 0x8000000 #define KA0C05_TIOP$M_TLBER_DCTCE 0x10000000 #define KA0C05_TIOP$M_TLBER_SEQE 0x20000000 #define KA0C05_TIOP$M_TLBER_DSE 0x40000000 #define KA0C05_TIOP$M_TLBER_DTO 0x80000000 #define KA0C05_TIOP$M_TLCNR_CWDD 0x1 #define KA0C05_TIOP$M_TLCNR_CRDD 0x2 #define KA0C05_TIOP$M_TLCNR_LKTOD 0x4 #define KA0C05_TIOP$M_TLCNR_DTOD 0x8 #define KA0C05_TIOP$M_TLCNR_NODE_ID 0xF0 #define KA0C05_TIOP$M_TLCNR_VCNT 0xF00 #define KA0C05_TIOP$M_TLCNR_STF_A 0x1000 #define KA0C05_TIOP$M_TLCNR_STF_B 0x2000 #define KA0C05_TIOP$M_TLCNR_STF_C 0x4000 #define KA0C05_TIOP$M_TLCNR_STF_D 0x8000 #define KA0C05_TIOP$M_TLCNR_STF_E 0x10000 #define KA0C05_TIOP$M_TLCNR_STF_F 0x20000 #define KA0C05_TIOP$M_TLCNR_STF_G 0x40000 #define KA0C05_TIOP$M_TLCNR_STF_H 0x80000 #define KA0C05_TIOP$M_TLCNR_HALT_A 0x100000 #define KA0C05_TIOP$M_TLCNR_HALT_B 0x200000 #define KA0C05_TIOP$M_TLCNR_HALT_C 0x400000 #define KA0C05_TIOP$M_TLCNR_HALT_D 0x800000 #define KA0C05_TIOP$M_TLCNR_HALT_E 0x1000000 #define KA0C05_TIOP$M_TLCNR_HALT_F 0x2000000 #define KA0C05_TIOP$M_TLCNR_HALT_G 0x4000000 #define KA0C05_TIOP$M_TLCNR_HALT_H 0x8000000 #define KA0C05_TIOP$M_TLCNR_RSTSTAT 0x10000000 #define KA0C05_TIOP$M_TLCNR_NRST 0x40000000 #define KA0C05_TIOP$M_TLCNR_LOFE 0x80000000 #define KA0C05_TIOP$M_TLMMR0_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR0_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR0_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR0_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR0_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR0_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR1_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR1_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR1_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR1_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR1_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR1_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR2_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR2_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR2_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR2_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR2_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR2_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR3_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR3_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR3_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR3_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR3_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR3_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR4_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR4_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR4_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR4_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR4_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR4_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR5_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR5_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR5_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR5_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR5_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR5_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR6_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR6_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR6_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR6_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR6_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR6_VALID 0x80000000 #define KA0C05_TIOP$M_TLMMR7_INTMASK 0x3 #define KA0C05_TIOP$M_TLMMR7_ADRMASK 0xF0 #define KA0C05_TIOP$M_TLMMR7_INTLV 0x700 #define KA0C05_TIOP$M_TLMMR7_SBANK 0x800 #define KA0C05_TIOP$M_TLMMR7_ADDRESS 0x3FFF000 #define KA0C05_TIOP$M_TLMMR7_VALID 0x80000000 #define KA0C05_TIOP$M_TLFADR0_FADR 0xFFFFFFF8 #define KA0C05_TIOP$M_TLFADR1_FADR 0xFF #define KA0C05_TIOP$M_TLFADR1_FCMD 0x70000 #define KA0C05_TIOP$M_TLFADR1_FBANK 0xF00000 #define KA0C05_TIOP$M_TLFADR1_ADRV 0x1000000 #define KA0C05_TIOP$M_TLFADR1_CMDV 0x2000000 #define KA0C05_TIOP$M_TLFADR1_BANKV 0x4000000 #define KA0C05_TIOP$M_TLESR0_SYND0 0xFF #define KA0C05_TIOP$M_TLESR0_SYND1 0xFF00 #define KA0C05_TIOP$M_TLESR0_TDE 0x10000 #define KA0C05_TIOP$M_TLESR0_TCE 0x20000 #define KA0C05_TIOP$M_TLESR0_DVTCE 0x40000 #define KA0C05_TIOP$M_TLESR0_UECC 0x80000 #define KA0C05_TIOP$M_TLESR0_CWECC 0x100000 #define KA0C05_TIOP$M_TLESR0_CRECC 0x200000 #define KA0C05_TIOP$M_TLESR0_LOFSYN 0x80000000 #define KA0C05_TIOP$M_TLESR1_SYND0 0xFF #define KA0C05_TIOP$M_TLESR1_SYND1 0xFF00 #define KA0C05_TIOP$M_TLESR1_TDE 0x10000 #define KA0C05_TIOP$M_TLESR1_TCE 0x20000 #define KA0C05_TIOP$M_TLESR1_DVTCE 0x40000 #define KA0C05_TIOP$M_TLESR1_UECC 0x80000 #define KA0C05_TIOP$M_TLESR1_CWECC 0x100000 #define KA0C05_TIOP$M_TLESR1_CRECC 0x200000 #define KA0C05_TIOP$M_TLESR1_LOFSYN 0x80000000 #define KA0C05_TIOP$M_TLESR2_SYND0 0xFF #define KA0C05_TIOP$M_TLESR2_SYND1 0xFF00 #define KA0C05_TIOP$M_TLESR2_TDE 0x10000 #define KA0C05_TIOP$M_TLESR2_TCE 0x20000 #define KA0C05_TIOP$M_TLESR2_DVTCE 0x40000 #define KA0C05_TIOP$M_TLESR2_UECC 0x80000 #define KA0C05_TIOP$M_TLESR2_CWECC 0x100000 #define KA0C05_TIOP$M_TLESR2_CRECC 0x200000 #define KA0C05_TIOP$M_TLESR2_LOFSYN 0x80000000 #define KA0C05_TIOP$M_TLESR3_SYND0 0xFF #define KA0C05_TIOP$M_TLESR3_SYND1 0xFF00 #define KA0C05_TIOP$M_TLESR3_TDE 0x10000 #define KA0C05_TIOP$M_TLESR3_TCE 0x20000 #define KA0C05_TIOP$M_TLESR3_DVTCE 0x40000 #define KA0C05_TIOP$M_TLESR3_UECC 0x80000 #define KA0C05_TIOP$M_TLESR3_CWECC 0x100000 #define KA0C05_TIOP$M_TLESR3_CRECC 0x200000 #define KA0C05_TIOP$M_TLESR3_LOFSYN 0x80000000 #define KA0C05_TIOP$M_TLILID0_IDENT 0xFFFF #define KA0C05_TIOP$M_TLILID1_IDENT 0xFFFF #define KA0C05_TIOP$M_TLILID2_IDENT 0xFFFF #define KA0C05_TIOP$M_TLILID3_IDENT 0xFFFF #define KA0C05_TIOP$M_TLCPUMASK_MASK 0xFFFF #define KA0C05_TIOP$M_TLRMR0A_MASK 0xF #define KA0C05_TIOP$M_TLRMR0A_ILV_EN 0x10 #define KA0C05_TIOP$M_TLRMR0A_BADR 0xFFFFF00 #define KA0C05_TIOP$M_TLRMR0A_NVRAM 0x40000000 #define KA0C05_TIOP$M_TLRMR0A_VALID 0x80000000 #define KA0C05_TIOP$M_TLRMR0B_MASK 0xF #define KA0C05_TIOP$M_TLRMR0B_ILV_EN 0x10 #define KA0C05_TIOP$M_TLRMR0B_BADR 0xFFFFF00 #define KA0C05_TIOP$M_TLRMR0B_NVRAM 0x40000000 #define KA0C05_TIOP$M_TLRMR0B_VALID 0x80000000 #define KA0C05_TIOP$M_TLRMR1A_MASK 0xF #define KA0C05_TIOP$M_TLRMR1A_ILV_EN 0x10 #define KA0C05_TIOP$M_TLRMR1A_BADR 0xFFFFF00 #define KA0C05_TIOP$M_TLRMR1A_NVRAM 0x40000000 #define KA0C05_TIOP$M_TLRMR1A_VALID 0x80000000 #define KA0C05_TIOP$M_TLRMR1B_MASK 0xF #define KA0C05_TIOP$M_TLRMR1B_ILV_EN 0x10 #define KA0C05_TIOP$M_TLRMR1B_BADR 0xFFFFF00 #define KA0C05_TIOP$M_TLRMR1B_NVRAM 0x40000000 #define KA0C05_TIOP$M_TLRMR1B_VALID 0x80000000 #define KA0C05_TIOP$M_TLICMSR_ARB_CTL 0x3 #define KA0C05_TIOP$M_TLICMSR_SUP_CTL 0xC #define KA0C05_TIOP$M_TLICMSR_FORCE_ACK 0x10 #define KA0C05_TIOP$M_TLICMSR_RMNXM 0x20 #define KA0C05_TIOP$M_TLICMSR_ACK_DSBL 0x40 #define KA0C05_TIOP$M_TLICNSE_ACK_DROP 0x4 #define KA0C05_TIOP$M_TLICNSE_RMNXM 0x8 #define KA0C05_TIOP$M_TLICNSE_MBX_STAT 0xF0 #define KA0C05_TIOP$M_TLICNSE_OFLO 0xF00 #define KA0C05_TIOP$M_TLICNSE_PKT_E 0xF000 #define KA0C05_TIOP$M_TLICNSE_PAR_E 0xF0000 #define KA0C05_TIOP$M_TLICNSE_UP_HDP_IE 0x300000 #define KA0C05_TIOP$M_TLICNSE_INT_E 0x400000 #define KA0C05_TIOP$M_TLICNSE_DN_VRTX_E 0x1800000 #define KA0C05_TIOP$M_TLICNSE_UP_VRTX_E 0x6000000 #define KA0C05_TIOP$M_TLICNSE_IE 0x8000000 #define KA0C05_TIOP$M_TLICNSE_BUS_PE 0x10000000 #define KA0C05_TIOP$M_TLICNSE_WND_OFLO 0x20000000 #define KA0C05_TIOP$M_TLICNSE_RM_OFLO 0x40000000 #define KA0C05_TIOP$M_TLICNSE_INT_NSES 0x80000000 #define KA0C05_TIOP$M_TLICDR_IDP_PE 0x1 #define KA0C05_TIOP$M_TLICDR_DSE 0x2 #define KA0C05_TIOP$M_TLICDR_DTO 0x4 #define KA0C05_TIOP$M_TLICDR_DIS_CMD 0x8 #define KA0C05_TIOP$M_TLICDR_DIS_FLT 0x10 #define KA0C05_TIOP$M_TLICDR_CMD_PE 0x20 #define KA0C05_TIOP$M_TLICDR_BNK_BSY 0x40 #define KA0C05_TIOP$M_TLICDR_IDP_CMD_PE 0x100 #define KA0C05_TIOP$M_TLICDR_EN_HID 0x80000000 #define KA0C05_TIOP$M_TLICMTR_MBX_TIP 0xF #define KA0C05_TIOP$M_TLICWRT_WIP 0xF #define KA0C05_TIOP$M_TLIDPNSE_ERR 0x1 #define KA0C05_TIOP$M_TLIDPNSE_POK 0x2 #define KA0C05_TIOP$M_TLIDPNSE_CBLOK 0x4 #define KA0C05_TIOP$M_TLIDPNSE_POK_TRAN 0x8 #define KA0C05_TIOP$M_TLIDPNSE_SOFT_ERR 0x10 #define KA0C05_TIOP$M_TLIDPNSE_RM_M_ERR 0xC00000 #define KA0C05_TIOP$M_TLIDPNSE_CPE 0x1000000 #define KA0C05_TIOP$M_TLIDPNSE_UP_V_ERR 0x6000000 #define KA0C05_TIOP$M_TLIDPNSE_IE 0x8000000 #define KA0C05_TIOP$M_TLIDPNSE_PE 0x10000000 #define KA0C05_TIOP$M_TLIDPNSE_RESET 0x80000000 #define KA0C05_TIOP$M_TLIPMASK_CPU 0xFFFF #define KA0C05_TIOP$M_TLIDPVR_VECTOR 0xFFFF #define KA0C05_TIOP$M_TLIBR_RCV_SDAT 0x1 #define KA0C05_TIOP$M_TLIBR_XMT_SDAT 0x2 #define KA0C05_TIOP$M_TLIBR_SCLK 0x4 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_tiop { #pragma __nomember_alignment __union { unsigned int ka0c05_tiop$l_tldev; __struct { unsigned ka0c05_tiop$v_tldev_dtype : 16; unsigned ka0c05_tiop$v_tldev_swrev : 8; unsigned ka0c05_tiop$v_tldev_hwrev : 8; } ka0c05_tiop$r_tldev_bits; } ka0c05_tiop$r_tldev_overlay; unsigned char ka0c05_tiop$b_f1400 [60]; __union { unsigned int ka0c05_tiop$l_tlber; __struct { unsigned ka0c05_tiop$v_tlber_atce : 1; unsigned ka0c05_tiop$v_tlber_ape : 1; unsigned ka0c05_tiop$v_tlber_bbe : 1; unsigned ka0c05_tiop$v_tlber_lkto : 1; unsigned ka0c05_tiop$v_tlber_nae : 1; unsigned ka0c05_tiop$v_tlber_rtce : 1; unsigned ka0c05_tiop$v_tlber_acktce : 1; unsigned ka0c05_tiop$v_tlber_mmre : 1; unsigned ka0c05_tiop$v_tlber_fnae : 1; unsigned ka0c05_tiop$v_tlber_reqde : 1; unsigned ka0c05_tiop$v_tlber_atde : 1; unsigned ka0c05_tiop$v_tlber_f1 : 5; unsigned ka0c05_tiop$v_tlber_ude : 1; unsigned ka0c05_tiop$v_tlber_cwde : 1; unsigned ka0c05_tiop$v_tlber_crde : 1; unsigned ka0c05_tiop$v_tlber_cwde2 : 1; unsigned ka0c05_tiop$v_tlber_ds0 : 1; unsigned ka0c05_tiop$v_tlber_ds1 : 1; unsigned ka0c05_tiop$v_tlber_ds2 : 1; unsigned ka0c05_tiop$v_tlber_ds3 : 1; unsigned ka0c05_tiop$v_tlber_dtde : 1; unsigned ka0c05_tiop$v_tlber_fdtce : 1; unsigned ka0c05_tiop$v_tlber_uacke : 1; unsigned ka0c05_tiop$v_tlber_abtce : 1; unsigned ka0c05_tiop$v_tlber_dctce : 1; unsigned ka0c05_tiop$v_tlber_seqe : 1; unsigned ka0c05_tiop$v_tlber_dse : 1; unsigned ka0c05_tiop$v_tlber_dto : 1; } ka0c05_tiop$r_tlber_bits; } ka0c05_tiop$r_tlber_overlay; unsigned char ka0c05_tiop$b_f1410 [60]; __union { unsigned int ka0c05_tiop$l_tlcnr; __struct { unsigned ka0c05_tiop$v_tlcnr_cwdd : 1; unsigned ka0c05_tiop$v_tlcnr_crdd : 1; unsigned ka0c05_tiop$v_tlcnr_lktod : 1; unsigned ka0c05_tiop$v_tlcnr_dtod : 1; unsigned ka0c05_tiop$v_tlcnr_node_id : 4; unsigned ka0c05_tiop$v_tlcnr_vcnt : 4; unsigned ka0c05_tiop$v_tlcnr_stf_a : 1; unsigned ka0c05_tiop$v_tlcnr_stf_b : 1; unsigned ka0c05_tiop$v_tlcnr_stf_c : 1; unsigned ka0c05_tiop$v_tlcnr_stf_d : 1; unsigned ka0c05_tiop$v_tlcnr_stf_e : 1; unsigned ka0c05_tiop$v_tlcnr_stf_f : 1; unsigned ka0c05_tiop$v_tlcnr_stf_g : 1; unsigned ka0c05_tiop$v_tlcnr_stf_h : 1; unsigned ka0c05_tiop$v_tlcnr_halt_a : 1; unsigned ka0c05_tiop$v_tlcnr_halt_b : 1; unsigned ka0c05_tiop$v_tlcnr_halt_c : 1; unsigned ka0c05_tiop$v_tlcnr_halt_d : 1; unsigned ka0c05_tiop$v_tlcnr_halt_e : 1; unsigned ka0c05_tiop$v_tlcnr_halt_f : 1; unsigned ka0c05_tiop$v_tlcnr_halt_g : 1; unsigned ka0c05_tiop$v_tlcnr_halt_h : 1; unsigned ka0c05_tiop$v_tlcnr_rststat : 1; unsigned ka0c05_tiop$v_tlcnr_f1 : 1; unsigned ka0c05_tiop$v_tlcnr_nrst : 1; unsigned ka0c05_tiop$v_tlcnr_lofe : 1; } ka0c05_tiop$r_tlcnr_bits; } ka0c05_tiop$r_tlcnr_overlay; unsigned char ka0c05_tiop$b_f1420 [380]; __union { unsigned int ka0c05_tiop$l_tlmmr0; __struct { unsigned ka0c05_tiop$v_tlmmr0_intmask : 2; unsigned ka0c05_tiop$v_tlmmr0_f1 : 2; unsigned ka0c05_tiop$v_tlmmr0_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr0_intlv : 3; unsigned ka0c05_tiop$v_tlmmr0_sbank : 1; unsigned ka0c05_tiop$v_tlmmr0_address : 14; unsigned ka0c05_tiop$v_tlmmr0_f2 : 5; unsigned ka0c05_tiop$v_tlmmr0_valid : 1; } ka0c05_tiop$r_tlmmr0_bits; } ka0c05_tiop$r_tlmmr0_overlay; unsigned char ka0c05_tiop$b_f1440 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr1; __struct { unsigned ka0c05_tiop$v_tlmmr1_intmask : 2; unsigned ka0c05_tiop$v_tlmmr1_f1 : 2; unsigned ka0c05_tiop$v_tlmmr1_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr1_intlv : 3; unsigned ka0c05_tiop$v_tlmmr1_sbank : 1; unsigned ka0c05_tiop$v_tlmmr1_address : 14; unsigned ka0c05_tiop$v_tlmmr1_f2 : 5; unsigned ka0c05_tiop$v_tlmmr1_valid : 1; } ka0c05_tiop$r_tlmmr1_bits; } ka0c05_tiop$r_tlmmr1_overlay; unsigned char ka0c05_tiop$b_f1450 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr2; __struct { unsigned ka0c05_tiop$v_tlmmr2_intmask : 2; unsigned ka0c05_tiop$v_tlmmr2_f1 : 2; unsigned ka0c05_tiop$v_tlmmr2_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr2_intlv : 3; unsigned ka0c05_tiop$v_tlmmr2_sbank : 1; unsigned ka0c05_tiop$v_tlmmr2_address : 14; unsigned ka0c05_tiop$v_tlmmr2_f2 : 5; unsigned ka0c05_tiop$v_tlmmr2_valid : 1; } ka0c05_tiop$r_tlmmr2_bits; } ka0c05_tiop$r_tlmmr2_overlay; unsigned char ka0c05_tiop$b_f1460 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr3; __struct { unsigned ka0c05_tiop$v_tlmmr3_intmask : 2; unsigned ka0c05_tiop$v_tlmmr3_f1 : 2; unsigned ka0c05_tiop$v_tlmmr3_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr3_intlv : 3; unsigned ka0c05_tiop$v_tlmmr3_sbank : 1; unsigned ka0c05_tiop$v_tlmmr3_address : 14; unsigned ka0c05_tiop$v_tlmmr3_f2 : 5; unsigned ka0c05_tiop$v_tlmmr3_valid : 1; } ka0c05_tiop$r_tlmmr3_bits; } ka0c05_tiop$r_tlmmr3_overlay; unsigned char ka0c05_tiop$b_f1470 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr4; __struct { unsigned ka0c05_tiop$v_tlmmr4_intmask : 2; unsigned ka0c05_tiop$v_tlmmr4_f1 : 2; unsigned ka0c05_tiop$v_tlmmr4_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr4_intlv : 3; unsigned ka0c05_tiop$v_tlmmr4_sbank : 1; unsigned ka0c05_tiop$v_tlmmr4_address : 14; unsigned ka0c05_tiop$v_tlmmr4_f2 : 5; unsigned ka0c05_tiop$v_tlmmr4_valid : 1; } ka0c05_tiop$r_tlmmr4_bits; } ka0c05_tiop$r_tlmmr4_overlay; unsigned char ka0c05_tiop$b_f1480 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr5; __struct { unsigned ka0c05_tiop$v_tlmmr5_intmask : 2; unsigned ka0c05_tiop$v_tlmmr5_f1 : 2; unsigned ka0c05_tiop$v_tlmmr5_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr5_intlv : 3; unsigned ka0c05_tiop$v_tlmmr5_sbank : 1; unsigned ka0c05_tiop$v_tlmmr5_address : 14; unsigned ka0c05_tiop$v_tlmmr5_f2 : 5; unsigned ka0c05_tiop$v_tlmmr5_valid : 1; } ka0c05_tiop$r_tlmmr5_bits; } ka0c05_tiop$r_tlmmr5_overlay; unsigned char ka0c05_tiop$b_f1490 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr6; __struct { unsigned ka0c05_tiop$v_tlmmr6_intmask : 2; unsigned ka0c05_tiop$v_tlmmr6_f1 : 2; unsigned ka0c05_tiop$v_tlmmr6_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr6_intlv : 3; unsigned ka0c05_tiop$v_tlmmr6_sbank : 1; unsigned ka0c05_tiop$v_tlmmr6_address : 14; unsigned ka0c05_tiop$v_tlmmr6_f2 : 5; unsigned ka0c05_tiop$v_tlmmr6_valid : 1; } ka0c05_tiop$r_tlmmr6_bits; } ka0c05_tiop$r_tlmmr6_overlay; unsigned char ka0c05_tiop$b_f1500 [60]; __union { unsigned int ka0c05_tiop$l_tlmmr7; __struct { unsigned ka0c05_tiop$v_tlmmr7_intmask : 2; unsigned ka0c05_tiop$v_tlmmr7_f1 : 2; unsigned ka0c05_tiop$v_tlmmr7_adrmask : 4; unsigned ka0c05_tiop$v_tlmmr7_intlv : 3; unsigned ka0c05_tiop$v_tlmmr7_sbank : 1; unsigned ka0c05_tiop$v_tlmmr7_address : 14; unsigned ka0c05_tiop$v_tlmmr7_f2 : 5; unsigned ka0c05_tiop$v_tlmmr7_valid : 1; } ka0c05_tiop$r_tlmmr7_bits; } ka0c05_tiop$r_tlmmr7_overlay; unsigned char ka0c05_tiop$b_f1510 [572]; __union { unsigned int ka0c05_tiop$l_tlfadr0; __struct { unsigned ka0c05_tiop$v_tlfadr0_f1 : 3; unsigned ka0c05_tiop$v_tlfadr0_fadr : 29; } ka0c05_tiop$r_tlfadr0_bits; } ka0c05_tiop$r_tlfadr0_overlay; unsigned char ka0c05_tiop$b_f1520 [60]; __union { unsigned int ka0c05_tiop$l_tlfadr1; __struct { unsigned ka0c05_tiop$v_tlfadr1_fadr : 8; unsigned ka0c05_tiop$v_tlfadr1_f1 : 8; unsigned ka0c05_tiop$v_tlfadr1_fcmd : 3; unsigned ka0c05_tiop$v_tlfadr1_f2 : 1; unsigned ka0c05_tiop$v_tlfadr1_fbank : 4; unsigned ka0c05_tiop$v_tlfadr1_adrv : 1; unsigned ka0c05_tiop$v_tlfadr1_cmdv : 1; unsigned ka0c05_tiop$v_tlfadr1_bankv : 1; unsigned ka0c05_tiop$v_tlfadr1_fill3 : 5; } ka0c05_tiop$r_tlfadr1_bits; } ka0c05_tiop$r_tlfadr1_overlay; unsigned char ka0c05_tiop$b_f1530 [60]; __union { unsigned int ka0c05_tiop$l_tlesr0; __struct { unsigned ka0c05_tiop$v_tlesr0_synd0 : 8; unsigned ka0c05_tiop$v_tlesr0_synd1 : 8; unsigned ka0c05_tiop$v_tlesr0_tde : 1; unsigned ka0c05_tiop$v_tlesr0_tce : 1; unsigned ka0c05_tiop$v_tlesr0_dvtce : 1; unsigned ka0c05_tiop$v_tlesr0_uecc : 1; unsigned ka0c05_tiop$v_tlesr0_cwecc : 1; unsigned ka0c05_tiop$v_tlesr0_crecc : 1; unsigned ka0c05_tiop$v_tlesr0_f1 : 9; unsigned ka0c05_tiop$v_tlesr0_lofsyn : 1; } ka0c05_tiop$r_tlesr0_bits; } ka0c05_tiop$r_tlesr0_overlay; unsigned char ka0c05_tiop$b_f1540 [60]; __union { unsigned int ka0c05_tiop$l_tlesr1; __struct { unsigned ka0c05_tiop$v_tlesr1_synd0 : 8; unsigned ka0c05_tiop$v_tlesr1_synd1 : 8; unsigned ka0c05_tiop$v_tlesr1_tde : 1; unsigned ka0c05_tiop$v_tlesr1_tce : 1; unsigned ka0c05_tiop$v_tlesr1_dvtce : 1; unsigned ka0c05_tiop$v_tlesr1_uecc : 1; unsigned ka0c05_tiop$v_tlesr1_cwecc : 1; unsigned ka0c05_tiop$v_tlesr1_crecc : 1; unsigned ka0c05_tiop$v_tlesr1_f1 : 9; unsigned ka0c05_tiop$v_tlesr1_lofsyn : 1; } ka0c05_tiop$r_tlesr1_bits; } ka0c05_tiop$r_tlesr1_overlay; unsigned char ka0c05_tiop$b_f1550 [60]; __union { unsigned int ka0c05_tiop$l_tlesr2; __struct { unsigned ka0c05_tiop$v_tlesr2_synd0 : 8; unsigned ka0c05_tiop$v_tlesr2_synd1 : 8; unsigned ka0c05_tiop$v_tlesr2_tde : 1; unsigned ka0c05_tiop$v_tlesr2_tce : 1; unsigned ka0c05_tiop$v_tlesr2_dvtce : 1; unsigned ka0c05_tiop$v_tlesr2_uecc : 1; unsigned ka0c05_tiop$v_tlesr2_cwecc : 1; unsigned ka0c05_tiop$v_tlesr2_crecc : 1; unsigned ka0c05_tiop$v_tlesr2_f1 : 9; unsigned ka0c05_tiop$v_tlesr2_lofsyn : 1; } ka0c05_tiop$r_tlesr2_bits; } ka0c05_tiop$r_tlesr2_overlay; unsigned char ka0c05_tiop$b_f1560 [60]; __union { unsigned int ka0c05_tiop$l_tlesr3; __struct { unsigned ka0c05_tiop$v_tlesr3_synd0 : 8; unsigned ka0c05_tiop$v_tlesr3_synd1 : 8; unsigned ka0c05_tiop$v_tlesr3_tde : 1; unsigned ka0c05_tiop$v_tlesr3_tce : 1; unsigned ka0c05_tiop$v_tlesr3_dvtce : 1; unsigned ka0c05_tiop$v_tlesr3_uecc : 1; unsigned ka0c05_tiop$v_tlesr3_cwecc : 1; unsigned ka0c05_tiop$v_tlesr3_crecc : 1; unsigned ka0c05_tiop$v_tlesr3_f1 : 9; unsigned ka0c05_tiop$v_tlesr3_lofsyn : 1; } ka0c05_tiop$r_tlesr3_bits; } ka0c05_tiop$r_tlesr3_overlay; unsigned char ka0c05_tiop$b_f1570 [700]; __union { unsigned int ka0c05_tiop$l_tlilid0; __struct { unsigned ka0c05_tiop$v_tlilid0_ident : 16; unsigned ka0c05_tiop$v_tlilid0_f1 : 16; } ka0c05_tiop$r_tlilid0_bits; } ka0c05_tiop$r_tlilid0_overlay; unsigned char ka0c05_tiop$b_f1580 [60]; __union { unsigned int ka0c05_tiop$l_tlilid1; __struct { unsigned ka0c05_tiop$v_tlilid1_ident : 16; unsigned ka0c05_tiop$v_tlilid1_f1 : 16; } ka0c05_tiop$r_tlilid1_bits; } ka0c05_tiop$r_tlilid1_overlay; unsigned char ka0c05_tiop$b_f1590 [60]; __union { unsigned int ka0c05_tiop$l_tlilid2; __struct { unsigned ka0c05_tiop$v_tlilid2_ident : 16; unsigned ka0c05_tiop$v_tlilid2_f1 : 16; } ka0c05_tiop$r_tlilid2_bits; } ka0c05_tiop$r_tlilid2_overlay; unsigned char ka0c05_tiop$b_f1600 [60]; __union { unsigned int ka0c05_tiop$l_tlilid3; __struct { unsigned ka0c05_tiop$v_tlilid3_ident : 16; unsigned ka0c05_tiop$v_tlilid3_f1 : 16; } ka0c05_tiop$r_tlilid3_bits; } ka0c05_tiop$r_tlilid3_overlay; unsigned char ka0c05_tiop$b_f1610 [60]; __union { unsigned int ka0c05_tiop$l_tlcpumask; __struct { unsigned ka0c05_tiop$v_tlcpumask_mask : 16; unsigned ka0c05_tiop$v_tlcpumask_f1 : 16; } ka0c05_tiop$r_tlcpumask_bits; } ka0c05_tiop$r_tlcpumask_overlay; unsigned char ka0c05_tiop$b_f1620 [252]; __union { __int64 ka0c05_tiop$q_tlmbpr; } ka0c05_tiop$r_tlmbpr_overlay; unsigned char ka0c05_tiop$b_f1630 [4600]; __union { unsigned int ka0c05_tiop$l_tlrmr0a; __struct { unsigned ka0c05_tiop$v_tlrmr0a_mask : 4; unsigned ka0c05_tiop$v_tlrmr0a_ilv_en : 1; unsigned ka0c05_tiop$v_tlrmr0a_f1 : 3; unsigned ka0c05_tiop$v_tlrmr0a_badr : 20; unsigned ka0c05_tiop$v_tlrmr0a_f2 : 2; unsigned ka0c05_tiop$v_tlrmr0a_nvram : 1; unsigned ka0c05_tiop$v_tlrmr0a_valid : 1; } ka0c05_tiop$r_tlrmr0a_bits; } ka0c05_tiop$r_tlrmr0a_overlay; unsigned char ka0c05_tiop$b_f1640 [60]; __union { unsigned int ka0c05_tiop$l_tlrmr0b; __struct { unsigned ka0c05_tiop$v_tlrmr0b_mask : 4; unsigned ka0c05_tiop$v_tlrmr0b_ilv_en : 1; unsigned ka0c05_tiop$v_tlrmr0b_f1 : 3; unsigned ka0c05_tiop$v_tlrmr0b_badr : 20; unsigned ka0c05_tiop$v_tlrmr0b_f2 : 2; unsigned ka0c05_tiop$v_tlrmr0b_nvram : 1; unsigned ka0c05_tiop$v_tlrmr0b_valid : 1; } ka0c05_tiop$r_tlrmr0b_bits; } ka0c05_tiop$r_tlrmr0b_overlay; unsigned char ka0c05_tiop$b_f1650 [60]; __union { unsigned int ka0c05_tiop$l_tlrmr1a; __struct { unsigned ka0c05_tiop$v_tlrmr1a_mask : 4; unsigned ka0c05_tiop$v_tlrmr1a_ilv_en : 1; unsigned ka0c05_tiop$v_tlrmr1a_f1 : 3; unsigned ka0c05_tiop$v_tlrmr1a_badr : 20; unsigned ka0c05_tiop$v_tlrmr1a_f2 : 2; unsigned ka0c05_tiop$v_tlrmr1a_nvram : 1; unsigned ka0c05_tiop$v_tlrmr1a_valid : 1; } ka0c05_tiop$r_tlrmr1a_bits; } ka0c05_tiop$r_tlrmr1a_overlay; unsigned char ka0c05_tiop$b_f1660 [60]; __union { unsigned int ka0c05_tiop$l_tlrmr1b; __struct { unsigned ka0c05_tiop$v_tlrmr1b_mask : 4; unsigned ka0c05_tiop$v_tlrmr1b_ilv_en : 1; unsigned ka0c05_tiop$v_tlrmr1b_f1 : 3; unsigned ka0c05_tiop$v_tlrmr1b_badr : 20; unsigned ka0c05_tiop$v_tlrmr1b_f2 : 2; unsigned ka0c05_tiop$v_tlrmr1b_nvram : 1; unsigned ka0c05_tiop$v_tlrmr1b_valid : 1; } ka0c05_tiop$r_tlrmr1b_bits; } ka0c05_tiop$r_tlrmr1b_overlay; unsigned char ka0c05_tiop$b_f1670 [316]; __union { unsigned int ka0c05_tiop$l_tlicmsr; __struct { unsigned ka0c05_tiop$v_tlicmsr_arb_ctl : 2; unsigned ka0c05_tiop$v_tlicmsr_sup_ctl : 2; unsigned ka0c05_tiop$v_tlicmsr_force_ack : 1; unsigned ka0c05_tiop$v_tlicmsr_rmnxm : 1; unsigned ka0c05_tiop$v_tlicmsr_ack_dsbl : 1; unsigned ka0c05_tiop$v_tlicmsr_f1 : 25; } ka0c05_tiop$r_tlicmsr_bits; } ka0c05_tiop$r_tlicmsr_overlay; unsigned char ka0c05_tiop$b_f1700 [60]; __union { unsigned int ka0c05_tiop$l_tlicnse; __struct { unsigned ka0c05_tiop$v_tlicnse_f1 : 2; unsigned ka0c05_tiop$v_tlicnse_ack_drop : 1; unsigned ka0c05_tiop$v_tlicnse_rmnxm : 1; unsigned ka0c05_tiop$v_tlicnse_mbx_stat : 4; unsigned ka0c05_tiop$v_tlicnse_oflo : 4; unsigned ka0c05_tiop$v_tlicnse_pkt_e : 4; unsigned ka0c05_tiop$v_tlicnse_par_e : 4; unsigned ka0c05_tiop$v_tlicnse_up_hdp_ie : 2; unsigned ka0c05_tiop$v_tlicnse_int_e : 1; unsigned ka0c05_tiop$v_tlicnse_dn_vrtx_e : 2; unsigned ka0c05_tiop$v_tlicnse_up_vrtx_e : 2; unsigned ka0c05_tiop$v_tlicnse_ie : 1; unsigned ka0c05_tiop$v_tlicnse_bus_pe : 1; unsigned ka0c05_tiop$v_tlicnse_wnd_oflo : 1; unsigned ka0c05_tiop$v_tlicnse_rm_oflo : 1; unsigned ka0c05_tiop$v_tlicnse_int_nses : 1; } ka0c05_tiop$r_tlicnse_bits; } ka0c05_tiop$r_tlicnse_overlay; unsigned char ka0c05_tiop$b_f1710 [60]; __union { unsigned int ka0c05_tiop$l_tlicdr; __struct { unsigned ka0c05_tiop$v_tlicdr_idp_pe : 1; unsigned ka0c05_tiop$v_tlicdr_dse : 1; unsigned ka0c05_tiop$v_tlicdr_dto : 1; unsigned ka0c05_tiop$v_tlicdr_dis_cmd : 1; unsigned ka0c05_tiop$v_tlicdr_dis_flt : 1; unsigned ka0c05_tiop$v_tlicdr_cmd_pe : 1; unsigned ka0c05_tiop$v_tlicdr_bnk_bsy : 1; unsigned ka0c05_tiop$v_tlicdr_f1 : 1; unsigned ka0c05_tiop$v_tlicdr_idp_cmd_pe : 1; unsigned ka0c05_tiop$v_tlicdr_f2 : 22; unsigned ka0c05_tiop$v_tlicdr_en_hid : 1; } ka0c05_tiop$r_tlicdr_bits; } ka0c05_tiop$r_tlicdr_overlay; unsigned char ka0c05_tiop$b_f1720 [60]; __union { unsigned int ka0c05_tiop$l_tlicmtr; __struct { unsigned ka0c05_tiop$v_tlicmtr_mbx_tip : 4; unsigned ka0c05_tiop$v_tlicmtr_f1 : 28; } ka0c05_tiop$r_tlicmtr_bits; } ka0c05_tiop$r_tlicmtr_overlay; unsigned char ka0c05_tiop$b_f1730 [60]; __union { unsigned int ka0c05_tiop$l_tlicwrt; __struct { unsigned ka0c05_tiop$v_tlicwrt_wip : 4; unsigned ka0c05_tiop$v_tlicwrt_f1 : 28; } ka0c05_tiop$r_tlicwrt_bits; } ka0c05_tiop$r_tlicwrt_overlay; unsigned char ka0c05_tiop$b_f1740 [60]; __union { unsigned int ka0c05_tiop$l_tlidpnse1; __struct { unsigned ka0c05_tiop$v_tlidpnse_err : 1; unsigned ka0c05_tiop$v_tlidpnse_pok : 1; unsigned ka0c05_tiop$v_tlidpnse_cblok : 1; unsigned ka0c05_tiop$v_tlidpnse_pok_tran : 1; unsigned ka0c05_tiop$v_tlidpnse_soft_err : 1; unsigned ka0c05_tiop$v_tlidpnse_f1 : 17; unsigned ka0c05_tiop$v_tlidpnse_rm_m_err : 2; unsigned ka0c05_tiop$v_tlidpnse_cpe : 1; unsigned ka0c05_tiop$v_tlidpnse_up_v_err : 2; unsigned ka0c05_tiop$v_tlidpnse_ie : 1; unsigned ka0c05_tiop$v_tlidpnse_pe : 1; unsigned ka0c05_tiop$v_tlidpnse_f2 : 2; unsigned ka0c05_tiop$v_tlidpnse_reset : 1; } ka0c05_tiop$r_tlidpnse_bits; } ka0c05_tiop$r_tlidpnse1_overlay; unsigned char ka0c05_tiop$b_f1750 [60]; __union { unsigned int ka0c05_tiop$l_tlidpdr1; } ka0c05_tiop$r_tlidpdr1_overlay; unsigned char ka0c05_tiop$b_f1760 [188]; __union { unsigned int ka0c05_tiop$l_tlidpnse2; } ka0c05_tiop$r_tlidpnse2_overlay; unsigned char ka0c05_tiop$b_f1770 [60]; __union { unsigned int ka0c05_tiop$l_tlidpdr2; } ka0c05_tiop$r_tlidpdr2_overlay; unsigned char ka0c05_tiop$b_f1780 [188]; __union { unsigned int ka0c05_tiop$l_tlidpnse3; } ka0c05_tiop$r_tlidpnse3_overlay; unsigned char ka0c05_tiop$b_f1790 [60]; __union { unsigned int ka0c05_tiop$l_tlidpdr3; } ka0c05_tiop$r_tlidpdr3_overlay; unsigned char ka0c05_tiop$b_f1800 [1724]; __union { unsigned int ka0c05_tiop$l_tlidpnse0; } ka0c05_tiop$r_tlidpnse0_overlay; unsigned char ka0c05_tiop$b_f1810 [60]; __union { unsigned int ka0c05_tiop$l_tlidpdr0; } ka0c05_tiop$r_tlidpdr0_overlay; unsigned char ka0c05_tiop$b_f1820 [60]; __union { unsigned int ka0c05_tiop$l_tlipmask; __struct { unsigned ka0c05_tiop$v_tlipmask_cpu : 16; unsigned ka0c05_tiop$v_tlipmask_f1 : 16; } ka0c05_tiop$r_tlipmask_bits; } ka0c05_tiop$r_tlipmask_overlay; unsigned char ka0c05_tiop$b_fill830 [124]; __union { unsigned int ka0c05_tiop$l_tlidpvr; __struct { unsigned ka0c05_tiop$v_tlidpvr_vector : 16; unsigned ka0c05_tiop$v_tlidpvr_f1 : 16; } ka0c05_tiop$r_tlidpvr_bits; } ka0c05_tiop$r_tlidpvr_overlay; unsigned char ka0c05_tiop$b_f1840 [60]; __union { unsigned int ka0c05_tiop$l_tlidpmsr; } ka0c05_tiop$r_tlidpmsr_overlay; unsigned char ka0c05_tiop$b_f1850 [60]; __union { unsigned int ka0c05_tiop$l_tlibr; __struct { unsigned ka0c05_tiop$v_tlibr_rcv_sdat : 1; unsigned ka0c05_tiop$v_tlibr_xmt_sdat : 1; unsigned ka0c05_tiop$v_tlibr_sclk : 1; unsigned ka0c05_tiop$v_tlibr_f1 : 29; } ka0c05_tiop$r_tlibr_bits; } ka0c05_tiop$r_tlibr_overlay; unsigned char ka0c05_tiop$b_f1860 [5180]; } KA0C05_TIOP; #if !defined(__VAXC) #define ka0c05_tiop$l_tldev ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$l_tldev #define ka0c05_tiop$v_tldev_dtype ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$r_tldev_bits.ka0c05_tiop$v_tldev_dtype #define ka0c05_tiop$v_tldev_swrev ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$r_tldev_bits.ka0c05_tiop$v_tldev_swrev #define ka0c05_tiop$v_tldev_hwrev ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$r_tldev_bits.ka0c05_tiop$v_tldev_hwrev #define ka0c05_tiop$l_tlber ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$l_tlber #define ka0c05_tiop$v_tlber_atce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_atce #define ka0c05_tiop$v_tlber_ape ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ape #define ka0c05_tiop$v_tlber_bbe ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_bbe #define ka0c05_tiop$v_tlber_lkto ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_lkto #define ka0c05_tiop$v_tlber_nae ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_nae #define ka0c05_tiop$v_tlber_rtce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_rtce #define ka0c05_tiop$v_tlber_acktce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_acktce #define ka0c05_tiop$v_tlber_mmre ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_mmre #define ka0c05_tiop$v_tlber_fnae ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_fnae #define ka0c05_tiop$v_tlber_reqde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_reqde #define ka0c05_tiop$v_tlber_atde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_atde #define ka0c05_tiop$v_tlber_ude ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ude #define ka0c05_tiop$v_tlber_cwde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_cwde #define ka0c05_tiop$v_tlber_crde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_crde #define ka0c05_tiop$v_tlber_ds0 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds0 #define ka0c05_tiop$v_tlber_ds1 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds1 #define ka0c05_tiop$v_tlber_ds2 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds2 #define ka0c05_tiop$v_tlber_ds3 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds3 #define ka0c05_tiop$v_tlber_dtde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dtde #define ka0c05_tiop$v_tlber_fdtce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_fdtce #define ka0c05_tiop$v_tlber_uacke ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_uacke #define ka0c05_tiop$v_tlber_abtce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_abtce #define ka0c05_tiop$v_tlber_dctce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dctce #define ka0c05_tiop$v_tlber_seqe ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_seqe #define ka0c05_tiop$v_tlber_dse ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dse #define ka0c05_tiop$v_tlber_dto ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dto #define ka0c05_tiop$l_tlcnr ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$l_tlcnr #define ka0c05_tiop$v_tlcnr_cwdd ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_cwdd #define ka0c05_tiop$v_tlcnr_crdd ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_crdd #define ka0c05_tiop$v_tlcnr_lktod ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_lktod #define ka0c05_tiop$v_tlcnr_dtod ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_dtod #define ka0c05_tiop$v_tlcnr_node_id ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_node_id #define ka0c05_tiop$v_tlcnr_vcnt ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_vcnt #define ka0c05_tiop$v_tlcnr_stf_a ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_a #define ka0c05_tiop$v_tlcnr_stf_b ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_b #define ka0c05_tiop$v_tlcnr_stf_c ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_c #define ka0c05_tiop$v_tlcnr_stf_d ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_d #define ka0c05_tiop$v_tlcnr_stf_e ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_e #define ka0c05_tiop$v_tlcnr_stf_f ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_f #define ka0c05_tiop$v_tlcnr_stf_g ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_g #define ka0c05_tiop$v_tlcnr_stf_h ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_h #define ka0c05_tiop$v_tlcnr_halt_a ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_a #define ka0c05_tiop$v_tlcnr_halt_b ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_b #define ka0c05_tiop$v_tlcnr_halt_c ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_c #define ka0c05_tiop$v_tlcnr_halt_d ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_d #define ka0c05_tiop$v_tlcnr_halt_e ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_e #define ka0c05_tiop$v_tlcnr_halt_f ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_f #define ka0c05_tiop$v_tlcnr_halt_g ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_g #define ka0c05_tiop$v_tlcnr_halt_h ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_h #define ka0c05_tiop$v_tlcnr_rststat ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_rststat #define ka0c05_tiop$v_tlcnr_nrst ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_nrst #define ka0c05_tiop$v_tlcnr_lofe ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_lofe #define ka0c05_tiop$l_tlmmr0 ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$l_tlmmr0 #define ka0c05_tiop$v_tlmmr0_intmask ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_intmask #define ka0c05_tiop$v_tlmmr0_adrmask ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_adrmask #define ka0c05_tiop$v_tlmmr0_intlv ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_intlv #define ka0c05_tiop$v_tlmmr0_sbank ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_sbank #define ka0c05_tiop$v_tlmmr0_address ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_address #define ka0c05_tiop$v_tlmmr0_valid ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_valid #define ka0c05_tiop$l_tlmmr1 ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$l_tlmmr1 #define ka0c05_tiop$v_tlmmr1_intmask ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_intmask #define ka0c05_tiop$v_tlmmr1_adrmask ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_adrmask #define ka0c05_tiop$v_tlmmr1_intlv ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_intlv #define ka0c05_tiop$v_tlmmr1_sbank ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_sbank #define ka0c05_tiop$v_tlmmr1_address ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_address #define ka0c05_tiop$v_tlmmr1_valid ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_valid #define ka0c05_tiop$l_tlmmr2 ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$l_tlmmr2 #define ka0c05_tiop$v_tlmmr2_intmask ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_intmask #define ka0c05_tiop$v_tlmmr2_adrmask ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_adrmask #define ka0c05_tiop$v_tlmmr2_intlv ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_intlv #define ka0c05_tiop$v_tlmmr2_sbank ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_sbank #define ka0c05_tiop$v_tlmmr2_address ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_address #define ka0c05_tiop$v_tlmmr2_valid ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_valid #define ka0c05_tiop$l_tlmmr3 ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$l_tlmmr3 #define ka0c05_tiop$v_tlmmr3_intmask ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_intmask #define ka0c05_tiop$v_tlmmr3_adrmask ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_adrmask #define ka0c05_tiop$v_tlmmr3_intlv ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_intlv #define ka0c05_tiop$v_tlmmr3_sbank ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_sbank #define ka0c05_tiop$v_tlmmr3_address ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_address #define ka0c05_tiop$v_tlmmr3_valid ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_valid #define ka0c05_tiop$l_tlmmr4 ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$l_tlmmr4 #define ka0c05_tiop$v_tlmmr4_intmask ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_intmask #define ka0c05_tiop$v_tlmmr4_adrmask ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_adrmask #define ka0c05_tiop$v_tlmmr4_intlv ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_intlv #define ka0c05_tiop$v_tlmmr4_sbank ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_sbank #define ka0c05_tiop$v_tlmmr4_address ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_address #define ka0c05_tiop$v_tlmmr4_valid ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_valid #define ka0c05_tiop$l_tlmmr5 ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$l_tlmmr5 #define ka0c05_tiop$v_tlmmr5_intmask ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_intmask #define ka0c05_tiop$v_tlmmr5_adrmask ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_adrmask #define ka0c05_tiop$v_tlmmr5_intlv ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_intlv #define ka0c05_tiop$v_tlmmr5_sbank ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_sbank #define ka0c05_tiop$v_tlmmr5_address ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_address #define ka0c05_tiop$v_tlmmr5_valid ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_valid #define ka0c05_tiop$l_tlmmr6 ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$l_tlmmr6 #define ka0c05_tiop$v_tlmmr6_intmask ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_intmask #define ka0c05_tiop$v_tlmmr6_adrmask ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_adrmask #define ka0c05_tiop$v_tlmmr6_intlv ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_intlv #define ka0c05_tiop$v_tlmmr6_sbank ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_sbank #define ka0c05_tiop$v_tlmmr6_address ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_address #define ka0c05_tiop$v_tlmmr6_valid ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_valid #define ka0c05_tiop$l_tlmmr7 ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$l_tlmmr7 #define ka0c05_tiop$v_tlmmr7_intmask ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_intmask #define ka0c05_tiop$v_tlmmr7_adrmask ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_adrmask #define ka0c05_tiop$v_tlmmr7_intlv ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_intlv #define ka0c05_tiop$v_tlmmr7_sbank ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_sbank #define ka0c05_tiop$v_tlmmr7_address ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_address #define ka0c05_tiop$v_tlmmr7_valid ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_valid #define ka0c05_tiop$l_tlfadr0 ka0c05_tiop$r_tlfadr0_overlay.ka0c05_tiop$l_tlfadr0 #define ka0c05_tiop$v_tlfadr0_fadr ka0c05_tiop$r_tlfadr0_overlay.ka0c05_tiop$r_tlfadr0_bits.ka0c05_tiop$v_tlfadr0_fadr #define ka0c05_tiop$l_tlfadr1 ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$l_tlfadr1 #define ka0c05_tiop$v_tlfadr1_fadr ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_fadr #define ka0c05_tiop$v_tlfadr1_fcmd ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_fcmd #define ka0c05_tiop$v_tlfadr1_fbank ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_fbank #define ka0c05_tiop$v_tlfadr1_adrv ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_adrv #define ka0c05_tiop$v_tlfadr1_cmdv ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_cmdv #define ka0c05_tiop$v_tlfadr1_bankv ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_bankv #define ka0c05_tiop$l_tlesr0 ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$l_tlesr0 #define ka0c05_tiop$v_tlesr0_synd0 ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_synd0 #define ka0c05_tiop$v_tlesr0_synd1 ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_synd1 #define ka0c05_tiop$v_tlesr0_tde ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_tde #define ka0c05_tiop$v_tlesr0_tce ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_tce #define ka0c05_tiop$v_tlesr0_dvtce ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_dvtce #define ka0c05_tiop$v_tlesr0_uecc ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_uecc #define ka0c05_tiop$v_tlesr0_cwecc ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_cwecc #define ka0c05_tiop$v_tlesr0_crecc ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_crecc #define ka0c05_tiop$v_tlesr0_lofsyn ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_lofsyn #define ka0c05_tiop$l_tlesr1 ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$l_tlesr1 #define ka0c05_tiop$v_tlesr1_synd0 ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_synd0 #define ka0c05_tiop$v_tlesr1_synd1 ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_synd1 #define ka0c05_tiop$v_tlesr1_tde ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_tde #define ka0c05_tiop$v_tlesr1_tce ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_tce #define ka0c05_tiop$v_tlesr1_dvtce ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_dvtce #define ka0c05_tiop$v_tlesr1_uecc ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_uecc #define ka0c05_tiop$v_tlesr1_cwecc ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_cwecc #define ka0c05_tiop$v_tlesr1_crecc ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_crecc #define ka0c05_tiop$v_tlesr1_lofsyn ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_lofsyn #define ka0c05_tiop$l_tlesr2 ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$l_tlesr2 #define ka0c05_tiop$v_tlesr2_synd0 ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_synd0 #define ka0c05_tiop$v_tlesr2_synd1 ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_synd1 #define ka0c05_tiop$v_tlesr2_tde ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_tde #define ka0c05_tiop$v_tlesr2_tce ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_tce #define ka0c05_tiop$v_tlesr2_dvtce ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_dvtce #define ka0c05_tiop$v_tlesr2_uecc ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_uecc #define ka0c05_tiop$v_tlesr2_cwecc ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_cwecc #define ka0c05_tiop$v_tlesr2_crecc ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_crecc #define ka0c05_tiop$v_tlesr2_lofsyn ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_lofsyn #define ka0c05_tiop$l_tlesr3 ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$l_tlesr3 #define ka0c05_tiop$v_tlesr3_synd0 ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_synd0 #define ka0c05_tiop$v_tlesr3_synd1 ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_synd1 #define ka0c05_tiop$v_tlesr3_tde ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_tde #define ka0c05_tiop$v_tlesr3_tce ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_tce #define ka0c05_tiop$v_tlesr3_dvtce ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_dvtce #define ka0c05_tiop$v_tlesr3_uecc ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_uecc #define ka0c05_tiop$v_tlesr3_cwecc ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_cwecc #define ka0c05_tiop$v_tlesr3_crecc ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_crecc #define ka0c05_tiop$v_tlesr3_lofsyn ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_lofsyn #define ka0c05_tiop$l_tlilid0 ka0c05_tiop$r_tlilid0_overlay.ka0c05_tiop$l_tlilid0 #define ka0c05_tiop$v_tlilid0_ident ka0c05_tiop$r_tlilid0_overlay.ka0c05_tiop$r_tlilid0_bits.ka0c05_tiop$v_tlilid0_ident #define ka0c05_tiop$l_tlilid1 ka0c05_tiop$r_tlilid1_overlay.ka0c05_tiop$l_tlilid1 #define ka0c05_tiop$v_tlilid1_ident ka0c05_tiop$r_tlilid1_overlay.ka0c05_tiop$r_tlilid1_bits.ka0c05_tiop$v_tlilid1_ident #define ka0c05_tiop$l_tlilid2 ka0c05_tiop$r_tlilid2_overlay.ka0c05_tiop$l_tlilid2 #define ka0c05_tiop$v_tlilid2_ident ka0c05_tiop$r_tlilid2_overlay.ka0c05_tiop$r_tlilid2_bits.ka0c05_tiop$v_tlilid2_ident #define ka0c05_tiop$l_tlilid3 ka0c05_tiop$r_tlilid3_overlay.ka0c05_tiop$l_tlilid3 #define ka0c05_tiop$v_tlilid3_ident ka0c05_tiop$r_tlilid3_overlay.ka0c05_tiop$r_tlilid3_bits.ka0c05_tiop$v_tlilid3_ident #define ka0c05_tiop$l_tlcpumask ka0c05_tiop$r_tlcpumask_overlay.ka0c05_tiop$l_tlcpumask #define ka0c05_tiop$v_tlcpumask_mask ka0c05_tiop$r_tlcpumask_overlay.ka0c05_tiop$r_tlcpumask_bits.ka0c05_tiop$v_tlcpumask_mask #define ka0c05_tiop$q_tlmbpr ka0c05_tiop$r_tlmbpr_overlay.ka0c05_tiop$q_tlmbpr #define ka0c05_tiop$l_tlrmr0a ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$l_tlrmr0a #define ka0c05_tiop$v_tlrmr0a_mask ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_mask #define ka0c05_tiop$v_tlrmr0a_ilv_en ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_ilv_en #define ka0c05_tiop$v_tlrmr0a_badr ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_badr #define ka0c05_tiop$v_tlrmr0a_nvram ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_nvram #define ka0c05_tiop$v_tlrmr0a_valid ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_valid #define ka0c05_tiop$l_tlrmr0b ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$l_tlrmr0b #define ka0c05_tiop$v_tlrmr0b_mask ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_mask #define ka0c05_tiop$v_tlrmr0b_ilv_en ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_ilv_en #define ka0c05_tiop$v_tlrmr0b_badr ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_badr #define ka0c05_tiop$v_tlrmr0b_nvram ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_nvram #define ka0c05_tiop$v_tlrmr0b_valid ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_valid #define ka0c05_tiop$l_tlrmr1a ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$l_tlrmr1a #define ka0c05_tiop$v_tlrmr1a_mask ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_mask #define ka0c05_tiop$v_tlrmr1a_ilv_en ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_ilv_en #define ka0c05_tiop$v_tlrmr1a_badr ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_badr #define ka0c05_tiop$v_tlrmr1a_nvram ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_nvram #define ka0c05_tiop$v_tlrmr1a_valid ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_valid #define ka0c05_tiop$l_tlrmr1b ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$l_tlrmr1b #define ka0c05_tiop$v_tlrmr1b_mask ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_mask #define ka0c05_tiop$v_tlrmr1b_ilv_en ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_ilv_en #define ka0c05_tiop$v_tlrmr1b_badr ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_badr #define ka0c05_tiop$v_tlrmr1b_nvram ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_nvram #define ka0c05_tiop$v_tlrmr1b_valid ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_valid #define ka0c05_tiop$l_tlicmsr ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$l_tlicmsr #define ka0c05_tiop$v_tlicmsr_arb_ctl ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_arb_ctl #define ka0c05_tiop$v_tlicmsr_sup_ctl ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_sup_ctl #define ka0c05_tiop$v_tlicmsr_force_ack ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_force_ack #define ka0c05_tiop$v_tlicmsr_rmnxm ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_rmnxm #define ka0c05_tiop$v_tlicmsr_ack_dsbl ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_ack_dsbl #define ka0c05_tiop$l_tlicnse ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$l_tlicnse #define ka0c05_tiop$v_tlicnse_ack_drop ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_ack_drop #define ka0c05_tiop$v_tlicnse_rmnxm ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_rmnxm #define ka0c05_tiop$v_tlicnse_mbx_stat ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_mbx_stat #define ka0c05_tiop$v_tlicnse_oflo ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_oflo #define ka0c05_tiop$v_tlicnse_pkt_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_pkt_e #define ka0c05_tiop$v_tlicnse_par_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_par_e #define ka0c05_tiop$v_tlicnse_up_hdp_ie ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_up_hdp_ie #define ka0c05_tiop$v_tlicnse_int_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_int_e #define ka0c05_tiop$v_tlicnse_dn_vrtx_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_dn_vrtx_e #define ka0c05_tiop$v_tlicnse_up_vrtx_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_up_vrtx_e #define ka0c05_tiop$v_tlicnse_ie ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_ie #define ka0c05_tiop$v_tlicnse_bus_pe ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_bus_pe #define ka0c05_tiop$v_tlicnse_wnd_oflo ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_wnd_oflo #define ka0c05_tiop$v_tlicnse_rm_oflo ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_rm_oflo #define ka0c05_tiop$v_tlicnse_int_nses ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_int_nses #define ka0c05_tiop$l_tlicdr ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$l_tlicdr #define ka0c05_tiop$v_tlicdr_idp_pe ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_idp_pe #define ka0c05_tiop$v_tlicdr_dse ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dse #define ka0c05_tiop$v_tlicdr_dto ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dto #define ka0c05_tiop$v_tlicdr_dis_cmd ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dis_cmd #define ka0c05_tiop$v_tlicdr_dis_flt ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dis_flt #define ka0c05_tiop$v_tlicdr_cmd_pe ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_cmd_pe #define ka0c05_tiop$v_tlicdr_bnk_bsy ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_bnk_bsy #define ka0c05_tiop$v_tlicdr_idp_cmd_pe ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_idp_cmd_pe #define ka0c05_tiop$v_tlicdr_en_hid ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_en_hid #define ka0c05_tiop$l_tlicmtr ka0c05_tiop$r_tlicmtr_overlay.ka0c05_tiop$l_tlicmtr #define ka0c05_tiop$v_tlicmtr_mbx_tip ka0c05_tiop$r_tlicmtr_overlay.ka0c05_tiop$r_tlicmtr_bits.ka0c05_tiop$v_tlicmtr_mbx_tip #define ka0c05_tiop$l_tlicwrt ka0c05_tiop$r_tlicwrt_overlay.ka0c05_tiop$l_tlicwrt #define ka0c05_tiop$v_tlicwrt_wip ka0c05_tiop$r_tlicwrt_overlay.ka0c05_tiop$r_tlicwrt_bits.ka0c05_tiop$v_tlicwrt_wip #define ka0c05_tiop$l_tlidpnse1 ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$l_tlidpnse1 #define ka0c05_tiop$v_tlidpnse_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_err #define ka0c05_tiop$v_tlidpnse_pok ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_pok #define ka0c05_tiop$v_tlidpnse_cblok ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_cblok #define ka0c05_tiop$v_tlidpnse_pok_tran ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_pok_tran #define ka0c05_tiop$v_tlidpnse_soft_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_soft_err #define ka0c05_tiop$v_tlidpnse_rm_m_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_rm_m_err #define ka0c05_tiop$v_tlidpnse_cpe ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_cpe #define ka0c05_tiop$v_tlidpnse_up_v_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_up_v_err #define ka0c05_tiop$v_tlidpnse_ie ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_ie #define ka0c05_tiop$v_tlidpnse_pe ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_pe #define ka0c05_tiop$v_tlidpnse_reset ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_reset #define ka0c05_tiop$l_tlidpdr1 ka0c05_tiop$r_tlidpdr1_overlay.ka0c05_tiop$l_tlidpdr1 #define ka0c05_tiop$l_tlidpnse2 ka0c05_tiop$r_tlidpnse2_overlay.ka0c05_tiop$l_tlidpnse2 #define ka0c05_tiop$l_tlidpdr2 ka0c05_tiop$r_tlidpdr2_overlay.ka0c05_tiop$l_tlidpdr2 #define ka0c05_tiop$l_tlidpnse3 ka0c05_tiop$r_tlidpnse3_overlay.ka0c05_tiop$l_tlidpnse3 #define ka0c05_tiop$l_tlidpdr3 ka0c05_tiop$r_tlidpdr3_overlay.ka0c05_tiop$l_tlidpdr3 #define ka0c05_tiop$l_tlidpnse0 ka0c05_tiop$r_tlidpnse0_overlay.ka0c05_tiop$l_tlidpnse0 #define ka0c05_tiop$l_tlidpdr0 ka0c05_tiop$r_tlidpdr0_overlay.ka0c05_tiop$l_tlidpdr0 #define ka0c05_tiop$l_tlipmask ka0c05_tiop$r_tlipmask_overlay.ka0c05_tiop$l_tlipmask #define ka0c05_tiop$v_tlipmask_cpu ka0c05_tiop$r_tlipmask_overlay.ka0c05_tiop$r_tlipmask_bits.ka0c05_tiop$v_tlipmask_cpu #define ka0c05_tiop$l_tlidpvr ka0c05_tiop$r_tlidpvr_overlay.ka0c05_tiop$l_tlidpvr #define ka0c05_tiop$v_tlidpvr_vector ka0c05_tiop$r_tlidpvr_overlay.ka0c05_tiop$r_tlidpvr_bits.ka0c05_tiop$v_tlidpvr_vector #define ka0c05_tiop$l_tlidpmsr ka0c05_tiop$r_tlidpmsr_overlay.ka0c05_tiop$l_tlidpmsr #define ka0c05_tiop$l_tlibr ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$l_tlibr #define ka0c05_tiop$v_tlibr_rcv_sdat ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$r_tlibr_bits.ka0c05_tiop$v_tlibr_rcv_sdat #define ka0c05_tiop$v_tlibr_xmt_sdat ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$r_tlibr_bits.ka0c05_tiop$v_tlibr_xmt_sdat #define ka0c05_tiop$v_tlibr_sclk ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$r_tlibr_bits.ka0c05_tiop$v_tlibr_sclk #endif /* #if !defined(__VAXC) */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_uart0b { #pragma __nomember_alignment __union { unsigned int ka0c05_uart0b$l_uart0b_rr0; __struct { unsigned ka0c05_uart0b$v_uart0b_rr0_f1 : 32; } ka0c05_uart0b$r_uart0b_rr0_bits; } ka0c05_uart0b$r_uart0b_rr0_overlay; unsigned char ka0c05_uart0b$b_f2000 [60]; __union { unsigned int ka0c05_uart0b$l_uart0b_rr8; __struct { unsigned ka0c05_uart0b$v_uart0b_rr8_f1 : 32; } ka0c05_uart0b$r_uart0b_rr8_bits; } ka0c05_uart0b$r_uart0b_rr8_overlay; unsigned char ka0c05_uart0b$b_f2010 [60]; __union { unsigned int ka0c05_uart0b$l_uart0a_rr0; __struct { unsigned ka0c05_uart0b$v_uart0a_rr0_f1 : 32; } ka0c05_uart0b$r_uart0a_rr0_bits; } ka0c05_uart0b$r_uart0a_rr0_overlay; unsigned char ka0c05_uart0b$b_f2020 [60]; __union { unsigned int ka0c05_uart0b$l_uart0a_rr8; __struct { unsigned ka0c05_uart0b$v_uart0a_rr8_f1 : 32; } ka0c05_uart0b$r_uart0a_rr8_bits; } ka0c05_uart0b$r_uart0a_rr8_overlay; unsigned char ka0c05_uart0b$b_f2030 [7996]; } KA0C05_UART0B; #if !defined(__VAXC) #define ka0c05_uart0b$l_uart0b_rr0 ka0c05_uart0b$r_uart0b_rr0_overlay.ka0c05_uart0b$l_uart0b_rr0 #define ka0c05_uart0b$l_uart0b_rr8 ka0c05_uart0b$r_uart0b_rr8_overlay.ka0c05_uart0b$l_uart0b_rr8 #define ka0c05_uart0b$l_uart0a_rr0 ka0c05_uart0b$r_uart0a_rr0_overlay.ka0c05_uart0b$l_uart0a_rr0 #define ka0c05_uart0b$l_uart0a_rr8 ka0c05_uart0b$r_uart0a_rr8_overlay.ka0c05_uart0b$l_uart0a_rr8 #endif /* #if !defined(__VAXC) */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_uart1b { #pragma __nomember_alignment __union { __union { unsigned int ka0c05_uart1b$l_uart1b_rr0; __struct { unsigned ka0c05_uart1b$v_uart1b_rr0_f1 : 32; } ka0c05_uart1b$r_uart1b_rr0_bits; } ka0c05_uart1b$r_uart1b_rr0_overlay; __struct { unsigned int ka0c05_uart1b$l_uart1b_wr0; } ka0c05_uart1b$r_uart1b_wr0_overlay; } ka0c05_uart1b$r_uart1b0_overlay; unsigned char ka0c05_uart1b$b_f2040 [60]; __union { unsigned int ka0c05_uart1b$l_uart1b_rr8; __struct { unsigned ka0c05_uart1b$v_uart1b_rr8_f1 : 32; } ka0c05_uart1b$r_uart1b_rr8_bits; } ka0c05_uart1b$r_uart1b_rr8_overlay; unsigned char ka0c05_uart1b$b_f2050 [60]; __union { unsigned int ka0c05_uart1b$l_uart1a_rr0; __struct { unsigned ka0c05_uart1b$v_uart1a_rr0_f1 : 32; } ka0c05_uart1b$r_uart1a_rr0_bits; } ka0c05_uart1b$r_uart1a_rr0_overlay; unsigned char ka0c05_uart1b$b_f2060 [60]; __union { unsigned int ka0c05_uart1b$l_uart1a_rr8; __struct { unsigned ka0c05_uart1b$v_uart1a_rr8_f1 : 32; } ka0c05_uart1b$r_uart1a_rr8_bits; } ka0c05_uart1b$r_uart1a_rr8_overlay; unsigned char ka0c05_uart1b$b_f2070 [7996]; } KA0C05_UART1B; #if !defined(__VAXC) #define ka0c05_uart1b$l_uart1b_rr0 ka0c05_uart1b$r_uart1b0_overlay.ka0c05_uart1b$r_uart1b_rr0_overlay.ka0c05_uart1b$l_uart1b_rr0 #define ka0c05_uart1b$l_uart1b_wr0 ka0c05_uart1b$r_uart1b0_overlay.ka0c05_uart1b$r_uart1b_wr0_overlay.ka0c05_uart1b$l_uart1b_wr0 #define ka0c05_uart1b$l_uart1b_rr8 ka0c05_uart1b$r_uart1b_rr8_overlay.ka0c05_uart1b$l_uart1b_rr8 #define ka0c05_uart1b$l_uart1a_rr0 ka0c05_uart1b$r_uart1a_rr0_overlay.ka0c05_uart1b$l_uart1a_rr0 #define ka0c05_uart1b$l_uart1a_rr8 ka0c05_uart1b$r_uart1a_rr8_overlay.ka0c05_uart1b$l_uart1a_rr8 #endif /* #if !defined(__VAXC) */ #define KA0C05_WATCH$M_WATCH_CSRA_RS 0xF #define KA0C05_WATCH$M_WATCH_CSRA_DV 0x70 #define KA0C05_WATCH$M_WATCH_CSRA_UIP 0x80 #define KA0C05_WATCH$M_WATCH_CSRB_DSE 0x1 #define KA0C05_WATCH$M_WATCH_CSRB_24_12 0x2 #define KA0C05_WATCH$M_WATCH_CSRB_DM 0x4 #define KA0C05_WATCH$M_WATCH_CSRB_SQWE 0x8 #define KA0C05_WATCH$M_WATCH_CSRB_UIE 0x10 #define KA0C05_WATCH$M_WATCH_CSRB_AIE 0x20 #define KA0C05_WATCH$M_WATCH_CSRB_PIE 0x40 #define KA0C05_WATCH$M_WATCH_CSRB_SET 0x80 #define KA0C05_WATCH$M_WATCH_CSRC_UF 0x10 #define KA0C05_WATCH$M_WATCH_CSRC_AF 0x20 #define KA0C05_WATCH$M_WATCH_CSRC_PF 0x40 #define KA0C05_WATCH$M_WATCH_CSRC_IRQF 0x80 #define KA0C05_WATCH$M_WATCH_CSRD_VRT 0x80 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_watch { #pragma __nomember_alignment __union { unsigned int ka0c05_watch$l_watch_seconds; __struct { unsigned ka0c05_watch$v_watch_seconds_f1 : 32; } ka0c05_watch$r_watch_seconds_bits; } ka0c05_watch$r_watch_seconds_overl; unsigned char ka0c05_watch$b_fill3000 [124]; __union { unsigned int ka0c05_watch$l_watch_minutes; __struct { unsigned ka0c05_watch$v_watch_minutes_f1 : 32; } ka0c05_watch$r_watch_minutes_bits; } ka0c05_watch$r_watch_minutes_overl; unsigned char ka0c05_watch$b_fill3010 [124]; __union { unsigned int ka0c05_watch$l_watch_hours; __struct { unsigned ka0c05_watch$v_watch_hours_f1 : 32; } ka0c05_watch$r_watch_hours_bits; } ka0c05_watch$r_watch_hours_overlay; unsigned char ka0c05_watch$b_fill3020 [188]; __union { unsigned int ka0c05_watch$l_watch_dom; __struct { unsigned ka0c05_watch$v_watch_dom_f1 : 32; } ka0c05_watch$r_watch_dom_bits; } ka0c05_watch$r_watch_dom_overlay; unsigned char ka0c05_watch$b_fill3030 [60]; __union { unsigned int ka0c05_watch$l_watch_month; __struct { unsigned ka0c05_watch$v_watch_month_f1 : 32; } ka0c05_watch$r_watch_month_bits; } ka0c05_watch$r_watch_month_overlay; unsigned char ka0c05_watch$b_fill3040 [60]; __union { unsigned int ka0c05_watch$l_watch_year; __struct { unsigned ka0c05_watch$v_watch_year_f1 : 32; } ka0c05_watch$r_watch_year_bits; } ka0c05_watch$r_watch_year_overlay; unsigned char ka0c05_watch$b_fill3050 [60]; __union { unsigned int ka0c05_watch$l_watch_csra; __struct { unsigned ka0c05_watch$v_watch_csra_rs : 4; unsigned ka0c05_watch$v_watch_csra_dv : 3; unsigned ka0c05_watch$v_watch_csra_uip : 1; unsigned ka0c05_watch$v_watch_csra_f1 : 24; } ka0c05_watch$r_watch_csra_bits; } ka0c05_watch$r_watch_csra_overlay; unsigned char ka0c05_watch$b_fill3060 [60]; __union { unsigned int ka0c05_watch$l_watch_csrb; __struct { unsigned ka0c05_watch$v_watch_csrb_dse : 1; unsigned ka0c05_watch$v_watch_csrb_24_12 : 1; unsigned ka0c05_watch$v_watch_csrb_dm : 1; unsigned ka0c05_watch$v_watch_csrb_sqwe : 1; unsigned ka0c05_watch$v_watch_csrb_uie : 1; unsigned ka0c05_watch$v_watch_csrb_aie : 1; unsigned ka0c05_watch$v_watch_csrb_pie : 1; unsigned ka0c05_watch$v_watch_csrb_set : 1; unsigned ka0c05_watch$v_watch_csrb_f1 : 24; } ka0c05_watch$r_watch_csrb_bits; } ka0c05_watch$r_watch_csrb_overlay; unsigned char ka0c05_watch$b_fill3070 [60]; __union { unsigned int ka0c05_watch$l_watch_csrc; __struct { unsigned ka0c05_watch$v_watch_csrc_f1 : 4; unsigned ka0c05_watch$v_watch_csrc_uf : 1; unsigned ka0c05_watch$v_watch_csrc_af : 1; unsigned ka0c05_watch$v_watch_csrc_pf : 1; unsigned ka0c05_watch$v_watch_csrc_irqf : 1; unsigned ka0c05_watch$v_watch_csrc_f2 : 24; } ka0c05_watch$r_watch_csrc_bits; } ka0c05_watch$r_watch_csrc_overlay; unsigned char ka0c05_watch$b_fill3080 [60]; __union { unsigned int ka0c05_watch$l_watch_csrd; __struct { unsigned ka0c05_watch$v_watch_csrd_f1 : 7; unsigned ka0c05_watch$v_watch_csrd_vrt : 1; unsigned ka0c05_watch$v_watch_csrd_f2 : 24; } ka0c05_watch$r_watch_csrd_bits; } ka0c05_watch$r_watch_csrd_overlay; unsigned char ka0c05_watch$b_fill3090 [60]; __union { unsigned int ka0c05_watch$l_watch_ram; __struct { unsigned ka0c05_watch$v_watch_ram_f1 : 32; } ka0c05_watch$r_watch_ram_bits; } ka0c05_watch$r_watch_ram_overlay; unsigned char ka0c05_watch$b_fill3100 [7292]; } KA0C05_WATCH; #if !defined(__VAXC) #define ka0c05_watch$l_watch_seconds ka0c05_watch$r_watch_seconds_overl.ka0c05_watch$l_watch_seconds #define ka0c05_watch$l_watch_minutes ka0c05_watch$r_watch_minutes_overl.ka0c05_watch$l_watch_minutes #define ka0c05_watch$l_watch_hours ka0c05_watch$r_watch_hours_overlay.ka0c05_watch$l_watch_hours #define ka0c05_watch$l_watch_dom ka0c05_watch$r_watch_dom_overlay.ka0c05_watch$l_watch_dom #define ka0c05_watch$l_watch_month ka0c05_watch$r_watch_month_overlay.ka0c05_watch$l_watch_month #define ka0c05_watch$l_watch_year ka0c05_watch$r_watch_year_overlay.ka0c05_watch$l_watch_year #define ka0c05_watch$l_watch_csra ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$l_watch_csra #define ka0c05_watch$v_watch_csra_rs ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$r_watch_csra_bits.ka0c05_watch$v_watch_csra_rs #define ka0c05_watch$v_watch_csra_dv ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$r_watch_csra_bits.ka0c05_watch$v_watch_csra_dv #define ka0c05_watch$v_watch_csra_uip ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$r_watch_csra_bits.ka0c05_watch$v_watch_csra_uip #define ka0c05_watch$l_watch_csrb ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$l_watch_csrb #define ka0c05_watch$v_watch_csrb_dse ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_dse #define ka0c05_watch$v_watch_csrb_24_12 ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_\ 24_12 #define ka0c05_watch$v_watch_csrb_dm ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_dm #define ka0c05_watch$v_watch_csrb_sqwe ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_s\ qwe #define ka0c05_watch$v_watch_csrb_uie ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_uie #define ka0c05_watch$v_watch_csrb_aie ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_aie #define ka0c05_watch$v_watch_csrb_pie ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_pie #define ka0c05_watch$v_watch_csrb_set ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_set #define ka0c05_watch$l_watch_csrc ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$l_watch_csrc #define ka0c05_watch$v_watch_csrc_uf ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_uf #define ka0c05_watch$v_watch_csrc_af ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_af #define ka0c05_watch$v_watch_csrc_pf ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_pf #define ka0c05_watch$v_watch_csrc_irqf ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_i\ rqf #define ka0c05_watch$l_watch_csrd ka0c05_watch$r_watch_csrd_overlay.ka0c05_watch$l_watch_csrd #define ka0c05_watch$v_watch_csrd_vrt ka0c05_watch$r_watch_csrd_overlay.ka0c05_watch$r_watch_csrd_bits.ka0c05_watch$v_watch_csrd_vrt #define ka0c05_watch$l_watch_ram ka0c05_watch$r_watch_ram_overlay.ka0c05_watch$l_watch_ram #endif /* #if !defined(__VAXC) */ #define KA0C05_GBUS$M_GWHAMI_CPU 0x1 #define KA0C05_GBUS$M_GWHAMI_NID 0xE #define KA0C05_GBUS$M_GWHAMI_BAD 0x10 #define KA0C05_GBUS$M_GWHAMI_CONWIN 0x20 #define KA0C05_GBUS$M_GWHAMI_MFG_MODE 0x40 #define KA0C05_GBUS$M_GMISCR_CACSIZ 0x3 #define KA0C05_GBUS$M_GMISCR_PROCCNT 0x4 #define KA0C05_GBUS$M_GMISCR_SECURE 0x8 #define KA0C05_GBUS$M_GMISCR_RUN 0x10 #define KA0C05_GBUS$M_GMISCR_CONWIN0 0x40 #define KA0C05_GBUS$M_GMISCR_CONWIN1 0x80 #define KA0C05_GBUS$M_GMISCW_DRIVE_BAD 0x4 #define KA0C05_GBUS$M_GMISCW_FPROM_WE 0x8 #define KA0C05_GBUS$M_GMISCW_DRIVE_RUN 0x10 #define KA0C05_GBUS$M_GMISCW_DRV_CONWIN 0x20 #define KA0C05_GBUS$M_GMISCW_CONWIN0 0x40 #define KA0C05_GBUS$M_GMISCW_CONWIN1 0x80 #define KA0C05_GBUS$M_GSERNUM_CLK 0x1 #define KA0C05_GBUS$M_GSERNUM_RCV_DATA 0x2 #define KA0C05_GBUS$M_GSERNUM_XMT_DATA 0x4 #define KA0C05_GBUS$M_GSERNUM_EXPSEL 0x18 #define KA0C05_GBUS$M_GSERNUM_PIUB 0x20 #define KA0C05_GBUS$M_GSERNUM_PIUA 0x40 #define KA0C05_GBUS$M_GSERNUM_STP 0x80 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ka0c05_gbus { #pragma __nomember_alignment __union { unsigned int ka0c05_gbus$l_gwhami; __struct { unsigned ka0c05_gbus$v_gwhami_cpu : 1; unsigned ka0c05_gbus$v_gwhami_nid : 3; unsigned ka0c05_gbus$v_gwhami_bad : 1; unsigned ka0c05_gbus$v_gwhami_conwin : 1; unsigned ka0c05_gbus$v_gwhami_mfg_mode : 1; unsigned ka0c05_gbus$v_gwhami_f1 : 25; } ka0c05_gbus$r_gwhami_bits; } ka0c05_gbus$r_gwhami_overlay; unsigned char ka0c05_gbus$b_fill3110 [8188]; __union { unsigned int ka0c05_gbus$l_gbus_led0; __struct { unsigned ka0c05_gbus$v_gbus_led0_f1 : 32; } ka0c05_gbus$r_gbus_led0_bits; } ka0c05_gbus$r_gbus_led0_overlay; unsigned char ka0c05_gbus$b_fill3120 [8188]; __union { unsigned int ka0c05_gbus$l_gbus_led1; __struct { unsigned ka0c05_gbus$v_gbus_led1_f1 : 32; } ka0c05_gbus$r_gbus_led1_bits; } ka0c05_gbus$r_gbus_led1_overlay; unsigned char ka0c05_gbus$b_fill3130 [8188]; __union { unsigned int ka0c05_gbus$l_gbus_led2; __struct { unsigned ka0c05_gbus$v_gbus_led2_f1 : 32; } ka0c05_gbus$r_gbus_led2_bits; } ka0c05_gbus$r_gbus_led2_overlay; unsigned char ka0c05_gbus$b_fill3140 [8188]; __union { unsigned int ka0c05_gbus$l_gmiscr; __struct { unsigned ka0c05_gbus$v_gmiscr_cacsiz : 2; unsigned ka0c05_gbus$v_gmiscr_proccnt : 1; unsigned ka0c05_gbus$v_gmiscr_secure : 1; unsigned ka0c05_gbus$v_gmiscr_run : 1; unsigned ka0c05_gbus$v_gmiscr_f1 : 1; unsigned ka0c05_gbus$v_gmiscr_conwin0 : 1; unsigned ka0c05_gbus$v_gmiscr_conwin1 : 1; unsigned ka0c05_gbus$v_gmiscr_f2 : 24; } ka0c05_gbus$r_gmiscr_bits; } ka0c05_gbus$r_gmiscr_overlay; unsigned char ka0c05_gbus$b_fill3150 [8188]; __union { unsigned int ka0c05_gbus$l_gmiscw; __struct { unsigned ka0c05_gbus$v_gmiscw_f1 : 2; unsigned ka0c05_gbus$v_gmiscw_drive_bad : 1; unsigned ka0c05_gbus$v_gmiscw_fprom_we : 1; unsigned ka0c05_gbus$v_gmiscw_drive_run : 1; unsigned ka0c05_gbus$v_gmiscw_drv_conwin : 1; unsigned ka0c05_gbus$v_gmiscw_conwin0 : 1; unsigned ka0c05_gbus$v_gmiscw_conwin1 : 1; unsigned ka0c05_gbus$v_gmiscw_f2 : 24; } ka0c05_gbus$r_gmiscw_bits; } ka0c05_gbus$r_gmiscw_overlay; unsigned char ka0c05_gbus$b_fill3160 [8188]; __union { unsigned int ka0c05_gbus$l_gbus_tlsbrst; __struct { unsigned ka0c05_gbus$v_gbus_tlsbrst_f1 : 32; } ka0c05_gbus$r_gbus_tlsbrst_bits; } ka0c05_gbus$r_gbus_tlsbrst_overlay; unsigned char ka0c05_gbus$b_fill3170 [8188]; __union { unsigned int ka0c05_gbus$l_gsernum; __struct { unsigned ka0c05_gbus$v_gsernum_clk : 1; unsigned ka0c05_gbus$v_gsernum_rcv_data : 1; unsigned ka0c05_gbus$v_gsernum_xmt_data : 1; unsigned ka0c05_gbus$v_gsernum_expsel : 2; unsigned ka0c05_gbus$v_gsernum_piub : 1; unsigned ka0c05_gbus$v_gsernum_piua : 1; unsigned ka0c05_gbus$v_gsernum_stp : 1; unsigned ka0c05_gbus$v_gsernum_f1 : 24; } ka0c05_gbus$r_gsernum_bits; } ka0c05_gbus$r_gsernum_overlay; unsigned char ka0c05_gbus$b_fill3180 [8188]; __union { unsigned int ka0c05_gbus$l_gbus_test; __struct { unsigned ka0c05_gbus$v_gbus_test_f1 : 32; } ka0c05_gbus$r_gbus_test_bits; } ka0c05_gbus$r_gbus_test_overlay; unsigned char ka0c05_gbus$b_fill3190 [8188]; } KA0C05_GBUS; #if !defined(__VAXC) #define ka0c05_gbus$l_gwhami ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$l_gwhami #define ka0c05_gbus$v_gwhami_cpu ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_cpu #define ka0c05_gbus$v_gwhami_nid ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_nid #define ka0c05_gbus$v_gwhami_bad ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_bad #define ka0c05_gbus$v_gwhami_conwin ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_conwin #define ka0c05_gbus$v_gwhami_mfg_mode ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_mfg_mode #define ka0c05_gbus$l_gbus_led0 ka0c05_gbus$r_gbus_led0_overlay.ka0c05_gbus$l_gbus_led0 #define ka0c05_gbus$l_gbus_led1 ka0c05_gbus$r_gbus_led1_overlay.ka0c05_gbus$l_gbus_led1 #define ka0c05_gbus$l_gbus_led2 ka0c05_gbus$r_gbus_led2_overlay.ka0c05_gbus$l_gbus_led2 #define ka0c05_gbus$l_gmiscr ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$l_gmiscr #define ka0c05_gbus$v_gmiscr_cacsiz ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_cacsiz #define ka0c05_gbus$v_gmiscr_proccnt ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_proccnt #define ka0c05_gbus$v_gmiscr_secure ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_secure #define ka0c05_gbus$v_gmiscr_run ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_run #define ka0c05_gbus$v_gmiscr_conwin0 ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_conwin0 #define ka0c05_gbus$v_gmiscr_conwin1 ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_conwin1 #define ka0c05_gbus$l_gmiscw ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$l_gmiscw #define ka0c05_gbus$v_gmiscw_drive_bad ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_drive_bad #define ka0c05_gbus$v_gmiscw_fprom_we ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_fprom_we #define ka0c05_gbus$v_gmiscw_drive_run ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_drive_run #define ka0c05_gbus$v_gmiscw_drv_conwin ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_drv_conwin #define ka0c05_gbus$v_gmiscw_conwin0 ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_conwin0 #define ka0c05_gbus$v_gmiscw_conwin1 ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_conwin1 #define ka0c05_gbus$l_gbus_tlsbrst ka0c05_gbus$r_gbus_tlsbrst_overlay.ka0c05_gbus$l_gbus_tlsbrst #define ka0c05_gbus$l_gsernum ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$l_gsernum #define ka0c05_gbus$v_gsernum_clk ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_clk #define ka0c05_gbus$v_gsernum_rcv_data ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_rcv_data #define ka0c05_gbus$v_gsernum_xmt_data ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_xmt_data #define ka0c05_gbus$v_gsernum_expsel ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_expsel #define ka0c05_gbus$v_gsernum_piub ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_piub #define ka0c05_gbus$v_gsernum_piua ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_piua #define ka0c05_gbus$v_gsernum_stp ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_stp #define ka0c05_gbus$l_gbus_test ka0c05_gbus$r_gbus_test_overlay.ka0c05_gbus$l_gbus_test #endif /* #if !defined(__VAXC) */ #define S_KA0C05DEF 73728 /* Old size name, synonym for KA0C05$S_KA0C05 */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __KA0C05DEF_LOADED */