/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:04 by OpenVMS SDL EV3-3 */ /* Source: 24-MAR-1993 14:47:16 $1$DGA7274:[LIB_H.SRC]KA0702DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $KA0702DEF ***/ #ifndef __KA0702DEF_LOADED #define __KA0702DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define KA0702$M_IR_SFB_INT 0x4 #define KA0702$M_IR_SCSI_INT 0x8 #define KA0702$M_IR_COREIO_INT 0x10 #define KA0702$M_IR_BC_TPE 0x8000000 #define KA0702$M_IR_TC_ORE 0x10000000 #define KA0702$M_IR_TC_TOE 0x20000000 #define KA0702$M_IR_BPE 0x40000000 #define KA0702$M_IR_MPE 0x80000000 #define KA0702$M_TCSR_AP0 0x1 #define KA0702$M_TCSR_AP1 0x2 #define KA0702$M_TCSR_AP2 0x4 #define KA0702$M_TCSR_AP3 0x8 #define KA0702$M_TCSR_AP4 0x10 #define KA0702$M_MCR_SP0_SIZE 0x1 #define KA0702$M_MCR_SP1_SIZE 0x2 #define KA0702$M_MCR_SP2_SIZE 0x4 #define KA0702$M_MCR_SP3_SIZE 0x8 #define KA0702$M_LDP_DMA_PA_LO 0xFFFE0 #define KA0702$M_LDP_DMA_PA_HI 0xFFF00000 #define KA0702$M_SCOMM_TR_DMA_PA 0xFFFFFFE0 #define KA0702$M_SCOMM_RC_DMA_PA 0xFFFFFFE0 #define KA0702$M_PRINTER_TR_DMA_PA 0xFFFFFFE0 #define KA0702$M_PRINTER_RC_DMA_PA 0xFFFFFFE0 #define KA0702$M_ISDN_TR_DMA_PA 0xFFFFFFE0 #define KA0702$M_ISDN_TR_BUF_DMA_PA 0xFFFFFFE0 #define KA0702$M_ISDN_RC_DMA_PA 0xFFFFFFE0 #define KA0702$M_ISDN_RC_BUF_DMA_PA 0xFFFFFFE0 #define KA0702$M_SSR_IO_MASK 0xF #define KA0702$M_SSR_IO_MASK_EN 0x10 #define KA0702$M_SSR_FPE 0x80 #define KA0702$M_SSR_LANCE_RESET 0x100 #define KA0702$M_SSR_RTC_RESET 0x400 #define KA0702$M_SSR_SCC_RESET 0x800 #define KA0702$M_SSR_ISDN_RESET 0x1000 #define KA0702$M_SSR_TXDIS 0x8000 #define KA0702$M_SSR_LANCE_DMA_EN 0x10000 #define KA0702$M_SSR_ISDN_RCV_EN 0x80000 #define KA0702$M_SSR_ISDN_TR_EN 0x100000 #define KA0702$M_SSR_SMR0 0x1000000 #define KA0702$M_SSR_SMR1 0x2000000 #define KA0702$M_SSR_SMRA 0x4000000 #define KA0702$M_SSR_FAST_MODE 0x8000000 #define KA0702$M_SSR_KBD_RC_DMA_EN 0x10000000 #define KA0702$M_SSR_KBD_TR_DMA_EN 0x20000000 #define KA0702$M_SSR_COMM_RC_DMA_EN 0x40000000 #define KA0702$M_SSR_COMM_TR_DMA_EN 0x80000000 #define KA0702$M_SIR_HALT0 0x1 #define KA0702$M_SIR_HALT1 0x2 #define KA0702$M_SIR_TC_SLOT0 0x4 #define KA0702$M_SIR_TC_SLOT1 0x8 #define KA0702$M_SIR_SCC0_INT 0x40 #define KA0702$M_SIR_SCC1_INT 0x80 #define KA0702$M_SIR_LANCE_INT 0x100 #define KA0702$M_SIR_ISDN_INT 0x2000 #define KA0702$M_SIR_CONS_SEL 0x8000 #define KA0702$M_SIR_LANCE_DMA_ER 0x10000 #define KA0702$M_SIR_ISDN_DMA_MRE 0x100000 #define KA0702$M_SIR_ISDN_DMA_RC_INTR 0x200000 #define KA0702$M_SIR_ISDN_DMA_TR_INTR 0x400000 #define KA0702$M_SIR_SCC1_DMA_OV 0x1000000 #define KA0702$M_SIR_SCC1_RCV_INT 0x2000000 #define KA0702$M_SIR_SCC1_TR_DMA_ME 0x4000000 #define KA0702$M_SIR_SCC1_TR_INT 0x8000000 #define KA0702$M_SIR_SCC0_DMA_OV 0x10000000 #define KA0702$M_SIR_SCC0_RCV_INT 0x20000000 #define KA0702$M_SIR_SCC0_TR_DMA_ME 0x40000000 #define KA0702$M_SIR_SCC0_TR_INT 0x80000000 #define KA0702$M_SIMR_HALT0 0x1 #define KA0702$M_SIMR_HALT1 0x2 #define KA0702$M_SIMR_TC_SLOT0 0x4 #define KA0702$M_SIMR_TC_SLOT1 0x8 #define KA0702$M_SIMR_SCC0_INT 0x40 #define KA0702$M_SIMR_SCC1_INT 0x80 #define KA0702$M_SIMR_LANCE_INT 0x100 #define KA0702$M_SIMR_ISDN_INT 0x2000 #define KA0702$M_SIMR_CONS_SEL 0x8000 #define KA0702$M_SIMR_LANCE_DMA_ER 0x10000 #define KA0702$M_SIMR_ISDN_DMA_MRE 0x100000 #define KA0702$M_SIMR_ISDN_DMA_RC_INTR 0x200000 #define KA0702$M_SIMR_ISDN_DMA_TR_INTR 0x400000 #define KA0702$M_SIMR_SCC1_DMA_OV 0x1000000 #define KA0702$M_SIMR_SCC1_RCV_INT 0x2000000 #define KA0702$M_SIMR_SCC1_TR_DMA_ME 0x4000000 #define KA0702$M_SIMR_SCC1_TR_INT 0x8000000 #define KA0702$M_SIMR_SCC0_DMA_OV 0x10000000 #define KA0702$M_SIMR_SCC0_RCV_INT 0x20000000 #define KA0702$M_SIMR_SCC0_TR_DMA_ME 0x40000000 #define KA0702$M_SIMR_SCC0_TR_INT 0x80000000 #define KA0702$M_SADR_TC_ADDR 0x1FFFFE0 #define KA0702$M_ISDN_DATA_TR_DATA 0xFFFFFF #define KA0702$M_ISDN_DATA_RC_DATA 0xFFFFFF #define KA0702$M_LANCE_SLOT_CS 0xF #define KA0702$M_LANCE_SLOT_HW_ADDR 0x3F0 #define KA0702$M_SCC0_SLOT_CS 0xF #define KA0702$M_SCC0_SLOT_HW_ADDR 0x3F0 #define KA0702$M_SCC1_SLOT_CS 0xF #define KA0702$M_SCC1_SLOT_HW_ADDR 0x3F0 #define KA0702$M_MODE_FIELD 0x7 #define KA0702$M_BOOLOP_OP 0xF #define KA0702$M_PIXELSHIFT_COUNT 0xF #define KA0702$M_ADDR_REG_VALUE 0xFFFFFF #define KA0702$M_BRES1_EI1 0xFFFF #define KA0702$M_BRES1_AI1 0xFFFF0000 #define KA0702$M_BRES2_EI2 0xFFFF #define KA0702$M_BRES2_AI2 0xFFFF0000 #define KA0702$M_BRES3_LL 0xF #define KA0702$M_BRES3_IEV 0xFFFF8000 #define KA0702$M_DEEP_PLANE 0x3 #define KA0702$M_V_REF_COUNT_VC 0x3FF #define KA0702$M_V_HOR_PIXELS 0x1FF #define KA0702$M_V_HOR_FP 0x3E00 #define KA0702$M_V_HOR_SYNCH 0x1FC000 #define KA0702$M_V_HOR_BP 0xFE00000 #define KA0702$M_V_VER_SL 0x7FF #define KA0702$M_V_VER_FP 0xF800 #define KA0702$M_V_VER_SYNCH 0x3F0000 #define KA0702$M_V_VER_BP 0xFC00000 #define KA0702$M_V_BASE_ADDR_ROW 0x1FF #define KA0702$M_RAMDAC_ADDR_LO_BYTE0 0xFF #define KA0702$M_RAMDAC_ADDR_HI_BYTE0 0xFF #define KA0702$M_RAMDAC_REG_ADDR_BYTE0 0xFF #define KA0702$M_RAMDAC_MAP_LOC_BYTE0 0xFF #define KA0702$S_KA0702DEF 2179072 /* Old size name, synonym for KA0702$S_KA0702 */ typedef struct _ka0702 { __union { unsigned int ka0702$l_ir; /* Interrupt register */ __struct { unsigned ka0702$v_ir_fill1 : 2; unsigned ka0702$v_ir_sfb_int : 1; unsigned ka0702$v_ir_scsi_int : 1; unsigned ka0702$v_ir_coreio_int : 1; unsigned ka0702$v_ir_fill2 : 22; unsigned ka0702$v_ir_bc_tpe : 1; unsigned ka0702$v_ir_tc_ore : 1; unsigned ka0702$v_ir_tc_toe : 1; unsigned ka0702$v_ir_bpe : 1; unsigned ka0702$v_ir_mpe : 1; } ka0702$r_ir_bits; } ka0702$r_ir_overlay; unsigned char ka0702$b_fill510 [12]; /* fill to next sparse space addr offset = 10 */ __union { unsigned int ka0702$l_tcsr; /* TC status and control register */ __struct { unsigned ka0702$v_tcsr_ap0 : 1; unsigned ka0702$v_tcsr_ap1 : 1; unsigned ka0702$v_tcsr_ap2 : 1; unsigned ka0702$v_tcsr_ap3 : 1; unsigned ka0702$v_tcsr_ap4 : 1; unsigned ka0702$v_tcsr_fill : 27; } ka0702$r_tcsr_bits; } ka0702$r_tcsr_overlay; unsigned char ka0702$b_fill511 [12]; /* fill to next sparse space addr offset = 20 */ __union { unsigned int ka0702$l_mcr; /* Memory Configuration Register */ __struct { unsigned ka0702$v_mcr_sp0_size : 1; /* SIMM PAIR0 Size */ unsigned ka0702$v_mcr_sp1_size : 1; /* SIMM PAIR1 Size */ unsigned ka0702$v_mcr_sp2_size : 1; /* SIMM PAIR2 Size */ unsigned ka0702$v_mcr_sp3_size : 1; /* SIMM PAIR3 Size */ unsigned ka0702$v_fill_0_ : 4; } ka0702$r_mcr_bits; } ka0702$r_mcr_overlay; unsigned char ka0702$b_fill520 [8156]; unsigned int ka0702$l_ioctl_csr; /* Core I/O base CSR address */ unsigned char ka0702$b_fill560 [60]; __union { unsigned int ka0702$l_ldp; /* Ethernet Lance DMA pointer */ __struct { unsigned ka0702$v_ldp_fill1 : 5; unsigned ka0702$v_ldp_dma_pa_lo : 15; unsigned ka0702$v_ldp_dma_pa_hi : 12; } ka0702$r_ldp_bits; } ka0702$r_ldp_overlay; unsigned char ka0702$b_fill570 [28]; __union { unsigned int ka0702$l_scomm_tr; /* Serial comm transmit port 1 DMA pointer */ __struct { unsigned ka0702$v_scomm_tr_fill1 : 5; unsigned ka0702$v_scomm_tr_dma_pa : 27; } ka0702$r_scomm_tr_bits; } ka0702$r_scomm_tr_overlay; unsigned char ka0702$b_fill580 [28]; __union { unsigned int ka0702$l_scomm_rc; /* Serial comm receive port 1 DMA pointer */ __struct { unsigned ka0702$v_scomm_rc_fill1 : 5; unsigned ka0702$v_scomm_rc_dma_pa : 27; } ka0702$r_scomm_rc_bits; } ka0702$r_scomm_rc_overlay; unsigned char ka0702$b_fill590 [28]; __union { unsigned int ka0702$l_printer_tr; /* Printer transmit port DMA pointer */ __struct { unsigned ka0702$v_printer_tr_fill1 : 5; unsigned ka0702$v_printer_tr_dma_pa : 27; } ka0702$r_printer_tr_bits; } ka0702$r_printer_tr_overlay; unsigned char ka0702$b_fill600 [28]; __union { unsigned int ka0702$l_printer_rc; /* Printer receive port DMA pointer */ __struct { unsigned ka0702$v_printer_rc_fill1 : 5; unsigned ka0702$v_printer_rc_dma_pa : 27; } ka0702$r_printer_rc_bits; } ka0702$r_printer_rc_overlay; unsigned char ka0702$b_fill610 [60]; __union { unsigned int ka0702$l_isdn_tr; /* ISDN transmit DMA pointer */ __struct { unsigned ka0702$v_isdn_tr_fill1 : 5; unsigned ka0702$v_isdn_tr_dma_pa : 27; } ka0702$r_isdn_tr_bits; } ka0702$r_isdn_tr_overlay; unsigned char ka0702$b_fill620 [28]; __union { unsigned int ka0702$l_isdn_tr_buf; /* ISDN transmit DMA buffer pointer */ __struct { unsigned ka0702$v_isdn_tr_buf_fill1 : 5; unsigned ka0702$v_isdn_tr_buf_dma_pa : 27; } ka0702$r_isdn_tr_buf_bits; } ka0702$r_isdn_tr_buf_overlay; unsigned char ka0702$b_fill630 [28]; __union { unsigned int ka0702$l_isdn_rc; /* ISDN receive DMA pointer */ __struct { unsigned ka0702$v_isdn_rc_fill1 : 5; unsigned ka0702$v_isdn_rc_dma_pa : 27; } ka0702$r_isdn_rc_bits; } ka0702$r_isdn_rc_overlay; unsigned char ka0702$b_fill640 [28]; __union { unsigned int ka0702$l_isdn_rc_buf; /* ISDN receive DMA buffer pointer */ __struct { unsigned ka0702$v_isdn_rc_buf_fill1 : 5; unsigned ka0702$v_isdn_rc_buf_dma_pa : 27; } ka0702$r_isdn_rc_buf_bits; } ka0702$r_isdn_rc_buf_overlay; unsigned char ka0702$b_fill650 [28]; unsigned int ka0702$l_data0; /* System Data Buffer 0 */ unsigned char ka0702$b_fill660 [28]; unsigned int ka0702$l_data1; /* System Data Buffer 1 */ unsigned char ka0702$b_fill670 [28]; unsigned int ka0702$l_data2; /* System Data Buffer 2 */ unsigned char ka0702$b_fill680 [28]; unsigned int ka0702$l_data3; /* System Data Buffer 3 */ unsigned char ka0702$b_fill690 [28]; __union { unsigned int ka0702$l_ssr; /* System support register */ __struct { unsigned ka0702$v_ssr_io_mask : 4; unsigned ka0702$v_ssr_io_mask_en : 1; unsigned ka0702$v_ssr_sys_ok_led : 1; unsigned ka0702$v_ssr_fill1 : 1; unsigned ka0702$v_ssr_fpe : 1; unsigned ka0702$v_ssr_lance_reset : 1; unsigned ka0702$v_ssr_fill2 : 1; unsigned ka0702$v_ssr_rtc_reset : 1; unsigned ka0702$v_ssr_scc_reset : 1; unsigned ka0702$v_ssr_isdn_reset : 1; unsigned ka0702$v_ssr_fill3 : 2; unsigned ka0702$v_ssr_txdis : 1; unsigned ka0702$v_ssr_lance_dma_en : 1; unsigned ka0702$v_ssr_fill4 : 2; unsigned ka0702$v_ssr_isdn_rcv_en : 1; unsigned ka0702$v_ssr_isdn_tr_en : 1; unsigned ka0702$v_ssr_fill5 : 3; unsigned ka0702$v_ssr_smr0 : 1; unsigned ka0702$v_ssr_smr1 : 1; unsigned ka0702$v_ssr_smra : 1; unsigned ka0702$v_ssr_fast_mode : 1; unsigned ka0702$v_ssr_kbd_rc_dma_en : 1; unsigned ka0702$v_ssr_kbd_tr_dma_en : 1; unsigned ka0702$v_ssr_comm_rc_dma_en : 1; unsigned ka0702$v_ssr_comm_tr_dma_en : 1; } ka0702$r_ssr_bits; } ka0702$r_ssr_overlay; unsigned char ka0702$b_fill700 [28]; __union { unsigned int ka0702$l_sir; /* System interrupt register */ __struct { unsigned ka0702$v_sir_halt0 : 1; unsigned ka0702$v_sir_halt1 : 1; unsigned ka0702$v_sir_tc_slot0 : 1; unsigned ka0702$v_sir_tc_slot1 : 1; unsigned ka0702$v_sir_fill1 : 2; unsigned ka0702$v_sir_scc0_int : 1; unsigned ka0702$v_sir_scc1_int : 1; unsigned ka0702$v_sir_lance_int : 1; unsigned ka0702$v_sir_fill2 : 4; unsigned ka0702$v_sir_isdn_int : 1; unsigned ka0702$v_sir_fill3 : 1; unsigned ka0702$v_sir_cons_sel : 1; unsigned ka0702$v_sir_lance_dma_er : 1; unsigned ka0702$v_sir_fill4 : 3; unsigned ka0702$v_sir_isdn_dma_mre : 1; unsigned ka0702$v_sir_isdn_dma_rc_intr : 1; unsigned ka0702$v_sir_isdn_dma_tr_intr : 1; unsigned ka0702$v_sir_fill6 : 1; unsigned ka0702$v_sir_scc1_dma_ov : 1; unsigned ka0702$v_sir_scc1_rcv_int : 1; unsigned ka0702$v_sir_scc1_tr_dma_me : 1; unsigned ka0702$v_sir_scc1_tr_int : 1; unsigned ka0702$v_sir_scc0_dma_ov : 1; unsigned ka0702$v_sir_scc0_rcv_int : 1; unsigned ka0702$v_sir_scc0_tr_dma_me : 1; unsigned ka0702$v_sir_scc0_tr_int : 1; } ka0702$r_sir_bits; } ka0702$r_sir_overlay; unsigned char ka0702$b_fill710 [28]; __union { unsigned int ka0702$l_simr; /* System interrupt mask register */ __struct { unsigned ka0702$v_simr_halt0 : 1; unsigned ka0702$v_simr_halt1 : 1; unsigned ka0702$v_simr_tc_slot0 : 1; unsigned ka0702$v_simr_tc_slot1 : 1; unsigned ka0702$v_simr_fill1 : 2; unsigned ka0702$v_simr_scc0_int : 1; unsigned ka0702$v_simr_scc1_int : 1; unsigned ka0702$v_simr_lance_int : 1; unsigned ka0702$v_simr_fill2 : 4; unsigned ka0702$v_simr_isdn_int : 1; unsigned ka0702$v_simr_fill3 : 1; unsigned ka0702$v_simr_cons_sel : 1; unsigned ka0702$v_simr_lance_dma_er : 1; unsigned ka0702$v_simr_fill4 : 3; unsigned ka0702$v_simr_isdn_dma_mre : 1; unsigned ka0702$v_simr_isdn_dma_rc_intr : 1; unsigned ka0702$v_simr_isdn_dma_tr_intr : 1; unsigned ka0702$v_simr_fill6 : 1; unsigned ka0702$v_simr_scc1_dma_ov : 1; unsigned ka0702$v_simr_scc1_rcv_int : 1; unsigned ka0702$v_simr_scc1_tr_dma_me : 1; unsigned ka0702$v_simr_scc1_tr_int : 1; unsigned ka0702$v_simr_scc0_dma_ov : 1; unsigned ka0702$v_simr_scc0_rcv_int : 1; unsigned ka0702$v_simr_scc0_tr_dma_me : 1; unsigned ka0702$v_simr_scc0_tr_int : 1; } ka0702$r_simr_bits; } ka0702$r_simr_overlay; unsigned char ka0702$b_fill720 [28]; __union { unsigned int ka0702$l_sadr; /* System address register */ __struct { unsigned ka0702$v_sadr_fill1 : 5; unsigned ka0702$v_sadr_tc_addr : 20; unsigned ka0702$v_sadr_fill2 : 7; } ka0702$r_sadr_bits; } ka0702$r_sadr_overlay; unsigned char ka0702$b_fill730 [28]; __union { unsigned int ka0702$l_isdn_data_tr; /* ISDN Data Transmit */ __struct { unsigned ka0702$v_isdn_data_tr_data : 24; unsigned ka0702$v_isdn_data_tr_fill : 8; } ka0702$r_isdn_data_tr_bits; } ka0702$r_isdn_data_tr_overlay; unsigned char ka0702$b_fill740 [28]; __union { unsigned int ka0702$l_isdn_data_rc; /* ISDN Data Receive */ __struct { unsigned ka0702$v_isdn_data_rc_data : 24; unsigned ka0702$v_isdn_data_rc_fill : 8; } ka0702$r_isdn_data_rc_bits; } ka0702$r_isdn_data_rc_overlay; unsigned char ka0702$b_fill750 [28]; __union { unsigned int ka0702$l_lance_slot; /* Lance slot register */ __struct { unsigned ka0702$v_lance_slot_cs : 4; unsigned ka0702$v_lance_slot_hw_addr : 6; unsigned ka0702$v_lance_slot_fill : 22; } ka0702$r_lance_slot_bits; } ka0702$r_lance_slot_overlay; unsigned char ka0702$b_fill760 [60]; __union { unsigned int ka0702$l_scc0_slot; /* SCC0 slot register */ __struct { unsigned ka0702$v_scc0_slot_cs : 4; unsigned ka0702$v_scc0_slot_hw_addr : 6; unsigned ka0702$v_scc0_slot_fill : 22; } ka0702$r_scc0_slot_bits; } ka0702$r_scc0_slot_overlay; unsigned char ka0702$b_fill770 [28]; __union { unsigned int ka0702$l_scc1_slot; /* SCC1 slot register */ __struct { unsigned ka0702$v_scc1_slot_cs : 4; unsigned ka0702$v_scc1_slot_hw_addr : 6; unsigned ka0702$v_scc1_slot_fill : 22; } ka0702$r_scc1_slot_bits; } ka0702$r_scc1_slot_overlay; unsigned char ka0702$b_fill780 [7388]; unsigned int ka0702$l_ni_adr_rom; /* Ethernet address ROM */ unsigned char ka0702$b_fill790 [8188]; unsigned int ka0702$l_lance_rdp; /* Lance ethernet CSR */ unsigned char ka0702$b_fill800 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_lance_rap; /* Lance ethernet CSR */ unsigned char ka0702$b_fill810 [8180]; unsigned int ka0702$l_scc0b_comm_rap; /* Comm Port 1 RAP */ unsigned char ka0702$b_fill820 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_scc0b_comm_data; /* Comm Port 1 data */ unsigned char ka0702$b_fill830 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_scc0a_mouse_rap; /* Mouse RAP */ unsigned char ka0702$b_fill840 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_scc0a_mouse_data; /* Mouse port data register */ unsigned char ka0702$b_fill850 [8164]; unsigned int ka0702$l_scc1b_print_rap; /* Printer Port 2 RAP */ unsigned char ka0702$b_fill860 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_scc1b_print_data; /* Printer Port 2 data */ unsigned char ka0702$b_fill870 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_scc1a_key_rap; /* Keyboard RAP */ unsigned char ka0702$b_fill880 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_scc1a_key_data; /* Keyboard port data register */ unsigned char ka0702$b_fill890 [8164]; unsigned int ka0702$l_rtc_sec; /* TOY clock CSR--seconds */ unsigned char ka0702$b_fill900 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_alms; /* TOY clock CSR--seconds alarm */ unsigned char ka0702$b_fill910 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_min; /* TOY clock CSR--minutes */ unsigned char ka0702$b_fill920 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_almn; /* TOY clock CSR--minutes alarm */ unsigned char ka0702$b_fill930 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_hour; /* TOY clock CSR--hours */ unsigned char ka0702$b_fill940 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_almh; /* TOY clock CSR--hours alarm */ unsigned char ka0702$b_fill950 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_dow; /* TOY clock CSR--day of week */ unsigned char ka0702$b_fill960 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_day; /* TOY clock CSR--date of month */ unsigned char ka0702$b_fill970 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_mon; /* TOY clock CSR--month */ unsigned char ka0702$b_fill980 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_year; /* TOY clock CSR--year */ unsigned char ka0702$b_fill990 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_rega; /* TOY clock CSR--register A */ unsigned char ka0702$b_fill1000 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_regb; /* TOY clock CSR--register B */ unsigned char ka0702$b_fill1010 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_regc; /* TOY clock CSR--register C */ unsigned char ka0702$b_fill1020 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_regd; /* TOY clock CSR--register D */ unsigned char ka0702$b_fill1030 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_rtc_ram; /* TOY clock CSR--base of BBU RAM */ unsigned char ka0702$b_fill1035 [260]; /* Fill to SCSI Host ID location */ unsigned int ka0702$l_scsi_host_id; /* SCSI Host ID */ unsigned char ka0702$b_fill1040 [7812]; unsigned int ka0702$l_isdn_audio; /* ISDN audio chip CSR */ unsigned char ka0702$b_fill1050 [8188]; unsigned int ka0702$l_cpybuf0; /* Copy Buffer register */ unsigned char ka0702$b_fill1070 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf1; /* Copy Buffer register */ unsigned char ka0702$b_fill1080 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf2; /* Copy Buffer register */ unsigned char ka0702$b_fill1090 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf3; /* Copy Buffer register */ unsigned char ka0702$b_fill1110 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf4; /* Copy Buffer register */ unsigned char ka0702$b_fill1120 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf5; /* Copy Buffer register */ unsigned char ka0702$b_fill1130 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf6; /* Copy Buffer register */ unsigned char ka0702$b_fill1140 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_cpybuf7; /* Copy Buffer register */ unsigned char ka0702$b_fill1150 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_fg; /* Foreground */ unsigned char ka0702$b_fill1160 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_bg; /* Background */ unsigned char ka0702$b_fill1170 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_planemask; /* Planemask */ unsigned char ka0702$b_fill1180 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_pixelmask; /* Pixel Mask register */ unsigned char ka0702$b_fill1190 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_mode; /* Mode register */ __struct { unsigned ka0702$v_mode_field : 3; unsigned ka0702$v_mode_fill : 29; } ka0702$r_mode_bits; } ka0702$r_mode_overlay; unsigned char ka0702$b_fill1200 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_boolop; /* Boolean Op register */ __struct { unsigned ka0702$v_boolop_op : 4; unsigned ka0702$v_boolop_fill : 28; } ka0702$r_boolop_bits; } ka0702$r_boolop_overlay; unsigned char ka0702$b_fill1210 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_pixelshift; /* Pixel Shift register */ __struct { unsigned ka0702$v_pixelshift_count : 4; unsigned ka0702$v_pixelshift_fill : 28; } ka0702$r_pixelshift_bits; } ka0702$r_pixelshift_overlay; unsigned char ka0702$b_fill1220 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_addr_reg; /* Address register */ __struct { unsigned ka0702$v_addr_reg_value : 24; unsigned ka0702$v_addr_reg_fill : 8; } ka0702$r_addr_reg_bits; } ka0702$r_addr_reg_overlay; unsigned char ka0702$b_fill1230 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_bres1; /* Bresenham register 1 */ __struct { unsigned ka0702$v_bres1_ei1 : 16; unsigned ka0702$v_bres1_ai1 : 16; } ka0702$r_bres1_bits; } ka0702$r_bres1_overlay; unsigned char ka0702$b_fill1240 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_bres2; /* Bresenham register 2 */ __struct { unsigned ka0702$v_bres2_ei2 : 16; unsigned ka0702$v_bres2_ai2 : 16; } ka0702$r_bres2_bits; } ka0702$r_bres2_overlay; unsigned char ka0702$b_fill1250 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_bres3; /* Bresenham register 3 */ __struct { unsigned ka0702$v_bres3_ll : 4; unsigned ka0702$v_bres3_fill1 : 11; unsigned ka0702$v_bres3_iev : 17; } ka0702$r_bres3_bits; } ka0702$r_bres3_overlay; unsigned char ka0702$b_fill1260 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_bcont; /* Bresenham continue */ unsigned char ka0702$b_fill1270 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_deep; /* Deep register */ __struct { unsigned ka0702$v_deep_plane : 2; unsigned ka0702$v_deep_fill : 30; } ka0702$r_deep_bits; } ka0702$r_deep_overlay; unsigned char ka0702$b_fill1280 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_start; /* Start register */ unsigned char ka0702$b_fill1290 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_ci; /* Clear interrupt */ unsigned char ka0702$b_fill1300 [12]; __union { unsigned int ka0702$l_v_ref_count; /* Video refresh count */ __struct { unsigned ka0702$v_v_ref_count_vc : 10; unsigned ka0702$v_v_ref_count_fill : 22; } ka0702$r_v_ref_count_bits; } ka0702$r_v_ref_count_overlay; unsigned char ka0702$b_fill1310 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_v_hor; /* Video horizontal setup */ __struct { unsigned ka0702$v_v_hor_pixels : 9; unsigned ka0702$v_v_hor_fp : 5; unsigned ka0702$v_v_hor_synch : 7; unsigned ka0702$v_v_hor_bp : 7; unsigned ka0702$v_v_hor_fill1 : 4; } ka0702$r_v_hor_bits; } ka0702$r_v_hor_overlay; unsigned char ka0702$b_fill1320 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_v_ver; /* Video vertical setup */ __struct { unsigned ka0702$v_v_ver_sl : 11; unsigned ka0702$v_v_ver_fp : 5; unsigned ka0702$v_v_ver_synch : 6; unsigned ka0702$v_v_ver_bp : 6; unsigned ka0702$v_v_ver_fill1 : 4; } ka0702$r_v_ver_bits; } ka0702$r_v_ver_overlay; unsigned char ka0702$b_fill1325 [4]; /* Fill to allow a longword of */ __union { unsigned int ka0702$l_v_base_addr; /* Video Base Address */ __struct { unsigned ka0702$v_v_base_addr_row : 9; unsigned ka0702$v_v_base_addr_fill : 23; } ka0702$r_v_base_addr_bits; } ka0702$r_v_base_addr_overlay; unsigned char ka0702$b_fill1330 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_vv; /* Video valid */ unsigned char ka0702$b_fill1340 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_ei; /* Enable interrupts */ unsigned char ka0702$b_fill1350 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_tcclk_count; /* TC clk count */ unsigned char ka0702$b_fill1360 [4]; /* Fill to allow sparse space byte mask */ unsigned int ka0702$l_vidclk_count; /* TC clk count */ unsigned char ka0702$b_fill1370 [7940]; __union { unsigned int ka0702$l_ramdac_addr_lo; /* RAMDAC color map and registers */ __struct { unsigned ka0702$v_ramdac_addr_lo_byte0 : 8; unsigned ka0702$v_ramdac_addr_lo_fill : 24; } ka0702$r_ramdac_addr_lo_bits; } ka0702$r_ramdac_addr_lo_overlay; unsigned char ka0702$b_fill1380 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_ramdac_addr_hi; /* RAMDAC color map and registers */ __struct { unsigned ka0702$v_ramdac_addr_hi_byte0 : 8; unsigned ka0702$v_ramdac_addr_hi_fill : 24; } ka0702$r_ramdac_addr_hi_bits; } ka0702$r_ramdac_addr_hi_overlay; unsigned char ka0702$b_fill1390 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_ramdac_reg_addr; /* RAMDAC color map and registers */ __struct { unsigned ka0702$v_ramdac_reg_addr_byte0 : 8; unsigned ka0702$v_ramdac_reg_addr_fill : 24; } ka0702$r_ramdac_reg_addr_bits; } ka0702$r_ramdac_reg_addr_overlay; unsigned char ka0702$b_fill1400 [4]; /* Fill to allow sparse space byte mask */ __union { unsigned int ka0702$l_ramdac_map_loc; /* RAMDAC color map and registers */ __struct { unsigned ka0702$v_ramdac_map_loc_byte0 : 8; unsigned ka0702$v_ramdac_map_loc_fill : 24; } ka0702$r_ramdac_map_loc_bits; } ka0702$r_ramdac_map_loc_overlay; unsigned char ka0702$b_fill1410 [8164]; unsigned int ka0702$l_fb; /* Video RAM (2 MB dense) */ unsigned char ka0702$b_fill1420 [2097148]; } KA0702; #if !defined(__VAXC) #define ka0702$l_ir ka0702$r_ir_overlay.ka0702$l_ir #define ka0702$v_ir_sfb_int ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_sfb_int #define ka0702$v_ir_scsi_int ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_scsi_int #define ka0702$v_ir_coreio_int ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_coreio_int #define ka0702$v_ir_bc_tpe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_bc_tpe #define ka0702$v_ir_tc_ore ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_tc_ore #define ka0702$v_ir_tc_toe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_tc_toe #define ka0702$v_ir_bpe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_bpe #define ka0702$v_ir_mpe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_mpe #define ka0702$l_tcsr ka0702$r_tcsr_overlay.ka0702$l_tcsr #define ka0702$v_tcsr_ap0 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap0 #define ka0702$v_tcsr_ap1 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap1 #define ka0702$v_tcsr_ap2 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap2 #define ka0702$v_tcsr_ap3 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap3 #define ka0702$v_tcsr_ap4 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap4 #define ka0702$l_mcr ka0702$r_mcr_overlay.ka0702$l_mcr #define ka0702$v_mcr_sp0_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp0_size #define ka0702$v_mcr_sp1_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp1_size #define ka0702$v_mcr_sp2_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp2_size #define ka0702$v_mcr_sp3_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp3_size #define ka0702$l_ldp ka0702$r_ldp_overlay.ka0702$l_ldp #define ka0702$v_ldp_dma_pa_lo ka0702$r_ldp_overlay.ka0702$r_ldp_bits.ka0702$v_ldp_dma_pa_lo #define ka0702$v_ldp_dma_pa_hi ka0702$r_ldp_overlay.ka0702$r_ldp_bits.ka0702$v_ldp_dma_pa_hi #define ka0702$l_scomm_tr ka0702$r_scomm_tr_overlay.ka0702$l_scomm_tr #define ka0702$v_scomm_tr_dma_pa ka0702$r_scomm_tr_overlay.ka0702$r_scomm_tr_bits.ka0702$v_scomm_tr_dma_pa #define ka0702$l_scomm_rc ka0702$r_scomm_rc_overlay.ka0702$l_scomm_rc #define ka0702$v_scomm_rc_dma_pa ka0702$r_scomm_rc_overlay.ka0702$r_scomm_rc_bits.ka0702$v_scomm_rc_dma_pa #define ka0702$l_printer_tr ka0702$r_printer_tr_overlay.ka0702$l_printer_tr #define ka0702$v_printer_tr_dma_pa ka0702$r_printer_tr_overlay.ka0702$r_printer_tr_bits.ka0702$v_printer_tr_dma_pa #define ka0702$l_printer_rc ka0702$r_printer_rc_overlay.ka0702$l_printer_rc #define ka0702$v_printer_rc_dma_pa ka0702$r_printer_rc_overlay.ka0702$r_printer_rc_bits.ka0702$v_printer_rc_dma_pa #define ka0702$l_isdn_tr ka0702$r_isdn_tr_overlay.ka0702$l_isdn_tr #define ka0702$v_isdn_tr_dma_pa ka0702$r_isdn_tr_overlay.ka0702$r_isdn_tr_bits.ka0702$v_isdn_tr_dma_pa #define ka0702$l_isdn_tr_buf ka0702$r_isdn_tr_buf_overlay.ka0702$l_isdn_tr_buf #define ka0702$v_isdn_tr_buf_dma_pa ka0702$r_isdn_tr_buf_overlay.ka0702$r_isdn_tr_buf_bits.ka0702$v_isdn_tr_buf_dma_pa #define ka0702$l_isdn_rc ka0702$r_isdn_rc_overlay.ka0702$l_isdn_rc #define ka0702$v_isdn_rc_dma_pa ka0702$r_isdn_rc_overlay.ka0702$r_isdn_rc_bits.ka0702$v_isdn_rc_dma_pa #define ka0702$l_isdn_rc_buf ka0702$r_isdn_rc_buf_overlay.ka0702$l_isdn_rc_buf #define ka0702$v_isdn_rc_buf_dma_pa ka0702$r_isdn_rc_buf_overlay.ka0702$r_isdn_rc_buf_bits.ka0702$v_isdn_rc_buf_dma_pa #define ka0702$l_ssr ka0702$r_ssr_overlay.ka0702$l_ssr #define ka0702$v_ssr_io_mask ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_io_mask #define ka0702$v_ssr_io_mask_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_io_mask_en #define ka0702$v_ssr_fpe ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_fpe #define ka0702$v_ssr_lance_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_lance_reset #define ka0702$v_ssr_rtc_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_rtc_reset #define ka0702$v_ssr_scc_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_scc_reset #define ka0702$v_ssr_isdn_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_isdn_reset #define ka0702$v_ssr_txdis ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_txdis #define ka0702$v_ssr_lance_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_lance_dma_en #define ka0702$v_ssr_isdn_rcv_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_isdn_rcv_en #define ka0702$v_ssr_isdn_tr_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_isdn_tr_en #define ka0702$v_ssr_smr0 ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_smr0 #define ka0702$v_ssr_smr1 ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_smr1 #define ka0702$v_ssr_smra ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_smra #define ka0702$v_ssr_fast_mode ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_fast_mode #define ka0702$v_ssr_kbd_rc_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_kbd_rc_dma_en #define ka0702$v_ssr_kbd_tr_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_kbd_tr_dma_en #define ka0702$v_ssr_comm_rc_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_comm_rc_dma_en #define ka0702$v_ssr_comm_tr_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_comm_tr_dma_en #define ka0702$l_sir ka0702$r_sir_overlay.ka0702$l_sir #define ka0702$v_sir_halt0 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_halt0 #define ka0702$v_sir_halt1 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_halt1 #define ka0702$v_sir_tc_slot0 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_tc_slot0 #define ka0702$v_sir_tc_slot1 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_tc_slot1 #define ka0702$v_sir_scc0_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_int #define ka0702$v_sir_scc1_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_int #define ka0702$v_sir_lance_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_lance_int #define ka0702$v_sir_isdn_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_int #define ka0702$v_sir_cons_sel ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_cons_sel #define ka0702$v_sir_lance_dma_er ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_lance_dma_er #define ka0702$v_sir_isdn_dma_mre ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_dma_mre #define ka0702$v_sir_isdn_dma_rc_intr ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_dma_rc_intr #define ka0702$v_sir_isdn_dma_tr_intr ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_dma_tr_intr #define ka0702$v_sir_scc1_dma_ov ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_dma_ov #define ka0702$v_sir_scc1_rcv_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_rcv_int #define ka0702$v_sir_scc1_tr_dma_me ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_tr_dma_me #define ka0702$v_sir_scc1_tr_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_tr_int #define ka0702$v_sir_scc0_dma_ov ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_dma_ov #define ka0702$v_sir_scc0_rcv_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_rcv_int #define ka0702$v_sir_scc0_tr_dma_me ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_tr_dma_me #define ka0702$v_sir_scc0_tr_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_tr_int #define ka0702$l_simr ka0702$r_simr_overlay.ka0702$l_simr #define ka0702$v_simr_halt0 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_halt0 #define ka0702$v_simr_halt1 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_halt1 #define ka0702$v_simr_tc_slot0 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_tc_slot0 #define ka0702$v_simr_tc_slot1 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_tc_slot1 #define ka0702$v_simr_scc0_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_int #define ka0702$v_simr_scc1_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_int #define ka0702$v_simr_lance_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_lance_int #define ka0702$v_simr_isdn_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_int #define ka0702$v_simr_cons_sel ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_cons_sel #define ka0702$v_simr_lance_dma_er ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_lance_dma_er #define ka0702$v_simr_isdn_dma_mre ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_dma_mre #define ka0702$v_simr_isdn_dma_rc_intr ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_dma_rc_intr #define ka0702$v_simr_isdn_dma_tr_intr ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_dma_tr_intr #define ka0702$v_simr_scc1_dma_ov ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_dma_ov #define ka0702$v_simr_scc1_rcv_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_rcv_int #define ka0702$v_simr_scc1_tr_dma_me ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_tr_dma_me #define ka0702$v_simr_scc1_tr_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_tr_int #define ka0702$v_simr_scc0_dma_ov ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_dma_ov #define ka0702$v_simr_scc0_rcv_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_rcv_int #define ka0702$v_simr_scc0_tr_dma_me ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_tr_dma_me #define ka0702$v_simr_scc0_tr_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_tr_int #define ka0702$l_sadr ka0702$r_sadr_overlay.ka0702$l_sadr #define ka0702$v_sadr_tc_addr ka0702$r_sadr_overlay.ka0702$r_sadr_bits.ka0702$v_sadr_tc_addr #define ka0702$l_isdn_data_tr ka0702$r_isdn_data_tr_overlay.ka0702$l_isdn_data_tr #define ka0702$v_isdn_data_tr_data ka0702$r_isdn_data_tr_overlay.ka0702$r_isdn_data_tr_bits.ka0702$v_isdn_data_tr_data #define ka0702$l_isdn_data_rc ka0702$r_isdn_data_rc_overlay.ka0702$l_isdn_data_rc #define ka0702$v_isdn_data_rc_data ka0702$r_isdn_data_rc_overlay.ka0702$r_isdn_data_rc_bits.ka0702$v_isdn_data_rc_data #define ka0702$l_lance_slot ka0702$r_lance_slot_overlay.ka0702$l_lance_slot #define ka0702$v_lance_slot_cs ka0702$r_lance_slot_overlay.ka0702$r_lance_slot_bits.ka0702$v_lance_slot_cs #define ka0702$v_lance_slot_hw_addr ka0702$r_lance_slot_overlay.ka0702$r_lance_slot_bits.ka0702$v_lance_slot_hw_addr #define ka0702$l_scc0_slot ka0702$r_scc0_slot_overlay.ka0702$l_scc0_slot #define ka0702$v_scc0_slot_cs ka0702$r_scc0_slot_overlay.ka0702$r_scc0_slot_bits.ka0702$v_scc0_slot_cs #define ka0702$v_scc0_slot_hw_addr ka0702$r_scc0_slot_overlay.ka0702$r_scc0_slot_bits.ka0702$v_scc0_slot_hw_addr #define ka0702$l_scc1_slot ka0702$r_scc1_slot_overlay.ka0702$l_scc1_slot #define ka0702$v_scc1_slot_cs ka0702$r_scc1_slot_overlay.ka0702$r_scc1_slot_bits.ka0702$v_scc1_slot_cs #define ka0702$v_scc1_slot_hw_addr ka0702$r_scc1_slot_overlay.ka0702$r_scc1_slot_bits.ka0702$v_scc1_slot_hw_addr #define ka0702$l_mode ka0702$r_mode_overlay.ka0702$l_mode #define ka0702$v_mode_field ka0702$r_mode_overlay.ka0702$r_mode_bits.ka0702$v_mode_field #define ka0702$l_boolop ka0702$r_boolop_overlay.ka0702$l_boolop #define ka0702$v_boolop_op ka0702$r_boolop_overlay.ka0702$r_boolop_bits.ka0702$v_boolop_op #define ka0702$l_pixelshift ka0702$r_pixelshift_overlay.ka0702$l_pixelshift #define ka0702$v_pixelshift_count ka0702$r_pixelshift_overlay.ka0702$r_pixelshift_bits.ka0702$v_pixelshift_count #define ka0702$l_addr_reg ka0702$r_addr_reg_overlay.ka0702$l_addr_reg #define ka0702$v_addr_reg_value ka0702$r_addr_reg_overlay.ka0702$r_addr_reg_bits.ka0702$v_addr_reg_value #define ka0702$l_bres1 ka0702$r_bres1_overlay.ka0702$l_bres1 #define ka0702$v_bres1_ei1 ka0702$r_bres1_overlay.ka0702$r_bres1_bits.ka0702$v_bres1_ei1 #define ka0702$v_bres1_ai1 ka0702$r_bres1_overlay.ka0702$r_bres1_bits.ka0702$v_bres1_ai1 #define ka0702$l_bres2 ka0702$r_bres2_overlay.ka0702$l_bres2 #define ka0702$v_bres2_ei2 ka0702$r_bres2_overlay.ka0702$r_bres2_bits.ka0702$v_bres2_ei2 #define ka0702$v_bres2_ai2 ka0702$r_bres2_overlay.ka0702$r_bres2_bits.ka0702$v_bres2_ai2 #define ka0702$l_bres3 ka0702$r_bres3_overlay.ka0702$l_bres3 #define ka0702$v_bres3_ll ka0702$r_bres3_overlay.ka0702$r_bres3_bits.ka0702$v_bres3_ll #define ka0702$v_bres3_iev ka0702$r_bres3_overlay.ka0702$r_bres3_bits.ka0702$v_bres3_iev #define ka0702$l_deep ka0702$r_deep_overlay.ka0702$l_deep #define ka0702$v_deep_plane ka0702$r_deep_overlay.ka0702$r_deep_bits.ka0702$v_deep_plane #define ka0702$l_v_ref_count ka0702$r_v_ref_count_overlay.ka0702$l_v_ref_count #define ka0702$v_v_ref_count_vc ka0702$r_v_ref_count_overlay.ka0702$r_v_ref_count_bits.ka0702$v_v_ref_count_vc #define ka0702$l_v_hor ka0702$r_v_hor_overlay.ka0702$l_v_hor #define ka0702$v_v_hor_pixels ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_pixels #define ka0702$v_v_hor_fp ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_fp #define ka0702$v_v_hor_synch ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_synch #define ka0702$v_v_hor_bp ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_bp #define ka0702$l_v_ver ka0702$r_v_ver_overlay.ka0702$l_v_ver #define ka0702$v_v_ver_sl ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_sl #define ka0702$v_v_ver_fp ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_fp #define ka0702$v_v_ver_synch ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_synch #define ka0702$v_v_ver_bp ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_bp #define ka0702$l_v_base_addr ka0702$r_v_base_addr_overlay.ka0702$l_v_base_addr #define ka0702$v_v_base_addr_row ka0702$r_v_base_addr_overlay.ka0702$r_v_base_addr_bits.ka0702$v_v_base_addr_row #define ka0702$l_ramdac_addr_lo ka0702$r_ramdac_addr_lo_overlay.ka0702$l_ramdac_addr_lo #define ka0702$v_ramdac_addr_lo_byte0 ka0702$r_ramdac_addr_lo_overlay.ka0702$r_ramdac_addr_lo_bits.ka0702$v_ramdac_addr_lo_byte0 #define ka0702$l_ramdac_addr_hi ka0702$r_ramdac_addr_hi_overlay.ka0702$l_ramdac_addr_hi #define ka0702$v_ramdac_addr_hi_byte0 ka0702$r_ramdac_addr_hi_overlay.ka0702$r_ramdac_addr_hi_bits.ka0702$v_ramdac_addr_hi_byte0 #define ka0702$l_ramdac_reg_addr ka0702$r_ramdac_reg_addr_overlay.ka0702$l_ramdac_reg_addr #define ka0702$v_ramdac_reg_addr_byte0 ka0702$r_ramdac_reg_addr_overlay.ka0702$r_ramdac_reg_addr_bits.ka0702$v_ramdac_reg_addr_byte0 #define ka0702$l_ramdac_map_loc ka0702$r_ramdac_map_loc_overlay.ka0702$l_ramdac_map_loc #define ka0702$v_ramdac_map_loc_byte0 ka0702$r_ramdac_map_loc_overlay.ka0702$r_ramdac_map_loc_bits.ka0702$v_ramdac_map_loc_byte0 #endif /* #if !defined(__VAXC) */ #define KA0702$K_IO_SCB_VEC 2048 #define KA0702$K_SCSI_TC_SLOT 3 #define KA0702$K_CORE_IO_TC_SLOT 4 #define KA0702$K_CXTURBO_TC_SLOT 2 #define KA0702$K_TC_SLOT0_VEC 0 #define KA0702$K_TC_SLOT1_VEC 1 #define KA0702$K_TC_EMPTY2_VEC 2 #define KA0702$K_TC_EMPTY3_VEC 3 #define KA0702$K_TC_SLOT4_VEC 4 #define KA0702$K_COREIO_VEC 5 #define KA0702$K_SFB_VEC 6 #define KA0702$K_ETHERNET_VEC 7 #define KA0702$K_SCC_VEC 8 #define KA0702$K_OPDRVR_XMIT 9 #define KA0702$K_OPDRVR_RCV 10 #define KA0702$K_ISDN_VEC 11 #define KA0702$K_TOTAL_VECTORS 12 #define KA0702$M_MASK0 0x1 #define KA0702$M_MASK1 0x2 #define KA0702$M_MASK2 0x4 #define KA0702$M_MASK3 0x8 typedef struct _ka0702$r_ka0702_mask_bits { __union { __struct { unsigned ka0702$v_mask0 : 1; unsigned ka0702$v_mask1 : 1; unsigned ka0702$v_mask2 : 1; unsigned ka0702$v_mask3 : 1; unsigned ka0702$v_fill_1_ : 4; } ka0702$r_byte_mask_bits; } ka0702$r_byte_mask_overlay; } KA0702$R_KA0702_MASK_BITS; #if !defined(__VAXC) #define ka0702$v_mask0 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask0 #define ka0702$v_mask1 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask1 #define ka0702$v_mask2 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask2 #define ka0702$v_mask3 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask3 #endif /* #if !defined(__VAXC) */ /* The following definition defines an entry of a Saved Error Register Table. */ /* This table is pointed to by a cell in the Turbo ADP. The table is divided up */ /* into an entry for each slot. Each entry contains saved copies of IR, TCEREG, */ /* and FADR. The entries are written by the machine check handler on an error, and */ /* read by a driver (at some appropriate time) to determine if a TC error */ /* occurred. */ /* Define Saved Register Table Entry */ #define KA0702$M_SAVED_IR_SFB_INT 0x4 #define KA0702$M_SAVED_IR_SCSI_INT 0x8 #define KA0702$M_SAVED_IR_COREIO_INT 0x10 #define KA0702$M_SAVED_IR_BC_TPE 0x8000000 #define KA0702$M_SAVED_IR_TC_ORE 0x10000000 #define KA0702$M_SAVED_IR_TC_TOE 0x20000000 #define KA0702$M_SAVED_IR_BPE 0x40000000 #define KA0702$M_SAVED_IR_MPE 0x80000000 #define KA0702$K_SAVED_REG_ENTRY_SIZE 8 typedef struct _ka0702_saved_reg { __union { unsigned int ka0702$l_saved_ir; /* Interrupt reason */ __struct { unsigned ka0702$v_saved_ir_fill1 : 2; unsigned ka0702$v_saved_ir_sfb_int : 1; unsigned ka0702$v_saved_ir_scsi_int : 1; unsigned ka0702$v_saved_ir_coreio_int : 1; unsigned ka0702$v_saved_ir_fill2 : 22; unsigned ka0702$v_saved_ir_bc_tpe : 1; unsigned ka0702$v_saved_ir_tc_ore : 1; unsigned ka0702$v_saved_ir_tc_toe : 1; unsigned ka0702$v_saved_ir_bpe : 1; unsigned ka0702$v_saved_ir_mpe : 1; } ka0702$r_saved_ir_bits; } ka0702$r_saved_ir_overlay; unsigned int ka0702$l_fill; /* to quad boundary */ } KA0702_SAVED_REG; #if !defined(__VAXC) #define ka0702$l_saved_ir ka0702$r_saved_ir_overlay.ka0702$l_saved_ir #define ka0702$v_saved_ir_sfb_int ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_sfb_int #define ka0702$v_saved_ir_scsi_int ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_scsi_int #define ka0702$v_saved_ir_coreio_int ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_coreio_int #define ka0702$v_saved_ir_bc_tpe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_bc_tpe #define ka0702$v_saved_ir_tc_ore ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_tc_ore #define ka0702$v_saved_ir_tc_toe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_tc_toe #define ka0702$v_saved_ir_bpe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_bpe #define ka0702$v_saved_ir_mpe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_mpe #endif /* #if !defined(__VAXC) */ /* Define indexes into error table. Indexes are 0 thru 10. */ /* The count of the number of entries is 11. */ #define KA0702$K_SLOT0_INDEX 0 #define KA0702$K_SLOT1_INDEX 1 #define KA0702$K_SLOT2_INDEX 2 #define KA0702$K_SLOT3_INDEX 3 #define KA0702$K_SCSI_INDEX 4 #define KA0702$K_COREIO_INDEX 5 #define KA0702$K_CXTURBO_INDEX 6 #define KA0702$K_SAVED_REG_ENTRY_COUNT 7 #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __KA0702DEF_LOADED */