/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:03 by OpenVMS SDL EV3-3 */ /* Source: 15-MAR-1993 09:30:33 $1$DGA7274:[LIB_H.SRC]KA0402DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $KA0402DEF ***/ #ifndef __KA0402DEF_LOADED #define __KA0402DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define KA0402$M_IOSLOT_SLOT0_SG 0x1 #define KA0402$M_IOSLOT_SLOT0_BM 0x2 #define KA0402$M_IOSLOT_SLOT0_PE 0x4 #define KA0402$M_IOSLOT_SLOT1_SG 0x8 #define KA0402$M_IOSLOT_SLOT1_BM 0x10 #define KA0402$M_IOSLOT_SLOT1_PE 0x20 #define KA0402$M_IOSLOT_SLOT2_SG 0x40 #define KA0402$M_IOSLOT_SLOT2_BM 0x80 #define KA0402$M_IOSLOT_SLOT2_PE 0x100 #define KA0402$M_IOSLOT_SLOT3_SG 0x200 #define KA0402$M_IOSLOT_SLOT3_BM 0x400 #define KA0402$M_IOSLOT_SLOT3_PE 0x800 #define KA0402$M_IOSLOT_SLOT4_SG 0x1000 #define KA0402$M_IOSLOT_SLOT4_BM 0x2000 #define KA0402$M_IOSLOT_SLOT4_PE 0x4000 #define KA0402$M_IOSLOT_SLOT5_SG 0x8000 #define KA0402$M_IOSLOT_SLOT5_BM 0x10000 #define KA0402$M_IOSLOT_SLOT5_PE 0x20000 #define KA0402$M_IOSLOT_SLOT6_SG 0x40000 #define KA0402$M_IOSLOT_SLOT6_BM 0x80000 #define KA0402$M_IOSLOT_SLOT6_PE 0x100000 #define KA0402$M_IOSLOT_CORE_SG 0x200000 #define KA0402$M_IOSLOT_CORE_BM 0x400000 #define KA0402$M_IOSLOT_CORE_PE 0x800000 #define KA0402$M_IOSLOT_CXTURBO_SG 0x1000000 #define KA0402$M_IOSLOT_CXTURBO_BM 0x2000000 #define KA0402$M_IOSLOT_CXTURBO_PE 0x4000000 #define KA0402$M_IOSLOT_RM_BYTE0 0x8000000 #define KA0402$M_IOSLOT_RM_BYTE1 0x10000000 #define KA0402$M_IOSLOT_RM_BYTE2 0x20000000 #define KA0402$M_IOSLOT_RM_BYTE3 0x40000000 #define KA0402$M_IOSLOT_RM_VALID 0x80000000 #define KA0402$M_TCCONFIG_MAGIC 0x1F #define KA0402$M_TCCONFIG_PAGE_SIZE 0x100 #define KA0402$M_TCEREG_SLOT_ID 0xF #define KA0402$M_TCEREG_SG 0x10 #define KA0402$M_TCEREG_BM 0x20 #define KA0402$M_TCEREG_PE 0x40 #define KA0402$M_TCEREG_LOCK 0x80 #define KA0402$M_TCEREG_OFFSET 0x1F00 #define KA0402$M_TCEREG_SYNDROME 0x7F0000 #define KA0402$M_TCEREG_WM_BYTE0 0x1000000 #define KA0402$M_TCEREG_WM_BYTE1 0x2000000 #define KA0402$M_TCEREG_WM_BYTE2 0x4000000 #define KA0402$M_TCEREG_WM_BYTE3 0x8000000 #define KA0402$M_TCEREG_W 0x40000000 #define KA0402$M_TCEREG_D 0x80000000 #define KA0402$M_IR_TC_INT 0x1FF #define KA0402$M_IR_SEO 0x80000 #define KA0402$M_IR_DBF 0x100000 #define KA0402$M_IR_X2K 0x200000 #define KA0402$M_IR_TCR 0x400000 #define KA0402$M_IR_TPE 0x800000 #define KA0402$M_IR_TER 0x1000000 #define KA0402$M_IR_SBE 0x2000000 #define KA0402$M_IR_DBE 0x4000000 #define KA0402$M_IR_TO 0x8000000 #define KA0402$M_IR_TL 0x10000000 #define KA0402$M_IR_IA 0x20000000 #define KA0402$M_IR_NV 0x40000000 #define KA0402$M_IR_PE 0x80000000 #define KA0402$M_IC_TC_INT 0x1FF #define KA0402$M_IC_SEO 0x80000 #define KA0402$M_IC_DBF 0x100000 #define KA0402$M_IC_X2K 0x200000 #define KA0402$M_IC_TCR 0x400000 #define KA0402$M_IC_TPE 0x800000 #define KA0402$M_IC_TER 0x1000000 #define KA0402$M_IC_SBE 0x2000000 #define KA0402$M_IC_DBE 0x4000000 #define KA0402$M_IC_TO 0x8000000 #define KA0402$M_IC_TL 0x10000000 #define KA0402$M_IC_IA 0x20000000 #define KA0402$M_IC_NV 0x40000000 #define KA0402$M_IC_PE 0x80000000 #define KA0402$M_LDP_DMA_PA_LO 0xFFFE0 #define KA0402$M_LDP_DMA_PA_HI 0xFFF00000 #define KA0402$M_SCOMM_TR_DMA_PA 0xFFFFFFE0 #define KA0402$M_SCOMM_RC_DMA_PA 0xFFFFFFE0 #define KA0402$M_PRINTER_TR_DMA_PA 0xFFFFFFE0 #define KA0402$M_PRINTER_RC_DMA_PA 0xFFFFFFE0 #define KA0402$M_ISDN_TR_DMA_PA 0xFFFFFFE0 #define KA0402$M_ISDN_TR_BUF_DMA_PA 0xFFFFFFE0 #define KA0402$M_ISDN_RC_DMA_PA 0xFFFFFFE0 #define KA0402$M_ISDN_RC_BUF_DMA_PA 0xFFFFFFE0 #define KA0402$M_SSR_LEDS 0xFF #define KA0402$M_SSR_LANCE_RESET 0x100 #define KA0402$M_SSR_RTC_RESET 0x400 #define KA0402$M_SSR_SSC_RESET 0x800 #define KA0402$M_SSR_ISDN_RESET 0x1000 #define KA0402$M_SSR_10BASET_SEL 0x2000 #define KA0402$M_SSR_NI_LOOPBACK 0x4000 #define KA0402$M_SSR_TXDIS 0x8000 #define KA0402$M_SSR_LANCE_DMA_EN 0x10000 #define KA0402$M_SSR_ISDN_RC_DMA_EN 0x80000 #define KA0402$M_SSR_ISDN_TR_DMA_EN 0x100000 #define KA0402$M_SSR_PRINTER_RC_DMA_EN 0x10000000 #define KA0402$M_SSR_PRINTER_TR_DMA_EN 0x20000000 #define KA0402$M_SSR_COMM_RC_DMA_EN 0x40000000 #define KA0402$M_SSR_COMM_TR_DMA_EN 0x80000000 #define KA0402$M_SIR_HALT0 0x1 #define KA0402$M_SIR_HALT1 0x2 #define KA0402$M_SIR_ALT_CONSOLE 0x8 #define KA0402$M_SIR_SCC0_SI 0x40 #define KA0402$M_SIR_SCC1_SI 0x80 #define KA0402$M_SIR_NI_INTR 0x100 #define KA0402$M_SIR_ISDN_INTR 0x2000 #define KA0402$M_SIR_LANCE_DMA_RE 0x10000 #define KA0402$M_SIR_ISDN_DMA_MRE 0x100000 #define KA0402$M_SIR_ISDN_DMA_RC_INTR 0x200000 #define KA0402$M_SIR_ISDN_DMA_TR_INTR 0x400000 #define KA0402$M_SIR_PP_RC_DMA_OVR 0x1000000 #define KA0402$M_SIR_PP_RC_HP_INTR 0x2000000 #define KA0402$M_SIR_PP_TR_DMA_MRE 0x4000000 #define KA0402$M_SIR_PP_TR_PE_INTR 0x8000000 #define KA0402$M_SIR_COMM_RC_DMA_OVR 0x10000000 #define KA0402$M_SIR_COMM_RC_HP_INTR 0x20000000 #define KA0402$M_SIR_COMM_TR_DMA_MRE 0x40000000 #define KA0402$M_SIR_COMM_TR_PE_INTR 0x80000000 #define KA0402$M_SIMR_HALT0 0x1 #define KA0402$M_SIMR_HALT1 0x2 #define KA0402$M_SIMR_ALT_CONSOLE 0x8 #define KA0402$M_SIMR_SCC0_SI 0x40 #define KA0402$M_SIMR_SCC1_SI 0x80 #define KA0402$M_SIMR_NI_INTR 0x100 #define KA0402$M_SIMR_ISDN_INTR 0x2000 #define KA0402$M_SIMR_LANCE_DMA_RE 0x10000 #define KA0402$M_SIMR_ISDN_DMA_MRE 0x100000 #define KA0402$M_SIMR_ISDN_DMA_RC_INTR 0x200000 #define KA0402$M_SIMR_ISDN_DMA_TR_INTR 0x400000 #define KA0402$M_SIMR_PP_RC_DMA_OVR 0x1000000 #define KA0402$M_SIMR_PP_RC_HP_INTR 0x2000000 #define KA0402$M_SIMR_PP_TR_DMA_MRE 0x4000000 #define KA0402$M_SIMR_PP_TR_PE_INTR 0x8000000 #define KA0402$M_SIMR_COMM_RC_DMA_OVR 0x10000000 #define KA0402$M_SIMR_COMM_RC_HP_INTR 0x20000000 #define KA0402$M_SIMR_COMM_TR_DMA_MRE 0x40000000 #define KA0402$M_SIMR_COMM_TR_PE_INTR 0x80000000 #define KA0402$M_SADR_TC_ADDR 0x1FFFFE0 #define KA0402$M_ISDN_DATA_TR_DATA 0xFFFFFF #define KA0402$M_ISDN_DATA_RC_DATA 0xFFFFFF #define KA0402$M_LANCE_SLOT_CS 0xF #define KA0402$M_LANCE_SLOT_HW_ADDR 0x3F0 #define KA0402$M_SCC0_SLOT_CS 0xF #define KA0402$M_SCC0_SLOT_HW_ADDR 0x3F0 #define KA0402$M_SCC1_SLOT_CS 0xF #define KA0402$M_SCC1_SLOT_HW_ADDR 0x3F0 #define KA0402$S_KA0402DEF 434176 /* Old KA0402 size for compatibility */ typedef struct _ka0402 { __union { void *ka0402$l_ioslot; /* Slot mode register */ __struct { unsigned ka0402$v_ioslot_slot0_sg : 1; unsigned ka0402$v_ioslot_slot0_bm : 1; unsigned ka0402$v_ioslot_slot0_pe : 1; unsigned ka0402$v_ioslot_slot1_sg : 1; unsigned ka0402$v_ioslot_slot1_bm : 1; unsigned ka0402$v_ioslot_slot1_pe : 1; unsigned ka0402$v_ioslot_slot2_sg : 1; unsigned ka0402$v_ioslot_slot2_bm : 1; unsigned ka0402$v_ioslot_slot2_pe : 1; unsigned ka0402$v_ioslot_slot3_sg : 1; unsigned ka0402$v_ioslot_slot3_bm : 1; unsigned ka0402$v_ioslot_slot3_pe : 1; unsigned ka0402$v_ioslot_slot4_sg : 1; unsigned ka0402$v_ioslot_slot4_bm : 1; unsigned ka0402$v_ioslot_slot4_pe : 1; unsigned ka0402$v_ioslot_slot5_sg : 1; unsigned ka0402$v_ioslot_slot5_bm : 1; unsigned ka0402$v_ioslot_slot5_pe : 1; unsigned ka0402$v_ioslot_slot6_sg : 1; unsigned ka0402$v_ioslot_slot6_bm : 1; unsigned ka0402$v_ioslot_slot6_pe : 1; unsigned ka0402$v_ioslot_core_sg : 1; unsigned ka0402$v_ioslot_core_bm : 1; unsigned ka0402$v_ioslot_core_pe : 1; unsigned ka0402$v_ioslot_cxturbo_sg : 1; unsigned ka0402$v_ioslot_cxturbo_bm : 1; unsigned ka0402$v_ioslot_cxturbo_pe : 1; unsigned ka0402$v_ioslot_rm_byte0 : 1; unsigned ka0402$v_ioslot_rm_byte1 : 1; unsigned ka0402$v_ioslot_rm_byte2 : 1; unsigned ka0402$v_ioslot_rm_byte3 : 1; unsigned ka0402$v_ioslot_rm_valid : 1; } ka0402$r_ioslot_bits; } ka0402$r_ioslot_overlay; unsigned char ka0402$b_fill390 [12]; __union { void *ka0402$l_tcconfig; /* TC Configuration register */ __struct { unsigned ka0402$v_tcconfig_magic : 5; unsigned ka0402$v_tcconfig_fill1 : 3; unsigned ka0402$v_tcconfig_page_size : 1; unsigned ka0402$v_tcconfig_fill : 23; } ka0402$r_tcconfig_bits; } ka0402$r_tcconfig_overlay; unsigned char ka0402$b_fill400 [12]; void *ka0402$l_fadr; /* Failing Address register */ unsigned char ka0402$b_fill410 [12]; __union { void *ka0402$l_tcereg; /* Error register */ __struct { unsigned ka0402$v_tcereg_slot_id : 4; unsigned ka0402$v_tcereg_sg : 1; unsigned ka0402$v_tcereg_bm : 1; unsigned ka0402$v_tcereg_pe : 1; unsigned ka0402$v_tcereg_lock : 1; unsigned ka0402$v_tcereg_offset : 5; unsigned ka0402$v_tcereg_fill2 : 3; unsigned ka0402$v_tcereg_syndrome : 7; unsigned ka0402$v_tcereg_fill3 : 1; unsigned ka0402$v_tcereg_wm_byte0 : 1; unsigned ka0402$v_tcereg_wm_byte1 : 1; unsigned ka0402$v_tcereg_wm_byte2 : 1; unsigned ka0402$v_tcereg_wm_byte3 : 1; unsigned ka0402$v_tcereg_fill4 : 2; unsigned ka0402$v_tcereg_w : 1; unsigned ka0402$v_tcereg_d : 1; } ka0402$r_tcereg_bits; } ka0402$r_tcereg_overlay; unsigned char ka0402$b_fill420 [8140]; void *ka0402$l_mcr0; /* Memory configuration 0 */ unsigned char ka0402$b_fill430 [8188]; void *ka0402$l_mcr1; /* Memory configuration 1 */ unsigned char ka0402$b_fill440 [8188]; void *ka0402$l_mcr2; /* Memory configuration 2 */ unsigned char ka0402$b_fill450 [8188]; void *ka0402$l_mcr3; /* Memory configuration 3 */ unsigned char ka0402$b_fill460 [8188]; void *ka0402$l_mcr4; /* Memory configuration 4 */ unsigned char ka0402$b_fill470 [8188]; void *ka0402$l_mcr5; /* Memory configuration 5 */ unsigned char ka0402$b_fill480 [8188]; void *ka0402$l_mcr6; /* Memory configuration 6 */ unsigned char ka0402$b_fill490 [8188]; void *ka0402$l_mcr7; /* Memory configuration 7 */ unsigned char ka0402$b_fill500 [8188]; __union { void *ka0402$l_ir; /* Interrupt register */ __struct { unsigned ka0402$v_ir_tc_int : 9; unsigned ka0402$v_ir_fill1 : 10; unsigned ka0402$v_ir_seo : 1; unsigned ka0402$v_ir_dbf : 1; unsigned ka0402$v_ir_x2k : 1; unsigned ka0402$v_ir_tcr : 1; unsigned ka0402$v_ir_tpe : 1; unsigned ka0402$v_ir_ter : 1; unsigned ka0402$v_ir_sbe : 1; unsigned ka0402$v_ir_dbe : 1; unsigned ka0402$v_ir_to : 1; unsigned ka0402$v_ir_tl : 1; unsigned ka0402$v_ir_ia : 1; unsigned ka0402$v_ir_nv : 1; unsigned ka0402$v_ir_pe : 1; } ka0402$r_ir_bits; } ka0402$r_ir_overlay; unsigned char ka0402$b_fill510 [8188]; __union { void *ka0402$l_ic; /* Interrupt Cause register */ __struct { unsigned ka0402$v_ic_tc_int : 9; unsigned ka0402$v_ic_fill1 : 10; unsigned ka0402$v_ic_seo : 1; unsigned ka0402$v_ic_dbf : 1; unsigned ka0402$v_ic_x2k : 1; unsigned ka0402$v_ic_tcr : 1; unsigned ka0402$v_ic_tpe : 1; unsigned ka0402$v_ic_ter : 1; unsigned ka0402$v_ic_sbe : 1; unsigned ka0402$v_ic_dbe : 1; unsigned ka0402$v_ic_to : 1; unsigned ka0402$v_ic_tl : 1; unsigned ka0402$v_ic_ia : 1; unsigned ka0402$v_ic_nv : 1; unsigned ka0402$v_ic_pe : 1; } ka0402$r_ic_bits; } ka0402$r_ic_overlay; unsigned char ka0402$b_fill520 [8188]; void *ka0402$l_sg_map; /* Scatter/gather map (32 pages) */ unsigned char ka0402$b_fill530 [262140]; void *ka0402$l_tcreset; /* TC reset register */ unsigned char ka0402$b_fill540 [8188]; void *ka0402$l_ioctl_csr; /* Core I/O base CSR address */ unsigned char ka0402$b_fill560 [60]; __union { void *ka0402$l_ldp; /* Ethernet Lance DMA pointer */ __struct { unsigned ka0402$v_ldp_fill1 : 5; unsigned ka0402$v_ldp_dma_pa_lo : 15; unsigned ka0402$v_ldp_dma_pa_hi : 12; } ka0402$r_ldp_bits; } ka0402$r_ldp_overlay; unsigned char ka0402$b_fill570 [28]; __union { void *ka0402$l_scomm_tr; /* Serial comm transmit port 1 DMA pointer */ __struct { unsigned ka0402$v_scomm_tr_fill1 : 5; unsigned ka0402$v_scomm_tr_dma_pa : 27; } ka0402$r_scomm_tr_bits; } ka0402$r_scomm_tr_overlay; unsigned char ka0402$b_fill580 [28]; __union { void *ka0402$l_scomm_rc; /* Serial comm receive port 1 DMA pointer */ __struct { unsigned ka0402$v_scomm_rc_fill1 : 5; unsigned ka0402$v_scomm_rc_dma_pa : 27; } ka0402$r_scomm_rc_bits; } ka0402$r_scomm_rc_overlay; unsigned char ka0402$b_fill590 [28]; __union { void *ka0402$l_printer_tr; /* Printer transmit port DMA pointer */ __struct { unsigned ka0402$v_printer_tr_fill1 : 5; unsigned ka0402$v_printer_tr_dma_pa : 27; } ka0402$r_printer_tr_bits; } ka0402$r_printer_tr_overlay; unsigned char ka0402$b_fill600 [28]; __union { void *ka0402$l_printer_rc; /* Printer receive port DMA pointer */ __struct { unsigned ka0402$v_printer_rc_fill1 : 5; unsigned ka0402$v_printer_rc_dma_pa : 27; } ka0402$r_printer_rc_bits; } ka0402$r_printer_rc_overlay; unsigned char ka0402$b_fill610 [60]; __union { void *ka0402$l_isdn_tr; /* ISDN transmit DMA pointer */ __struct { unsigned ka0402$v_isdn_tr_fill1 : 5; unsigned ka0402$v_isdn_tr_dma_pa : 27; } ka0402$r_isdn_tr_bits; } ka0402$r_isdn_tr_overlay; unsigned char ka0402$b_fill620 [28]; __union { void *ka0402$l_isdn_tr_buf; /* ISDN transmit DMA buffer pointer */ __struct { unsigned ka0402$v_isdn_tr_buf_fill1 : 5; unsigned ka0402$v_isdn_tr_buf_dma_pa : 27; } ka0402$r_isdn_tr_buf_bits; } ka0402$r_isdn_tr_buf_overlay; unsigned char ka0402$b_fill630 [28]; __union { void *ka0402$l_isdn_rc; /* ISDN receive DMA pointer */ __struct { unsigned ka0402$v_isdn_rc_fill1 : 5; unsigned ka0402$v_isdn_rc_dma_pa : 27; } ka0402$r_isdn_rc_bits; } ka0402$r_isdn_rc_overlay; unsigned char ka0402$b_fill640 [28]; __union { void *ka0402$l_isdn_rc_buf; /* ISDN receive DMA buffer pointer */ __struct { unsigned ka0402$v_isdn_rc_buf_fill1 : 5; unsigned ka0402$v_isdn_rc_buf_dma_pa : 27; } ka0402$r_isdn_rc_buf_bits; } ka0402$r_isdn_rc_buf_overlay; unsigned char ka0402$b_fill650 [28]; void *ka0402$l_data0; /* System Data Buffer 0 */ unsigned char ka0402$b_fill660 [28]; void *ka0402$l_data1; /* System Data Buffer 1 */ unsigned char ka0402$b_fill670 [28]; void *ka0402$l_data2; /* System Data Buffer 2 */ unsigned char ka0402$b_fill680 [28]; void *ka0402$l_data3; /* System Data Buffer 3 */ unsigned char ka0402$b_fill690 [28]; __union { void *ka0402$l_ssr; /* System support register */ __struct { unsigned ka0402$v_ssr_leds : 8; unsigned ka0402$v_ssr_lance_reset : 1; unsigned ka0402$v_ssr_fill1 : 1; unsigned ka0402$v_ssr_rtc_reset : 1; unsigned ka0402$v_ssr_ssc_reset : 1; unsigned ka0402$v_ssr_isdn_reset : 1; unsigned ka0402$v_ssr_10baset_sel : 1; unsigned ka0402$v_ssr_ni_loopback : 1; unsigned ka0402$v_ssr_txdis : 1; unsigned ka0402$v_ssr_lance_dma_en : 1; unsigned ka0402$v_ssr_fill3 : 2; unsigned ka0402$v_ssr_isdn_rc_dma_en : 1; unsigned ka0402$v_ssr_isdn_tr_dma_en : 1; unsigned ka0402$v_ssr_fill4 : 2; unsigned ka0402$v_ssr_fill5 : 5; unsigned ka0402$v_ssr_printer_rc_dma_en : 1; unsigned ka0402$v_ssr_printer_tr_dma_en : 1; unsigned ka0402$v_ssr_comm_rc_dma_en : 1; unsigned ka0402$v_ssr_comm_tr_dma_en : 1; } ka0402$r_ssr_bits; } ka0402$r_ssr_overlay; unsigned char ka0402$b_fill700 [28]; __union { void *ka0402$l_sir; /* System interrupt register */ __struct { unsigned ka0402$v_sir_halt0 : 1; unsigned ka0402$v_sir_halt1 : 1; unsigned ka0402$v_sir_fill1 : 1; unsigned ka0402$v_sir_alt_console : 1; unsigned ka0402$v_sir_fill2 : 2; unsigned ka0402$v_sir_scc0_si : 1; unsigned ka0402$v_sir_scc1_si : 1; unsigned ka0402$v_sir_ni_intr : 1; unsigned ka0402$v_sir_fill3 : 4; unsigned ka0402$v_sir_isdn_intr : 1; unsigned ka0402$v_sir_fill4 : 2; unsigned ka0402$v_sir_lance_dma_re : 1; unsigned ka0402$v_sir_fill5 : 3; unsigned ka0402$v_sir_isdn_dma_mre : 1; unsigned ka0402$v_sir_isdn_dma_rc_intr : 1; unsigned ka0402$v_sir_isdn_dma_tr_intr : 1; unsigned ka0402$v_sir_fill6 : 1; unsigned ka0402$v_sir_pp_rc_dma_ovr : 1; unsigned ka0402$v_sir_pp_rc_hp_intr : 1; unsigned ka0402$v_sir_pp_tr_dma_mre : 1; unsigned ka0402$v_sir_pp_tr_pe_intr : 1; unsigned ka0402$v_sir_comm_rc_dma_ovr : 1; unsigned ka0402$v_sir_comm_rc_hp_intr : 1; unsigned ka0402$v_sir_comm_tr_dma_mre : 1; unsigned ka0402$v_sir_comm_tr_pe_intr : 1; } ka0402$r_sir_bits; } ka0402$r_sir_overlay; unsigned char ka0402$b_fill710 [28]; __union { void *ka0402$l_simr; /* System interrupt mask register */ __struct { unsigned ka0402$v_simr_halt0 : 1; unsigned ka0402$v_simr_halt1 : 1; unsigned ka0402$v_simr_fill1 : 1; unsigned ka0402$v_simr_alt_console : 1; unsigned ka0402$v_simr_fill2 : 2; unsigned ka0402$v_simr_scc0_si : 1; unsigned ka0402$v_simr_scc1_si : 1; unsigned ka0402$v_simr_ni_intr : 1; unsigned ka0402$v_simr_fill3 : 4; unsigned ka0402$v_simr_isdn_intr : 1; unsigned ka0402$v_simr_fill4 : 2; unsigned ka0402$v_simr_lance_dma_re : 1; unsigned ka0402$v_simr_fill5 : 3; unsigned ka0402$v_simr_isdn_dma_mre : 1; unsigned ka0402$v_simr_isdn_dma_rc_intr : 1; unsigned ka0402$v_simr_isdn_dma_tr_intr : 1; unsigned ka0402$v_simr_fill6 : 1; unsigned ka0402$v_simr_pp_rc_dma_ovr : 1; unsigned ka0402$v_simr_pp_rc_hp_intr : 1; unsigned ka0402$v_simr_pp_tr_dma_mre : 1; unsigned ka0402$v_simr_pp_tr_pe_intr : 1; unsigned ka0402$v_simr_comm_rc_dma_ovr : 1; unsigned ka0402$v_simr_comm_rc_hp_intr : 1; unsigned ka0402$v_simr_comm_tr_dma_mre : 1; unsigned ka0402$v_simr_comm_tr_pe_intr : 1; } ka0402$r_simr_bits; } ka0402$r_simr_overlay; unsigned char ka0402$b_fill720 [28]; __union { void *ka0402$l_sadr; /* System address register */ __struct { unsigned ka0402$v_sadr_fill1 : 5; unsigned ka0402$v_sadr_tc_addr : 20; unsigned ka0402$v_sadr_fill2 : 7; } ka0402$r_sadr_bits; } ka0402$r_sadr_overlay; unsigned char ka0402$b_fill730 [28]; __union { void *ka0402$l_isdn_data_tr; /* ISDN Data Transmit */ __struct { unsigned ka0402$v_isdn_data_tr_data : 24; unsigned ka0402$v_isdn_data_tr_fill : 8; } ka0402$r_isdn_data_tr_bits; } ka0402$r_isdn_data_tr_overlay; unsigned char ka0402$b_fill740 [28]; __union { void *ka0402$l_isdn_data_rc; /* ISDN Data Receive */ __struct { unsigned ka0402$v_isdn_data_rc_data : 24; unsigned ka0402$v_isdn_data_rc_fill : 8; } ka0402$r_isdn_data_rc_bits; } ka0402$r_isdn_data_rc_overlay; unsigned char ka0402$b_fill750 [28]; __union { void *ka0402$l_lance_slot; /* Lance slot register */ __struct { unsigned ka0402$v_lance_slot_cs : 4; unsigned ka0402$v_lance_slot_hw_addr : 6; unsigned ka0402$v_lance_slot_fill : 22; } ka0402$r_lance_slot_bits; } ka0402$r_lance_slot_overlay; unsigned char ka0402$b_fill760 [60]; __union { void *ka0402$l_scc0_slot; /* SCC0 slot register */ __struct { unsigned ka0402$v_scc0_slot_cs : 4; unsigned ka0402$v_scc0_slot_hw_addr : 6; unsigned ka0402$v_scc0_slot_fill : 22; } ka0402$r_scc0_slot_bits; } ka0402$r_scc0_slot_overlay; unsigned char ka0402$b_fill770 [28]; __union { void *ka0402$l_scc1_slot; /* SCC1 slot register */ __struct { unsigned ka0402$v_scc1_slot_cs : 4; unsigned ka0402$v_scc1_slot_hw_addr : 6; unsigned ka0402$v_scc1_slot_fill : 22; } ka0402$r_scc1_slot_bits; } ka0402$r_scc1_slot_overlay; unsigned char ka0402$b_fill780 [7388]; void *ka0402$l_ni_adr_rom; /* Ethernet address ROM */ unsigned char ka0402$b_fill790 [8188]; void *ka0402$l_lance_rdp; /* Lance ethernet CSR */ unsigned char ka0402$b_fill800 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_lance_rap; /* Lance ethernet CSR */ unsigned char ka0402$b_fill810 [8180]; void *ka0402$l_scc0b_comm_rap; /* Comm Port 1 RAP */ unsigned char ka0402$b_fill820 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_scc0b_comm_data; /* Comm Port 1 data */ unsigned char ka0402$b_fill830 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_scc0a_mouse_rap; /* Mouse RAP */ unsigned char ka0402$b_fill840 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_scc0a_mouse_data; /* Mouse port data register */ unsigned char ka0402$b_fill850 [8164]; void *ka0402$l_scc1b_print_rap; /* Printer Port 2 RAP */ unsigned char ka0402$b_fill860 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_scc1b_print_data; /* Printer Port 2 data */ unsigned char ka0402$b_fill870 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_scc1a_key_rap; /* Keyboard RAP */ unsigned char ka0402$b_fill880 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_scc1a_key_data; /* Keyboard port data register */ unsigned char ka0402$b_fill890 [8164]; void *ka0402$l_rtc_sec; /* TOY clock CSR--seconds */ unsigned char ka0402$b_fill900 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_alms; /* TOY clock CSR--seconds alarm */ unsigned char ka0402$b_fill910 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_min; /* TOY clock CSR--minutes */ unsigned char ka0402$b_fill920 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_almn; /* TOY clock CSR--minutes alarm */ unsigned char ka0402$b_fill930 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_hour; /* TOY clock CSR--hours */ unsigned char ka0402$b_fill940 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_almh; /* TOY clock CSR--hours alarm */ unsigned char ka0402$b_fill950 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_dow; /* TOY clock CSR--day of week */ unsigned char ka0402$b_fill960 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_day; /* TOY clock CSR--date of month */ unsigned char ka0402$b_fill970 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_mon; /* TOY clock CSR--month */ unsigned char ka0402$b_fill980 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_year; /* TOY clock CSR--year */ unsigned char ka0402$b_fill990 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_rega; /* TOY clock CSR--register A */ unsigned char ka0402$b_fill1000 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_regb; /* TOY clock CSR--register B */ unsigned char ka0402$b_fill1010 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_regc; /* TOY clock CSR--register C */ unsigned char ka0402$b_fill1020 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_regd; /* TOY clock CSR--register D */ unsigned char ka0402$b_fill1030 [4]; /* Fill to allow sparse space byte mask */ void *ka0402$l_rtc_ram; /* TOY clock CSR--base of BBU RAM */ unsigned char ka0402$b_fill1035 [260]; /* Fill to SCSO HOST ID location */ unsigned int ka0402$l_scsi_host_id; /* SCSI Host id for use by PKCDRIVER. */ unsigned char ka0402$b_fill1040 [7812]; void *ka0402$l_isdn_audio; /* ISDN audio chip CSR */ unsigned char ka0402$b_fill1050 [8188]; /* Fill to page boundary */ unsigned int ka0402$l_imask_read; /* Interrupt mask, read */ unsigned char ka0402$b_fill1060 [8188]; /* Fill to page boundary */ unsigned char ka0402$b_fill1065 [8188]; /* Fill to last lw in page */ unsigned int ka0402$l_imask_write; /* Interrupt mask, write */ } KA0402; #if !defined(__VAXC) #define ka0402$l_ioslot ka0402$r_ioslot_overlay.ka0402$l_ioslot #define ka0402$v_ioslot_slot0_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot0_sg #define ka0402$v_ioslot_slot0_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot0_bm #define ka0402$v_ioslot_slot0_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot0_pe #define ka0402$v_ioslot_slot1_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot1_sg #define ka0402$v_ioslot_slot1_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot1_bm #define ka0402$v_ioslot_slot1_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot1_pe #define ka0402$v_ioslot_slot2_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot2_sg #define ka0402$v_ioslot_slot2_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot2_bm #define ka0402$v_ioslot_slot2_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot2_pe #define ka0402$v_ioslot_slot3_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot3_sg #define ka0402$v_ioslot_slot3_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot3_bm #define ka0402$v_ioslot_slot3_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot3_pe #define ka0402$v_ioslot_slot4_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot4_sg #define ka0402$v_ioslot_slot4_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot4_bm #define ka0402$v_ioslot_slot4_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot4_pe #define ka0402$v_ioslot_slot5_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot5_sg #define ka0402$v_ioslot_slot5_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot5_bm #define ka0402$v_ioslot_slot5_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot5_pe #define ka0402$v_ioslot_slot6_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot6_sg #define ka0402$v_ioslot_slot6_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot6_bm #define ka0402$v_ioslot_slot6_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot6_pe #define ka0402$v_ioslot_core_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_core_sg #define ka0402$v_ioslot_core_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_core_bm #define ka0402$v_ioslot_core_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_core_pe #define ka0402$v_ioslot_cxturbo_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_cxturbo_sg #define ka0402$v_ioslot_cxturbo_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_cxturbo_bm #define ka0402$v_ioslot_cxturbo_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_cxturbo_pe #define ka0402$v_ioslot_rm_byte0 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte0 #define ka0402$v_ioslot_rm_byte1 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte1 #define ka0402$v_ioslot_rm_byte2 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte2 #define ka0402$v_ioslot_rm_byte3 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte3 #define ka0402$v_ioslot_rm_valid ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_valid #define ka0402$l_tcconfig ka0402$r_tcconfig_overlay.ka0402$l_tcconfig #define ka0402$v_tcconfig_magic ka0402$r_tcconfig_overlay.ka0402$r_tcconfig_bits.ka0402$v_tcconfig_magic #define ka0402$v_tcconfig_page_size ka0402$r_tcconfig_overlay.ka0402$r_tcconfig_bits.ka0402$v_tcconfig_page_size #define ka0402$l_tcereg ka0402$r_tcereg_overlay.ka0402$l_tcereg #define ka0402$v_tcereg_slot_id ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_slot_id #define ka0402$v_tcereg_sg ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_sg #define ka0402$v_tcereg_bm ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_bm #define ka0402$v_tcereg_pe ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_pe #define ka0402$v_tcereg_lock ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_lock #define ka0402$v_tcereg_offset ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_offset #define ka0402$v_tcereg_syndrome ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_syndrome #define ka0402$v_tcereg_wm_byte0 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte0 #define ka0402$v_tcereg_wm_byte1 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte1 #define ka0402$v_tcereg_wm_byte2 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte2 #define ka0402$v_tcereg_wm_byte3 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte3 #define ka0402$v_tcereg_w ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_w #define ka0402$v_tcereg_d ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_d #define ka0402$l_ir ka0402$r_ir_overlay.ka0402$l_ir #define ka0402$v_ir_tc_int ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tc_int #define ka0402$v_ir_seo ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_seo #define ka0402$v_ir_dbf ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_dbf #define ka0402$v_ir_x2k ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_x2k #define ka0402$v_ir_tcr ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tcr #define ka0402$v_ir_tpe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tpe #define ka0402$v_ir_ter ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_ter #define ka0402$v_ir_sbe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_sbe #define ka0402$v_ir_dbe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_dbe #define ka0402$v_ir_to ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_to #define ka0402$v_ir_tl ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tl #define ka0402$v_ir_ia ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_ia #define ka0402$v_ir_nv ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_nv #define ka0402$v_ir_pe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_pe #define ka0402$l_ic ka0402$r_ic_overlay.ka0402$l_ic #define ka0402$v_ic_tc_int ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tc_int #define ka0402$v_ic_seo ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_seo #define ka0402$v_ic_dbf ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_dbf #define ka0402$v_ic_x2k ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_x2k #define ka0402$v_ic_tcr ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tcr #define ka0402$v_ic_tpe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tpe #define ka0402$v_ic_ter ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_ter #define ka0402$v_ic_sbe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_sbe #define ka0402$v_ic_dbe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_dbe #define ka0402$v_ic_to ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_to #define ka0402$v_ic_tl ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tl #define ka0402$v_ic_ia ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_ia #define ka0402$v_ic_nv ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_nv #define ka0402$v_ic_pe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_pe #define ka0402$l_ldp ka0402$r_ldp_overlay.ka0402$l_ldp #define ka0402$v_ldp_dma_pa_lo ka0402$r_ldp_overlay.ka0402$r_ldp_bits.ka0402$v_ldp_dma_pa_lo #define ka0402$v_ldp_dma_pa_hi ka0402$r_ldp_overlay.ka0402$r_ldp_bits.ka0402$v_ldp_dma_pa_hi #define ka0402$l_scomm_tr ka0402$r_scomm_tr_overlay.ka0402$l_scomm_tr #define ka0402$v_scomm_tr_dma_pa ka0402$r_scomm_tr_overlay.ka0402$r_scomm_tr_bits.ka0402$v_scomm_tr_dma_pa #define ka0402$l_scomm_rc ka0402$r_scomm_rc_overlay.ka0402$l_scomm_rc #define ka0402$v_scomm_rc_dma_pa ka0402$r_scomm_rc_overlay.ka0402$r_scomm_rc_bits.ka0402$v_scomm_rc_dma_pa #define ka0402$l_printer_tr ka0402$r_printer_tr_overlay.ka0402$l_printer_tr #define ka0402$v_printer_tr_dma_pa ka0402$r_printer_tr_overlay.ka0402$r_printer_tr_bits.ka0402$v_printer_tr_dma_pa #define ka0402$l_printer_rc ka0402$r_printer_rc_overlay.ka0402$l_printer_rc #define ka0402$v_printer_rc_dma_pa ka0402$r_printer_rc_overlay.ka0402$r_printer_rc_bits.ka0402$v_printer_rc_dma_pa #define ka0402$l_isdn_tr ka0402$r_isdn_tr_overlay.ka0402$l_isdn_tr #define ka0402$v_isdn_tr_dma_pa ka0402$r_isdn_tr_overlay.ka0402$r_isdn_tr_bits.ka0402$v_isdn_tr_dma_pa #define ka0402$l_isdn_tr_buf ka0402$r_isdn_tr_buf_overlay.ka0402$l_isdn_tr_buf #define ka0402$v_isdn_tr_buf_dma_pa ka0402$r_isdn_tr_buf_overlay.ka0402$r_isdn_tr_buf_bits.ka0402$v_isdn_tr_buf_dma_pa #define ka0402$l_isdn_rc ka0402$r_isdn_rc_overlay.ka0402$l_isdn_rc #define ka0402$v_isdn_rc_dma_pa ka0402$r_isdn_rc_overlay.ka0402$r_isdn_rc_bits.ka0402$v_isdn_rc_dma_pa #define ka0402$l_isdn_rc_buf ka0402$r_isdn_rc_buf_overlay.ka0402$l_isdn_rc_buf #define ka0402$v_isdn_rc_buf_dma_pa ka0402$r_isdn_rc_buf_overlay.ka0402$r_isdn_rc_buf_bits.ka0402$v_isdn_rc_buf_dma_pa #define ka0402$l_ssr ka0402$r_ssr_overlay.ka0402$l_ssr #define ka0402$v_ssr_leds ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_leds #define ka0402$v_ssr_lance_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_lance_reset #define ka0402$v_ssr_rtc_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_rtc_reset #define ka0402$v_ssr_ssc_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_ssc_reset #define ka0402$v_ssr_isdn_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_isdn_reset #define ka0402$v_ssr_10baset_sel ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_10baset_sel #define ka0402$v_ssr_ni_loopback ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_ni_loopback #define ka0402$v_ssr_txdis ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_txdis #define ka0402$v_ssr_lance_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_lance_dma_en #define ka0402$v_ssr_isdn_rc_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_isdn_rc_dma_en #define ka0402$v_ssr_isdn_tr_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_isdn_tr_dma_en #define ka0402$v_ssr_printer_rc_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_printer_rc_dma_en #define ka0402$v_ssr_printer_tr_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_printer_tr_dma_en #define ka0402$v_ssr_comm_rc_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_comm_rc_dma_en #define ka0402$v_ssr_comm_tr_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_comm_tr_dma_en #define ka0402$l_sir ka0402$r_sir_overlay.ka0402$l_sir #define ka0402$v_sir_halt0 ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_halt0 #define ka0402$v_sir_halt1 ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_halt1 #define ka0402$v_sir_alt_console ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_alt_console #define ka0402$v_sir_scc0_si ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_scc0_si #define ka0402$v_sir_scc1_si ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_scc1_si #define ka0402$v_sir_ni_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_ni_intr #define ka0402$v_sir_isdn_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_intr #define ka0402$v_sir_lance_dma_re ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_lance_dma_re #define ka0402$v_sir_isdn_dma_mre ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_dma_mre #define ka0402$v_sir_isdn_dma_rc_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_dma_rc_intr #define ka0402$v_sir_isdn_dma_tr_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_dma_tr_intr #define ka0402$v_sir_pp_rc_dma_ovr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_rc_dma_ovr #define ka0402$v_sir_pp_rc_hp_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_rc_hp_intr #define ka0402$v_sir_pp_tr_dma_mre ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_tr_dma_mre #define ka0402$v_sir_pp_tr_pe_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_tr_pe_intr #define ka0402$v_sir_comm_rc_dma_ovr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_rc_dma_ovr #define ka0402$v_sir_comm_rc_hp_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_rc_hp_intr #define ka0402$v_sir_comm_tr_dma_mre ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_tr_dma_mre #define ka0402$v_sir_comm_tr_pe_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_tr_pe_intr #define ka0402$l_simr ka0402$r_simr_overlay.ka0402$l_simr #define ka0402$v_simr_halt0 ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_halt0 #define ka0402$v_simr_halt1 ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_halt1 #define ka0402$v_simr_alt_console ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_alt_console #define ka0402$v_simr_scc0_si ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_scc0_si #define ka0402$v_simr_scc1_si ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_scc1_si #define ka0402$v_simr_ni_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_ni_intr #define ka0402$v_simr_isdn_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_intr #define ka0402$v_simr_lance_dma_re ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_lance_dma_re #define ka0402$v_simr_isdn_dma_mre ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_dma_mre #define ka0402$v_simr_isdn_dma_rc_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_dma_rc_intr #define ka0402$v_simr_isdn_dma_tr_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_dma_tr_intr #define ka0402$v_simr_pp_rc_dma_ovr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_rc_dma_ovr #define ka0402$v_simr_pp_rc_hp_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_rc_hp_intr #define ka0402$v_simr_pp_tr_dma_mre ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_tr_dma_mre #define ka0402$v_simr_pp_tr_pe_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_tr_pe_intr #define ka0402$v_simr_comm_rc_dma_ovr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_rc_dma_ovr #define ka0402$v_simr_comm_rc_hp_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_rc_hp_intr #define ka0402$v_simr_comm_tr_dma_mre ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_tr_dma_mre #define ka0402$v_simr_comm_tr_pe_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_tr_pe_intr #define ka0402$l_sadr ka0402$r_sadr_overlay.ka0402$l_sadr #define ka0402$v_sadr_tc_addr ka0402$r_sadr_overlay.ka0402$r_sadr_bits.ka0402$v_sadr_tc_addr #define ka0402$l_isdn_data_tr ka0402$r_isdn_data_tr_overlay.ka0402$l_isdn_data_tr #define ka0402$v_isdn_data_tr_data ka0402$r_isdn_data_tr_overlay.ka0402$r_isdn_data_tr_bits.ka0402$v_isdn_data_tr_data #define ka0402$l_isdn_data_rc ka0402$r_isdn_data_rc_overlay.ka0402$l_isdn_data_rc #define ka0402$v_isdn_data_rc_data ka0402$r_isdn_data_rc_overlay.ka0402$r_isdn_data_rc_bits.ka0402$v_isdn_data_rc_data #define ka0402$l_lance_slot ka0402$r_lance_slot_overlay.ka0402$l_lance_slot #define ka0402$v_lance_slot_cs ka0402$r_lance_slot_overlay.ka0402$r_lance_slot_bits.ka0402$v_lance_slot_cs #define ka0402$v_lance_slot_hw_addr ka0402$r_lance_slot_overlay.ka0402$r_lance_slot_bits.ka0402$v_lance_slot_hw_addr #define ka0402$l_scc0_slot ka0402$r_scc0_slot_overlay.ka0402$l_scc0_slot #define ka0402$v_scc0_slot_cs ka0402$r_scc0_slot_overlay.ka0402$r_scc0_slot_bits.ka0402$v_scc0_slot_cs #define ka0402$v_scc0_slot_hw_addr ka0402$r_scc0_slot_overlay.ka0402$r_scc0_slot_bits.ka0402$v_scc0_slot_hw_addr #define ka0402$l_scc1_slot ka0402$r_scc1_slot_overlay.ka0402$l_scc1_slot #define ka0402$v_scc1_slot_cs ka0402$r_scc1_slot_overlay.ka0402$r_scc1_slot_bits.ka0402$v_scc1_slot_cs #define ka0402$v_scc1_slot_hw_addr ka0402$r_scc1_slot_overlay.ka0402$r_scc1_slot_bits.ka0402$v_scc1_slot_hw_addr #endif /* #if !defined(__VAXC) */ #define KA0402$M_SG_MAP_PPN 0x1FFFFF #define KA0402$M_SG_MAP_P 0x200000 #define KA0402$M_SG_MAP_F 0x400000 #define KA0402$M_SG_MAP_V 0x800000 typedef struct _ka0402$r_sg_map_entry_bits { __union { __struct { unsigned ka0402$v_sg_map_ppn : 21; unsigned ka0402$v_sg_map_p : 1; unsigned ka0402$v_sg_map_f : 1; unsigned ka0402$v_sg_map_v : 1; } ka0402$r_sg_map_entry_bits; } ka0402$r_sg_map_entry_overlay; } KA0402$R_SG_MAP_ENTRY_BITS; #if !defined(__VAXC) #define ka0402$v_sg_map_ppn ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_ppn #define ka0402$v_sg_map_p ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_p #define ka0402$v_sg_map_f ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_f #define ka0402$v_sg_map_v ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_v #endif /* #if !defined(__VAXC) */ #define KA0402$M_SG_MAP_VA_LW_IN_PAGE 0x1FFF #define KA0402$M_SG_MAP_VA_PAGE 0xFFFE000 typedef struct _ka0402$r_sg_map_va_bits { __union { __struct { unsigned ka0402$v_sg_map_va_lw_in_page : 13; unsigned ka0402$v_sg_map_va_page : 15; unsigned ka0402$v_fill_0_ : 4; } ka0402$r_sg_map_va_bits; } ka0402$r_sg_map_va_overlay; } KA0402$R_SG_MAP_VA_BITS; #if !defined(__VAXC) #define ka0402$v_sg_map_va_lw_in_page ka0402$r_sg_map_va_overlay.ka0402$r_sg_map_va_bits.ka0402$v_sg_map_va_lw_in_page #define ka0402$v_sg_map_va_page ka0402$r_sg_map_va_overlay.ka0402$r_sg_map_va_bits.ka0402$v_sg_map_va_page #endif /* #if !defined(__VAXC) */ #define KA0402$K_IO_SCB_VEC 2048 #define KA0402$K_CORE_IO_TC_SLOT 7 #define KA0402$K_CXTURBO_TC_SLOT 8 #define KA0402$K_TC_SLOT0_VEC 0 #define KA0402$K_TC_SLOT1_VEC 1 #define KA0402$K_TC_SLOT2_VEC 2 #define KA0402$K_TC_SLOT3_VEC 3 #define KA0402$K_TC_SLOT4_VEC 4 #define KA0402$K_TC_SLOT5_VEC 5 #define KA0402$K_TC_SLOT6_VEC 6 #define KA0402$K_ETHERNET_VEC 7 #define KA0402$K_ISDN_VEC 8 #define KA0402$K_CXTURBO_VEC 9 #define KA0402$K_SCC_VEC 10 #define KA0402$K_OPDRVR_XMIT 11 #define KA0402$K_OPDRVR_RCV 12 #define KA0402$K_TOTAL_VECTORS 13 #define KA0402$M_MASK0 0x1 #define KA0402$M_MASK1 0x2 #define KA0402$M_MASK2 0x4 #define KA0402$M_MASK3 0x8 typedef struct _ka0402$r_byte_mask_bits { __union { __struct { unsigned ka0402$v_mask0 : 1; unsigned ka0402$v_mask1 : 1; unsigned ka0402$v_mask2 : 1; unsigned ka0402$v_mask3 : 1; unsigned ka0402$v_fill_1_ : 4; } ka0402$r_byte_mask_bits; } ka0402$r_byte_mask_overlay; } KA0402$R_BYTE_MASK_BITS; #if !defined(__VAXC) #define ka0402$v_mask0 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask0 #define ka0402$v_mask1 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask1 #define ka0402$v_mask2 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask2 #define ka0402$v_mask3 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask3 #endif /* #if !defined(__VAXC) */ /* The following definition defines an entry of a Saved Error Register Table. */ /* This table is pointed to by a cell in the Turbo ADP. The table is divided up */ /* into an entry for each slot. Each entry contains saved copies of IR, TCEREG, */ /* and FADR. The entries are written by the machine check handler on an error, and */ /* read by a driver (at some appropriate time) to determine if a TC error */ /* occurred. */ /* Define Saved Register Table Entry */ #define KA0402$M_SAVED_IR_TC_INT 0x1FF #define KA0402$M_SAVED_IR_SEO 0x80000 #define KA0402$M_SAVED_IR_DBF 0x100000 #define KA0402$M_SAVED_IR_X2K 0x200000 #define KA0402$M_SAVED_IR_TCR 0x400000 #define KA0402$M_SAVED_IR_TPE 0x800000 #define KA0402$M_SAVED_IR_TER 0x1000000 #define KA0402$M_SAVED_IR_SBE 0x2000000 #define KA0402$M_SAVED_IR_DBE 0x4000000 #define KA0402$M_SAVED_IR_TO 0x8000000 #define KA0402$M_SAVED_IR_TL 0x10000000 #define KA0402$M_SAVED_IR_IA 0x20000000 #define KA0402$M_SAVED_IR_NV 0x40000000 #define KA0402$M_SAVED_IR_PE 0x80000000 #define KA0402$M_SAVED_TCEREG_SLOT_ID 0xF #define KA0402$M_SAVED_TCEREG_SG 0x10 #define KA0402$M_SAVED_TCEREG_BM 0x20 #define KA0402$M_SAVED_TCEREG_PE 0x40 #define KA0402$M_SAVED_TCEREG_LOCK 0x80 #define KA0402$M_SAVED_TCEREG_OFFSET 0x1F00 #define KA0402$M_SAVED_TCEREG_SYNDROME 0x7F0000 #define KA0402$M_SAVED_TCEREG_WM_BYTE0 0x1000000 #define KA0402$M_SAVED_TCEREG_WM_BYTE1 0x2000000 #define KA0402$M_SAVED_TCEREG_WM_BYTE2 0x4000000 #define KA0402$M_SAVED_TCEREG_WM_BYTE3 0x8000000 #define KA0402$M_SAVED_TCEREG_W 0x40000000 #define KA0402$M_SAVED_TCEREG_D 0x80000000 #define KA0402$K_SAVED_REG_ENTRY_SIZE 16 typedef struct _saved_reg_entry { __union { unsigned int ka0402$l_saved_ir; /* Interrupt reason */ __struct { unsigned ka0402$v_saved_ir_tc_int : 9; unsigned ka0402$v_saved_ir_fill1 : 10; unsigned ka0402$v_saved_ir_seo : 1; unsigned ka0402$v_saved_ir_dbf : 1; unsigned ka0402$v_saved_ir_x2k : 1; unsigned ka0402$v_saved_ir_tcr : 1; unsigned ka0402$v_saved_ir_tpe : 1; unsigned ka0402$v_saved_ir_ter : 1; unsigned ka0402$v_saved_ir_sbe : 1; unsigned ka0402$v_saved_ir_dbe : 1; unsigned ka0402$v_saved_ir_to : 1; unsigned ka0402$v_saved_ir_tl : 1; unsigned ka0402$v_saved_ir_ia : 1; unsigned ka0402$v_saved_ir_nv : 1; unsigned ka0402$v_saved_ir_pe : 1; } ka0402$r_saved_ir_bits; } ka0402$r_saved_ir_overlay; __union { unsigned int ka0402$l_saved_tcereg; /* Error register */ __struct { unsigned ka0402$v_saved_tcereg_slot_id : 4; unsigned ka0402$v_saved_tcereg_sg : 1; unsigned ka0402$v_saved_tcereg_bm : 1; unsigned ka0402$v_saved_tcereg_pe : 1; unsigned ka0402$v_saved_tcereg_lock : 1; unsigned ka0402$v_saved_tcereg_offset : 5; unsigned ka0402$v_saved_tcereg_fill2 : 3; unsigned ka0402$v_saved_tcereg_syndrome : 7; unsigned ka0402$v_saved_tcereg_fill3 : 1; unsigned ka0402$v_saved_tcereg_wm_byte0 : 1; unsigned ka0402$v_saved_tcereg_wm_byte1 : 1; unsigned ka0402$v_saved_tcereg_wm_byte2 : 1; unsigned ka0402$v_saved_tcereg_wm_byte3 : 1; unsigned ka0402$v_saved_tcereg_fill4 : 2; unsigned ka0402$v_saved_tcereg_w : 1; unsigned ka0402$v_saved_tcereg_d : 1; } ka0402$r_saved_tcereg_bits; } ka0402$r_saved_tcereg_overlay; void *ka0402$l_saved_fadr; /* Failing Address */ unsigned int ka0402$l_fill; /* to quad boundary */ } SAVED_REG_ENTRY; #if !defined(__VAXC) #define ka0402$l_saved_ir ka0402$r_saved_ir_overlay.ka0402$l_saved_ir #define ka0402$v_saved_ir_tc_int ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tc_int #define ka0402$v_saved_ir_seo ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_seo #define ka0402$v_saved_ir_dbf ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_dbf #define ka0402$v_saved_ir_x2k ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_x2k #define ka0402$v_saved_ir_tcr ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tcr #define ka0402$v_saved_ir_tpe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tpe #define ka0402$v_saved_ir_ter ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_ter #define ka0402$v_saved_ir_sbe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_sbe #define ka0402$v_saved_ir_dbe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_dbe #define ka0402$v_saved_ir_to ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_to #define ka0402$v_saved_ir_tl ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tl #define ka0402$v_saved_ir_ia ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_ia #define ka0402$v_saved_ir_nv ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_nv #define ka0402$v_saved_ir_pe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_pe #define ka0402$l_saved_tcereg ka0402$r_saved_tcereg_overlay.ka0402$l_saved_tcereg #define ka0402$v_saved_tcereg_slot_id ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_slot_id #define ka0402$v_saved_tcereg_sg ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_sg #define ka0402$v_saved_tcereg_bm ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_bm #define ka0402$v_saved_tcereg_pe ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_pe #define ka0402$v_saved_tcereg_lock ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_lock #define ka0402$v_saved_tcereg_offset ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_offset #define ka0402$v_saved_tcereg_syndrome ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_syndrome #define ka0402$v_saved_tcereg_wm_byte0 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte0 #define ka0402$v_saved_tcereg_wm_byte1 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte1 #define ka0402$v_saved_tcereg_wm_byte2 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte2 #define ka0402$v_saved_tcereg_wm_byte3 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte3 #define ka0402$v_saved_tcereg_w ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_w #define ka0402$v_saved_tcereg_d ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_d #endif /* #if !defined(__VAXC) */ /* Define indexes into error table. Indexes are 0 thru 10. */ /* The count of the number of entries is 11. */ #define KA0402$K_SLOT0_INDEX 0 #define KA0402$K_SLOT1_INDEX 1 #define KA0402$K_SLOT2_INDEX 2 #define KA0402$K_SLOT3_INDEX 3 #define KA0402$K_SLOT4_INDEX 4 #define KA0402$K_SLOT5_INDEX 5 #define KA0402$K_SCSI_INDEX 6 #define KA0402$K_CORE_NI_INDEX 7 #define KA0402$K_CORE_SLU_INDEX 8 #define KA0402$K_CORE_ISDN_INDEX 9 #define KA0402$K_CXTURBO_INDEX 10 #define KA0402$K_SAVED_REG_ENTRY_COUNT 11 #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __KA0402DEF_LOADED */