/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:54 by OpenVMS SDL EV3-3 */ /* Source: 18-MAR-2008 16:15:05 $1$DGA7274:[LIB_H.SRC]IOCDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $IOCDEF ***/ #ifndef __IOCDEF_LOADED #define __IOCDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*+ */ /* */ /* $IOCDEF - flag bits used in I/O database search routines. */ /* */ /*- */ #define IOC$M_PHY 0x1 #define IOC$M_TYPE 0x2 #define IOC$M_CLASS 0x4 #define IOC$M_LOCAL 0x8 #define IOC$M_EXISTS 0x10 #define IOC$M_2P 0x20 #define IOC$M_ANY 0x40 #define IOC$M_MOUNT 0x80 #define IOC$M_ALT 0x100 #define IOC$M_NO_TRANS 0x200 #define IOC$M_ALLOC 0x400 #define IOC$M_DTN 0x800 #define IOC$M_NOLOCK 0x1000 #define IOC$M_PAC 0x2000 #define IOC$M_B4CREATE 0x4000 #define IOC$S_IOCDEF 2 /* Old size name, synonym for IOC$S_IOC */ typedef struct _ioc { /* IOC$V_PHY must be bit 0!! */ unsigned ioc$v_phy : 1; /* physical device specified */ unsigned ioc$v_type : 1; /* device type name specified */ unsigned ioc$v_class : 1; /* allocation class present */ unsigned ioc$v_local : 1; /* search local devices only */ unsigned ioc$v_exists : 1; /* device exists */ unsigned ioc$v_2p : 1; /* device is on UCB secondary path */ unsigned ioc$v_any : 1; /* find any matching device */ unsigned ioc$v_mount : 1; /* find only mountable devices */ unsigned ioc$v_alt : 1; /* alternate UCB found */ unsigned ioc$v_no_trans : 1; /* caller translated logical name */ unsigned ioc$v_alloc : 1; /* allocate mountable device */ unsigned ioc$v_dtn : 1; /* search for DDRed device */ unsigned ioc$v_nolock : 1; /* don't take out device lock */ unsigned ioc$v_pac : 1; /* This is a port allocation class */ unsigned ioc$v_b4create : 1; /* don't skip UCB$V_NO_ASSIGN or UCB$V_CDP devices */ unsigned ioc$v_fill_0_ : 1; } IOC; /* */ /* */ /************************************************************************** */ /* Format of AGP Command Register as defined by AGP Spec V2.0 */ /************************************************************************** */ /* */ #define IOC$M_AGP_CMD_1X 0x1 #define IOC$M_AGP_CMD_2X 0x2 #define IOC$M_AGP_CMD_4X 0x4 #define IOC$M_AGP_CMD_FW 0x10 #define IOC$M_AGP_CMD_4G 0x20 #define IOC$M_AGP_ENABLE 0x100 #define IOC$M_AGP_CMD_SBA 0x200 #define IOC$M_AGP_RQ_DEPTH 0xFF000000 typedef struct _agpr_cmd { unsigned ioc$v_agp_cmd_1x : 1; /* AGP RATE = 1 */ unsigned ioc$v_agp_cmd_2x : 1; /* AGP RATE = 2 */ unsigned ioc$v_agp_cmd_4x : 1; /* AGP RATE = 4 */ unsigned ioc$v_reserved1 : 1; /* RESERVED */ unsigned ioc$v_agp_cmd_fw : 1; /* AGP FASTWRITE */ unsigned ioc$v_agp_cmd_4g : 1; /* AGP ADDRESS > 4GIGABYTE */ unsigned ioc$v_reserved2 : 2; /* RESERVED */ unsigned ioc$v_agp_enable : 1; /* AGP ENABLE */ unsigned ioc$v_agp_cmd_sba : 1; /* SIDEBAND ADDRESS MECHANISM */ unsigned ioc$v_reserved3 : 14; /* RESERVED */ unsigned ioc$v_agp_rq_depth : 8; /* AGP REQUEST QUEUE DEPTH */ } AGPR_CMD; /* */ /* */ /************************************************************************** */ /* Format of AGP Status Register as defined by AGP Spec V2.0 */ /************************************************************************** */ /* */ #define IOC$M_AGP_STS_1X 0x1 #define IOC$M_AGP_STS_2X 0x2 #define IOC$M_AGP_STS_4X 0x4 #define IOC$M_AGP_STS_FW 0x10 #define IOC$M_AGP_STS_4G 0x20 #define IOC$M_AGP_STS_SBA 0x200 #define IOC$M_AGP_RQ 0xFF000000 typedef struct _agpr_sts { unsigned ioc$v_agp_sts_1x : 1; /* AGP RATE = 1 */ unsigned ioc$v_agp_sts_2x : 1; /* AGP RATE = 2 */ unsigned ioc$v_agp_sts_4x : 1; /* AGP RATE = 4 */ unsigned ioc$v_reserved1 : 1; /* RESERVED */ unsigned ioc$v_agp_sts_fw : 1; /* AGP FASTWRITE */ unsigned ioc$v_agp_sts_4g : 1; /* AGP ADDRESS > 4GIGABYTE */ unsigned ioc$v_reserved2 : 3; /* RESERVED */ unsigned ioc$v_agp_sts_sba : 1; /* SIDEBAND ADDRESS MECHANISM */ unsigned ioc$v_reserved3 : 14; /* RESERVED */ unsigned ioc$v_agp_rq : 8; /* AGP REQUEST QUEUE DEPTH */ } AGPR_STS; /* */ /* */ /************************************************************************** */ /* Function codes used by system routines ioc$read_io, ioc$write_io */ /************************************************************************** */ /* */ #define IOC$K_BYTE_LANED 1 #define IOC$K_WORD_LANED 2 #define IOC$K_LONGWORD 4 #define IOC$K_QUADWORD 8 #define IOC$K_BYTE 256 #define IOC$K_WORD 512 /* */ /* */ /************************************************************************** */ /* Function codes used by system routine ioc$node_function */ /************************************************************************** */ /* */ #define IOC$K_ENABLE_INTR 1 #define IOC$K_DISABLE_INTR 2 #define IOC$K_ENABLE_SG 3 #define IOC$K_DISABLE_SG 4 #define IOC$K_ENABLE_PAR 5 #define IOC$K_DISABLE_PAR 6 #define IOC$K_ENABLE_BLKM 7 #define IOC$K_DISABLE_BLKM 8 #define IOC$K_ISSUE_EOI 9 #define IOC$K_ENABLE_DISTRIB_INTR 10 #define IOC$K_DISABLE_DISTRIB_INTR 11 #define IOC$K_AGP_READ_COMMAND 12 #define IOC$K_AGP_WRITE_COMMAND 13 /* */ /*------------------------------------------------------------------------- */ /* Multiple Vector Interrupt ioc$node_function codes */ /* */ #define IOC$K_MVI_MASK_EVENT 14 #define IOC$K_MVI_UNMASK_EVENT 15 #define IOC$K_MVI_REQUEST_VECTORS 16 #define IOC$K_MVI_MAP_VECTOR 17 #define IOC$K_MVI_DISPATCH_EVENT 18 #define IOC$K_MVI_DISPATCH_VECTOR 19 #define IOC$K_MVI_DISPATCH_UNIQUE 20 /* */ /* */ /************************************************************************** */ /* Function codes used by system routine ioc$node_data */ /************************************************************************** */ /* */ #define IOC$K_TURBO_SLOT_DENSE_PA 1 #define IOC$K_TURBO_SLOT_SPARSE_PA 2 #define IOC$K_FBUS_INT_LOC 3 #define IOC$K_EISA_IRQ 4 #define IOC$K_EISA_DMA_CHAN 5 #define IOC$K_EISA_CONFIG_BLOCK 6 #define IOC$K_EISA_MEM_CONFIG 7 #define IOC$K_LBUS_DEV_BLK_PTR 8 #define IOC$K_EISA_IO_PORT 9 #define IOC$K_SCSI_CLK_PERIOD 10 #define IOC$K_CPU_INT_MASK 11 #define IOC$K_IO_PORT_RAD 12 /* */ /* */ /*------------------------------------------------------------------------- */ /* The following codes are actually used by the I/O space */ /* mapping routine IOC$MAP_IO. But, add them anyway to the */ /* IOC$NODE_DATA list as unique codes. */ /* */ /* Add synonyms for the IOC$MAP_IO function codes until the */ /* old ones are legislated out of existence. */ /* */ #define IOC$K_IO_CSR_BYTE_ACCESS 11 #define IOC$K_BUS_IO_BYTE_GRAN 11 #define IOC$K_IO_CSR_LONG_ACCESS 12 #define IOC$K_IO_MEM_BYTE_ACCESS 13 #define IOC$K_BUS_MEM_BYTE_GRAN 13 #define IOC$K_IO_MEM_LONG_ACCESS 14 #define IOC$K_BUS_MEM_DENSE 14 /* */ /* */ /*------------------------------------------------------------------------- */ /* The following code is used by drivers to request the address */ /* swizzle factor of an I/O bus. */ /* */ #define IOC$K_IO_ADDRESS_SWIZZLE 15 /* */ /* */ /*------------------------------------------------------------------------- */ /* The following two are synonyms to request the bus address */ /* of the direct DMA window. */ /* */ #define IOC$K_DIRECT_DMA_BASE 16 #define IOC$K_DDMA_BASE_BA 16 /* */ /* */ /*------------------------------------------------------------------------- */ /* Old code uses this function code to get the size of the */ /* direct dma window. If the system is a Galaxy system, */ /* and the minpfn is nonzero, this function code will */ /* return a size of zero, even if it isn't. See DDMA_WIN_SIZE */ /* below. */ /* */ #define IOC$K_DIRECT_DMA_SIZE 17 /* */ /* */ /*------------------------------------------------------------------------- */ /* add an ioc$node_data code for the ISA bus user parameter. */ /* also an ioc$node_data code for the dipl problem. */ /* these are added here so that it is easy to see what the next */ /* number to use will be. (could be added to node_data list above) */ /* */ #define IOC$K_ISA_USER_PARAM 18 #define IOC$K_DEVICE_IPL 19 /* */ /*------------------------------------------------------------------------- */ /* Add an ioc$node_data code for monster windows */ /* */ #define IOC$K_MONSTER_WINDOW 20 /* */ /* */ /*------------------------------------------------------------------------- */ /* This function code will always return the true size of */ /* the direct dma window. DDMA_BASE_PA will return the */ /* memory address of the direct dma window, no longer to */ /* be presumed zero. */ #define IOC$K_DDMA_WIN_SIZE 21 #define IOC$K_DDMA_BASE_PA 22 /* */ /* */ /*------------------------------------------------------------------------- */ /* Add an ioc$node_data code for AGP capabilities mask */ /* The data returned is formatted to conform to the AGP STATUS longword */ /* found in the configuration header for the AGP bus. */ #define IOC$K_AGP_CAP_MASK 23 /* */ /* */ /* */ /*------------------------------------------------------------------------- */ /* This ioc$node_data function code will identify the system building block */ /* in which an adapter resides. Support for this code is currently */ /* planned only for Wildfire and Marvel class alpha systems. All others */ /* will return SS$_ILLIOFUNC. */ /* */ #define IOC$K_IO_PORT_LOC 24 /* */ /* */ /*------------------------------------------------------------------------- */ /* This ioc$node_data function returns the translation offset quadword */ /* from the ADP for the specified CRB. If the ADP doesn't contain a */ /* valid translation offset, this function returns SS$_ILLIOFUNC. */ /* */ #define IOC$K_IO_TRA_OFFSET 25 /* */ /* */ /*------------------------------------------------------------------------- */ /* Return a pointer to the BUSARRAYENTRY */ /* */ #define IOC$K_BUSARRAYENTRY 26 /* */ /* */ /*------------------------------------------------------------------------- */ /* MSI and Multiple Vector Interrupt ioc$node_data codes */ /* */ #define IOC$K_INT_MECH 27 #define IOC$K_MSIABS 28 #define IOC$K_MVI_DEV_VECTORS_REQ 29 #define IOC$K_MVI_SYS_VECTORS_GRA 30 #define IOC$K_MVI_DATA 31 #define IOC$K_MVI_PENDING_EVENT 32 /* */ /* */ /*------------------------------------------------------------------------- */ /* Return a mask of platform DMA capabilities as defined in ADPDEF */ /* */ #define IOC$K_DMA_CAP_MASK 33 /* */ /* */ /*------------------------------------------------------------------------- */ /* Additional MSI and Multiple Vector Interrupt ioc$node_data codes */ /* */ #define IOC$K_MVI_USR_VECTORS_REQ 34 /* */ /* */ /*------------------------------------------------------------------------- */ /* A function code for IOC$NODE_DATA that drivers can call to see if */ /* their platform has a SG Map. (The only platforms that should fail with */ /* SS$_ITEMNOTFOUND are Sentosa, Kauai and Bucchaneer and later platforms). */ /* */ #define IOC$K_SG_MAP_PRESENT 35 /* */ /* */ /************************************************************************** */ /* Values returned by IOC$K_INT_MECH node_data call. */ /* These values are mutually exclusive. */ /************************************************************************** */ /* */ #define IOC$K_INT_MECH_IOSAPIC 1 /* IOSAPIC delivery mechanism */ #define IOC$K_INT_MECH_MSI 2 /* Standard MSI mechanism */ #define IOC$K_INT_MECH_MSIX 3 /* MSI-X mechanism */ /* */ /* */ /************************************************************************** */ /* MVI_DATA and MVI_QENTRY */ /************************************************************************** */ /* */ /* These structures contain Data returned by calling ioc$node_function */ /* with the function code IOC$K_MSI_REQUEST_VECTORS. */ /* */ /* The Hash Table created maps Interrupt Vectors and Vector Table */ /* Entries to ISR subroutines. */ /* */ /* The sequence of events that builds this tree is as follows. */ /* */ /* AT UNIT INIT TIME: */ /* */ /* . A driver calls ioc$node_function for IOC$K_MVI_REQUEST_VECTORS */ /* */ /* . This call returns an MVI_DATA structure containing the number */ /* of interrupt vectors requested by the device, the number of */ /* vectors granted by the system, and a pointer to an array of */ /* queue headers, one for each of the vectors granted, containing */ /* the vector. */ /* */ /* . The driver implements its policy for distributing the vectors */ /* granted to it by walking the mvi_array and for each vector */ /* in the array, the driver calls ioc$node_function again for */ /* IOC$K_MVI_MAP_FUNCTION with the Interrupt Vector, the Pointer */ /* to the Subroutine for handling the Interrupt, and, in the case */ /* of MSI-X, the Vector Table Entry Index. */ /* */ /* . In the case where the driver was granted fewer vectors than */ /* requested, and the driver must share the vectors with more */ /* than one ISR subroutine or Vector Table Entry, a queue will */ /* be formed for each shared Interrupt Vector. */ /* */ /* AT RUN TIME */ /* */ /* . When an interrupt occurs, the driver will call ioc$node_function */ /* for IOC$K_MVI_DISPATCH_VECTOR, which will run down each ISR */ /* subroutine in the queue for the given vector. The driver should */ /* fork and lower IPL before calling this function. */ /* */ /* . Before exiting, the driver should call ioc$node_function for */ /* IOC$K_MVI_PENDING to see if there are any other interrupts */ /* pending. This call will return the Vector Table Index of any */ /* pending interrupts. */ /* */ /* . For each pending interrupt the driver should call */ /* ioc$node_function for IOC$K_MVI_DISPATCH_VTE in a loop */ /* until all pending interrupts have been handled. */ /* */ /* . Optionally, a driver can call ioc$node_function with a code */ /* of IOC$K_MASK_VTE to mask interrupts from a Vector Table Entry */ /* or IOC$_UNMASK_VTE to unmask interrupts from a Vector Table */ /* Entry. */ /* */ /* . In the case where a driver wants to assign a different vector */ /* to a given Vector Table Entry, it will call ioc$node_function */ /* for IOC$K_MVI_CHANGE_VECTOR with the new vector, the Vector */ /* Table Index, and the Pointer to the ISR subroutine. */ /* */ /* */ /* MVI_DATA */ /* +-------------+ */ /* | Requested | */ /* +-------------+ */ /* | Granted | */ /* +-------------+ */ /* .------| Hash_Table | */ /* | +-------------+ */ /* | */ /* | .-----------------------------------------------------------------. */ /* | | | */ /* | | .-------------------------------------------------------------. | */ /* | | | | | */ /* | | | MULTIPLE VECTOR INTERRUPT HASH TABLE | | */ /* | | | | | */ /* | | | MVI_QENTRY MVI_QENTRY MVI_QENTRY | | */ /* | | | +-------------+ +-------------+ +-------------+ | | */ /* | | `->| Flink |----->| Flink |----->| Flink |>-' | */ /* `----->| |<--. | |<--. | |<---' */ /* | +-------------+ | +-------------+ | +-------------+ */ /* `---<| Blink | `--| Blink | `--| Blink | */ /* +-------------+ +-------------+ +-------------+ */ /* | Vector | | Vector | | Vector | */ /* +-------------+ +-------------+ +-------------+ */ /* | CPU ID | | CPU ID | | CPU ID | */ /* +-------------+ +-------------+ +-------------+ */ /* | Func Ptr | | Func Ptr | | Func Ptr | */ /* +-------------+ +-------------+ +-------------+ */ /* | Vec Tab Idx | | Vec Tab Idx | | Vec Tab Idx | */ /* +-------------+ +-------------+ +-------------+ */ /* | */ /* v */ /* +-------------+ +-------------+ +-------------+ */ /* | Flink |----->| Flink |----->| Flink | */ /* | |<--. | |<--. | | */ /* +-------------+ | +-------------+ | +-------------+ */ /* | Blink | `--| Blink | `--| Blink | */ /* +-------------+ +-------------+ +-------------+ */ /* | Vector | | Vector | | Vector | */ /* +-------------+ +-------------+ +-------------+ */ /* | CPU ID | | CPU ID | | CPU ID | */ /* +-------------+ +-------------+ +-------------+ */ /* | Func Ptr | | Func Ptr | | Func Ptr | */ /* +-------------+ +-------------+ +-------------+ */ /* | Vec Tab Idx | | Vec Tab Idx | | Vec Tab Idx | */ /* +-------------+ +-------------+ +-------------+ */ /* | */ /* v */ /* */ /************************************************************************** */ /* MVI_QENTRY Multiple Vector Interrupt Queue Entry */ /************************************************************************** */ /* */ /* MVI_QENTRY Maps an Interrupt Vector to an ISR subroutine, and, for */ /* MSIX, an MSIX Vector Table Entry. */ /* */ /* There will be one instance of these for every vector, and in the case */ /* of MSIX, every Vector Table Entry. Additionally, for MSI, there is an */ /* array of pointers to every MVI_QENTRY structure, one for each Vector */ /* Table Entry. */ /* */ /* Because it is possible that the OS will not return all the vectors */ /* that a device requests, vectors will have to be shared among the */ /* various ISR subroutines and, in the case of MSIX, associated Vector */ /* Table Entries. */ /* */ /* Vectors that hash to the same MVI_QENTRY index will be chained in a */ /* queue. For the sake of performance, we hope our hash algorithm is */ /* good enough to hash only one vector to each queue. */ /* */ /* When the ISR dispatch function runs down a given vector, it will be */ /* hashed to a chain in the MVI_QENTRY has table and the dispatch function */ /* will execute all the ISR subroutines in that chain. */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mvi_qentry { #pragma __nomember_alignment struct _mvi_qentry *mvi_qe$ps_flink; struct _mvi_qentry *mvi_qe$ps_blink; int (*mvi_qe$ps_function)(); /* ISR Subroutine */ int mvi_qe$l_vector; int mvi_qe$l_cpuid; int mvi_qe$l_vte_index; /* Useful to MVI-X only */ /* */ /* Insure quadword alignment. */ /* */ } MVI_QENTRY; #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mvi_data { #pragma __nomember_alignment int mvi_data$l_requested; /* Number of vectors requested */ int mvi_data$l_granted; /* Number of vectors granted */ int *mvi_data$ps_vec_array; /* List of granted vectors */ int *mvi_data$ps_vte_array; /* Vector Table Entry Array */ struct _mvi_qentry *mvi_data$ps_hash_table; /* Pointer to the Hash Table */ int *mvi_data$ps_bitmap; /* Bitmap for hash table */ int mvi_data$l_bitmap_size; /* Size of Bitmap in bits */ /* */ /* Insure quadword alignment. */ /* */ char mvi_data$b_quad_fill [4]; } MVI_DATA; #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __IOCDEF_LOADED */