/**/
/***************************************************************************/
/**                                                                       **/
/** © Copyright 2010, Hewlett-Packard Development Company, L.P.           **/
/**                                                                       **/
/** Confidential computer software.  Valid license from HP and/or         **/
/** its subsidiaries required for possession, use, or copying.            **/
/**                                                                       **/
/** Consistent with FAR 12.211 and 12.212, Commercial Computer Software,  **/
/** Computer Software Documentation, and Technical Data for Commercial    **/
/** Items are licensed to the U.S. Government under vendor's standard     **/
/** commercial license.                                                   **/
/**                                                                       **/
/** Neither HP nor any of its subsidiaries shall be liable for technical  **/
/** or editorial errors or omissions contained herein.  The information   **/
/** in this document is provided "as is" without warranty of any kind and **/
/** is subject to change without notice.  The warranties for HP products  **/
/** are set forth in the express limited warranty statements accompanying **/
/** such products.  Nothing herein should be construed as constituting an **/
/** additional warranty.                                                  **/
/**                                                                       **/
/***************************************************************************/
/********************************************************************************************************************************/
/* Created: 30-Mar-2010 17:26:53 by OpenVMS SDL EV3-3      */
/* Source:  07-MAR-1997 16:37:42 $1$DGA7274:[LIB_H.SRC]IO0F05DEF.SDL;1 */
/********************************************************************************************************************************/
/*** MODULE $IO0F05DEF IDENT X-3 ***/
#ifndef __IO0F05DEF_LOADED
#define __IO0F05DEF_LOADED 1
 
#pragma __nostandard			 /* This file uses non-ANSI-Standard features */
#pragma __member_alignment __save
#pragma __nomember_alignment
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __save		 /* Save the previously-defined required ptr size */
#pragma __required_pointer_size __short		 /* And set ptr size default to 32-bit pointers */
#endif
 
#ifdef __cplusplus
    extern "C" {
#define __unknown_params ...
#define __optional_params ...
#else
#define __unknown_params
#define __optional_params ...
#endif
 
#ifndef __struct
#if !defined(__VAXC)
#define __struct struct
#else
#define __struct variant_struct
#endif
#endif
 
#ifndef __union
#if !defined(__VAXC)
#define __union union
#else
#define __union variant_union
#endif
#endif
 
#define IO0F05$L_NODE_PA_H 135          /* High order word                  */
#define IO0F05$L_CIA_GENERAL_L 1073741824
#define IO0F05$L_CIA_MEMORY_L 1342177280
#define IO0F05$L_CIA_PCI_ADDR_L 1610612736
#define IO0F05$L_FLASH_AND_GRU_L -2147483648
#define IO0F05$L_PCI_REV_L 128          /*PCI revision                      */
#define IO0F05$L_PCI_LAT_L 192          /*PCI Latency                       */
#define IO0F05$L_CIA_CTRL_L 256         /*CIA COntrol                       */
#define IO0F05$L_HAE_MEM_L 1024         /*HAE memory                        */
#define IO0F05$L_HAE_IO_L 1088          /*HAE I/O                           */
#define IO0F05$L_HAE_CFG_L 1152         /*COnfig                            */
#define IO0F05$L_CIA_CACK_EN_L 1536     /*Ack control                       */
#define IO0F05$L_CIA_DIAG_L 8192        /*Diag control                      */
#define IO0F05$L_CIA_CHECK_L 12288      /*Diag check                        */
#define IO0F05$L_PERF_MON_L 16384       /*Perf monitor                      */
#define IO0F05$L_PERF_CNTR_L 16448      /*Perf control                      */
#define IO0F05$L_CPU_ERR0_L 32768       /*Cpu err info 0                    */
#define IO0F05$L_CPU_ERR1_L 32832       /*Cpu err info 1                    */
#define IO0F05$L_CIA_ERR_L 33280        /*CIA err                           */
#define IO0F05$L_CIA_STAT_L 33344       /*CIA status                        */
#define IO0F05$L_CIA_ERR_MSK_L 33408    /*CIA err mask                      */
#define IO0F05$L_CIA_SYN_L 33536        /*CIA syndrome                      */
#define IO0F05$L_CPU_MPSR0_L 33792      /*Memport stat0                     */
#define IO0F05$L_CPU_MPSR1_L 33856      /*Memport stat1                     */
#define IO0F05$L_PCI_ERR0_L 34816       /*PCI Err 0                         */
#define IO0F05$L_PCI_ERR1_L 34880       /*PCI Err 1                         */
#define IO0F05$L_PCI_ERR2_L 34944       /*PCI Err 1                         */
#define IO0F05$L_MEM_CNFG_L 0           /*Memory config                     */
#define IO0F05$L_MEM_BA0_L 1536         /*Mem base addr0                    */
#define IO0F05$L_MEM_BA2_L 1664         /*Mem base addr2                    */
#define IO0F05$L_MEM_BA4_L 1792         /*Mem base addr4                    */
#define IO0F05$L_MEM_BA6_L 1920         /*Mem base addr6                    */
#define IO0F05$L_MEM_BA8_L 2048         /*Mem base addr8                    */
#define IO0F05$L_MEM_BAA_L 2176         /*Mem base addrA                    */
#define IO0F05$L_MEM_BAC_L 2304         /*Mem base addrC                    */
#define IO0F05$L_MEM_BAE_L 2432         /*Mem base addrE                    */
#define IO0F05$L_MEM_TMG0_L 2816        /*Mem timing 0                      */
#define IO0F05$L_MEM_TMG1_L 2880        /*Mem timing 1                      */
#define IO0F05$L_MEM_TMG2_L 2944        /*Mem timing 2                      */
#define IO0F05$L_PCI_TBIA_L 256         /*SG TB inval                       */
#define IO0F05$L_PCI_W0_BASE_L 1024     /*Window base0                      */
#define IO0F05$L_PCI_W0_MASK_L 1088     /*Window mask0                      */
#define IO0F05$L_PCI_T0_BASE_L 1152     /*Trans base0                       */
#define IO0F05$L_PCI_W1_BASE_L 1280     /*Window base1                      */
#define IO0F05$L_PCI_W1_MASK_L 1344     /*Window mask1                      */
#define IO0F05$L_PCI_T1_BASE_L 1408     /*Trans base1                       */
#define IO0F05$L_PCI_W2_BASE_L 1536     /*Window base2                      */
#define IO0F05$L_PCI_W2_MASK_L 1600     /*Window mask2                      */
#define IO0F05$L_PCI_T2_BASE_L 1664     /*Trans base2                       */
#define IO0F05$L_PCI_W3_BASE_L 1792     /*Window base3                      */
#define IO0F05$L_PCI_W3_MASK_L 1856     /*Window mask3                      */
#define IO0F05$L_PCI_T3_BASE_L 1920     /*Trans base3                       */
#define IO0F05$L_PCI_DAC_BASE_L 1984    /*DAC Base                          */
#define IO0F05$L_PCI_LTB_TAG0_L 2048    /*Lock TB tag0                      */
#define IO0F05$L_PCI_LTB_TAG1_L 2112    /*Lock TB tag1                      */
#define IO0F05$L_PCI_LTB_TAG2_L 2176    /*Lock TB tag2                      */
#define IO0F05$L_PCI_LTB_TAG3_L 2240    /*Lock TB tag3                      */
#define IO0F05$L_PCI_TB_TAG0_L 2304     /* TB tag0                          */
#define IO0F05$L_PCI_TB_TAG1_L 2368     /* TB tag1                          */
#define IO0F05$L_PCI_TB_TAG2_L 2432     /* TB tag2                          */
#define IO0F05$L_PCI_TB_TAG3_L 2496     /* TB tag3                          */
#define IO0F05$L_PCI_TB0_PAGE0_L 4096   /* TB0 page0                        */
#define IO0F05$L_PCI_TB0_PAGE1_L 4160   /* TB0 page1                        */
#define IO0F05$L_PCI_TB0_PAGE2_L 4224   /* TB0 page2                        */
#define IO0F05$L_PCI_TB0_PAGE3_L 4288   /* TB0 page3                        */
#define IO0F05$L_PCI_TB1_PAGE0_L 4352   /* TB1 page0                        */
#define IO0F05$L_PCI_TB1_PAGE1_L 4416   /* TB1 page1                        */
#define IO0F05$L_PCI_TB1_PAGE2_L 4480   /* TB1 page2                        */
#define IO0F05$L_PCI_TB1_PAGE3_L 4544   /* TB1 page3                        */
#define IO0F05$L_PCI_TB2_PAGE0_L 4608   /* TB2 page0                        */
#define IO0F05$L_PCI_TB2_PAGE1_L 4672   /* TB2 page1                        */
#define IO0F05$L_PCI_TB2_PAGE2_L 4736   /* TB2 page2                        */
#define IO0F05$L_PCI_TB2_PAGE3_L 4800   /* TB2 page3                        */
#define IO0F05$L_PCI_TB3_PAGE0_L 4864   /* TB3 page0                        */
#define IO0F05$L_PCI_TB3_PAGE1_L 4928   /* TB3 page1                        */
#define IO0F05$L_PCI_TB3_PAGE2_L 4992   /* TB3 page2                        */
#define IO0F05$L_PCI_TB3_PAGE3_L 5056   /* TB3 page3                        */
#define IO0F05$L_PCI_TB4_PAGE0_L 5120   /* TB4 page0                        */
#define IO0F05$L_PCI_TB4_PAGE1_L 5184   /* TB4 page1                        */
#define IO0F05$L_PCI_TB4_PAGE2_L 5248   /* TB4 page2                        */
#define IO0F05$L_PCI_TB4_PAGE3_L 5312   /* TB4 page3                        */
#define IO0F05$L_PCI_TB5_PAGE0_L 5376   /* TB5 page0                        */
#define IO0F05$L_PCI_TB5_PAGE1_L 5440   /* TB5 page1                        */
#define IO0F05$L_PCI_TB5_PAGE2_L 5504   /* TB5 page2                        */
#define IO0F05$L_PCI_TB5_PAGE3_L 5568   /* TB5 page3                        */
#define IO0F05$L_PCI_TB6_PAGE0_L 5632   /* TB6 page0                        */
#define IO0F05$L_PCI_TB6_PAGE1_L 5696   /* TB6 page1                        */
#define IO0F05$L_PCI_TB6_PAGE2_L 5760   /* TB6 page2                        */
#define IO0F05$L_PCI_TB6_PAGE3_L 5824   /* TB6 page3                        */
#define IO0F05$L_PCI_TB7_PAGE0_L 5888   /* TB7 page0                        */
#define IO0F05$L_PCI_TB7_PAGE1_L 5952   /* TB7 page1                        */
#define IO0F05$L_PCI_TB7_PAGE2_L 6016   /* TB7 page2                        */
#define IO0F05$L_PCI_TB7_PAGE3_L 6080   /* TB7 page3                        */
#define IO0F05$L_GRU_INT_REQ_L 0        /* Int request                      */
#define IO0F05$L_GRU_INT_MASK_L 64      /* Int mask                         */
#define IO0F05$L_GRU_INT_EDGE_L 128     /* Level/edge selct                 */
#define IO0F05$L_GRU_INT_HILO_L 192     /* Hi/lo irq select                 */
#define IO0F05$L_GRU_INT_CLR_L 256      /* Clear Int                        */
#define IO0F05$L_GRU_CACHE_CNFG_L 512   /* Cache config                     */
#define IO0F05$L_GRU_SET_CNFG_L 768     /* Set Cache config                 */
#define IO0F05$L_GRU_LEDS_L 2048        /* LEDs                             */
#define IO0F05$L_GRU_RESET_L 2304       /* Force system reset               */
 
#pragma __member_alignment __restore
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __restore		 /* Restore the previously-defined required ptr size */
#endif
#ifdef __cplusplus
    }
#endif
#pragma __standard
 
#endif /* __IO0F05DEF_LOADED */