/**/
/***************************************************************************/
/**                                                                       **/
/** © Copyright 2010, Hewlett-Packard Development Company, L.P.           **/
/**                                                                       **/
/** Confidential computer software.  Valid license from HP and/or         **/
/** its subsidiaries required for possession, use, or copying.            **/
/**                                                                       **/
/** Consistent with FAR 12.211 and 12.212, Commercial Computer Software,  **/
/** Computer Software Documentation, and Technical Data for Commercial    **/
/** Items are licensed to the U.S. Government under vendor's standard     **/
/** commercial license.                                                   **/
/**                                                                       **/
/** Neither HP nor any of its subsidiaries shall be liable for technical  **/
/** or editorial errors or omissions contained herein.  The information   **/
/** in this document is provided "as is" without warranty of any kind and **/
/** is subject to change without notice.  The warranties for HP products  **/
/** are set forth in the express limited warranty statements accompanying **/
/** such products.  Nothing herein should be construed as constituting an **/
/** additional warranty.                                                  **/
/**                                                                       **/
/***************************************************************************/
/********************************************************************************************************************************/
/* Created: 30-Mar-2010 17:26:43 by OpenVMS SDL EV3-3      */
/* Source:  22-JAN-1998 14:14:23 $1$DGA7274:[LIB_H.SRC]IO0C05DEF.SDL;1 */
/********************************************************************************************************************************/
/*** MODULE $IO0C05DEF ***/
#ifndef __IO0C05DEF_LOADED
#define __IO0C05DEF_LOADED 1
 
#pragma __nostandard			 /* This file uses non-ANSI-Standard features */
#pragma __member_alignment __save
#pragma __nomember_alignment
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __save		 /* Save the previously-defined required ptr size */
#pragma __required_pointer_size __short		 /* And set ptr size default to 32-bit pointers */
#endif
 
#ifdef __cplusplus
    extern "C" {
#define __unknown_params ...
#define __optional_params ...
#else
#define __unknown_params
#define __optional_params ...
#endif
 
#ifndef __struct
#if !defined(__VAXC)
#define __struct struct
#else
#define __struct variant_struct
#endif
#endif
 
#ifndef __union
#if !defined(__VAXC)
#define __union union
#else
#define __union variant_union
#endif
#endif
 
#define IO0C05$L_IO_PA_H 3968
#define IO0C05$L_NODE_PA_H 4095
#define IO0C05$L_NODE0_PA_L -2013265920
#define IO0C05$L_NODE1_PA_L -2009071616
#define IO0C05$L_NODE2_PA_L -2004877312
#define IO0C05$L_NODE3_PA_L -2000683008
#define IO0C05$L_NODE4_PA_L -1996488704
#define IO0C05$L_NODE5_PA_L -1992294400
#define IO0C05$L_NODE6_PA_L -1988100096
#define IO0C05$L_NODE7_PA_L -1983905792
#define IO0C05$L_NODE8_PA_L -1979711488
#define IO0C05$L_BROADCAST_L -1912602624 /* BROADCAST SPACE                 */
#define IO0C05$L_UART0_L -1610612736    /* UART 0                           */
#define IO0C05$L_UART1_L -1593835520    /* UART 1                           */
#define IO0C05$L_WATCH_L -1342177280    /* WATCH CHIP                       */
#define IO0C05$L_GBUS_L -1073741824     /* GBUS                             */
#define IO0C05$K_TLIPINTR 64            /* IP INTR REG                      */
#define IO0C05$K_TLIOINTR4 256          /* I/O INT REG 4                    */
#define IO0C05$K_TLIOINTR5 320          /* I/O INT REG 5                    */
#define IO0C05$K_TLIOINTR6 384          /* I/O INT REG 6                    */
#define IO0C05$K_TLIOINTR7 448          /* I/O INT REG 4                    */
#define IO0C05$K_TLIOINTR8 512          /* I/O INT REG 7                    */
#define IO0C05$K_TLWSDQR4 1024          /* WIND SPACE DC4                   */
#define IO0C05$K_TLWSDQR5 1088          /* WIND SPACE DC5                   */
#define IO0C05$K_TLWSDQR6 1152          /* WIND SPACE DC6                   */
#define IO0C05$K_TLWSDQR7 1216          /* WIND SPACE DC7                   */
#define IO0C05$K_TLWSDQR8 1280          /* WIND SPACE DC8                   */
#define IO0C05$K_TLRMDQRX 1536          /* RM DEC CNT X                     */
#define IO0C05$K_TLRMDQR8 1600          /* RM DEC CNT 8                     */
#define IO0C05$K_TLRDRD 2048            /* WIND SP RD DATA DATA             */
#define IO0C05$K_TLRDRE 2112            /* WIND SP RD DATA ERR              */
#define IO0C05$K_B_RR0 0
#define IO0C05$K_B_RR8 64
#define IO0C05$K_A_RR0 128
#define IO0C05$K_A_RR8 192
#define IO0C05$K_SECONDS 0
#define IO0C05$K_MINUTES 128
#define IO0C05$K_HOURS 256
#define IO0C05$K_DAY_OF_MONTH 448
#define IO0C05$K_MONTH 512
#define IO0C05$K_YEAR 576
#define IO0C05$K_CSRA 640
#define IO0C05$K_CSRB 704
#define IO0C05$K_CSRC 768
#define IO0C05$K_CSRD 832
#define IO0C05$K_RAM 896
#define IO0C05$K_WHAMI 0
#define IO0C05$K_LED0 16777216
#define IO0C05$K_LED1 33554432
#define IO0C05$K_LED2 50331648
#define IO0C05$K_MISCR 67108864
#define IO0C05$K_MISCW 83886080
#define IO0C05$K_TLSBRST 100663296
#define IO0C05$K_SERNUM 117440512
#define IO0C05$K_TEST 134217728
#define IO0C05$K_TLDEV 0                /* DEVICE                           */
#define IO0C05$K_TLBER 64               /* ERROR                            */
#define IO0C05$K_TLCNR 128              /* CONFIGURATION                    */
#define IO0C05$K_TLVID 192              /* VIRT ID                          */
#define IO0C05$K_TLMMR0 512             /* MEM MAPPING 0                    */
#define IO0C05$K_TLMMR1 576             /* MEM MAPPING 1                    */
#define IO0C05$K_TLMMR2 640             /* MEM MAPPING 2                    */
#define IO0C05$K_TLMMR3 704             /* MEM MAPPING 3                    */
#define IO0C05$K_TLMMR4 768             /* MEM MAPPING 4                    */
#define IO0C05$K_TLMMR5 832             /* MEM MAPPING 5                    */
#define IO0C05$K_TLMMR6 896             /* MEM MAPPING 6                    */
#define IO0C05$K_TLMMR7 960             /* MEM MAPPING 7                    */
#define IO0C05$K_TLFADR0 1536           /* FAILING ADDR 0                   */
#define IO0C05$K_TLFADR1 1600           /* FAILING ADDR 1                   */
#define IO0C05$K_TLESR0 1664            /* BUS ERROR SYNDROME 0             */
#define IO0C05$K_TLESR1 1728            /* BUS ERROR SYNDROME 1             */
#define IO0C05$K_TLESR2 1792            /* BUS ERROR SYNDROME 2             */
#define IO0C05$K_TLESR3 1856            /* BUS ERROR SYNDROME 3             */
#define IO0C05$K_TLILID0 2560           /* TIOP INT LVL 0                   */
#define IO0C05$K_TLILID1 2624           /* TIOP INT LVL 1                   */
#define IO0C05$K_TLILID2 2688           /* TIOP INT LVL 2                   */
#define IO0C05$K_TLILID3 2752           /* TIOP INT LVL 3                   */
#define IO0C05$K_TLCPUMASK 2816         /* TIOP CPU INT MASK                */
#define IO0C05$K_TLMBPR 3072            /* TIOP MBX PNTR REG                */
#define IO0C05$K_TLDIAG 4096            /* TLEP DIAG SETUP                  */
#define IO0C05$K_TLDTAGDATA 4160        /* TLEP DTAG DATA                   */
#define IO0C05$K_TLDTAGSTAT 4224        /* TLEP DTAG STAT                   */
#define IO0C05$K_TLMODCONFIG 4288       /* TLEP MOD CONFIG                  */
#define IO0C05$K_TLINTRMASK0 4352       /* TLEP INT MASK 0                  */
#define IO0C05$K_TLINTRMASK1 4416       /* TLEP INT MASK 1                  */
#define IO0C05$K_TLINTRSUM0 4480        /* TLEP INT SUM 0                   */
#define IO0C05$K_TLINTRSUM1 4544        /* TLEP INT SUM 1                   */
#define IO0C05$K_TLCON00 4608           /* TLEP CONS COMM                   */
#define IO0C05$K_TLCON00A 4672          /* TLEP DIGA COMM TEST              */
#define IO0C05$K_TLCON00B 4736          /* TLEP DIGA COMM TEST              */
#define IO0C05$K_TLCON00C 4800          /* TLEP DIGA COMM TEST              */
#define IO0C05$K_TLCON10 4864           /* TLEP CONS COMM                   */
#define IO0C05$K_TLCON10A 4928          /* TLEP DIGA COMM TEST              */
#define IO0C05$K_TLCON10B 4992          /* TLEP DIGA COMM TEST              */
#define IO0C05$K_TLCON10C 5056          /* TLEP DIGA COMM TEST              */
#define IO0C05$K_TLCON01 5120           /* TLEP CONS COMM                   */
#define IO0C05$K_TLCON11 5184           /* TLEP CONS COMM                   */
#define IO0C05$K_TLEPAERR 5376          /* TLEP ADG ERROR                   */
#define IO0C05$K_TLEPDERR 5440          /* TLEP DIGA ERROR                  */
#define IO0C05$K_TLEPMERR 5504          /* TLEP MMG ERROR                   */
#define IO0C05$K_TLEP_VMG 5568          /* TLEP VOLT MARG                   */
#define IO0C05$K_TLDMCMD 5632           /* TLEP DM CMD                      */
#define IO0C05$K_TLDMADRA 5760          /* TLEP DM A                        */
#define IO0C05$K_TLDMADRB 5824          /* TLEP DM B                        */
#define IO0C05$K_TLPM_CMD 6144          /* TLEP PERF MON CMD                */
#define IO0C05$K_TLPM_TOT_CYC 6208      /* TLEP # OF CYCLES                 */
#define IO0C05$K_TLPM_EV5_LAT 6272      /* TLEP EV5 RD LAT                  */
#define IO0C05$K_TLPM_READ_LAT 6336     /* TLEP AV RD LAT                   */
#define IO0C05$K_TLPM_SYS_OWNER 6400    /* TLEP # CYC OF SYS OWNER          */
#define IO0C05$K_TLPM_CMD_SILO 6464     /* TLEP CMD SILO                    */
#define IO0C05$K_TLPM_LOCK 6528         /* TLEP # LOCK ACKS                 */
#define IO0C05$K_TLPM_MB 6592           /* TLEP # MB ACKS                   */
#define IO0C05$K_TLPM_SD_TOTAL 6656     /* TLEP # SD                        */
#define IO0C05$K_TLPM_SD_ACKED 6720     /* TLEP # SD ACKS                   */
#define IO0C05$K_TLPM_RD_CSR 6784       /* TLEP # CSR RDS                   */
#define IO0C05$K_TLPM_RD 6848           /* TLEP # MEM RD MISS               */
#define IO0C05$K_TLPM_RD_MOD 6912       /* TLEP # RD MISS MODS              */
#define IO0C05$K_TLPM_RD_STC 6976       /* TLEP # RD MISS STXC              */
#define IO0C05$K_TLPM_VICTIM 7040       /* TLEP # BC VICTIMS                */
#define IO0C05$K_TLPM_WR_CSR 7104       /* TLEP # CSR WR CMDS               */
#define IO0C05$K_TLPM_WR 7168           /* TLEP # WR BLK CMDS ACKED         */
#define IO0C05$K_TLPM_WR_LOCK 7232      /* TLEP # WR BLK LK CMDS ACKED      */
#define IO0C05$K_TLPM_INVAL 7296        /* TLEP # INVAL                     */
#define IO0C05$K_TLPM_SET_SHRD 7360     /* TLEP # SET SHRDS                 */
#define IO0C05$K_TLPM_RD_DIRTY 7424     /* TLEP # RD DIRTYS                 */
#define IO0C05$K_TLPM_ADR_SILO 7488     /* TLEP ADR SILO REG                */
#define IO0C05$K_RM_RANG_REG0A 7680     /* TLEP RM MR CHAN0A                */
#define IO0C05$K_RM_RANG_REG0B 7744     /* TLEP RM MR CHAN0B                */
#define IO0C05$K_RM_RANG_REG1A 7808     /* TLEP RM MR CHAN1A                */
#define IO0C05$K_RM_RANG_REG1B 7872     /* TLEP RM MR CHAN1B                */
#define IO0C05$K_TLMODCONFIG0 4096      /* TL-6 MODULE CONFIG REG 0         */
#define IO0C05$K_TLDTAGADDR 4224        /* TL-6 DTAG ADDRESS REG            */
#define IO0C05$K_TLMODCONFIG1 4288      /* TL-6 MODULE CONFIG REG 1         */
#define IO0C05$K_TCCERR 5376            /* TL-6 TCC ERROR REGISTER          */
#define IO0C05$K_TDIERR 5440            /* TL-6 TDI ERROR REGISTER          */
#define IO0C05$K_TL6_VMG 5568           /* TL-6 VOLTAGE MARGINING REG       */
#define IO0C05$K_TL6WERR 5632           /* TL-6 WINDOW SPACE ERROR REG      */
#define IO0C05$K_TLDTAGEX 6144          /* TL-6 DTAG TEST EXECUTE REG       */
#define IO0C05$K_TLLOOPBCK 6208         /* TL-6 DIAG LOOPBACK REG.          */
#define IO0C05$K_TLICCMSR 8192          /* TIOP I/O CNTRL CHIP MODE SEL     */
#define IO0C05$K_TLICCNSE 8256          /* TIOP I/O CNTRL CHIP NODE SPEC ERR */
#define IO0C05$K_TLICCDR 8320           /* TIOP I/O CNTRL CHIP DIAG REG     */
#define IO0C05$K_TLICCMTR 8384          /* TIOP I/O CNTRL CHIP MBX TRANS REG */
#define IO0C05$K_TLICCWRT 8448          /* TIOP I/O CNTRL CHIP CSR WIND TRANS */
#define IO0C05$K_TLIDPNSE1 8512         /* TIOP NODE SPEC DPATH ERROR 1     */
#define IO0C05$K_TLIDPDR1 8576          /* TIOP I/O DPATH DIAG REG 1        */
#define IO0C05$K_TLIDPNSE2 8768         /* TIOP NODE SPEC DPATH ERROR 2     */
#define IO0C05$K_TLIDPDR2 8832          /* TIOP I/O DPATH DIAG REG 2        */
#define IO0C05$K_TLIDPNSE3 9024         /* TIOP NODE SPEC DPATH ERROR 3     */
#define IO0C05$K_TLIDPDR3 9088          /* TIOP I/O DPATH DIAG REG 3        */
#define IO0C05$K_TLIDPNSE0 10816        /* TIOP NODE SPEC DPATH ERROR 0     */
#define IO0C05$K_TLIDPDR0 10880         /* TIOP I/O DPATH DIAG REG 0        */
#define IO0C05$K_TLIPCPUMASK 10944      /* TIOP IP CPU INTR MASK            */
#define IO0C05$K_TLIDPVR 11072          /* TIOP I/O DPATH VECT              */
#define IO0C05$K_TLIDPMSR 11136         /* TIOP I/O DPATH MODE SEL          */
#define IO0C05$K_TLIBR 11200            /* TIOP INFO BASE REPAIR            */
#define IO0C05$K_TLDHRR0A 12288         /* TIOP DOWN HOSE RANGE REGISTER 0A */
#define IO0C05$K_TLDHRR0B 12352         /* TIOP DOWN HOSE RANGE REGISTER 0B */
#define IO0C05$K_TLDHRR1A 12416         /* TIOP DOWN HOSE RANGE REGISTER 1A */
#define IO0C05$K_TLDHRR1B 12480         /* TIOP DOWN HOSE RANGE REGISTER 1B */
#define IO0C05$K_TLSECR 6144            /* TLMEM SECR EEPROM CNTL           */
#define IO0C05$K_TLMIR 6208             /* TLMEM MEM INTERLEAVE             */
#define IO0C05$K_TLMCR 6272             /* TLMEM MEM CONFIG                 */
#define IO0C05$K_TLSTAIR 6336           /* TLMEM SELFTEST ADR ISOL          */
#define IO0C05$K_TLSTER 6400            /* TLMEM SELFTEST ERR REG           */
#define IO0C05$K_TLMER 6464             /* TLMEM MEM ERROR REG              */
#define IO0C05$K_TLMDRA 6528            /* TLMEM MEM DIAG REG A             */
#define IO0C05$K_TLMDRB 6592            /* TLMEM MEM DIAG REG B             */
#define IO0C05$K_TLSTDERA_0 65536       /* TLMEM SELFTEST DATA ERR REG A0   */
#define IO0C05$K_TLSTDERB_0 65600       /* TLMEM SELFTEST DATA ERR REG B0   */
#define IO0C05$K_TLSTDERC_0 65664       /* TLMEM SELFTEST DATA ERR REG C0   */
#define IO0C05$K_TLSTDERD_0 65728       /* TLMEM SELFTEST DATA ERR REG D0   */
#define IO0C05$K_TLSTDERE_0 65792       /* TLMEM SELFTEST DATA ERR REG E0   */
#define IO0C05$K_TLDDR0 65856           /* TLMEM DATA DIAG REG 0            */
#define IO0C05$K_TLSTDERA_1 81920       /* TLMEM SELFTEST DATA ERR REG A1   */
#define IO0C05$K_TLSTDERB_1 81984       /* TLMEM SELFTEST DATA ERR REG B1   */
#define IO0C05$K_TLSTDERC_1 82048       /* TLMEM SELFTEST DATA ERR REG C1   */
#define IO0C05$K_TLSTDERD_1 82112       /* TLMEM SELFTEST DATA ERR REG D1   */
#define IO0C05$K_TLSTDERE_1 82176       /* TLMEM SELFTEST DATA ERR REG E1   */
#define IO0C05$K_TLDDR1 82240           /* TLMEM DATA DIAG REG 1            */
#define IO0C05$K_TLSTDERA_2 98304       /* TLMEM SELFTEST DATA ERR REG A2   */
#define IO0C05$K_TLSTDERB_2 98368       /* TLMEM SELFTEST DATA ERR REG B2   */
#define IO0C05$K_TLSTDERC_2 98432       /* TLMEM SELFTEST DATA ERR REG C2   */
#define IO0C05$K_TLSTDERD_2 98496       /* TLMEM SELFTEST DATA ERR REG D2   */
#define IO0C05$K_TLSTDERE_2 98560       /* TLMEM SELFTEST DATA ERR REG E2   */
#define IO0C05$K_TLDDR2 98624           /* TLMEM DATA DIAG REG 2            */
#define IO0C05$K_TLSTDERA_3 114688      /* TLMEM SELFTEST DATA ERR REG A3   */
#define IO0C05$K_TLSTDERB_3 114752      /* TLMEM SELFTEST DATA ERR REG B3   */
#define IO0C05$K_TLSTDERC_3 114816      /* TLMEM SELFTEST DATA ERR REG C3   */
#define IO0C05$K_TLSTDERD_3 114880      /* TLMEM SELFTEST DATA ERR REG D3   */
#define IO0C05$K_TLSTDERE_3 114944      /* TLMEM SELFTEST DATA ERR REG E3   */
#define IO0C05$K_TLDDR3 115008          /* TLMEM DATA DIAG REG 3            */
 
#pragma __member_alignment __restore
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __restore		 /* Restore the previously-defined required ptr size */
#endif
#ifdef __cplusplus
    }
#endif
#pragma __standard
 
#endif /* __IO0C05DEF_LOADED */