/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:41 by OpenVMS SDL EV3-3 */ /* Source: 24-JUN-1992 16:22:38 $1$DGA7274:[LIB_H.SRC]IO0702DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $IO0702DEF ***/ #ifndef __IO0702DEF_LOADED #define __IO0702DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define IO0702$Q_TC_NUMBER 1 /* Turbochannel number. */ /* Upper lw of physical */ /* address */ #define IO0702$Q_SCSI_CIR -1878523904 /* SCSI Control Interrupts */ #define IO0702$Q_SCSI_IMER -1878523896 /* SCSI Interrupt Mask Enable */ #define IO0702$Q_SCSI0_SDA -1878515712 /* SCSI DMA Address */ #define IO0702$Q_SCSI0_SDIC -1878515704 /* SCSI DMA Interrupt Control */ #define IO0702$Q_SCSI0_DMA_UNAL0 -1878515696 /* SCSI DMA Unaligned Data 0 */ #define IO0702$Q_SCSI0_DMA_UNAL1 -1878515688 /* SCSI DMA Unaligned Data 1 */ #define IO0702$Q_SCSI0_TC_LSB -1877999616 /* SCSI Transfer Counter LSB */ #define IO0702$Q_SCSI0_TC_MSB -1877999608 /* SCSI Transfer Counter MSB */ #define IO0702$Q_SCSI0_FIFO -1877999600 /* SCSI FIFO */ #define IO0702$Q_SCSI0_CMD -1877999592 /* SCSI Command */ #define IO0702$Q_SCSI0_STATUS -1877999584 /* SCSI Status */ #define IO0702$Q_SCSI0_INTR -1877999576 /* SCSI Interrupt/Timeout */ #define IO0702$Q_SCSI0_SEQ -1877999568 /* SCSI Sequence Step */ #define IO0702$Q_SCSI0_FF -1877999560 /* SCSI FIFO Flags */ #define IO0702$Q_SCSI0_CONFIG1 -1877999552 /* SCSI Configuration 1 */ #define IO0702$Q_SCSI0_CC -1877999544 /* SCSI reserved/Clock Conversion */ #define IO0702$Q_SCSI0_TM -1877999536 /* SCSI reserved/Test Mode */ #define IO0702$Q_SCSI0_CONFIG2 -1877999528 /* SCSI Configuration 2 */ #define IO0702$Q_SCSI0_CONFIG3 -1877999520 /* SCSI Configuration 3 */ #define IO0702$Q_SCSI0_DMA -1877475328 /* SCSI DMA Buffer */ #define IO0702$Q_IR -268435456 /* Interrupt Register */ #define IO0702$Q_TCSR -268435440 /* TC Control & Status Register */ #define IO0702$Q_MCR -268435424 /* Memory Config Register */ #define IO0702$Q_FLASH_EEPROM -1342177280 /* CORE I/O ASIC registers - system ROM, part 2 */ #define IO0702$Q_IOCTL_CSR -1341652992 /* CORE I/O base CSR address */ #define IO0702$Q_LDP -1341652928 /* Ethernet DMA pointer */ #define IO0702$Q_SCOMM_TR -1341652896 /* Serial comm transmit port 1 DMA pointer */ #define IO0702$Q_SCOMM_RC -1341652864 /* Serial comm receive port 1 DMA pointer */ #define IO0702$Q_PRINTER_TR -1341652832 /* Serial comm transmit port 2 DMA pointer */ #define IO0702$Q_PRINTER_RC -1341652800 /* Serial comm receive port 2 DMA pointer */ #define IO0702$Q_ISDN_TR -1341652736 /* ISDN transmit DMA pointer */ #define IO0702$Q_ISDN_TR_BUF -1341652704 /* ISDN transmit DMA buffer pointer */ #define IO0702$Q_ISDN_RC -1341652672 /* ISDN receive DMA pointer */ #define IO0702$Q_ISDN_RC_BUF -1341652640 /* ISDN receive DMA buffer pointer */ #define IO0702$Q_DATA0 -1341652608 /* System Data Buffer 0 */ #define IO0702$Q_DATA1 -1341652576 /* System Data Buffer 1 */ #define IO0702$Q_DATA2 -1341652544 /* System Data Buffer 2 */ #define IO0702$Q_DATA3 -1341652512 /* System Data Buffer 3 */ #define IO0702$Q_SSR -1341652480 /* System support register */ #define IO0702$Q_SIR -1341652448 /* System interrupt register */ #define IO0702$Q_SIMR -1341652416 /* System interrupt mask register */ #define IO0702$Q_SADR -1341652384 /* System address register */ #define IO0702$Q_ISDN_DATA_TR -1341652352 /* ISDN Data Transmit */ #define IO0702$Q_ISDN_DATA_RC -1341652320 /* ISDN Data Receive */ #define IO0702$Q_LANCE_SLOT -1341652288 /* Lance slot register */ #define IO0702$Q_SCC0_SLOT -1341652224 /* SCC1 slot register */ #define IO0702$Q_SCC1_SLOT -1341652192 /* SCC0 slot register */ #define IO0702$Q_NI_ADR_ROM -1341128704 /* Ethernet address ROM */ #define IO0702$Q_LANCE_RDP -1340604416 /* Lance ethernet CSR */ #define IO0702$Q_LANCE_RAP -1340604408 /* Lance ethernet CSR */ #define IO0702$Q_SCC0B_COMM_RAP -1340080128 /* Comm Port 1 RAP */ #define IO0702$Q_SCC0B_COMM_DATA -1340080120 /* Comm Port 1 data */ #define IO0702$Q_SCC0A_MOUSE_RAP -1340080112 /* Mouse RAP */ #define IO0702$Q_SCC0A_MOUSE_DATA -1340080104 /* Mouse port data register */ #define IO0702$Q_SCC1B_PRINTER_RAP -1339031552 /* Comm Port 2 RAP */ #define IO0702$Q_SCC1B_PRINTER_DATA -1339031544 /* Comm Port 2 data */ #define IO0702$Q_SCC1A_KEY_RAP -1339031536 /* Keyboard RAP */ #define IO0702$Q_SCC1A_KEY_DATA -1339031528 /* Keyboard port data register */ #define IO0702$Q_RTC_SEC -1337982976 /* TOY clock CSR--seconds */ #define IO0702$Q_RTC_ALMS -1337982968 /* TOY clock CSR--seconds alarm */ #define IO0702$Q_RTC_MIN -1337982960 /* TOY clock CSR--minutes */ #define IO0702$Q_RTC_ALMN -1337982952 /* TOY clock CSR--minutes alarm */ #define IO0702$Q_RTC_HOUR -1337982944 /* TOY clock CSR--hours */ #define IO0702$Q_RTC_ALMH -1337982936 /* TOY clock CSR--hours alarm */ #define IO0702$Q_RTC_DOW -1337982928 /* TOY clock CSR--day of week */ #define IO0702$Q_RTC_DAY -1337982920 /* TOY clock CSR--date of month */ #define IO0702$Q_RTC_MON -1337982912 /* TOY clock CSR--month */ #define IO0702$Q_RTC_YEAR -1337982904 /* TOY clock CSR--year */ #define IO0702$Q_RTC_REGA -1337982896 /* TOY clock CSR--register A */ #define IO0702$Q_RTC_REGB -1337982888 /* TOY clock CSR--register B */ #define IO0702$Q_RTC_REGC -1337982880 /* TOY clock CSR--register C */ #define IO0702$Q_RTC_REGD -1337982872 /* TOY clock CSR--register D */ #define IO0702$Q_RTC_RAM -1337982864 /* TOY clock CSR--base of BBU RAM */ #define IO0702$Q_ISDN_AUDIO -1337458688 /* ISDN audio chip CSR */ #define IO0702$Q_SYSTEM_EEPROM -1073741824 /* base of system ROM, part 1 */ #define IO0702$Q_CPYBUF0 -1072693248 #define IO0702$Q_CPYBUF1 -1072693244 #define IO0702$Q_CPYBUF2 -1072693240 #define IO0702$Q_CPYBUF3 -1072693236 #define IO0702$Q_CPYBUF4 -1072693232 #define IO0702$Q_CPYBUF5 -1072693228 #define IO0702$Q_CPYBUF6 -1072693224 #define IO0702$Q_CPYBUF7 -1072693220 #define IO0702$Q_FG -1072693216 #define IO0702$Q_BG -1072693212 #define IO0702$Q_PLANEMASK -1072693208 #define IO0702$Q_PIXMASK -1072693204 #define IO0702$Q_MODE -1072693200 #define IO0702$Q_BOOLOP -1072693196 #define IO0702$Q_PIXSHIFT -1072693192 #define IO0702$Q_ADDR_REG -1072693188 #define IO0702$Q_BRES1 -1072693184 #define IO0702$Q_BRES2 -1072693180 #define IO0702$Q_BRES3 -1072693176 #define IO0702$Q_BCONT -1072693172 #define IO0702$Q_DEEP -1072693168 #define IO0702$Q_START -1072693164 #define IO0702$Q_CI -1072693160 #define IO0702$Q_V_REF_COUNT -1072693152 #define IO0702$Q_V_HOR -1072693148 #define IO0702$Q_V_VER -1072693144 #define IO0702$Q_V_BASE_ADDR -1072693140 #define IO0702$Q_VV -1072693136 #define IO0702$Q_EI -1072693132 #define IO0702$Q_TCCLK_COUNT -1072693128 #define IO0702$Q_VIDCLK_COUNT -1072693124 #define IO0702$Q_RAMDAC_ADDR_LO -1071906816 #define IO0702$Q_RAMDAC_ADDR_HI -1071906812 #define IO0702$Q_RAMDAC_REG_ADDR -1071906808 #define IO0702$Q_RAMDAC_MAP_LOC -1071906804 #define IO0702$Q_FB -1071644672 #define IO0702$Q_SLOT0_DENSE_BASE 0 #define IO0702$Q_SLOT1_DENSE_BASE 536870912 #define IO0702$Q_SLOT4_DENSE_BASE -2147483648 #define IO0702$Q_SLOT5_DENSE_BASE -1610612736 #define IO0702$Q_SLOT6_DENSE_BASE -1073741824 #define IO0702$Q_SLOT0_SPARSE_BASE 268435456 #define IO0702$Q_SLOT1_SPARSE_BASE 805306368 #define IO0702$Q_SLOT4_SPARSE_BASE -1879048192 #define IO0702$Q_SLOT5_SPARSE_BASE -1342177280 #define IO0702$Q_LDP_DENSE -1610350560 /* Ethernet DMA pointer */ #define IO0702$Q_NI_ADR_ROM_DENSE -1610088448 /* Ethernet address ROM */ #define IO0702$Q_LANCE_RDP_DENSE -1609826304 /* Lance ethernet CSR */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __IO0702DEF_LOADED */