/**/
/***************************************************************************/
/**                                                                       **/
/** © Copyright 2010, Hewlett-Packard Development Company, L.P.           **/
/**                                                                       **/
/** Confidential computer software.  Valid license from HP and/or         **/
/** its subsidiaries required for possession, use, or copying.            **/
/**                                                                       **/
/** Consistent with FAR 12.211 and 12.212, Commercial Computer Software,  **/
/** Computer Software Documentation, and Technical Data for Commercial    **/
/** Items are licensed to the U.S. Government under vendor's standard     **/
/** commercial license.                                                   **/
/**                                                                       **/
/** Neither HP nor any of its subsidiaries shall be liable for technical  **/
/** or editorial errors or omissions contained herein.  The information   **/
/** in this document is provided "as is" without warranty of any kind and **/
/** is subject to change without notice.  The warranties for HP products  **/
/** are set forth in the express limited warranty statements accompanying **/
/** such products.  Nothing herein should be construed as constituting an **/
/** additional warranty.                                                  **/
/**                                                                       **/
/***************************************************************************/
/********************************************************************************************************************************/
/* Created: 30-Mar-2010 17:26:41 by OpenVMS SDL EV3-3      */
/* Source:  04-FEB-1993 14:36:01 $1$DGA7274:[LIB_H.SRC]IO0602DEF.SDL;1 */
/********************************************************************************************************************************/
/*** MODULE $IO0602DEF ***/
#ifndef __IO0602DEF_LOADED
#define __IO0602DEF_LOADED 1
 
#pragma __nostandard			 /* This file uses non-ANSI-Standard features */
#pragma __member_alignment __save
#pragma __nomember_alignment
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __save		 /* Save the previously-defined required ptr size */
#pragma __required_pointer_size __short		 /* And set ptr size default to 32-bit pointers */
#endif
 
#ifdef __cplusplus
    extern "C" {
#define __unknown_params ...
#define __optional_params ...
#else
#define __unknown_params
#define __optional_params ...
#endif
 
#ifndef __struct
#if !defined(__VAXC)
#define __struct struct
#else
#define __struct variant_struct
#endif
#endif
 
#ifndef __union
#if !defined(__VAXC)
#define __union union
#else
#define __union variant_union
#endif
#endif
 
#define IO0602$K_EISA_LOCAL 1
#define IO0602$K_EISA_MEM 2
#define IO0602$K_EISA_IO 3
#define IO0602$Q_EISA_INTA_CYCLE 0
#define IO0602$Q_EISA_COMBO_CHIP -1073741824 /* base address of COMBO ADDR space */
#define IO0602$Q_EISA_COMBO_CHIP_RTC -1073553408 /* base address of COMBO ADDR space, RTC */
#define IO0602$B_KBD_PS2 -1073696768    /* PS2 keyboard register, read      */
#define IO0602$B_KBD_DBB -1073696768    /* PS2 keyboard register, write     */
#define IO0602$B_KBD_PS2S -1073694720   /* PS2 status register              */
#define IO0602$B_TOY_R_INDX_REG -1073684480 /* address of index register for read addr. */
#define IO0602$B_TOY_R_DATA_REG -1073683968 /* address of data register for read data. */
#define IO0602$B_TOY_W_INDX_REG -1073553408 /* address of index register for write addr. */
#define IO0602$B_TOY_W_DATA_REG -1073552896 /* address of data register for write data. */
#define IO0602$K_TOY_SECS 0             /* seconds of TOY clock.            */
#define IO0602$K_TOY_ASECS 1            /* seconds of TOY clock, alarm func. */
#define IO0602$K_TOY_MINS 2             /* minutes of TOY clock.            */
#define IO0602$K_TOY_AMINS 3            /* minutes of TOY clock, alarm func. */
#define IO0602$K_TOY_HOURS 4            /* hours of TOY clock.              */
#define IO0602$K_TOY_AHOURS 5           /* hours of TOY clock, alarm func.  */
#define IO0602$K_TOY_DAY 6              /* day of week, 1-7                 */
#define IO0602$K_TOY_DATE 7             /* date of month                    */
#define IO0602$K_TOY_MONTH 8            /* month                            */
#define IO0602$K_TOY_YEAR 9             /* year                             */
#define IO0602$K_TOY_CNTRLA 10          /* control register A               */
#define IO0602$K_TOY_CNTRLB 11          /* control register B               */
#define IO0602$K_TOY_CNTRLC 12          /* control register C               */
#define IO0602$K_TOY_CNTRLD 13          /* control register D               */
#define IO0602$B_COMB_RBR -1073352704   /* Recieve Buffer Register          */
#define IO0602$B_COMB_THR -1073352704   /* Transmitter Holding Register     */
#define IO0602$B_COMB_DLL -1073352704   /* Divisor Latch Register(LSB)      */
#define IO0602$B_COMB_DLM -1073352192   /* Divisor Latch Register(MSB)      */
#define IO0602$B_COMB_IER -1073352192   /* Interrupt Enable Register        */
#define IO0602$B_COMB_FCR -1073351680   /*                                  */
#define IO0602$B_COMB_IIR -1073351680   /* Interrupt Identification Register */
#define IO0602$B_COMB_LCR -1073351168   /* Line Control Register            */
#define IO0602$B_COMB_MCR -1073350656   /* Modem Control Register           */
#define IO0602$B_COMB_LSR -1073350144   /* Line Status Register             */
#define IO0602$B_COMB_MSR -1073349632   /* Modem Status Register            */
#define IO0602$B_COMB_SCR -1073349120   /* Scratch Register                 */
#define IO0602$B_LPT_REG0 -1073252352   /* Data Register                    */
#define IO0602$B_LPT_REG1 -1073251840   /* Status Register                  */
#define IO0602$B_LPT_REG2 -1073251328   /* Control Register                 */
#define IO0602$B_COMA_RBR -1073221632   /* Recieve Buffer Register          */
#define IO0602$B_COMA_THR -1073221632   /* Transmitter Holding Register     */
#define IO0602$B_COMA_DLL -1073221632   /* Divisor Latch Register(LSB)      */
#define IO0602$B_COMA_DLM -1073221120   /* Divisor Latch Register(MSB)      */
#define IO0602$B_COMA_IER -1073221120   /* Interrupt Enable Register        */
#define IO0602$B_COMA_FCR -1073220608   /*                                  */
#define IO0602$B_COMA_IIR -1073220608   /* Interrupt Identification Register */
#define IO0602$B_COMA_LCR -1073220096   /* Line Control Register            */
#define IO0602$B_COMA_MCR -1073219584   /* Modem Control Register           */
#define IO0602$B_COMA_LSR -1073219072   /* Line Status Register             */
#define IO0602$B_COMA_MSR -1073218560   /* Modem Status Register            */
#define IO0602$B_COMA_SCR -1073218048   /* Scratch Register                 */
#define IO0602$Q_EISA_CONFIG_DATA -1409286144
#define IO0602$Q_EISA_CONFIG_IRQ 107520
#define IO0602$Q_EISA_CONFIG_DMA 114688
#define IO0602$Q_EISA_CONFIG_MEM 76288
#define IO0602$Q_EISA_CONFIG_IO_PORT 102912
#define IO0602$Q_HOST_ADDR_EXT -805306368
#define IO0602$Q_SYS_CNTRL_REG -536870912
#define IO0602$Q_SPARE_REG -268435456
#define IO0602$Q_EISA_MEM_BASE 0
#define IO0602$Q_EISA_IO_BASE 0
#define IO0602$Q_EISA_IO_ISP 0          /* base addr of ISP chip(82357)     */
#define IO0602$B_DMA1_CH0_ADDR 0        /* 0 addr of DMA1 CH-0 Base and Current Address */
#define IO0602$B_DMA1_CH0_CNT 128       /* 1 addr of DMA1 CH-0 Base and Current Address */
#define IO0602$B_DMA1_CH1_ADDR 256      /* 2 addr of DMA1 CH-1 Base and Current Address */
#define IO0602$B_DMA1_CH1_CNT 384       /* 3 addr of DMA1 CH-1 Base and Current Address */
#define IO0602$B_DMA1_CH2_ADDR 512      /* 4 addr of DMA1 CH-2 Base and Current Address */
#define IO0602$B_DMA1_CH2_CNT 640       /* 5 addr of DMA1 CH-2 Base and Current Address */
#define IO0602$B_DMA1_CH3_ADDR 768      /* 6 addr of DMA1 CH-3 Base and Current Address */
#define IO0602$B_DMA1_CH3_CNT 896       /* 7 addr of DMA1 CH-3 Base and Current Address */
#define IO0602$B_DMA1_STATUS 1024       /* 8 addr of DMA1 status            */
#define IO0602$B_DMA1_WR_REQ 1152       /* 9 addr of DMA1 write request     */
#define IO0602$B_DMA1_WR_MASK 1280      /* A addr of DMA1 write single mask bit */
#define IO0602$B_DMA1_WR_MODE 1408      /* B addr of DMA1 write mode register */
#define IO0602$B_DMA1_CL_BYTE 1536      /* C addr of DMA1 clear byte pointer */
#define IO0602$B_DMA1_MASTER_CLR 1664   /* D addr of DMA1 master clear      */
#define IO0602$B_DMA1_CLR_MASK 1792     /* E addr of DMA1 clear mask reg    */
#define IO0602$B_DMA1_RW_MASK_REG 1920  /* F addr of DMA1 read/write all mask reg bits */
#define IO0602$B_INT_1_CNTRL 4096       /* 20 INT1 control register         */
#define IO0602$B_INT_1_MASK 4224        /* 21 INT1 mask register            */
#define IO0602$B_INTV_TIMER1 8192       /* 40 Interval Timer 1              */
#define IO0602$B_REF_REQ 8320           /* 41 Refresh Request Register      */
#define IO0602$B_SKR_TONE 8448          /* 42 Speaker Tone Register         */
#define IO0602$B_CMD_MODE 8576          /* 43 Command Mode Register         */
#define IO0602$B_INTV_TIMER2 9216       /* 48 Interval Timer 2              */
#define IO0602$B_SPD_CNTRL 9472         /* 4A CPU Speed Control             */
#define IO0602$B_CMD_MODE2 9600         /* 4B Command Mode Register         */
#define IO0602$B_NMI_STATUS 12416       /* 61 NMI Status                    */
#define IO0602$B_NMI_ENABLE 14336       /* 70 NMI Enable Register           */
#define IO0602$B_DMA_PAGE_R1 16384      /* 80 DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_CH2 16512     /* 81 DMA PAGE Register CH 2        */
#define IO0602$B_DMA_PAGE_CH3 16640     /* 82 DMA PAGE Register Ch 3        */
#define IO0602$B_DMA_PAGE_CH1 16768     /* 83 DMA PAGE Register Ch 1        */
#define IO0602$B_DMA_PAGE_R2 16896      /* 84 DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_R3 17024      /* 85 DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_R4 17152      /* 86 DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_CH0 17280     /* 87 DMA PAGE Register CH 0        */
#define IO0602$B_DMA_PAGE_R5 17408      /* 88 DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_CH6 17536     /* 89 DMA PAGE Register CH 6        */
#define IO0602$B_DMA_PAGE_CH7 17664     /* 8A DMA PAGE Register CH 7        */
#define IO0602$B_DMA_PAGE_CH5 17792     /* 8B DMA PAGE Register CH 5        */
#define IO0602$B_DMA_PAGE_R6 17920      /* 8C DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_R7 18048      /* 8D DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_R8 18176      /* 8E DMA PAGE Register(reserved)   */
#define IO0602$B_DMA_PAGE_REF 18304     /* 8F DMA PAGE Register Refresh Page */
#define IO0602$B_INT2_CNTRL 20480       /* A0 INT-2 control register        */
#define IO0602$B_INT2_MASK 20608        /* A1 INT-2 mask register           */
#define IO0602$B_DMA2_CH0_ADDR 24576    /* C0 addr of DMA2 CH-0 Base and Current Address */
#define IO0602$B_DMA2_CH0_CNT 24832     /* C2 addr of DMA2 CH-0 Base and Current Address */
#define IO0602$B_DMA2_CH1_ADDR 25088    /* C4 addr of DMA2 CH-1 Base and Current Address */
#define IO0602$B_DMA2_CH1_CNT 25344     /* C6 addr of DMA2 CH-1 Base and Current Address */
#define IO0602$B_DMA2_CH2_ADDR 25600    /* C8 addr of DMA2 CH-2 Base and Current Address */
#define IO0602$B_DMA2_CH2_CNT 25856     /* CA addr of DMA2 CH-2 Base and Current Address */
#define IO0602$B_DMA2_CH3_ADDR 26112    /* CC addr of DMA2 CH-3 Base and Current Address */
#define IO0602$B_DMA2_CH3_CNT 26368     /* CE addr of DMA2 CH-3 Base and Current Address */
#define IO0602$B_DMA2_STATUS 26624      /* D0 addr of DMA2 status           */
#define IO0602$B_DMA2_WR_REQ 26880      /* D2 addr of DMA2 write request    */
#define IO0602$B_DMA2_WR_MASK 27136     /* D4 addr of DMA2 write single mask bit */
#define IO0602$B_DMA2_WR_MODE 27392     /* D6 addr of DMA2 write mode register */
#define IO0602$B_DMA2_CL_BYTE 27648     /* D8 addr of DMA2 clear byte pointer */
#define IO0602$B_DMA2_MASTER_CLR 27904  /* DA addr of DMA2 master clear     */
#define IO0602$B_DMA2_CLR_MASK 28160    /* DC addr of DMA2 clear mask reg   */
#define IO0602$B_DMA2_RW_MASK_REG 28416 /* DE addr of DMA2 read/write all mask reg bits */
#define IO0602$B_DMA1_CH0_CNT_HIGH 131200 /* 401 DMA1 Ch0 base/current count high */
#define IO0602$B_DMA1_CH1_CNT_HIGH 131456 /* 403 DMA1 Ch1 base/current count high */
#define IO0602$B_DMA1_CH2_CNT_HIGH 131712 /* 405 DMA1 Ch2 base/current count high */
#define IO0602$B_DMA1_CH3_CNT_HIGH 131968 /* 407 DMA1 Ch3 base/current count high */
#define IO0602$B_DMA1_CHN_MODE 132352   /* 40A DMA1 Set Chaining Mode(w), Int status (r) */
#define IO0602$B_DMA1_WRT_MODE 132480   /* 40B DMA1 Ext Write Mode Reg      */
#define IO0602$B_DMA1_CHN_BUF_CNTRL 132608 /* 40C DMA1 Chain Buf Control    */
#define IO0602$B_DMA1_STEP_LVL 132736   /* 40D DMA1 Stepping LEvel Reg      */
#define IO0602$B_EXNMI_CNTRL 143488     /* 461 Extended NMI and reset control */
#define IO0602$B_NMI_IO_INT_PORT 143616 /* 462 NMI IO Int Port(casual)      */
#define IO0602$B_LAST_BUS_MSTR 143872   /* 464 LAst Bus MAster Granted      */
#define IO0602$B_DMA_CH2_HIGH_PAGE 147584 /* 481 DMA High Page Resgister CH-2 PAge */
#define IO0602$B_DMA_CH3_HIGH_PAGE 147712 /* 482 DMA High Page Resgister CH-3 PAge */
#define IO0602$B_DMA_CH1_HIGH_PAGE 147840 /* 483 DMA High Page Resgister CH-1 PAge */
#define IO0602$B_DMA_CH0_HIGH_PAGE 148352 /* 487 DMA High Page Resgister CH-0 PAge */
#define IO0602$B_DMA_CH6_HIGH_PAGE 148608 /* 489 DMA High Page Resgister CH-6 PAge */
#define IO0602$B_DMA_CH7_HIGH_PAGE 148736 /* 48A DMA High Page Resgister CH-7 PAge */
#define IO0602$B_DMA_CH5_HIGH_PAGE 148864 /* 48B DMA High Page Resgister CH-5 PAge */
#define IO0602$B_DMA_REG_REFRESH 149376 /* 48F DMA High Page Resgister Refresh */
#define IO0602$B_DMA2_CH5_CNT_HIGH 156416 /* 4C6 DMA2 Ch 5 base/current count high */
#define IO0602$B_DMA2_CH6_CNT_HIGH 156928 /* 4CA DMA2 Ch 6 base/current count high */
#define IO0602$B_DMA2_CH7_CNT_HIGH 157440 /* 4CE DMA2 Ch 7 base/current count high */
#define IO0602$B_INT1_LVL_CTRL 157696   /* 4D0 INT-1 Edge LEvel Control Reg */
#define IO0602$B_INT2_LVL_CTRL 157824   /* 4D1 INT-2 Edge LEvel Control Reg */
#define IO0602$B_DMA2_CHN_MODE 158208   /* 4D4 DMA2 Set chaining mode       */
#define IO0602$B_DMA2_EXT_WRT_MODE 158464 /* 4D6 DMA2 Ext Write Mode Reg    */
#define IO0602$B_DMA_CH0_STOP_7_2 159744 /* 4E0 DMA CH0 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH0_STOP_15_8 159872 /* 4E1 DMA CH0 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH0_STOP_23_16 160000 /* 4E2 DMA CH0 Stop Reg Bits<23:16> */
#define IO0602$B_DMA_CH1_STOP_7_2 160256 /* 4E4 DMA CH1 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH1_STOP_15_8 160384 /* 4E5 DMA CH1 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH1_STOP_23_16 160512 /* 4E6 DMA CH1 Stop Reg Bits<23:16> */
#define IO0602$B_DMA_CH2_STOP_7_2 160768 /* 4E8 DMA CH2 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH2_STOP_15_8 160896 /* 4E9 DMA CH2 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH2_STOP_23_16 161024 /* 4EA DMA CH2 Stop Reg Bits<23:16> */
#define IO0602$B_DMA_CH3_STOP_7_2 161280 /* 4EC DMA CH3 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH3_STOP_15_8 161408 /* 4ED DMA CH3 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH3_STOP_23_16 161536 /* 4EE DMA CH3 Stop Reg Bits<23:16> */
#define IO0602$B_DMA_CH5_STOP_7_2 162304 /* 4F4 DMA CH5 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH5_STOP_15_8 162432 /* 4F5 DMA CH5 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH5_STOP_23_16 162560 /* 4F6 DMA CH5 Stop Reg Bits<23:16> */
#define IO0602$B_DMA_CH6_STOP_7_2 162816 /* 4F8 DMA CH6 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH6_STOP_15_8 162944 /* 4F9 DMA CH6 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH6_STOP_23_16 163072 /* 4FA DMA CH6 Stop Reg Bits<23:16> */
#define IO0602$B_DMA_CH7_STOP_7_2 163328 /* 4FC DMA CH7 Stop Reg Bits<7:2>  */
#define IO0602$B_DMA_CH7_STOP_15_8 163456 /* 4FD DMA CH7 Stop Reg Bits<15:8> */
#define IO0602$B_DMA_CH7_STOP_23_16 163584 /* 4FE DMA CH7 Stop Reg Bits<23:16> */
#define IO0602$Q_EISA_SLOT1_BASE 524288 /* 1000                             */
#define IO0602$Q_EISA_SLOT2_BASE 1048576 /* 2000                            */
#define IO0602$Q_EISA_SLOT3_BASE 1572864 /* 3000                            */
#define IO0602$Q_EISA_SLOT4_BASE 2097152 /* 4000                            */
#define IO0602$Q_EISA_SLOT5_BASE 2621440 /* 5000                            */
#define IO0602$Q_EISA_SLOT6_BASE 3145728 /* 6000                            */
 
#pragma __member_alignment __restore
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __restore		 /* Restore the previously-defined required ptr size */
#endif
#ifdef __cplusplus
    }
#endif
#pragma __standard
 
#endif /* __IO0602DEF_LOADED */