/**/
/***************************************************************************/
/**                                                                       **/
/** © Copyright 2010, Hewlett-Packard Development Company, L.P.           **/
/**                                                                       **/
/** Confidential computer software.  Valid license from HP and/or         **/
/** its subsidiaries required for possession, use, or copying.            **/
/**                                                                       **/
/** Consistent with FAR 12.211 and 12.212, Commercial Computer Software,  **/
/** Computer Software Documentation, and Technical Data for Commercial    **/
/** Items are licensed to the U.S. Government under vendor's standard     **/
/** commercial license.                                                   **/
/**                                                                       **/
/** Neither HP nor any of its subsidiaries shall be liable for technical  **/
/** or editorial errors or omissions contained herein.  The information   **/
/** in this document is provided "as is" without warranty of any kind and **/
/** is subject to change without notice.  The warranties for HP products  **/
/** are set forth in the express limited warranty statements accompanying **/
/** such products.  Nothing herein should be construed as constituting an **/
/** additional warranty.                                                  **/
/**                                                                       **/
/***************************************************************************/
/********************************************************************************************************************************/
/* Created: 30-Mar-2010 17:26:40 by OpenVMS SDL EV3-3      */
/* Source:  13-JUL-1992 20:06:46 $1$DGA7274:[LIB_H.SRC]IO0402DEF.SDL;1 */
/********************************************************************************************************************************/
/*** MODULE $IO0402DEF ***/
#ifndef __IO0402DEF_LOADED
#define __IO0402DEF_LOADED 1
 
#pragma __nostandard			 /* This file uses non-ANSI-Standard features */
#pragma __member_alignment __save
#pragma __nomember_alignment
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __save		 /* Save the previously-defined required ptr size */
#pragma __required_pointer_size __short		 /* And set ptr size default to 32-bit pointers */
#endif
 
#ifdef __cplusplus
    extern "C" {
#define __unknown_params ...
#define __optional_params ...
#else
#define __unknown_params
#define __optional_params ...
#endif
 
#ifndef __struct
#if !defined(__VAXC)
#define __struct struct
#else
#define __struct variant_struct
#endif
#endif
 
#ifndef __union
#if !defined(__VAXC)
#define __union union
#else
#define __union variant_union
#endif
#endif
 
#define IO0402$Q_TC_NUMBER 1            /* Turbochannel number.             */
/* Upper lw of physical                                                     */
/* address                                                                  */
#define IO0402$Q_SCSI_CIR -804782080    /* SCSI Control Interrupts          */
#define IO0402$Q_SCSI_IMER -804782072   /* SCSI Interrupt Mask Enable       */
#define IO0402$Q_SCSI0_SDA -804773888   /* SCSI DMA Address                 */
#define IO0402$Q_SCSI0_SDIC -804773880  /* SCSI DMA Interrupt Control       */
#define IO0402$Q_SCSI0_DMA_UNAL0 -804773872 /* SCSI DMA Unaligned Data 0    */
#define IO0402$Q_SCSI0_DMA_UNAL1 -804773864 /* SCSI DMA Unaligned Data 1    */
#define IO0402$Q_SCSI1_SDA -804773376   /* SCSI DMA Address                 */
#define IO0402$Q_SCSI1_SDIC -804773368  /* SCSI DMA Interrupt Control       */
#define IO0402$Q_SCSI1_DMA_UNAL0 -804773360 /* SCSI DMA Unaligned Data 0    */
#define IO0402$Q_SCSI1_DMA_UNAL1 -804773352 /* SCSI DMA Unaligned Data 1    */
#define IO0402$Q_SCSI0_TC_LSB -804257792 /* SCSI Transfer Counter LSB       */
#define IO0402$Q_SCSI0_TC_MSB -804257784 /* SCSI Transfer Counter MSB       */
#define IO0402$Q_SCSI0_FIFO -804257776  /* SCSI FIFO                        */
#define IO0402$Q_SCSI0_CMD -804257768   /* SCSI Command                     */
#define IO0402$Q_SCSI0_STATUS -804257760 /* SCSI Status                     */
#define IO0402$Q_SCSI0_INTR -804257752  /* SCSI Interrupt/Timeout           */
#define IO0402$Q_SCSI0_SEQ -804257744   /* SCSI Sequence Step               */
#define IO0402$Q_SCSI0_FF -804257736    /* SCSI FIFO Flags                  */
#define IO0402$Q_SCSI0_CONFIG1 -804257728 /* SCSI Configuration 1           */
#define IO0402$Q_SCSI0_CC -804257720    /* SCSI reserved/Clock Conversion   */
#define IO0402$Q_SCSI0_TM -804257712    /* SCSI reserved/Test Mode          */
#define IO0402$Q_SCSI0_CONFIG2 -804257704 /* SCSI Configuration 2           */
#define IO0402$Q_SCSI0_CONFIG3 -804257696 /* SCSI Configuration 3           */
#define IO0402$Q_SCSI1_TC_LSB -804257280 /* SCSI Transfer Counter LSB       */
#define IO0402$Q_SCSI1_TC_MSB -804257272 /* SCSI Transfer Counter MSB       */
#define IO0402$Q_SCSI1_FIFO -804257264  /* SCSI FIFO                        */
#define IO0402$Q_SCSI1_CMD -804257256   /* SCSI Command                     */
#define IO0402$Q_SCSI1_STATUS -804257248 /* SCSI Status                     */
#define IO0402$Q_SCSI1_INTR -804257240  /* SCSI Interrupt                   */
#define IO0402$Q_SCSI1_SEQ -804257232   /* SCSI Sequence Step               */
#define IO0402$Q_SCSI1_FF -804257224    /* SCSI FIFO Flags                  */
#define IO0402$Q_SCSI1_CONFIG1 -804257216 /* SCSI Configuration 1           */
#define IO0402$Q_SCSI1_CC -804257208    /* SCSI reserved/Clock Conversion   */
#define IO0402$Q_SCSI1_TM -804257200    /* SCSI reserved/Test Mode          */
#define IO0402$Q_SCSI1_CONFIG2 -804257192 /* SCSI Configuration 2           */
#define IO0402$Q_SCSI1_CONFIG3 -804257184 /* SCSI Configuration 3           */
#define IO0402$Q_SCSI0_DMA -803733504   /* SCSI DMA Buffer                  */
#define IO0402$Q_SCSI1_DMA -803732992   /* SCSI DMA Buffer                  */
#define IO0402$Q_IOSLOT -738197504      /* IO Slot Configuration            */
#define IO0402$Q_TCCONFIG -738197488    /* TC Configuration                 */
#define IO0402$Q_FADR -738197472        /* Failing Address                  */
#define IO0402$Q_TCEREG -738197456      /* Turbochannel Error Register      */
#define IO0402$Q_MCR0 -734003200        /* Memory Configuration 0           */
#define IO0402$Q_MCR1 -733872128        /* Memory Configuration 1           */
#define IO0402$Q_MCR2 -733741056        /* Memory Configuration 2           */
#define IO0402$Q_MCR3 -733609984        /* Memory Configuration 3           */
#define IO0402$Q_MCR4 -733478912        /* Memory Configuration 4           */
#define IO0402$Q_MCR5 -733347840        /* Memory Configuration 5           */
#define IO0402$Q_MCR6 -733216768        /* Memory Configuration 6           */
#define IO0402$Q_MCR7 -733085696        /* Memory Configuration 7           */
#define IO0402$Q_IR -729808896          /* Interrupt Register               */
#define IO0402$Q_IC -725614592          /* Interrupt Cause                  */
#define IO0402$Q_SG_MAP -721420288      /* Scatter/Gather                   */
#define IO0402$Q_TCRESET -717225984     /* Turbochannel Reset               */
#define IO0402$Q_FLASH_EEPROM -268435456 /* CORE I/O ASIC registers - system ROM, part 2 */
#define IO0402$Q_IOCTL_CSR -267911168   /* CORE I/O base CSR address        */
#define IO0402$Q_LDP -267911104         /* Ethernet DMA pointer             */
#define IO0402$Q_SCOMM_TR -267911072    /* Serial comm transmit port 1 DMA pointer */
#define IO0402$Q_SCOMM_RC -267911040    /* Serial comm receive port 1 DMA pointer */
#define IO0402$Q_PRINTER_TR -267911008  /* Serial comm transmit port 2 DMA pointer */
#define IO0402$Q_PRINTER_RC -267910976  /* Serial comm receive port 2 DMA pointer */
#define IO0402$Q_ISDN_TR -267910912     /* ISDN transmit DMA pointer        */
#define IO0402$Q_ISDN_TR_BUF -267910880 /* ISDN transmit DMA buffer pointer */
#define IO0402$Q_ISDN_RC -267910848     /* ISDN receive DMA pointer         */
#define IO0402$Q_ISDN_RC_BUF -267910816 /* ISDN receive DMA buffer pointer  */
#define IO0402$Q_DATA0 -267910784       /* System Data Buffer 0             */
#define IO0402$Q_DATA1 -267910752       /* System Data Buffer 1             */
#define IO0402$Q_DATA2 -267910720       /* System Data Buffer 2             */
#define IO0402$Q_DATA3 -267910688       /* System Data Buffer 3             */
#define IO0402$Q_SSR -267910656         /* System support register          */
#define IO0402$Q_SIR -267910624         /* System interrupt register        */
#define IO0402$Q_SIMR -267910592        /* System interrupt mask register   */
#define IO0402$Q_SADR -267910560        /* System address register          */
#define IO0402$Q_ISDN_DATA_TR -267910528 /* ISDN Data Transmit              */
#define IO0402$Q_ISDN_DATA_RC -267910496 /* ISDN Data Receive               */
#define IO0402$Q_LANCE_SLOT -267910464  /* Lance slot register              */
#define IO0402$Q_SCC0_SLOT -267910400   /* SCC1 slot register               */
#define IO0402$Q_SCC1_SLOT -267910368   /* SCC0 slot register               */
#define IO0402$Q_NI_ADR_ROM -267386880  /* Ethernet address ROM             */
#define IO0402$Q_LANCE_RDP -266862592   /* Lance ethernet CSR               */
#define IO0402$Q_LANCE_RAP -266862584   /* Lance ethernet CSR               */
#define IO0402$Q_SCC0B_COMM_RAP -266338304 /* Comm Port 1 RAP               */
#define IO0402$Q_SCC0B_COMM_DATA -266338296 /* Comm Port 1 data             */
#define IO0402$Q_SCC0A_MOUSE_RAP -266338288 /* Mouse RAP                    */
#define IO0402$Q_SCC0A_MOUSE_DATA -266338280 /* Mouse port data register    */
#define IO0402$Q_SCC1B_PRINTER_RAP -265289728 /* Comm Port 2 RAP            */
#define IO0402$Q_SCC1B_PRINTER_DATA -265289720 /* Comm Port 2 data          */
#define IO0402$Q_SCC1A_KEY_RAP -265289712 /* Keyboard RAP                   */
#define IO0402$Q_SCC1A_KEY_DATA -265289704 /* Keyboard port data register   */
#define IO0402$Q_RTC_SEC -264241152     /* TOY clock CSR--seconds           */
#define IO0402$Q_RTC_ALMS -264241144    /* TOY clock CSR--seconds alarm     */
#define IO0402$Q_RTC_MIN -264241136     /* TOY clock CSR--minutes           */
#define IO0402$Q_RTC_ALMN -264241128    /* TOY clock CSR--minutes alarm     */
#define IO0402$Q_RTC_HOUR -264241120    /* TOY clock CSR--hours             */
#define IO0402$Q_RTC_ALMH -264241112    /* TOY clock CSR--hours alarm       */
#define IO0402$Q_RTC_DOW -264241104     /* TOY clock CSR--day of week       */
#define IO0402$Q_RTC_DAY -264241096     /* TOY clock CSR--date of month     */
#define IO0402$Q_RTC_MON -264241088     /* TOY clock CSR--month             */
#define IO0402$Q_RTC_YEAR -264241080    /* TOY clock CSR--year              */
#define IO0402$Q_RTC_REGA -264241072    /* TOY clock CSR--register A        */
#define IO0402$Q_RTC_REGB -264241064    /* TOY clock CSR--register B        */
#define IO0402$Q_RTC_REGC -264241056    /* TOY clock CSR--register C        */
#define IO0402$Q_RTC_REGD -264241048    /* TOY clock CSR--register D        */
#define IO0402$Q_RTC_RAM -264241040     /* TOY clock CSR--base of BBU RAM   */
#define IO0402$Q_ISDN_AUDIO -263716864  /* ISDN audio chip CSR              */
#define IO0402$Q_SYSTEM_EEPROM -201326592 /* base of system ROM, part 1     */
#define IO0402$Q_CPYBUF0 -199229440
#define IO0402$Q_CPYBUF1 -199229432
#define IO0402$Q_CPYBUF2 -199229424
#define IO0402$Q_CPYBUF3 -199229416
#define IO0402$Q_CPYBUF4 -199229408
#define IO0402$Q_CPYBUF5 -199229400
#define IO0402$Q_CPYBUF6 -199229392
#define IO0402$Q_CPYBUF7 -199229384
#define IO0402$Q_FG -199229376
#define IO0402$Q_BG -199229368
#define IO0402$Q_PLANEMASK -199229360
#define IO0402$Q_PIXMASK -199229352
#define IO0402$Q_MODE -199229344
#define IO0402$Q_BOOLOP -199229336
#define IO0402$Q_PIXSHIFT -199229328
#define IO0402$Q_ADDR_REG -199229320
#define IO0402$Q_BRES1 -199229312
#define IO0402$Q_BRES2 -199229304
#define IO0402$Q_BRES3 -199229296
#define IO0402$Q_BCONT -199229288
#define IO0402$Q_DEEP -199229280
#define IO0402$Q_START -199229272
#define IO0402$Q_CI -199229264
#define IO0402$Q_V_REF_COUNT -199229248
#define IO0402$Q_V_HOR -199229240
#define IO0402$Q_V_VER -199229232
#define IO0402$Q_VV -199229216
#define IO0402$Q_EI -199229208
#define IO0402$Q_TCCLK_COUNT -199229200
#define IO0402$Q_VIDCLK_COUNT -199229192
#define IO0402$Q_RAMDAC_ADDR_LO -197656576
#define IO0402$Q_RAMDAC_ADDR_HI -197656568
#define IO0402$Q_RAMDAC_REG_ADDR -197656560
#define IO0402$Q_RAMDAC_MAP_LOC -197656552
#define IO0402$Q_FB -501219328
#define IO0402$Q_SLOT0_DENSE_BASE 0
#define IO0402$Q_SLOT1_DENSE_BASE 536870912
#define IO0402$Q_SLOT2_DENSE_BASE 1073741824
#define IO0402$Q_SLOT3_DENSE_BASE 1610612736
#define IO0402$Q_SLOT4_DENSE_BASE -2147483648
#define IO0402$Q_SLOT5_DENSE_BASE -1610612736
#define IO0402$Q_SLOT6_DENSE_BASE -1073741824
#define IO0402$Q_SLOT7_DENSE_BASE -536870912
#define IO0402$Q_CXTURBO_DENSE_BASE -503316480
#define IO0402$Q_SLOT0_SPARSE_BASE 268435456
#define IO0402$Q_SLOT1_SPARSE_BASE 805306368
#define IO0402$Q_SLOT2_SPARSE_BASE 1342177280
#define IO0402$Q_SLOT3_SPARSE_BASE 1879048192
#define IO0402$Q_SLOT4_SPARSE_BASE -1879048192
#define IO0402$Q_SLOT5_SPARSE_BASE -1342177280
#define IO0402$Q_SLOT6_SPARSE_BASE -805306368
#define IO0402$Q_SLOT7_SPARSE_BASE -268435456
#define IO0402$Q_LDP_DENSE -536608736   /* Ethernet DMA pointer             */
#define IO0402$Q_NI_ADR_ROM_DENSE -536346624 /* Ethernet address ROM        */
#define IO0402$Q_LANCE_RDP_DENSE -536084480 /* Lance ethernet CSR           */
#define IO0402$Q_IMASK_READ -1035993088 /* IR dense space                   */
#define IO0402$Q_SG_DENSE -1031675904   /* Base of last page of SG dense space */
 
#pragma __member_alignment __restore
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __restore		 /* Restore the previously-defined required ptr size */
#endif
#ifdef __cplusplus
    }
#endif
#pragma __standard
 
#endif /* __IO0402DEF_LOADED */