/**/
/***************************************************************************/
/**                                                                       **/
/** © Copyright 2010, Hewlett-Packard Development Company, L.P.           **/
/**                                                                       **/
/** Confidential computer software.  Valid license from HP and/or         **/
/** its subsidiaries required for possession, use, or copying.            **/
/**                                                                       **/
/** Consistent with FAR 12.211 and 12.212, Commercial Computer Software,  **/
/** Computer Software Documentation, and Technical Data for Commercial    **/
/** Items are licensed to the U.S. Government under vendor's standard     **/
/** commercial license.                                                   **/
/**                                                                       **/
/** Neither HP nor any of its subsidiaries shall be liable for technical  **/
/** or editorial errors or omissions contained herein.  The information   **/
/** in this document is provided "as is" without warranty of any kind and **/
/** is subject to change without notice.  The warranties for HP products  **/
/** are set forth in the express limited warranty statements accompanying **/
/** such products.  Nothing herein should be construed as constituting an **/
/** additional warranty.                                                  **/
/**                                                                       **/
/***************************************************************************/
/********************************************************************************************************************************/
/* Created: 30-Mar-2010 17:26:40 by OpenVMS SDL EV3-3      */
/* Source:  13-JUN-1992 19:05:33 $1$DGA7274:[LIB_H.SRC]IO0302DEF.SDL;1 */
/********************************************************************************************************************************/
/*** MODULE $IO0302DEF ***/
#ifndef __IO0302DEF_LOADED
#define __IO0302DEF_LOADED 1
 
#pragma __nostandard			 /* This file uses non-ANSI-Standard features */
#pragma __member_alignment __save
#pragma __nomember_alignment
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __save		 /* Save the previously-defined required ptr size */
#pragma __required_pointer_size __short		 /* And set ptr size default to 32-bit pointers */
#endif
 
#ifdef __cplusplus
    extern "C" {
#define __unknown_params ...
#define __optional_params ...
#else
#define __unknown_params
#define __optional_params ...
#endif
 
#ifndef __struct
#if !defined(__VAXC)
#define __struct struct
#else
#define __struct variant_struct
#endif
#endif
 
#ifndef __union
#if !defined(__VAXC)
#define __union union
#else
#define __union variant_union
#endif
#endif
 
#define IO0302$L_UART0A_RR0 -201326592
#define IO0302$L_UART0A_RR8 -201326528
#define IO0302$L_UART0B_RR0 -201326464
#define IO0302$L_UART0B_RR8 -201326400
#define IO0302$L_UART1B_RR0 -192937984
#define IO0302$L_UART1B_RR8 -192937920
#define IO0302$L_UART1A_RR0 -192937856
#define IO0302$L_UART1A_RR8 -192937792
#define IO0302$L_UART2B_RR0 -184549376
#define IO0302$L_UART2B_RR8 -184549312
#define IO0302$L_UART2A_RR0 -184549248
#define IO0302$L_UART2A_RR8 -184549184
#define IO0302$L_WATCH_SECONDS -167772160
#define IO0302$L_WATCH_MINUTES -167772032
#define IO0302$L_WATCH_HOURS -167771904
#define IO0302$L_WATCH_DAY_OF_MONTH -167771712
#define IO0302$L_WATCH_MONTH -167771648
#define IO0302$L_WATCH_YEAR -167771584
#define IO0302$L_WATCH_CSRA -167771520
#define IO0302$L_WATCH_CSRB -167771456
#define IO0302$L_WATCH_CSRC -167771392
#define IO0302$L_WATCH_CSRD -167771328
#define IO0302$L_WATCH_RAM -167771264
#define IO0302$L_GBUS_WHAMI -150994944
#define IO0302$L_GBUS_LEDS -150994880
#define IO0302$L_GBUS_PMASK -150994816
#define IO0302$L_GBUS_INTR -150994752
#define IO0302$L_GBUS_HALT -150994688
#define IO0302$L_GBUS_LSBRST -150994624
#define IO0302$L_GBUS_MISC -150994560
#define IO0302$L_GBUS_RMODE_ENA -142606336
#define IO0302$L_SLOT0_LDEV -134217728  /* DEVICE                           */
#define IO0302$L_SLOT0_LBER -134217664  /* ERROR                            */
#define IO0302$L_SLOT0_LCNF -134217600  /* CONFIGURATION                    */
#define IO0302$L_SLOT0_IBR -134217536   /* REPAIR                           */
#define IO0302$L_SLOT0_LMMR0 -134217216 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT0_LMMR1 -134217152 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT0_LMMR2 -134217088 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT0_LMMR3 -134217024 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT0_LMMR4 -134216960 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT0_LMMR5 -134216896 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT0_LMMR6 -134216832 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT0_LMMR7 -134216768 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT0_LBESR0 -134216192 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT0_LBESR1 -134216128 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT0_LBESR2 -134216064 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT0_LBESR3 -134216000 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT0_LBECR0 -134215936 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT0_LBECR1 -134215872 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT1_LDEV -130023424  /* DEVICE REG                       */
#define IO0302$L_SLOT1_LBER -130023360  /* ERROR                            */
#define IO0302$L_SLOT1_LCNF -130023296  /* CONFIGURATION                    */
#define IO0302$L_SLOT1_IBR -130023232   /* REPAIR                           */
#define IO0302$L_SLOT1_LMMR0 -130022912 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT1_LMMR1 -130022848 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT1_LMMR2 -130022784 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT1_LMMR3 -130022720 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT1_LMMR4 -130022656 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT1_LMMR5 -130022592 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT1_LMMR6 -130022528 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT1_LMMR7 -130022464 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT1_LBESR0 -130021888 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT1_LBESR1 -130021824 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT1_LBESR2 -130021760 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT1_LBESR3 -130021696 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT1_LBECR0 -130021632 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT1_LBECR1 -130021568 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT2_LDEV -125829120  /* DEVICE REG                       */
#define IO0302$L_SLOT2_LBER -125829056  /* ERROR                            */
#define IO0302$L_SLOT2_LCNF -125828992  /* CONFIGURATION                    */
#define IO0302$L_SLOT2_IBR -125828928   /* REPAIR                           */
#define IO0302$L_SLOT2_LMMR0 -125828608 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT2_LMMR1 -125828544 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT2_LMMR2 -125828480 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT2_LMMR3 -125828416 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT2_LMMR4 -125828352 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT2_LMMR5 -125828288 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT2_LMMR6 -125828224 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT2_LMMR7 -125828160 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT2_LBESR0 -125827584 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT2_LBESR1 -125827520 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT2_LBESR2 -125827456 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT2_LBESR3 -125827392 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT2_LBECR0 -125827328 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT2_LBECR1 -125827264 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT3_LDEV -121634816  /* DEVICE REG                       */
#define IO0302$L_SLOT3_LBER -121634752  /* ERROR                            */
#define IO0302$L_SLOT3_LCNF -121634688  /* CONFIGURATION                    */
#define IO0302$L_SLOT3_IBR -121634624   /* REPAIR                           */
#define IO0302$L_SLOT3_LMMR0 -121634304 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT3_LMMR1 -121634240 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT3_LMMR2 -121634176 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT3_LMMR3 -121634112 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT3_LMMR4 -121634048 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT3_LMMR5 -121633984 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT3_LMMR6 -121633920 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT3_LMMR7 -121633856 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT3_LBESR0 -121633280 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT3_LBESR1 -121633216 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT3_LBESR2 -121633152 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT3_LBESR3 -121633088 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT3_LBECR0 -121633024 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT3_LBECR1 -121632960 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT4_LDEV -117440512  /* DEVICE REG                       */
#define IO0302$L_SLOT4_LBER -117440448  /* ERROR                            */
#define IO0302$L_SLOT4_LCNF -117440384  /* CONFIGURATION                    */
#define IO0302$L_SLOT4_IBR -117440320   /* REPAIR                           */
#define IO0302$L_SLOT4_LMMR0 -117440000 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT4_LMMR1 -117439936 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT4_LMMR2 -117439872 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT4_LMMR3 -117439808 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT4_LMMR4 -117439744 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT4_LMMR5 -117439680 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT4_LMMR6 -117439616 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT4_LMMR7 -117439552 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT4_LBESR0 -117438976 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT4_LBESR1 -117438912 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT4_LBESR2 -117438848 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT4_LBESR3 -117438784 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT4_LBECR0 -117438720 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT4_LBECR1 -117438656 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT5_LDEV -113246208  /* DEVICE REG                       */
#define IO0302$L_SLOT5_LBER -113246144  /* ERROR                            */
#define IO0302$L_SLOT5_LCNF -113246080  /* CONFIGURATION                    */
#define IO0302$L_SLOT5_IBR -113246016   /* REPAIR                           */
#define IO0302$L_SLOT5_LMMR0 -113245696 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT5_LMMR1 -113245632 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT5_LMMR2 -113245568 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT5_LMMR3 -113245504 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT5_LMMR4 -113245440 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT5_LMMR5 -113245376 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT5_LMMR6 -113245312 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT5_LMMR7 -113245248 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT5_LBESR0 -113244672 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT5_LBESR1 -113244608 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT5_LBESR2 -113244544 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT5_LBESR3 -113244480 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT5_LBECR0 -113244416 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT5_LBECR1 -113244352 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT6_LDEV -109051904  /* DEVICE REG                       */
#define IO0302$L_SLOT6_LBER -109051840  /* ERROR                            */
#define IO0302$L_SLOT6_LCNF -109051776  /* CONFIGURATION                    */
#define IO0302$L_SLOT6_IBR -109051712   /* REPAIR                           */
#define IO0302$L_SLOT6_LMMR0 -109051392 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT6_LMMR1 -109051328 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT6_LMMR2 -109051264 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT6_LMMR3 -109051200 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT6_LMMR4 -109051136 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT6_LMMR5 -109051072 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT6_LMMR6 -109051008 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT6_LMMR7 -109050944 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT6_LBESR0 -109050368 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT6_LBESR1 -109050304 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT6_LBESR2 -109050240 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT6_LBESR3 -109050176 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT6_LBECR0 -109050112 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT6_LBECR1 -109050048 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT7_LDEV -104857600  /* DEVICE REG                       */
#define IO0302$L_SLOT7_LBER -104857536  /* ERROR                            */
#define IO0302$L_SLOT7_LCNF -104857472  /* CONFIGURATION                    */
#define IO0302$L_SLOT7_IBR -104857408   /* REPAIR                           */
#define IO0302$L_SLOT7_LMMR0 -104857088 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT7_LMMR1 -104857024 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT7_LMMR2 -104856960 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT7_LMMR3 -104856896 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT7_LMMR4 -104856832 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT7_LMMR5 -104856768 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT7_LMMR6 -104856704 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT7_LMMR7 -104856640 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT7_LBESR0 -104856064 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT7_LBESR1 -104856000 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT7_LBESR2 -104855936 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT7_LBESR3 -104855872 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT7_LBECR0 -104855808 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT7_LBECR1 -104855744 /* BUS ERROR COMMAND 1             */
#define IO0302$L_SLOT8_LDEV -100663296  /* DEVICE REG                       */
#define IO0302$L_SLOT8_LBER -100663232  /* ERROR                            */
#define IO0302$L_SLOT8_LCNF -100663168  /* CONFIGURATION                    */
#define IO0302$L_SLOT8_IBR -100663104   /* REPAIR                           */
#define IO0302$L_SLOT8_LMMR0 -100662784 /* MEM MAPPING 0                    */
#define IO0302$L_SLOT8_LMMR1 -100662720 /* MEM MAPPING 1                    */
#define IO0302$L_SLOT8_LMMR2 -100662656 /* MEM MAPPING 2                    */
#define IO0302$L_SLOT8_LMMR3 -100662592 /* MEM MAPPING 3                    */
#define IO0302$L_SLOT8_LMMR4 -100662528 /* MEM MAPPING 4                    */
#define IO0302$L_SLOT8_LMMR5 -100662464 /* MEM MAPPING 5                    */
#define IO0302$L_SLOT8_LMMR6 -100662400 /* MEM MAPPING 6                    */
#define IO0302$L_SLOT8_LMMR7 -100662336 /* MEM MAPPING 7                    */
#define IO0302$L_SLOT8_LBESR0 -100661760 /* BUS ERROR SYNDROME 0            */
#define IO0302$L_SLOT8_LBESR1 -100661696 /* BUS ERROR SYNDROME 1            */
#define IO0302$L_SLOT8_LBESR2 -100661632 /* BUS ERROR SYNDROME 2            */
#define IO0302$L_SLOT8_LBESR3 -100661568 /* BUS ERROR SYNDROME 3            */
#define IO0302$L_SLOT8_LBECR0 -100661504 /* BUS ERROR COMMAND 0             */
#define IO0302$L_SLOT8_LBECR1 -100661440 /* BUS ERROR COMMAND 1             */
#define IO0302$L_LILID0 -100660736      /* INTERRUPT LEVEL0 IDENT           */
#define IO0302$L_LILID1 -100660672      /* INTERRUPT LEVEL1 IDENT           */
#define IO0302$L_LILID2 -100660608      /* INTERRUPT LEVEL2 IDENT           */
#define IO0302$L_LILID3 -100660544      /* INTERRUPT LEVEL3 IDENT           */
#define IO0302$L_LCPUMASK -100660480    /* CPU INTERRUPT MASK               */
#define IO0302$L_LMBPR -100660224       /* MAILBOX POINTER                  */
#define IO0302$L_IPCNSE -100655104      /* IO Port Chip Error               */
#define IO0302$L_IPCVR -100655040       /* IO Port Chip Vector              */
#define IO0302$L_IPCMSR -100654976      /* IO Port Chip Mode Select         */
#define IO0302$L_IPCHST -100654912      /* IO Port Chip Hose Status         */
#define IO0302$L_IPCDR -100654848       /* IO Port Chip Diagnostic          */
#define IO0302$L_LIOINTR -33554432      /* IO Interrupt reg                 */
#define IO0302$L_LIPINTR -33554368      /* IP Interrupt reg                 */
 
#pragma __member_alignment __restore
#ifdef __INITIAL_POINTER_SIZE			 /* Defined whenever ptr size pragmas supported */
#pragma __required_pointer_size __restore		 /* Restore the previously-defined required ptr size */
#endif
#ifdef __cplusplus
    }
#endif
#pragma __standard
 
#endif /* __IO0302DEF_LOADED */