/* * IDENT X-2A1 * * Copyright (C) 1996 by * Digital Equipment Corporation, Maynard, Massachusetts. * All rights reserved. * * This software is furnished under a license and may be used and copied * only in accordance of the terms of such license and with the * inclusion of the above copyright notice. This software or any other * copies thereof may not be provided or otherwise made available to any * other person. No title to and ownership of the software is hereby * transferred. * * The information in this software is subject to change without notice * and should not be construed as a commitment by Digital Equipment * Corporation. * * Digital assumes no responsibility for the use or reliability of its * software on equipment which is not supplied by Digital. * * * Abstract: * * This file contains various definitions for use with IIC device * driver (IIDRIVER). * * Authors: * * Paul A. Jacobi, May 1997 * * Modified by: * * X-2A1 PAJ1012 Paul A. Jacobi 01-Sep-1998 * Add definitions for Goldrush server management registers. * * X-2 PAJ0942 Paul A. Jacobi 11-Jun-1997 * Define IIC_R_PSR_TEMP_MASK bitmask. * */ #ifndef __IIC_IOCTL_LOADED #define __IIC_IOCTL_LOADED 1 #endif /* * The following IOCTL codes are supported: * */ /* Read functions */ #define II_IOCTL_READ_TEMPERATURE 1 #define II_IOCTL_READ_POWER_STATUS 2 #define II_IOCTL_READ_FAN_STATUS 3 #define II_IOCTL_READ_OCP_TEXT 4 /* All write function codes must be less than zero */ #define II_IOCTL_WRITE_OCP_TEXT -1 /* Define buffer size for each function */ #define II_LENGTH_READ_TEMPERATURE 16 #define II_LENGTH_READ_POWER_STATUS 16 #define II_LENGTH_READ_FAN_STATUS 16 #define II_LENGTH_READ_OCP_TEXT 16 #define II_LENGTH_WRITE_OCP_TEXT 16 #define IIDRIVER_MAX_BUFFER_SIZE 256 /* * Known IIC node addresses for Sable and Mikasa */ #define IIC_CONT 0xB6 #define IIC_OCP0 0x40 #define IIC_OCP1 0x42 /* * Known IIC node addresses for Sable. Note CPU3 and MEM1 share the same * physical slot and have the same IIC node address. */ #define IIC_MEM0 0xA0 #define IIC_MEM1 0xA2 #define IIC_MEM2 0xA4 #define IIC_MEM3 0xA6 #define IIC_CPU0 0xA8 #define IIC_CPU1 0xAA #define IIC_CPU2 0xAE #define IIC_CPU3 0xA2 #define IIC_IO 0xAC #define IIC_PSC 0x46 /* IIC node addresses for Rawhide */ #define IIC_R_GCD 0xA0 // GCD module #define IIC_R_MB 0xA2 // Motherboard #define IIC_R_CPU0 0xA4 // CPU 0 #define IIC_R_CPU1 0xA6 // CPU 1 #define IIC_R_H0 0xA8 // Horse 0 #define IIC_R_S0 0xAA // Saddle 0 #define IIC_R_CPU2 0xAC // CPU 2/Horse 1 #define IIC_R_CPU3 0xAE // CPU 3/Saddle 1 #define IIC_R_OCP0 0x40 // OCP controller #define IIC_R_OCP1 0x42 // OCP controller #define IIC_R_MEM0 0x48 // Memory pair 0 #define IIC_R_MEM1 0x4A // Memory pair 1 #define IIC_R_MEM2 0x4C // Memory pair 2 #define IIC_R_MEM3 0x4E // Memory pair 3 #define IIC_R_FFR 0x70 // Failing fan and power supply register #define IIC_R_PSR 0x72 // Fan/Temp/Power Sensor function register #define IIC_R_FFR_PS0_MASK 0x80 /* Power supply 0, 0=present, 1=NA */ #define IIC_R_FFR_PS1_MASK 0x10 /* Power supply 1, 0=present, 1=NA */ #define IIC_R_FFR_PS2_MASK 0x40 /* Power supply 2, 0=present, 1=NA */ #define IIC_R_PSR_PS0_MASK 0x20 /* Power supply 0, 0=good, 1=bad */ #define IIC_R_PSR_PS1_MASK 0x40 /* Power supply 1, 0=good, 1=bad */ #define IIC_R_PSR_PS2_MASK 0x80 /* Power supply 2, 0=good, 1=bad */ #define IIC_R_PSR_TEMP_MASK 0x01 /* Temperature warning status, 1=OK */ #define IIC_R_PSR_SYSFAN_MASK 0x02 /* System fan status, 1=OK */ #define IIC_R_PSR_CPUFAN_MASK 0x08 /* CPU fan status, 1=OK */ /* Define KCSRM addresses */ #define IIC_KCRSM_TEMP 0x9E /* Temperature Sensor */ #define IIC_KCRSM_NVRAM0 0xC0 /* NVRAM location 0 */ #define IIC_KCRSM_NVRAM1 0xC2 /* NVRAM location 1 */ #define IIC_KCRSM_NVRAM2 0xC4 /* NVRAM location 2 */ #define IIC_KCRSM_NVRAM3 0xC6 /* NVRAM location 3 */ #define IIC_KCRSM_NVRAM4 0xC8 /* NVRAM location 4 */ #define IIC_KCRSM_NVRAM5 0xCA /* NVRAM location 5 */ #define IIC_KCRSM_NVRAM6 0xCC /* NVRAM location 6 */ #define IIC_KCRSM_NVRAM7 0xCE /* NVRAM location 7 */ /* IIC node addresses for Goldrush */ #define IIC_G_MB 0xA2 // Motherboard #define IIC_G_CPU0 0xA4 // CPU 0 #define IIC_G_CPU1 0xA6 // CPU 1 #define IIC_G_OCP0 0x40 // OCP controller #define IIC_G_OCP1 0x42 // OCP controller #define IIC_G_MEM0 0x48 // Memory pair 0 #define IIC_G_MEM1 0x4A // Memory pair 1 #define IIC_G_MEM2 0x4C // Memory pair 2 #define IIC_G_MEM3 0x4E // Memory pair 3 #define IIC_G_FFR 0x70 // Failing fan and power supply register #define IIC_G_PSR 0x72 // Fan/Temp/Power Sensor function register #define IIC_G_FFR_PS0_MASK 0x80 /* Power supply 0, 0=present, 1=NA */ #define IIC_G_FFR_PS1FT_MASK 0x10 /* PS1 or fan tray, 0=present, 1=NA */ #define IIC_G_PSR_TEMP_MASK 0x01 /* Temperature warning status, 1=OK */ #define IIC_G_PSR_SYSFAN_MASK 0x02 /* System fan status, 1=OK */ #define IIC_G_PSR_CPUFAN_MASK 0x08 /* CPU fan status, 1=OK */ #define IIC_G_PSR_FT_MASK 0x10 /* Fan Tray, 0=good, 1=bad */ #define IIC_G_PSR_PS0_MASK 0x20 /* Power supply 0, 0=good, 1=bad */ #define IIC_G_PSR_PS1_MASK 0x40 /* Power supply 1, 0=good, 1=bad */