/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:26 by OpenVMS SDL EV3-3 */ /* Source: 04-MAY-2009 04:04:55 $1$DGA7274:[LIB_H.SRC]HWRPBDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $HWRPBDEF ***/ #ifndef __HWRPBDEF_LOADED #define __HWRPBDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #ifndef __ALPHA #ifdef EFI64 #pragma pack(push,hwrpbdef) #pragma pack(8) #pragma warning(disable:4068) #endif #endif /*IA64 */ /* Verified for IA64 port - WBF */ #define EXE$K_SECBOOT 0 /* Address of secondary boot */ #define EXE$K_HWRPB 268435456 /* Address of HWRPB = 256Mb */ #define EXE$K_PRIMBOOT 536870912 /* Address of primary bootstrap */ #define EXE$K_NETBOOT 805306368 /* Address of network bootstrap */ #define EXE$K_DEBUGBOOT 939524096 /* Address of debug bootstrap */ #define EXE$K_BOOTPT 1073741824 /* Fixed addr. of page tbl =1Gb */ /* */ /* Main HWRPB definition */ /* */ #define HWRPB_SYSTYPE$K_ADU 1 /* 1 Alpha Demonstation Unit-proto */ #define HWRPB_SYSTYPE$K_COBRA 2 /* 2 Similar to MicroVAX */ #define HWRPB_SYSTYPE$K_LASER 3 /* 3 Similar to Calypso */ #define HWRPB_SYSTYPE$K_FLAMINGO 4 /* 4 Similar to PV2 workstation */ #define HWRPB_SYSTYPE$K_MANNEQUIN 5 /* 5 Manniquin simulator */ #define HWRPB_SYSTYPE$K_JENSEN 6 /* 6 EISA PC/Server */ #define HWRPB_SYSTYPE$K_PELICAN 7 /* 7 Turbochannel workstation */ #define HWRPB_SYSTYPE$K_MORGAN 8 /* 8 PCI based system */ #define HWRPB_SYSTYPE$K_SABLE 9 /* 9 PCI server follow-on to Cobra */ #define HWRPB_SYSTYPE$K_MEDULLA 10 /* A Single board computer */ #define HWRPB_SYSTYPE$K_WHITEGABLES 11 /* B Single board computer */ #define HWRPB_SYSTYPE$K_TURBOLASER 12 /* C Next generation laser */ #define HWRPB_SYSTYPE$K_AVANTI 13 /* D PCI-ISA EV4 */ #define HWRPB_SYSTYPE$K_MUSTANG 14 /* E PCI-ISA LCA */ #define HWRPB_SYSTYPE$K_ALCOR 15 /* F EV5,PCI workstation */ #define HWRPB_SYSTYPE$K_TRADEWIND 16 /* 10 EV4 based system */ #define HWRPB_SYSTYPE$K_MIKASA 17 /* 11 PCI-EISA EV4 based server */ #define HWRPB_SYSTYPE$K_EB64 18 /* 12 EV4 single-board system */ #define HWRPB_SYSTYPE$K_EB66 19 /* 13 LCA Single-board system */ #define HWRPB_SYSTYPE$K_EB64P 20 /* 14 Enhanced single-board system */ #define HWRPB_SYSTYPE$K_BURNS 21 /* 15 LCA Laptop system */ #define HWRPB_SYSTYPE$K_RAWHIDE 22 /* 16 EV5 Based SMP Server */ #define HWRPB_SYSTYPE$K_K2 23 /* 17 EV45 PCI/ISA SBC */ #define HWRPB_SYSTYPE$K_LYNX 24 /* 18 Sable/Gamma with more I/O */ #define HWRPB_SYSTYPE$K_ALPHA_XL 25 /* 19 No OpenVMS Support */ #define HWRPB_SYSTYPE$K_EB164 26 /* 1A EV5 Single-board system */ #define HWRPB_SYSTYPE$K_NORITAKE 27 /* 1B Noritake PCI-EISA EV45 server */ #define HWRPB_SYSTYPE$K_CORTEX 28 /* 1C No OpenVMS Support */ #define HWRPB_SYSTYPE$K_UNDEFINED_1 29 /* 1D Undefined at this time */ #define HWRPB_SYSTYPE$K_MIATA 30 /* 1E EV56 WorkStation */ #define HWRPB_SYSTYPE$K_XXM 31 /* 1F No OpenVMS Support */ #define HWRPB_SYSTYPE$K_TAKARA 32 /* 20 EV56 PCI/ISA SBC */ #define HWRPB_SYSTYPE$K_YUKON 33 /* 21 No OpenVMS Support */ #define HWRPB_SYSTYPE$K_TSUNAMI 34 /* 22 Tsunami-based platforms */ #define HWRPB_SYSTYPE$K_WILDFIRE 35 /* 23 Wildfire */ #define HWRPB_SYSTYPE$K_CUSCO 36 /* 24 CUSCO Compact PCI */ #define HWRPB_SYSTYPE$K_EIGER 37 /* 25 Eiger */ #define HWRPB_SYSTYPE$K_TITAN 38 /* 26 Titan-based platforms */ #define HWRPB_SYSTYPE$K_MARVEL 39 /* 27 Marvel */ #define HWRPB_SYSTYPE$K_PHOENIX 40 /* 28 Phoenix */ #define HWRPB_SYSTYPE$K_MAX_SYSTYPE 40 /* */ #define HWRPB$M_MPCAP 0x1 #define HWRPB$M_CNSLE 0x2 #define HWRPB$M_PWRFL 0x20 #define HWRPB$M_PWRFL_RESTART 0x100 #define HWRPB$M_GRAPHICS 0x200 #define HWRPB$M_MEMBER_ID 0x400 #define HWRPB$M_FILL0 0x1 #define HWRPB$M_BIGCONFIG 0x400 #define HWRPB$M_VIRBND 0x1 #define HWRPB$M_RXTX_EXTENT 0x2 #define HWRPB_MEMBER_ID$K_NORITAKE 1 #define HWRPB_MEMBER_ID$K_PINNACLE 2 #define HWRPB_MEMBER_ID$K_PNORITAKE 3 #define HWRPB_MEMBER_ID$K_CORELLE 4 /* */ #define HWRPB_MEMBER_ID$K_PC264 1 #define HWRPB_MEMBER_ID$K_DP264 1 #define HWRPB_MEMBER_ID$K_WARHOL 2 #define HWRPB_MEMBER_ID$K_WINDJAMMER 3 #define HWRPB_MEMBER_ID$K_MONET 4 #define HWRPB_MEMBER_ID$K_CLIPPER 5 #define HWRPB_MEMBER_ID$K_GOLDRUSH 6 #define HWRPB_MEMBER_ID$K_WEBBRICK 7 #define HWRPB_MEMBER_ID$K_GOLDRACK 8 #define HWRPB_MEMBER_ID$K_PRIVATEER 1 #define HWRPB_MEMBER_ID$K_FALCON_E 2 #define HWRPB_MEMBER_ID$K_FALCON_S 3 #define HWRPB_MEMBER_ID$K_GRANITE 4 #define HWRPB_MEMBER_ID$K_HYPERBRICK 5 #define HWRPB_MEMBER_ID$K_HYPERSLATE 6 /* */ #define HWRPB$M_TXRDY_SUMMARY 0x1 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hwrpb { /* */ /* Physical address of the HWRPB */ /******************************* */ #pragma __nomember_alignment __union { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb$pq_base; /* Physical address of HWRPB */ #else unsigned __int64 hwrpb$pq_base; #endif __struct { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif void *hwrpb$pl_base_l; int hwrpb$l_base_h; } hwrpb$r_base_fields; } hwrpb$r_base_overlay; /* */ /* ASCIIZ "HWRPB" */ /**************** */ __union { unsigned __int64 hwrpb$iq_ident; /* Contains ASCIZ "HWRPB" */ __struct { unsigned int hwrpb$il_ident_l; unsigned int hwrpb$il_ident_h; } hwrpb$r_ident_fields; } hwrpb$r_ident_overlay; /* */ /* HWRPB revision */ /**************** */ __union { unsigned __int64 hwrpb$iq_revision; /* HWRPB revision number */ __struct { unsigned int hwrpb$il_revision_l; unsigned int hwrpb$il_revision_h; } hwrpb$r_revision_fields; } hwrpb$r_revision_overlay; /* */ /* HWRPB size */ /************ */ __union { unsigned __int64 hwrpb$iq_size; /* HWRPB Size */ __struct { unsigned int hwrpb$il_size_l; unsigned int hwrpb$il_size_h; } hwrpb$r_size_fields; } hwrpb$r_size_overlay; /* */ /* Primary CPU ID */ /**************** */ __union { unsigned __int64 hwrpb$iq_primary; /* Primary CPU ID */ __struct { unsigned int hwrpb$il_primary_l; unsigned int hwrpb$il_primary_h; } hwrpb$r_primary_fields; } hwrpb$r_primary_overlay; /* */ /* Page size in bytes */ /******************** */ __union { unsigned __int64 hwrpb$iq_pagesize; /* Page size in bytes */ __struct { unsigned int hwrpb$il_pagesize_l; unsigned int hwrpb$il_pagesize_h; } hwrpb$r_pagesize_fields; } hwrpb$r_pagesize_overlay; /* */ /* Number of Physical Address Bits */ /********************************* */ __union { unsigned __int64 hwrpb$iq_pa_size; /* Number of Phys. addr. bits */ __struct { unsigned int hwrpb$il_pa_size_l; unsigned int hwrpb$il_pa_size_h; } hwrpb$r_pa_size_fields; } hwrpb$r_pa_size_overlay; /* */ /* Maximum ASN */ /************* */ __union { unsigned __int64 hwrpb$iq_asn_max; /* Maximum ASN */ __struct { unsigned int hwrpb$il_asn_max_l; unsigned int hwrpb$il_asn_max_h; } hwrpb$r_asn_max_fields; } hwrpb$r_asn_max_overlay; /* */ /* System Serial Number */ /*********************** */ /*** Revision info still TBD by the FMA */ /* */ unsigned char hwrpb$b_sys_serialnum [16]; /* System Serial number */ /* */ /* System Type */ /************* */ __union { unsigned __int64 hwrpb$iq_systype; /* System type */ __struct { unsigned int hwrpb$il_systype_l; unsigned int hwrpb$il_systype_h; } hwrpb$r_systype_fields; } hwrpb$r_systype_overlay; /* */ /* System Variation */ /****************** */ __union { unsigned __int64 hwrpb$iq_sysvar; /* System variation quadword */ __struct { __union { unsigned int hwrpb$il_sysvar_l; __struct { unsigned hwrpb$v_mpcap : 1; /* Capable of Multi-Processors */ unsigned hwrpb$v_cnsle : 4 /** WARNING: bitfield array has been reduced to a string **/ ; /* Console Type */ unsigned hwrpb$v_pwrfl : 3 /** WARNING: bitfield array has been reduced to a string **/ ; /* Powerfail Type */ unsigned hwrpb$v_pwrfl_restart : 1; /* Powerfail Restart */ unsigned hwrpb$v_graphics : 1; /* Embedded graphics processor */ unsigned hwrpb$v_member_id : 6 /** WARNING: bitfield array has been reduced to a string **/ ; /* Member ID fiel\ d */ unsigned hwrpb$v_fill1 : 16 /** WARNING: bitfield array has been reduced to a string **/ ; } hwrpb$r_sysvar_field1; /* */ /* The following definition is for backward compatibility with */ /* Laser/Blazer code, which only used one bit of the member ID */ /* field. */ /* */ __struct { unsigned hwrpb$v_fill0 : 10 /** WARNING: bitfield array has been reduced to a string **/ ; unsigned hwrpb$v_bigconfig : 1; /* Blazer (vs. Laser) */ unsigned hwrpb$v_fill1 : 21 /** WARNING: bitfield array has been reduced to a string **/ ; } hwrpb$r_sysvar_field2; } hwrpb$r_sysvar_fields_overlay; __union { unsigned int hwrpb$il_sysvar_h; __struct { unsigned hwrpb$v_virbnd : 1; /* Virtual Address Boundary Register support */ unsigned hwrpb$v_rxtx_extent : 1; /* ECO 123 discriminator */ unsigned hwrpb$v_fill2 : 30 /** WARNING: bitfield array has been reduced to a string **/ ; } hwrpb$r_sysvar_field3; } hwrpb$r_sysvar_h_fields_overlay; } hwrpb$r_sysvar_fields; } hwrpb$r_sysvar_overlay; /******************************************* */ /** Define constants for member ID field. ** */ /******************************************* */ /* */ /* This field is used to identify a system only after first examining */ /* SYSTEM_TYPE and CPU_TYPE fields. It is possible that platforms with */ /* different SYSTEM_TYPE to re-use previously defined values as a different */ /* member ID. */ /* */ /* */ /* System Revision */ /***************** */ __union { unsigned __int64 hwrpb$iq_sysrev; /* System revision */ __struct { unsigned int hwrpb$il_sysrev_l; unsigned int hwrpb$il_sysrev_h; } hwrpb$r_sysrev_fields; } hwrpb$r_sysrev_overlay; /* */ /* Clock Interrupt Frequency */ /*************************** */ __union { unsigned __int64 hwrpb$iq_clock_int_freq; /* Clock interrupt frequency */ __struct { unsigned int hwrpb$il_clock_int_freq_l; unsigned int hwrpb$il_clock_int_freq_h; } hwrpb$r_clock_int_freq_fields; } hwrpb$r_clock_int_freq_overlay; /* */ /* Cycle Counter Frequency */ /************************* */ __union { unsigned __int64 hwrpb$iq_cycle_count_freq; /* Cycle counter frequency */ __struct { unsigned int hwrpb$il_cycle_count_freq_l; unsigned int hwrpb$il_cycle_count_freq_h; } hwrpb$r_cycle_count_freq_fields; } hwrpb$r_cycle_count_freq_overlay; /* */ /* Virtual Page Table Base */ /************************* */ __union { unsigned __int64 hwrpb$iq_vptb; /* Virtual Page Table Base */ __struct { unsigned int hwrpb$il_vptb_l; unsigned int hwrpb$il_vptb_h; } hwrpb$r_vptb_fields; } hwrpb$r_vptb_overlay; /* */ /* Reserved for Architecture use */ /******************************* */ unsigned __int64 hwrpb$iq_fill1; /* Reserved for future use */ /* */ /* Offset to Translation Buffer Hint Block */ /***************************************** */ __union { unsigned __int64 hwrpb$iq_tb_hint_offset; /* TB Hint Offset */ __struct { unsigned int hwrpb$il_tb_hint_offset_l; unsigned int hwrpb$il_tb_hint_offset_h; } hwrpb$r_tb_hint_offset_fields; } hwrpb$r_tb_hint_offset_overlay; /* */ /* Number of Per-CPU Slots */ /************************* */ __union { unsigned __int64 hwrpb$iq_nproc; /* Number of Per-CPU slots */ __struct { unsigned int hwrpb$il_nproc_l; unsigned int hwrpb$il_nproc_h; } hwrpb$r_nproc_fields; } hwrpb$r_nproc_overlay; /* */ /* Size of Per-CPU slots */ /*********************** */ __union { unsigned __int64 hwrpb$iq_slot_size; /* Size of Per-CPU slots */ __struct { unsigned int hwrpb$il_slot_size_l; unsigned int hwrpb$il_slot_size_h; } hwrpb$r_slot_size_fields; } hwrpb$r_slot_size_overlay; /* */ /* Offset to Per-CPU slots */ /************************* */ __union { unsigned __int64 hwrpb$iq_slot_offset; /* Offset to Per-CPU slots */ __struct { unsigned int hwrpb$il_slot_offset_l; unsigned int hwrpb$il_slot_offset_h; } hwrpb$r_slot_offset_fields; } hwrpb$r_slot_offset_overlay; /* */ /* Number of Console Terminal Blocks */ /*********************************** */ __union { unsigned __int64 hwrpb$iq_ctb_quantity; /* Number of CTB's */ __struct { unsigned int hwrpb$il_ctb_quantity_l; unsigned int hwrpb$il_ctb_quantity_h; } hwrpb$r_ctb_quantity_fields; } hwrpb$r_ctb_quantity_overlay; /* */ /* Size of Console Terminal Block */ /******************************** */ __union { unsigned __int64 hwrpb$iq_ctb_size; /* Size of CTB */ __struct { unsigned int hwrpb$il_ctb_size_l; unsigned int hwrpb$il_ctb_size_h; } hwrpb$r_ctb_size_fields; } hwrpb$r_ctb_size_overlay; /* */ /* Offset to Console Terminal Block Table */ /**************************************** */ __union { unsigned __int64 hwrpb$iq_ctb_offset; /* Offset to CTB */ __struct { unsigned int hwrpb$il_ctb_offset_l; unsigned int hwrpb$il_ctb_offset_h; } hwrpb$r_ctb_offset_fields; } hwrpb$r_ctb_offset_overlay; /* */ /* Offset to Console Routine Block */ /********************************* */ __union { unsigned __int64 hwrpb$iq_crb_offset; /* Offset to Console routine blk */ __struct { unsigned int hwrpb$il_crb_offset_l; unsigned int hwrpb$il_crb_offset_h; } hwrpb$r_crb_offset_fields; } hwrpb$r_crb_offset_overlay; /* */ /* Offset to Memory Data Descriptor Table */ /**************************************** */ __union { unsigned __int64 hwrpb$iq_mem_offset; /* Offset to memory descriptor */ __struct { unsigned int hwrpb$il_mem_offset_l; unsigned int hwrpb$il_mem_offset_h; } hwrpb$r_mem_offset_fields; } hwrpb$r_mem_offset_overlay; /* */ /* Offset to Configuration Data Block */ /************************************ */ __union { unsigned __int64 hwrpb$iq_cdb_offset; /* Offset to Config Data Block */ __struct { unsigned int hwrpb$il_cdb_offset_l; unsigned int hwrpb$il_cdb_offset_h; } hwrpb$r_cdb_offset_fields; } hwrpb$r_cdb_offset_overlay; /* */ /* Offset to Field Replaceable Unit Table */ /**************************************** */ __union { unsigned __int64 hwrpb$iq_fru_offset; /* Offset to FRU table */ __struct { unsigned int hwrpb$il_fru_offset_l; unsigned int hwrpb$il_fru_offset_h; } hwrpb$r_fru_offset_fields; } hwrpb$r_fru_offset_overlay; /* */ /* Virtual Address of terminal save-state routine */ /************************************************ */ __union { unsigned __int64 hwrpb$iq_save_term; /* VA of term save state routine */ __struct { void *hwrpb$il_save_term_l; unsigned int hwrpb$il_save_term_h; } hwrpb$r_save_term_fields; } hwrpb$r_save_term_overlay; /* */ /* Procedure Descriptor of terminal save-state routine */ /***************************************************** */ __union { unsigned __int64 hwrpb$iq_save_pd; /* Proc. value of save state rout. */ __struct { int (*hwrpb$il_save_pd_l)(); unsigned int hwrpb$il_save_pd_h; } hwrpb$r_save_pd_fields; } hwrpb$r_save_pd_overlay; /* */ /* Virtual Address of terminal restore-state routine */ /*************************************************** */ __union { unsigned __int64 hwrpb$iq_restore_term; /* VA of term restore state routine */ __struct { void *hwrpb$il_restore_term_l; unsigned int hwrpb$il_restore_term_h; } hwrpb$r_restore_term_fields; } hwrpb$r_restore_term_overlay; /* */ /* Procedure Descriptor for terminal restore-state routine */ /********************************************************* */ __union { unsigned __int64 hwrpb$iq_restore_pd; /* Proc. value of restore state rout. */ __struct { int (*hwrpb$il_restore_pd_l)(); unsigned int hwrpb$il_restore_pd_h; } hwrpb$r_restore_pd_fields; } hwrpb$r_restore_pd_overlay; /* */ /* Virtual Address of CPU restart routine */ /**************************************** */ __union { unsigned __int64 hwrpb$iq_restart; /* VA of restart routine */ __struct { void *hwrpb$il_restart_l; unsigned int hwrpb$il_restart_h; } hwrpb$r_restart_fields; } hwrpb$r_restart_overlay; /* */ /* Procedure Descriptor for CPU restart routine */ /********************************************** */ __union { unsigned __int64 hwrpb$iq_restart_pd; /* Restart Procedure Descriptor */ __struct { unsigned int hwrpb$il_restart_pd_l; unsigned int hwrpb$il_restart_pd_h; } hwrpb$r_restart_pd_fields; } hwrpb$r_restart_pd_overlay; /* */ /* SWRPB - Software Restart Parameter Block */ /****************************************** */ __union { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb$pq_swrpb; /* Resevered for software */ #else unsigned __int64 hwrpb$pq_swrpb; #endif __struct { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif void *hwrpb$pl_swrpb_l; int hwrpb$il_swrpb_h; } hwrpb$r_swrpb_fields; } hwrpb$r_swrpb_overlay; /* */ /* Reserved for Hardware */ /*********************** */ __union { unsigned __int64 hwrpb$iq_hardware1; /* Resevered for hardware */ __struct { unsigned int hwrpb$il_hardware1_l; unsigned int hwrpb$il_hardware1_h; } hwrpb$r_hardware1_fields; } hwrpb$r_hardware1_overlay; /* */ /* Checksum of HWRPB */ /******************* */ __union { unsigned __int64 hwrpb$iq_chksum; /* Checksum of HWRPB */ __struct { unsigned int hwrpb$il_chksum_l; unsigned int hwrpb$il_chksum_h; } hwrpb$r_chksum_fields; } hwrpb$r_chksum_overlay; /* */ /* RXRDY bitmask */ /************************* */ __union { unsigned __int64 hwrpb$iq_rxrdy; /* RXRDY bitmask */ unsigned __int64 hwrpb$iq_rxrdy_offset; /* Offset to RXRDY bitmask for ECO 123 */ __struct { unsigned int hwrpb$il_rxrdy_l; unsigned int hwrpb$il_rxrdy_h; } hwrpb$r_rxrdy_fields; } hwrpb$r_rxrdy_overlay; /* */ /* TXRDY bitmask */ /************************* */ __union { unsigned __int64 hwrpb$iq_txrdy; /* TXRDY bitmask */ __struct { __union { unsigned int hwrpb$il_txrdy_l; __struct { unsigned hwrpb$v_txrdy_summary : 1; /* ECO 123 - At least 1 bitmask is nonzero */ unsigned hwrpb$v_fill1 : 31 /** WARNING: bitfield array has been reduced to a string **/ ; } hwrpb$r_txrdy_field1; } hwrpb$r_txrdy_fields_overlay; unsigned int hwrpb$il_txrdy_h; } hwrpb$r_txrdy_fields; } hwrpb$r_txrdy_overlay; /* */ /* Offset to Dynamic System Recognition Data Base (DSRDB) */ /******************************************************** */ __union { unsigned __int64 hwrpb$iq_dsrdb_offset; /* Offset to DSR D.B. */ __struct { unsigned int hwrpb$il_dsrdb_offset_l; unsigned int hwrpb$il_dsrdb_offset_h; } hwrpb$r_dsrdb_offset_fields; } hwrpb$r_dsrdb_offset_overlay; } HWRPB; #if !defined(__VAXC) #define hwrpb$pq_base hwrpb$r_base_overlay.hwrpb$pq_base #define hwrpb$pl_base_l hwrpb$r_base_overlay.hwrpb$r_base_fields.hwrpb$pl_base_l #define hwrpb$l_base_h hwrpb$r_base_overlay.hwrpb$r_base_fields.hwrpb$l_base_h #define hwrpb$iq_ident hwrpb$r_ident_overlay.hwrpb$iq_ident #define hwrpb$il_ident_l hwrpb$r_ident_overlay.hwrpb$r_ident_fields.hwrpb$il_ident_l #define hwrpb$il_ident_h hwrpb$r_ident_overlay.hwrpb$r_ident_fields.hwrpb$il_ident_h #define hwrpb$iq_revision hwrpb$r_revision_overlay.hwrpb$iq_revision #define hwrpb$il_revision_l hwrpb$r_revision_overlay.hwrpb$r_revision_fields.hwrpb$il_revision_l #define hwrpb$il_revision_h hwrpb$r_revision_overlay.hwrpb$r_revision_fields.hwrpb$il_revision_h #define hwrpb$iq_size hwrpb$r_size_overlay.hwrpb$iq_size #define hwrpb$il_size_l hwrpb$r_size_overlay.hwrpb$r_size_fields.hwrpb$il_size_l #define hwrpb$il_size_h hwrpb$r_size_overlay.hwrpb$r_size_fields.hwrpb$il_size_h #define hwrpb$iq_primary hwrpb$r_primary_overlay.hwrpb$iq_primary #define hwrpb$il_primary_l hwrpb$r_primary_overlay.hwrpb$r_primary_fields.hwrpb$il_primary_l #define hwrpb$il_primary_h hwrpb$r_primary_overlay.hwrpb$r_primary_fields.hwrpb$il_primary_h #define hwrpb$iq_pagesize hwrpb$r_pagesize_overlay.hwrpb$iq_pagesize #define hwrpb$il_pagesize_l hwrpb$r_pagesize_overlay.hwrpb$r_pagesize_fields.hwrpb$il_pagesize_l #define hwrpb$il_pagesize_h hwrpb$r_pagesize_overlay.hwrpb$r_pagesize_fields.hwrpb$il_pagesize_h #define hwrpb$iq_pa_size hwrpb$r_pa_size_overlay.hwrpb$iq_pa_size #define hwrpb$il_pa_size_l hwrpb$r_pa_size_overlay.hwrpb$r_pa_size_fields.hwrpb$il_pa_size_l #define hwrpb$il_pa_size_h hwrpb$r_pa_size_overlay.hwrpb$r_pa_size_fields.hwrpb$il_pa_size_h #define hwrpb$iq_asn_max hwrpb$r_asn_max_overlay.hwrpb$iq_asn_max #define hwrpb$il_asn_max_l hwrpb$r_asn_max_overlay.hwrpb$r_asn_max_fields.hwrpb$il_asn_max_l #define hwrpb$il_asn_max_h hwrpb$r_asn_max_overlay.hwrpb$r_asn_max_fields.hwrpb$il_asn_max_h #define hwrpb$iq_systype hwrpb$r_systype_overlay.hwrpb$iq_systype #define hwrpb$il_systype_l hwrpb$r_systype_overlay.hwrpb$r_systype_fields.hwrpb$il_systype_l #define hwrpb$il_systype_h hwrpb$r_systype_overlay.hwrpb$r_systype_fields.hwrpb$il_systype_h #define hwrpb$iq_sysvar hwrpb$r_sysvar_overlay.hwrpb$iq_sysvar #define hwrpb$il_sysvar_l hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$il_sysvar_l #define hwrpb$v_mpcap hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb$v_mpcap #define hwrpb$v_cnsle hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb$v_cnsle #define hwrpb$v_pwrfl hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb$v_pwrfl #define hwrpb$v_pwrfl_restart hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrp\ b$v_pwrfl_restart #define hwrpb$v_graphics hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb$v_g\ raphics #define hwrpb$v_member_id hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb$v_\ member_id #define hwrpb$v_fill0 hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field2.hwrpb$v_fill0 #define hwrpb$v_bigconfig hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field2.hwrpb$v_\ bigconfig #define hwrpb$il_sysvar_h hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$il_sysvar_h #define hwrpb$v_virbnd hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$r_sysvar_field3.hwrpb$v_v\ irbnd #define hwrpb$v_rxtx_extent hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$r_sysvar_field3.hwrp\ b$v_rxtx_extent #define hwrpb$iq_sysrev hwrpb$r_sysrev_overlay.hwrpb$iq_sysrev #define hwrpb$il_sysrev_l hwrpb$r_sysrev_overlay.hwrpb$r_sysrev_fields.hwrpb$il_sysrev_l #define hwrpb$il_sysrev_h hwrpb$r_sysrev_overlay.hwrpb$r_sysrev_fields.hwrpb$il_sysrev_h #define hwrpb$iq_clock_int_freq hwrpb$r_clock_int_freq_overlay.hwrpb$iq_clock_int_freq #define hwrpb$il_clock_int_freq_l hwrpb$r_clock_int_freq_overlay.hwrpb$r_clock_int_freq_fields.hwrpb$il_clock_int_freq_l #define hwrpb$il_clock_int_freq_h hwrpb$r_clock_int_freq_overlay.hwrpb$r_clock_int_freq_fields.hwrpb$il_clock_int_freq_h #define hwrpb$iq_cycle_count_freq hwrpb$r_cycle_count_freq_overlay.hwrpb$iq_cycle_count_freq #define hwrpb$il_cycle_count_freq_l hwrpb$r_cycle_count_freq_overlay.hwrpb$r_cycle_count_freq_fields.hwrpb$il_cycle_count_freq_l #define hwrpb$il_cycle_count_freq_h hwrpb$r_cycle_count_freq_overlay.hwrpb$r_cycle_count_freq_fields.hwrpb$il_cycle_count_freq_h #define hwrpb$iq_vptb hwrpb$r_vptb_overlay.hwrpb$iq_vptb #define hwrpb$il_vptb_l hwrpb$r_vptb_overlay.hwrpb$r_vptb_fields.hwrpb$il_vptb_l #define hwrpb$il_vptb_h hwrpb$r_vptb_overlay.hwrpb$r_vptb_fields.hwrpb$il_vptb_h #define hwrpb$iq_tb_hint_offset hwrpb$r_tb_hint_offset_overlay.hwrpb$iq_tb_hint_offset #define hwrpb$il_tb_hint_offset_l hwrpb$r_tb_hint_offset_overlay.hwrpb$r_tb_hint_offset_fields.hwrpb$il_tb_hint_offset_l #define hwrpb$il_tb_hint_offset_h hwrpb$r_tb_hint_offset_overlay.hwrpb$r_tb_hint_offset_fields.hwrpb$il_tb_hint_offset_h #define hwrpb$iq_nproc hwrpb$r_nproc_overlay.hwrpb$iq_nproc #define hwrpb$il_nproc_l hwrpb$r_nproc_overlay.hwrpb$r_nproc_fields.hwrpb$il_nproc_l #define hwrpb$il_nproc_h hwrpb$r_nproc_overlay.hwrpb$r_nproc_fields.hwrpb$il_nproc_h #define hwrpb$iq_slot_size hwrpb$r_slot_size_overlay.hwrpb$iq_slot_size #define hwrpb$il_slot_size_l hwrpb$r_slot_size_overlay.hwrpb$r_slot_size_fields.hwrpb$il_slot_size_l #define hwrpb$il_slot_size_h hwrpb$r_slot_size_overlay.hwrpb$r_slot_size_fields.hwrpb$il_slot_size_h #define hwrpb$iq_slot_offset hwrpb$r_slot_offset_overlay.hwrpb$iq_slot_offset #define hwrpb$il_slot_offset_l hwrpb$r_slot_offset_overlay.hwrpb$r_slot_offset_fields.hwrpb$il_slot_offset_l #define hwrpb$il_slot_offset_h hwrpb$r_slot_offset_overlay.hwrpb$r_slot_offset_fields.hwrpb$il_slot_offset_h #define hwrpb$iq_ctb_quantity hwrpb$r_ctb_quantity_overlay.hwrpb$iq_ctb_quantity #define hwrpb$il_ctb_quantity_l hwrpb$r_ctb_quantity_overlay.hwrpb$r_ctb_quantity_fields.hwrpb$il_ctb_quantity_l #define hwrpb$il_ctb_quantity_h hwrpb$r_ctb_quantity_overlay.hwrpb$r_ctb_quantity_fields.hwrpb$il_ctb_quantity_h #define hwrpb$iq_ctb_size hwrpb$r_ctb_size_overlay.hwrpb$iq_ctb_size #define hwrpb$il_ctb_size_l hwrpb$r_ctb_size_overlay.hwrpb$r_ctb_size_fields.hwrpb$il_ctb_size_l #define hwrpb$il_ctb_size_h hwrpb$r_ctb_size_overlay.hwrpb$r_ctb_size_fields.hwrpb$il_ctb_size_h #define hwrpb$iq_ctb_offset hwrpb$r_ctb_offset_overlay.hwrpb$iq_ctb_offset #define hwrpb$il_ctb_offset_l hwrpb$r_ctb_offset_overlay.hwrpb$r_ctb_offset_fields.hwrpb$il_ctb_offset_l #define hwrpb$il_ctb_offset_h hwrpb$r_ctb_offset_overlay.hwrpb$r_ctb_offset_fields.hwrpb$il_ctb_offset_h #define hwrpb$iq_crb_offset hwrpb$r_crb_offset_overlay.hwrpb$iq_crb_offset #define hwrpb$il_crb_offset_l hwrpb$r_crb_offset_overlay.hwrpb$r_crb_offset_fields.hwrpb$il_crb_offset_l #define hwrpb$il_crb_offset_h hwrpb$r_crb_offset_overlay.hwrpb$r_crb_offset_fields.hwrpb$il_crb_offset_h #define hwrpb$iq_mem_offset hwrpb$r_mem_offset_overlay.hwrpb$iq_mem_offset #define hwrpb$il_mem_offset_l hwrpb$r_mem_offset_overlay.hwrpb$r_mem_offset_fields.hwrpb$il_mem_offset_l #define hwrpb$il_mem_offset_h hwrpb$r_mem_offset_overlay.hwrpb$r_mem_offset_fields.hwrpb$il_mem_offset_h #define hwrpb$iq_cdb_offset hwrpb$r_cdb_offset_overlay.hwrpb$iq_cdb_offset #define hwrpb$il_cdb_offset_l hwrpb$r_cdb_offset_overlay.hwrpb$r_cdb_offset_fields.hwrpb$il_cdb_offset_l #define hwrpb$il_cdb_offset_h hwrpb$r_cdb_offset_overlay.hwrpb$r_cdb_offset_fields.hwrpb$il_cdb_offset_h #define hwrpb$iq_fru_offset hwrpb$r_fru_offset_overlay.hwrpb$iq_fru_offset #define hwrpb$il_fru_offset_l hwrpb$r_fru_offset_overlay.hwrpb$r_fru_offset_fields.hwrpb$il_fru_offset_l #define hwrpb$il_fru_offset_h hwrpb$r_fru_offset_overlay.hwrpb$r_fru_offset_fields.hwrpb$il_fru_offset_h #define hwrpb$iq_save_term hwrpb$r_save_term_overlay.hwrpb$iq_save_term #define hwrpb$il_save_term_l hwrpb$r_save_term_overlay.hwrpb$r_save_term_fields.hwrpb$il_save_term_l #define hwrpb$il_save_term_h hwrpb$r_save_term_overlay.hwrpb$r_save_term_fields.hwrpb$il_save_term_h #define hwrpb$iq_save_pd hwrpb$r_save_pd_overlay.hwrpb$iq_save_pd #define hwrpb$il_save_pd_l hwrpb$r_save_pd_overlay.hwrpb$r_save_pd_fields.hwrpb$il_save_pd_l #define hwrpb$il_save_pd_h hwrpb$r_save_pd_overlay.hwrpb$r_save_pd_fields.hwrpb$il_save_pd_h #define hwrpb$iq_restore_term hwrpb$r_restore_term_overlay.hwrpb$iq_restore_term #define hwrpb$il_restore_term_l hwrpb$r_restore_term_overlay.hwrpb$r_restore_term_fields.hwrpb$il_restore_term_l #define hwrpb$il_restore_term_h hwrpb$r_restore_term_overlay.hwrpb$r_restore_term_fields.hwrpb$il_restore_term_h #define hwrpb$iq_restore_pd hwrpb$r_restore_pd_overlay.hwrpb$iq_restore_pd #define hwrpb$il_restore_pd_l hwrpb$r_restore_pd_overlay.hwrpb$r_restore_pd_fields.hwrpb$il_restore_pd_l #define hwrpb$il_restore_pd_h hwrpb$r_restore_pd_overlay.hwrpb$r_restore_pd_fields.hwrpb$il_restore_pd_h #define hwrpb$iq_restart hwrpb$r_restart_overlay.hwrpb$iq_restart #define hwrpb$il_restart_l hwrpb$r_restart_overlay.hwrpb$r_restart_fields.hwrpb$il_restart_l #define hwrpb$il_restart_h hwrpb$r_restart_overlay.hwrpb$r_restart_fields.hwrpb$il_restart_h #define hwrpb$iq_restart_pd hwrpb$r_restart_pd_overlay.hwrpb$iq_restart_pd #define hwrpb$il_restart_pd_l hwrpb$r_restart_pd_overlay.hwrpb$r_restart_pd_fields.hwrpb$il_restart_pd_l #define hwrpb$il_restart_pd_h hwrpb$r_restart_pd_overlay.hwrpb$r_restart_pd_fields.hwrpb$il_restart_pd_h #define hwrpb$pq_swrpb hwrpb$r_swrpb_overlay.hwrpb$pq_swrpb #define hwrpb$pl_swrpb_l hwrpb$r_swrpb_overlay.hwrpb$r_swrpb_fields.hwrpb$pl_swrpb_l #define hwrpb$il_swrpb_h hwrpb$r_swrpb_overlay.hwrpb$r_swrpb_fields.hwrpb$il_swrpb_h #define hwrpb$iq_hardware1 hwrpb$r_hardware1_overlay.hwrpb$iq_hardware1 #define hwrpb$il_hardware1_l hwrpb$r_hardware1_overlay.hwrpb$r_hardware1_fields.hwrpb$il_hardware1_l #define hwrpb$il_hardware1_h hwrpb$r_hardware1_overlay.hwrpb$r_hardware1_fields.hwrpb$il_hardware1_h #define hwrpb$iq_chksum hwrpb$r_chksum_overlay.hwrpb$iq_chksum #define hwrpb$il_chksum_l hwrpb$r_chksum_overlay.hwrpb$r_chksum_fields.hwrpb$il_chksum_l #define hwrpb$il_chksum_h hwrpb$r_chksum_overlay.hwrpb$r_chksum_fields.hwrpb$il_chksum_h #define hwrpb$iq_rxrdy hwrpb$r_rxrdy_overlay.hwrpb$iq_rxrdy #define hwrpb$iq_rxrdy_offset hwrpb$r_rxrdy_overlay.hwrpb$iq_rxrdy_offset #define hwrpb$il_rxrdy_l hwrpb$r_rxrdy_overlay.hwrpb$r_rxrdy_fields.hwrpb$il_rxrdy_l #define hwrpb$il_rxrdy_h hwrpb$r_rxrdy_overlay.hwrpb$r_rxrdy_fields.hwrpb$il_rxrdy_h #define hwrpb$iq_txrdy hwrpb$r_txrdy_overlay.hwrpb$iq_txrdy #define hwrpb$il_txrdy_l hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$r_txrdy_fields_overlay.hwrpb$il_txrdy_l #define hwrpb$v_txrdy_summary hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$r_txrdy_fields_overlay.hwrpb$r_txrdy_field1.hwrpb$v_\ txrdy_summary #define hwrpb$il_txrdy_h hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$il_txrdy_h #define hwrpb$iq_dsrdb_offset hwrpb$r_dsrdb_offset_overlay.hwrpb$iq_dsrdb_offset #define hwrpb$il_dsrdb_offset_l hwrpb$r_dsrdb_offset_overlay.hwrpb$r_dsrdb_offset_fields.hwrpb$il_dsrdb_offset_l #define hwrpb$il_dsrdb_offset_h hwrpb$r_dsrdb_offset_overlay.hwrpb$r_dsrdb_offset_fields.hwrpb$il_dsrdb_offset_h #endif /* #if !defined(__VAXC) */ /* */ /* */ #define HWRPB$C_LENGTH 320 /* Length of HWRPB */ #define HWRPB$K_LENGTH 320 /* Length of HWRPB */ #define HWRPB$S_HWRPBDEF 320 /* Old size name - synonym */ /* */ /* DSR data block Definition */ /*************************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _dsrdb { /* */ /* SMM Value */ /*********** */ #pragma __nomember_alignment __union { unsigned __int64 dsrdb$iq_smm; /* SMM value */ __struct { unsigned int dsrdb$il_smm_l; unsigned int dsrdb$il_smm_h; } dsrdb$r_smm_fields; } dsrdb$r_smm_overlay; /* */ /* Offset to LURT count field */ /**************************** */ __union { unsigned __int64 dsrdb$iq_lurt_offset; /* Offset to LURT count field */ __struct { unsigned int dsrdb$il_lurt_offset_l; unsigned int dsrdb$il_lurt_offset_h; } dsrdb$r_lurt_offset_fields; } dsrdb$r_lurt_overlay; /* */ /* Offset to name count field */ /**************************** */ __union { unsigned __int64 dsrdb$iq_name_ct_offset; /* Offset to Name count field */ __struct { unsigned int dsrdb$il_name_ct_offset_l; unsigned int dsrdb$il_name_ct_offset_h; } dsrdb$r_name_ct_offset_fields; } dsrdb$r_name_ct_overlay; } DSRDB; #if !defined(__VAXC) #define dsrdb$iq_smm dsrdb$r_smm_overlay.dsrdb$iq_smm #define dsrdb$il_smm_l dsrdb$r_smm_overlay.dsrdb$r_smm_fields.dsrdb$il_smm_l #define dsrdb$il_smm_h dsrdb$r_smm_overlay.dsrdb$r_smm_fields.dsrdb$il_smm_h #define dsrdb$iq_lurt_offset dsrdb$r_lurt_overlay.dsrdb$iq_lurt_offset #define dsrdb$il_lurt_offset_l dsrdb$r_lurt_overlay.dsrdb$r_lurt_offset_fields.dsrdb$il_lurt_offset_l #define dsrdb$il_lurt_offset_h dsrdb$r_lurt_overlay.dsrdb$r_lurt_offset_fields.dsrdb$il_lurt_offset_h #define dsrdb$iq_name_ct_offset dsrdb$r_name_ct_overlay.dsrdb$iq_name_ct_offset #define dsrdb$il_name_ct_offset_l dsrdb$r_name_ct_overlay.dsrdb$r_name_ct_offset_fields.dsrdb$il_name_ct_offset_l #define dsrdb$il_name_ct_offset_h dsrdb$r_name_ct_overlay.dsrdb$r_name_ct_offset_fields.dsrdb$il_name_ct_offset_h #endif /* #if !defined(__VAXC) */ /* */ /* */ #define DSRDB$S_DSRDBDEF 24 /* Old size name - synonym */ /* */ /* Per-CPU slot definitions */ /************************** */ #define SLOT$M_BIP 0x1 #define SLOT$M_RC 0x2 #define SLOT$M_PA 0x4 #define SLOT$M_PP 0x8 #define SLOT$M_OH 0x10 #define SLOT$M_CV 0x20 #define SLOT$M_PV 0x40 #define SLOT$M_PMV 0x80 #define SLOT$M_PL 0x100 #define SLOT$M_RSVD 0x200 #define SLOT$M_HLTREQ 0xFF0000 #define HWRPB_HALT$K_NO_ACTION 0 /* Just Halt */ #define HWRPB_HALT$K_SAVE_RESTORE_TERM 1 /* Save or restore term */ #define HWRPB_HALT$K_COLD_REBOOT 2 /* Cold bootstrap request */ #define HWRPB_HALT$K_WARM_REBOOT 3 /* Warm bootstrap request */ #define HWRPB_HALT$K_REMAIN_HALTED 4 /* Don't restart */ #define HWRPB_HALT$K_POWEROFF 5 /* Power-off system */ /* reserved */ #define HWRPB_HALT$K_MIGRATE 7 /* Galaxy CPU migration */ #define HWRPB_HALT$K_DEASSIGN 8 /* Galaxy CPU deassignment */ /* reserved */ #define SLOT$M_PARTID 0xFFFF #define HWRPB_PAL_REV$K_STANDARD 0 /* Standard PAL code */ #define HWRPB_PAL_REV$K_ULTRIX 1 /* ULTRIX varient of PAL code */ /* */ #define HWRPB_CPU_TYPE$K_EV3 1 /* Reduced functionality EVAX */ #define HWRPB_CPU_TYPE$K_EV4 2 /* First fully functional EVAX */ #define HWRPB_CPU_TYPE$K_MANNEQUIN 3 /* Mannequin simulator */ #define HWRPB_CPU_TYPE$K_LCA 4 /* Low Cost Alpha */ #define HWRPB_CPU_TYPE$K_EV5 5 /* CMOS 5 EVAX */ #define HWRPB_CPU_TYPE$K_EV45 6 /* EV4 shrink on CMOS 5 process */ #define HWRPB_CPU_TYPE$K_EV56 7 /* EV5 shrink on CMOS 6 process */ #define HWRPB_CPU_TYPE$K_EV6 8 /* CMOS 6 EVAX */ #define HWRPB_CPU_TYPE$K_PCA56 9 /* Low cost EV56 */ #define HWRPB_CPU_TYPE$K_PCA57 10 #define HWRPB_CPU_TYPE$K_EV67 11 /* EV6 shrink, cmos 7 */ #define HWRPB_CPU_TYPE$K_EV68CB 12 /* EV6 shrink, cmos 8 */ #define HWRPB_CPU_TYPE$K_EV68A 13 /* Samsung */ #define HWRPB_CPU_TYPE$K_EV68CX 14 #define HWRPB_CPU_TYPE$K_EV7 15 /* */ #define HWRPB_CPU_TYPE$K_MAX_CPU_TYPE 15 /* */ #define SLOT$M_VAX_FP 0x1 #define SLOT$M_IEEE_FP 0x2 #define SLOT$M_PE 0x4 #define HWRPB$K_RESTART 0 /* Btstrap,procr strt, or pwrfl. */ #define HWRPB$K_CRASH_CMD 1 /* Crash via cosole request */ #define HWRPB$K_KSP_NOT_VALID 2 /* Kernel stack not valid halt */ #define HWRPB$K_INVALID_SCBB 3 /* Invalid SCB Base register */ #define HWRPB$K_INVALID_PTBR 4 /* Invalid Page Table Base Reg. */ #define HWRPB$K_CALL_PAL_HALT 5 /* Processor executed in ker. mode */ #define HWRPB$K_DOUBLE_ERROR 6 /* Double error abort */ #define HWRPB$K_MCHECK_IN_PAL 7 /* Mcheck in PAL environment */ #define HWRPB$K_LAST_HALT_REASON 7 /* */ #define SLOT$M_CPU_CACHE_WRITE_BACK 0x1 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _cpu_slot { /* */ /* Restart/Boot HWPCB */ /******************** */ #pragma __nomember_alignment unsigned __int64 slot$iq_hwpcb [16]; /* Restart/Boot HWPCB */ /* */ /* Per-CPU state bits */ /******************** */ __union { unsigned __int64 slot$iq_state; /* Per-CPU state bits */ __struct { __union { unsigned int slot$il_state; __struct { unsigned slot$v_bip : 1; /* Bootstrap in progress */ unsigned slot$v_rc : 1; /* Restart capable */ unsigned slot$v_pa : 1; /* Processor available */ unsigned slot$v_pp : 1; /* Processor present */ unsigned slot$v_oh : 1; /* Operator halted */ unsigned slot$v_cv : 1; /* Context valid */ unsigned slot$v_pv : 1; /* PAL code valid */ unsigned slot$v_pmv : 1; /* PAL code memory valid */ unsigned slot$v_pl : 1; /* PAL code loaded */ unsigned slot$v_rsvd : 1; /* Reserved */ unsigned slot$v_fill1 : 6 /** WARNING: bitfield array has been reduced to a string **/ ; unsigned slot$v_hltreq : 8; unsigned slot$v_fill2 : 8 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_state_field1; } slot$r_state_fields_overlay; __union { unsigned int slot$il_state_h; __struct { unsigned slot$v_partid : 16; unsigned slot$v_fill3 : 16 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_state_field2; } slot$r_state_fields2_overlay; } slot$r_state_fields; } slot$r_state_overlay; /* */ /* PALcode Memory length */ /*********************** */ __union { unsigned __int64 slot$iq_pal_mem_len; /* PALcode Memory Length */ __struct { unsigned int slot$il_pal_mem_len_l; unsigned int slot$il_pal_mem_len_h; } slot$r_pal_mem_len_fields; } slot$r_pal_mem_len_overlay; /* */ /* PALcode scratch length */ /************************ */ __union { unsigned __int64 slot$iq_pal_scr_len; /* PALcode Scratch Length */ __struct { unsigned int slot$il_pal_scr_len_l; unsigned int slot$il_pal_scr_len_h; } slot$r_pal_scr_len_fields; } slot$r_pal_scr_len_overlay; /* */ /* Physical Address of PALcode memory space */ /****************************************** */ __union { unsigned __int64 slot$iq_pal_mem_pa; /* Phy addr of PAL code memory */ __struct { unsigned int slot$il_pal_mem_pa_l; unsigned int slot$il_pal_mem_pa_h; } slot$r_pal_mem_pa_fields; } slot$r_pal_mem_pa_overlay; /* */ /* Physical Address of PALcode scratch space */ /******************************************* */ __union { unsigned __int64 slot$iq_pal_scr_adr; /* Phys addr of PAL scratch sp */ __struct { unsigned int slot$il_pal_scr_adr_l; unsigned int slot$il_pal_scr_adr_h; } slot$r_pal_scr_adr_fields; } slot$r_pal_scr_adr_overlay; /* */ /* PALcode revision required by processor */ /**************************************** */ __union { unsigned __int64 slot$iq_pal_rev; /* Revision of PAL code required */ __struct { __union { unsigned int slot$il_pal_rev_l; __struct { unsigned char slot$b_pal_min_rev; /* PAL code minor revision */ unsigned char slot$b_pal_maj_rev; /* PAL code major revision */ unsigned char slot$b_pal_var; /* PAL code variation */ char slot$b_fill1 [1]; } slot$r_pal_rev_fields; } slot$r_pal_rev_fields1_overlay; __union { unsigned int slot$il_pal_rev_h; __struct { unsigned short int slot$iw_pal_compt; /* PAL code compatibility */ unsigned short int slot$iw_max_share; /* Max number CPUs to share */ } slot$r_pal_rev_h_fields; } slot$r_pal_rev_fields_h_overlay; } slot$r_pal_rev_fields; } slot$r_pal_rev_overlay; /* */ /* Processor Type */ /**************** */ __union { unsigned __int64 slot$iq_cpu_type; /* Processor type */ __struct { unsigned int slot$il_cpu_type_l; unsigned int slot$il_cpu_type_h; } slot$r_cpu_type_fields; } slot$r_cpu_type_overlay; /* */ /* Processor Variation */ /********************* */ __union { unsigned __int64 slot$iq_cpu_var; /* Processor variation */ __struct { __union { unsigned int slot$il_cpu_var_l; __struct { unsigned slot$v_vax_fp : 1; /* VAX floating point */ unsigned slot$v_ieee_fp : 1; /* IEEE floating point */ unsigned slot$v_pe : 1; /* Processor Eligibility */ unsigned slot$v_fill1 : 29 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_cpu_var_field1; } slot$r_cpu_var_fields_overlay; unsigned int slot$il_cpu_var_h; } slot$r_cpu_var_fields; } slot$r_cpu_var_overlay; /* */ /* Processor Revision */ /******************** */ __union { unsigned __int64 slot$iq_cpu_rev; /* Processor revision */ __struct { unsigned int slot$il_cpu_rev_l; unsigned int slot$il_cpu_rev_h; } slot$r_cpu_rev_fields; } slot$r_cpu_rev_overlay; /* */ /* CPU serial number */ /******************* */ unsigned char slot$b_cpu_serialnum [16]; /* CPU Serial number */ /* */ /* Physical Address of logout area */ /********************************* */ __union { unsigned __int64 slot$iq_logout_pa; /* Physical Addr of logout area */ __struct { unsigned int slot$il_logout_pa_l; unsigned int slot$il_logout_pa_h; } slot$r_logout_pa_fields; } slot$r_logout_pa_overlay; /* */ /* Size of logout area */ /********************* */ __union { unsigned __int64 slot$iq_logout_len; /* Size of logout area */ __struct { unsigned int slot$il_logout_len_l; unsigned int slot$il_logout_len_h; } slot$r_logout_len_fields; } slot$r_logout_len_overlay; /* */ /* Halt PCBB */ /*********** */ __union { unsigned __int64 slot$iq_halt_pcbb; /* Halt PCBB */ __struct { unsigned int slot$il_halt_pcbb_l; unsigned int slot$il_halt_pcbb_h; } slot$r_halt_pcbb_fields; } slot$r_halt_pcbb_overlay; /* */ /* Halt PC */ /********* */ __union { unsigned __int64 slot$iq_halt_pc; /* Halt PC */ __struct { unsigned int slot$il_halt_pc_l; unsigned int slot$il_halt_pc_h; } slot$r_halt_pc_fields; } slot$r_halt_pc_overlay; /* */ /* Halt PS */ /********* */ __union { unsigned __int64 slot$iq_halt_ps; /* Halt PS */ __struct { unsigned int slot$il_halt_ps_l; unsigned int slot$il_halt_ps_h; } slot$r_halt_ps_fields; } slot$r_halt_ps_overlay; /* */ /* Halt Argument List */ /******************** */ __union { unsigned __int64 slot$iq_halt_arg; /* Halt Argument List */ __struct { unsigned int slot$il_halt_arg_l; unsigned int slot$il_halt_arg_h; } slot$r_halt_arg_fields; } slot$r_halt_arg_overlay; /* */ /* Halt Return Address */ /********************* */ __union { unsigned __int64 slot$iq_halt_ret; /* Halt Return Address */ __struct { unsigned int slot$il_halt_ret_l; unsigned int slot$il_halt_ret_h; } slot$r_halt_ret_fields; } slot$r_halt_ret_overlay; /* */ /* Halt Procedure Value */ /********************** */ __union { unsigned __int64 slot$iq_halt_pv; /* Halt PV */ __struct { unsigned int slot$il_halt_pv_l; unsigned int slot$il_halt_pv_h; } slot$r_halt_pv_fields; } slot$r_halt_pv_overlay; /* */ /* Halt Code */ /*********** */ __union { unsigned __int64 slot$iq_haltcode; /* Halt code */ __struct { unsigned int slot$il_haltcode_l; unsigned int slot$il_haltcode_h; } slot$r_haltcode_fields; } slot$r_haltcode_overlay; /* */ /* Reserved for Software */ /*********************** */ __union { unsigned __int64 slot$iq_soft_flags; /* Reserved to software */ __struct { unsigned int slot$il_soft_flags_l; unsigned int slot$il_soft_flags_h; } slot$r_soft_flags_fields; } slot$r_soft_flags_overlay; /* */ /* Interprocessor Console Buffer Area */ /************************************ */ __union { unsigned char slot$b_incon_buf_area [168]; /* SMP Console Buf Area */ __struct { unsigned int slot$il_rxlen; unsigned int slot$il_txlen; unsigned char slot$b_rxbuffer [80]; unsigned char slot$b_txbuffer [80]; } slot$r_incon_buf_fields; } slot$r_incon_buf_overlay; /* */ /* The next 16 quadwords are reserved for the */ /* "PALcode Revisions Available Block". */ /* The format of the first quadword is platform specific. */ /* The format of each subsequent quadword follows the */ /* PALcode revision field (SLOT[168]) */ /* */ unsigned __int64 slot$q_pal_rev_avail [16]; /* PALcode Revisions Available Block */ /* */ /* Processor Software Compatibility */ /********************************** */ __union { unsigned __int64 slot$iq_cpu_sw_comp; /* Processor software compatibility */ __struct { unsigned int slot$il_cpu_sw_comp_l; unsigned int slot$il_cpu_sw_comp_h; } slot$r_cpu_sw_comp_fields; } slot$r_cpu_sw_comp_overlay; __union { unsigned __int64 slot$iq_console_data_pa; /* Console frame data buffer base PA */ __struct { unsigned int slot$il_console_data_pa_l; unsigned int slot$il_console_data_pa_h; } slot$r_console_data_pa_fields; } slot$r_console_data_pa_overlay; __union { unsigned __int64 slot$iq_console_data_size; /* Console frame data buffer length */ __struct { unsigned int slot$il_console_data_size_l; unsigned int slot$il_console_data_size_h; } slot$r_console_data_size_fields; } slot$r_console_data_size_overlay; /* */ /* Cache Information */ /******************************************** */ __union { unsigned __int64 slot$iq_cpu_cache; /* Cache Information */ __struct { unsigned int slot$il_cpu_cache_l; /* Total size of cache in kbytes */ __union { unsigned int slot$il_cpu_cache_h; __struct { unsigned char slot$b_cpu_cache_assoc_degree; /* Degree of set associativity */ __struct { unsigned slot$v_cpu_cache_write_back : 1; /* Write-back or Write-through */ unsigned slot$v_cpu_cache_fill1 : 7 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_cpu_cache_field2; unsigned short int slot$iw_cpu_cache_block_size; /* Size of individual cache block */ } slot$r_cpu_cache_field1; } slot$r_cpu_cache_fields_overlay; } slot$r_cpu_cache_fields; } slot$r_cpu_cache_overlay; /* */ /* Cycle Counter Frequency */ /************************* */ __union { unsigned __int64 slot$iq_cycle_count_freq; /* Cycle counter frequency */ __struct { unsigned int slot$il_cycle_count_freq_l; unsigned int slot$il_cycle_count_freq_h; } slot$r_cycle_count_freq_fields; } slot$r_cycle_count_freq_overlay; /* */ /* Clock Interrupt Frequency */ /*************************** */ __union { unsigned __int64 slot$iq_clock_int_freq; /* Clock interrupt frequency */ __struct { unsigned int slot$il_clock_int_freq_l; unsigned int slot$il_clock_int_freq_h; } slot$r_clock_int_freq_fields; } slot$r_clock_int_freq_overlay; /* */ /* The rest is reserved for architecture use. */ /******************************************** */ unsigned __int64 slot$q_fill1 [2]; /* Reserved for architecture use. */ } CPU_SLOT; #if !defined(__VAXC) #define slot$iq_state slot$r_state_overlay.slot$iq_state #define slot$il_state slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$il_state #define slot$v_bip slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_bip #define slot$v_rc slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_rc #define slot$v_pa slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pa #define slot$v_pp slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pp #define slot$v_oh slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_oh #define slot$v_cv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_cv #define slot$v_pv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pv #define slot$v_pmv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pmv #define slot$v_pl slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pl #define slot$v_rsvd slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_rsvd #define slot$v_hltreq slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_hltreq #define slot$il_state_h slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields2_overlay.slot$il_state_h #define slot$v_partid slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields2_overlay.slot$r_state_field2.slot$v_partid #define slot$iq_pal_mem_len slot$r_pal_mem_len_overlay.slot$iq_pal_mem_len #define slot$il_pal_mem_len_l slot$r_pal_mem_len_overlay.slot$r_pal_mem_len_fields.slot$il_pal_mem_len_l #define slot$il_pal_mem_len_h slot$r_pal_mem_len_overlay.slot$r_pal_mem_len_fields.slot$il_pal_mem_len_h #define slot$iq_pal_scr_len slot$r_pal_scr_len_overlay.slot$iq_pal_scr_len #define slot$il_pal_scr_len_l slot$r_pal_scr_len_overlay.slot$r_pal_scr_len_fields.slot$il_pal_scr_len_l #define slot$il_pal_scr_len_h slot$r_pal_scr_len_overlay.slot$r_pal_scr_len_fields.slot$il_pal_scr_len_h #define slot$iq_pal_mem_pa slot$r_pal_mem_pa_overlay.slot$iq_pal_mem_pa #define slot$il_pal_mem_pa_l slot$r_pal_mem_pa_overlay.slot$r_pal_mem_pa_fields.slot$il_pal_mem_pa_l #define slot$il_pal_mem_pa_h slot$r_pal_mem_pa_overlay.slot$r_pal_mem_pa_fields.slot$il_pal_mem_pa_h #define slot$iq_pal_scr_adr slot$r_pal_scr_adr_overlay.slot$iq_pal_scr_adr #define slot$il_pal_scr_adr_l slot$r_pal_scr_adr_overlay.slot$r_pal_scr_adr_fields.slot$il_pal_scr_adr_l #define slot$il_pal_scr_adr_h slot$r_pal_scr_adr_overlay.slot$r_pal_scr_adr_fields.slot$il_pal_scr_adr_h #define slot$iq_pal_rev slot$r_pal_rev_overlay.slot$iq_pal_rev #define slot$il_pal_rev_l slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$il_pal_rev_l #define slot$b_pal_min_rev slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_fields.slot$b\ _pal_min_rev #define slot$b_pal_maj_rev slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_fields.slot$b\ _pal_maj_rev #define slot$b_pal_var slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_fields.slot$b_pal\ _var #define slot$il_pal_rev_h slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$il_pal_rev_h #define slot$iw_pal_compt slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$r_pal_rev_h_fields.slot\ $iw_pal_compt #define slot$iw_max_share slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$r_pal_rev_h_fields.slot\ $iw_max_share #define slot$iq_cpu_type slot$r_cpu_type_overlay.slot$iq_cpu_type #define slot$il_cpu_type_l slot$r_cpu_type_overlay.slot$r_cpu_type_fields.slot$il_cpu_type_l #define slot$il_cpu_type_h slot$r_cpu_type_overlay.slot$r_cpu_type_fields.slot$il_cpu_type_h #define slot$iq_cpu_var slot$r_cpu_var_overlay.slot$iq_cpu_var #define slot$il_cpu_var_l slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$il_cpu_var_l #define slot$v_vax_fp slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_vax_fp #define slot$v_ieee_fp slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_ieee\ _fp #define slot$v_pe slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_pe #define slot$il_cpu_var_h slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$il_cpu_var_h #define slot$iq_cpu_rev slot$r_cpu_rev_overlay.slot$iq_cpu_rev #define slot$il_cpu_rev_l slot$r_cpu_rev_overlay.slot$r_cpu_rev_fields.slot$il_cpu_rev_l #define slot$il_cpu_rev_h slot$r_cpu_rev_overlay.slot$r_cpu_rev_fields.slot$il_cpu_rev_h #define slot$iq_logout_pa slot$r_logout_pa_overlay.slot$iq_logout_pa #define slot$il_logout_pa_l slot$r_logout_pa_overlay.slot$r_logout_pa_fields.slot$il_logout_pa_l #define slot$il_logout_pa_h slot$r_logout_pa_overlay.slot$r_logout_pa_fields.slot$il_logout_pa_h #define slot$iq_logout_len slot$r_logout_len_overlay.slot$iq_logout_len #define slot$il_logout_len_l slot$r_logout_len_overlay.slot$r_logout_len_fields.slot$il_logout_len_l #define slot$il_logout_len_h slot$r_logout_len_overlay.slot$r_logout_len_fields.slot$il_logout_len_h #define slot$iq_halt_pcbb slot$r_halt_pcbb_overlay.slot$iq_halt_pcbb #define slot$il_halt_pcbb_l slot$r_halt_pcbb_overlay.slot$r_halt_pcbb_fields.slot$il_halt_pcbb_l #define slot$il_halt_pcbb_h slot$r_halt_pcbb_overlay.slot$r_halt_pcbb_fields.slot$il_halt_pcbb_h #define slot$iq_halt_pc slot$r_halt_pc_overlay.slot$iq_halt_pc #define slot$il_halt_pc_l slot$r_halt_pc_overlay.slot$r_halt_pc_fields.slot$il_halt_pc_l #define slot$il_halt_pc_h slot$r_halt_pc_overlay.slot$r_halt_pc_fields.slot$il_halt_pc_h #define slot$iq_halt_ps slot$r_halt_ps_overlay.slot$iq_halt_ps #define slot$il_halt_ps_l slot$r_halt_ps_overlay.slot$r_halt_ps_fields.slot$il_halt_ps_l #define slot$il_halt_ps_h slot$r_halt_ps_overlay.slot$r_halt_ps_fields.slot$il_halt_ps_h #define slot$iq_halt_arg slot$r_halt_arg_overlay.slot$iq_halt_arg #define slot$il_halt_arg_l slot$r_halt_arg_overlay.slot$r_halt_arg_fields.slot$il_halt_arg_l #define slot$il_halt_arg_h slot$r_halt_arg_overlay.slot$r_halt_arg_fields.slot$il_halt_arg_h #define slot$iq_halt_ret slot$r_halt_ret_overlay.slot$iq_halt_ret #define slot$il_halt_ret_l slot$r_halt_ret_overlay.slot$r_halt_ret_fields.slot$il_halt_ret_l #define slot$il_halt_ret_h slot$r_halt_ret_overlay.slot$r_halt_ret_fields.slot$il_halt_ret_h #define slot$iq_halt_pv slot$r_halt_pv_overlay.slot$iq_halt_pv #define slot$il_halt_pv_l slot$r_halt_pv_overlay.slot$r_halt_pv_fields.slot$il_halt_pv_l #define slot$il_halt_pv_h slot$r_halt_pv_overlay.slot$r_halt_pv_fields.slot$il_halt_pv_h #define slot$iq_haltcode slot$r_haltcode_overlay.slot$iq_haltcode #define slot$il_haltcode_l slot$r_haltcode_overlay.slot$r_haltcode_fields.slot$il_haltcode_l #define slot$il_haltcode_h slot$r_haltcode_overlay.slot$r_haltcode_fields.slot$il_haltcode_h #define slot$iq_soft_flags slot$r_soft_flags_overlay.slot$iq_soft_flags #define slot$il_soft_flags_l slot$r_soft_flags_overlay.slot$r_soft_flags_fields.slot$il_soft_flags_l #define slot$il_soft_flags_h slot$r_soft_flags_overlay.slot$r_soft_flags_fields.slot$il_soft_flags_h #define slot$b_incon_buf_area slot$r_incon_buf_overlay.slot$b_incon_buf_area #define slot$il_rxlen slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$il_rxlen #define slot$il_txlen slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$il_txlen #define slot$b_rxbuffer slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$b_rxbuffer #define slot$b_txbuffer slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$b_txbuffer #define slot$iq_cpu_sw_comp slot$r_cpu_sw_comp_overlay.slot$iq_cpu_sw_comp #define slot$il_cpu_sw_comp_l slot$r_cpu_sw_comp_overlay.slot$r_cpu_sw_comp_fields.slot$il_cpu_sw_comp_l #define slot$il_cpu_sw_comp_h slot$r_cpu_sw_comp_overlay.slot$r_cpu_sw_comp_fields.slot$il_cpu_sw_comp_h #define slot$iq_console_data_pa slot$r_console_data_pa_overlay.slot$iq_console_data_pa #define slot$il_console_data_pa_l slot$r_console_data_pa_overlay.slot$r_console_data_pa_fields.slot$il_console_data_pa_l #define slot$il_console_data_pa_h slot$r_console_data_pa_overlay.slot$r_console_data_pa_fields.slot$il_console_data_pa_h #define slot$iq_console_data_size slot$r_console_data_size_overlay.slot$iq_console_data_size #define slot$il_console_data_size_l slot$r_console_data_size_overlay.slot$r_console_data_size_fields.slot$il_console_data_size_l #define slot$il_console_data_size_h slot$r_console_data_size_overlay.slot$r_console_data_size_fields.slot$il_console_data_size_h #define slot$iq_cpu_cache slot$r_cpu_cache_overlay.slot$iq_cpu_cache #define slot$il_cpu_cache_l slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$il_cpu_cache_l #define slot$il_cpu_cache_h slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$r_cpu_cache_fields_overlay.slot$il_cpu_cache_h #define slot$b_cpu_cache_assoc_degree slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$r_cpu_cache_fields_overlay.slot$r_cpu_c\ ache_field1.slot$b_cpu_cache_assoc_degree #define slot$v_cpu_cache_write_back slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$r_cpu_cache_fields_overlay.slot$r_cpu_cac\ he_field1.slot$r_cpu_cache_field2.slot$v_cpu_cache_write_back #define slot$iw_cpu_cache_block_size slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$r_cpu_cache_fields_overlay.slot$r_cpu_ca\ che_field1.slot$iw_cpu_cache_block_size #define slot$iq_cycle_count_freq slot$r_cycle_count_freq_overlay.slot$iq_cycle_count_freq #define slot$il_cycle_count_freq_l slot$r_cycle_count_freq_overlay.slot$r_cycle_count_freq_fields.slot$il_cycle_count_freq_l #define slot$il_cycle_count_freq_h slot$r_cycle_count_freq_overlay.slot$r_cycle_count_freq_fields.slot$il_cycle_count_freq_h #define slot$iq_clock_int_freq slot$r_clock_int_freq_overlay.slot$iq_clock_int_freq #define slot$il_clock_int_freq_l slot$r_clock_int_freq_overlay.slot$r_clock_int_freq_fields.slot$il_clock_int_freq_l #define slot$il_clock_int_freq_h slot$r_clock_int_freq_overlay.slot$r_clock_int_freq_fields.slot$il_clock_int_freq_h #endif /* #if !defined(__VAXC) */ /* */ /* Length of SLOT$ is defined to be rounded to nearest 128 bytes */ /* */ #define SLOT$C_LENGTH 768 #define SLOT$K_LENGTH 768 #define SLOT$S_SLOTDEF 656 /* Old size name, synonym */ /* */ /* HWPCB structure in Per-CPU slot definitions - zero relative */ /************************************************************* */ #define HWPCB$M_ASTEN 0xF #define HWPCB$M_ASTSR 0xF0 #define HWPCB$M_ASTEN_KEN 0x1 #define HWPCB$M_ASTEN_EEN 0x2 #define HWPCB$M_ASTEN_SEN 0x4 #define HWPCB$M_ASTEN_UEN 0x8 #define HWPCB$M_ASTSR_KPD 0x10 #define HWPCB$M_ASTSR_EPD 0x20 #define HWPCB$M_ASTSR_SPD 0x40 #define HWPCB$M_ASTSR_UPD 0x80 #define HWPCB$M_FEN 0x1 #define HWPCB$M_PME 0x4000000000000000 #define HWPCB$M_DATFX 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hwpcb { /* */ /* Base of HWPCB */ /*************** */ #pragma __nomember_alignment __union { unsigned __int64 hwpcb$iq_hwpcb_base; /* Base of HWPCB */ /* */ /* Kernel Stack Pointer */ /********************** */ __union { unsigned __int64 hwpcb$iq_ksp; /* Kernel stack pointer */ __struct { unsigned int hwpcb$il_ksp_l; unsigned int hwpcb$il_ksp_h; } hwpcb$r_ksp_fields; } hwpcb$r_ksp_overlay; } hwpcb$r_hwpcb_overlay; /* */ /* Executive Stack Pointer */ /************************* */ __union { unsigned __int64 hwpcb$iq_esp; /* Executive stack pointer */ __struct { unsigned int hwpcb$il_esp_l; unsigned int hwpcb$il_esp_h; } hwpcb$r_esp_fields; } hwpcb$r_esp_overlay; /* */ /* Supervisor Stack Pointer */ /************************** */ __union { unsigned __int64 hwpcb$iq_ssp; /* Supervisor stack pointer */ __struct { unsigned int hwpcb$il_ssp_l; unsigned int hwpcb$il_ssp_h; } hwpcb$r_ssp_fields; } hwpcb$r_ssp_overlay; /* */ /* User Stack Pointer */ /******************** */ __union { unsigned __int64 hwpcb$iq_usp; /* User stack pointer */ __struct { unsigned int hwpcb$il_usp_l; unsigned int hwpcb$il_usp_h; } hwpcb$r_usp_fields; } hwpcb$r_usp_overlay; /* */ /* Page Table Base Register */ /************************** */ __union { unsigned __int64 hwpcb$iq_ptbr; /* Page Table Base Register */ __struct { unsigned int hwpcb$il_ptbr_l; unsigned int hwpcb$il_ptbr_h; } hwpcb$r_ptbr_fields; } hwpcb$r_ptbr_overlay; /* */ /* Address Space Number (ASN) */ /**************************** */ __union { unsigned __int64 hwpcb$iq_asn; /* Address space number */ __struct { unsigned int hwpcb$il_asn_l; unsigned int hwpcb$il_asn_h; } hwpcb$r_asn_fields; } hwpcb$r_asn_overlay; /* */ /* AST Enable and Summary Registers (ASTSR and ASTEN) */ /**************************************************** */ __union { unsigned __int64 hwpcb$iq_astsr_asten; /* ASTSR / ASTEN quadword */ __struct { unsigned int hwpcb$il_ast_l; unsigned int hwpcb$il_ast_h; } hwpcb$r_ast_fields; __struct { unsigned hwpcb$v_asten : 4; /* AST Enable Register */ unsigned hwpcb$v_astsr : 4; /* AST Pending Summary Register */ } hwpcb$r_ast_bits0; __struct { unsigned hwpcb$v_asten_ken : 1; /* Kernel AST Enable = 1 */ unsigned hwpcb$v_asten_een : 1; /* Executive AST Enable = 1 */ unsigned hwpcb$v_asten_sen : 1; /* Supervisor AST Enable = 1 */ unsigned hwpcb$v_asten_uen : 1; /* User AST Enable = 1 */ unsigned hwpcb$v_astsr_kpd : 1; /* Kernel AST Pending = 1 */ unsigned hwpcb$v_astsr_epd : 1; /* Executive AST Pending = 1 */ unsigned hwpcb$v_astsr_spd : 1; /* Supervisor AST Pending = 1 */ unsigned hwpcb$v_astsr_upd : 1; /* User AST Pending = 1 */ } hwpcb$r_ast_bits1; } hwpcb$r_ast_overlay; /* */ /* Floating Point Enable Register (FEN) */ /************************************** */ __union { unsigned __int64 hwpcb$iq_fen; /* Floating Point Enable / PME / DATFX */ __struct { unsigned int hwpcb$il_fen_l; unsigned int hwpcb$il_fen_h; } hwpcb$r_fen_fields; __struct { unsigned hwpcb$v_fen : 1; /* Floating Point Enable = 1 */ unsigned hwpcb$v_fill_61_1 : 32; unsigned hwpcb$v_fill_61_2 : 29; unsigned hwpcb$v_pme : 1; /* Performance Monitor Enable */ unsigned hwpcb$v_datfx : 1; /* Data Alignment Trap Fixup */ } hwpcb$r_fen_datfx_overlay; } hwpcb$r_fen_overlay; /* */ /* Cycle Counter */ /*************** */ __union { unsigned __int64 hwpcb$iq_cc; /* Cycle Counter */ __struct { unsigned int hwpcb$il_cc_l; unsigned int hwpcb$il_cc_h; } hwpcb$r_cc_fields; } hwpcb$r_cc_overlay; /* */ /* Process Unique Value */ /********************** */ __union { unsigned __int64 hwpcb$iq_unq; /* Process Unique Value */ __struct { unsigned int hwpcb$il_unq_l; unsigned int hwpcb$il_unq_h; } hwpcb$r_unq_fields; } hwpcb$r_unq_overlay; /* */ /* CPU Id */ /* */ unsigned int hwpcb$l_cpu_id; /* CPU id */ int hwpcb$l_reserved_1; /* */ /* Reserved for PALcode scratch */ /****************************** */ __union { __int64 hwpcb$iq_pal_rsvd [5]; /* Reserved for PAL scratch */ __struct { unsigned int hwpcb$il_pal_rsvd_l; unsigned int hwpcb$il_pal_rsvd_h; } hwpcb$r_pal_rsvd_fields; } hwpcb$r_pal_rsvd_overlay; } HWPCB; #if !defined(__VAXC) #define hwpcb$iq_hwpcb_base hwpcb$r_hwpcb_overlay.hwpcb$iq_hwpcb_base #define hwpcb$iq_ksp hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$iq_ksp #define hwpcb$il_ksp_l hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$r_ksp_fields.hwpcb$il_ksp_l #define hwpcb$il_ksp_h hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$r_ksp_fields.hwpcb$il_ksp_h #define hwpcb$iq_esp hwpcb$r_esp_overlay.hwpcb$iq_esp #define hwpcb$il_esp_l hwpcb$r_esp_overlay.hwpcb$r_esp_fields.hwpcb$il_esp_l #define hwpcb$il_esp_h hwpcb$r_esp_overlay.hwpcb$r_esp_fields.hwpcb$il_esp_h #define hwpcb$iq_ssp hwpcb$r_ssp_overlay.hwpcb$iq_ssp #define hwpcb$il_ssp_l hwpcb$r_ssp_overlay.hwpcb$r_ssp_fields.hwpcb$il_ssp_l #define hwpcb$il_ssp_h hwpcb$r_ssp_overlay.hwpcb$r_ssp_fields.hwpcb$il_ssp_h #define hwpcb$iq_usp hwpcb$r_usp_overlay.hwpcb$iq_usp #define hwpcb$il_usp_l hwpcb$r_usp_overlay.hwpcb$r_usp_fields.hwpcb$il_usp_l #define hwpcb$il_usp_h hwpcb$r_usp_overlay.hwpcb$r_usp_fields.hwpcb$il_usp_h #define hwpcb$iq_ptbr hwpcb$r_ptbr_overlay.hwpcb$iq_ptbr #define hwpcb$il_ptbr_l hwpcb$r_ptbr_overlay.hwpcb$r_ptbr_fields.hwpcb$il_ptbr_l #define hwpcb$il_ptbr_h hwpcb$r_ptbr_overlay.hwpcb$r_ptbr_fields.hwpcb$il_ptbr_h #define hwpcb$iq_asn hwpcb$r_asn_overlay.hwpcb$iq_asn #define hwpcb$il_asn_l hwpcb$r_asn_overlay.hwpcb$r_asn_fields.hwpcb$il_asn_l #define hwpcb$il_asn_h hwpcb$r_asn_overlay.hwpcb$r_asn_fields.hwpcb$il_asn_h #define hwpcb$iq_astsr_asten hwpcb$r_ast_overlay.hwpcb$iq_astsr_asten #define hwpcb$il_ast_l hwpcb$r_ast_overlay.hwpcb$r_ast_fields.hwpcb$il_ast_l #define hwpcb$il_ast_h hwpcb$r_ast_overlay.hwpcb$r_ast_fields.hwpcb$il_ast_h #define hwpcb$v_asten hwpcb$r_ast_overlay.hwpcb$r_ast_bits0.hwpcb$v_asten #define hwpcb$v_astsr hwpcb$r_ast_overlay.hwpcb$r_ast_bits0.hwpcb$v_astsr #define hwpcb$v_asten_ken hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_ken #define hwpcb$v_asten_een hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_een #define hwpcb$v_asten_sen hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_sen #define hwpcb$v_asten_uen hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_uen #define hwpcb$v_astsr_kpd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_kpd #define hwpcb$v_astsr_epd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_epd #define hwpcb$v_astsr_spd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_spd #define hwpcb$v_astsr_upd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_upd #define hwpcb$iq_fen hwpcb$r_fen_overlay.hwpcb$iq_fen #define hwpcb$il_fen_l hwpcb$r_fen_overlay.hwpcb$r_fen_fields.hwpcb$il_fen_l #define hwpcb$il_fen_h hwpcb$r_fen_overlay.hwpcb$r_fen_fields.hwpcb$il_fen_h #define hwpcb$v_fen hwpcb$r_fen_overlay.hwpcb$r_fen_datfx_overlay.hwpcb$v_fen #define hwpcb$v_pme hwpcb$r_fen_overlay.hwpcb$r_fen_datfx_overlay.hwpcb$v_pme #define hwpcb$v_datfx hwpcb$r_fen_overlay.hwpcb$r_fen_datfx_overlay.hwpcb$v_datfx #define hwpcb$iq_cc hwpcb$r_cc_overlay.hwpcb$iq_cc #define hwpcb$il_cc_l hwpcb$r_cc_overlay.hwpcb$r_cc_fields.hwpcb$il_cc_l #define hwpcb$il_cc_h hwpcb$r_cc_overlay.hwpcb$r_cc_fields.hwpcb$il_cc_h #define hwpcb$iq_unq hwpcb$r_unq_overlay.hwpcb$iq_unq #define hwpcb$il_unq_l hwpcb$r_unq_overlay.hwpcb$r_unq_fields.hwpcb$il_unq_l #define hwpcb$il_unq_h hwpcb$r_unq_overlay.hwpcb$r_unq_fields.hwpcb$il_unq_h #define hwpcb$iq_pal_rsvd hwpcb$r_pal_rsvd_overlay.hwpcb$iq_pal_rsvd #define hwpcb$il_pal_rsvd_l hwpcb$r_pal_rsvd_overlay.hwpcb$r_pal_rsvd_fields.hwpcb$il_pal_rsvd_l #define hwpcb$il_pal_rsvd_h hwpcb$r_pal_rsvd_overlay.hwpcb$r_pal_rsvd_fields.hwpcb$il_pal_rsvd_h #endif /* #if !defined(__VAXC) */ /* */ #define HWPCB$C_LENGTH 128 /* Length of HWPCB$ */ #define HWPCB$K_LENGTH 128 /* Length of HWPCB$ */ #define HWPCB$S_HWPCBDEF 128 /* Old size name - synonym */ /* */ /* Physical Memory Cluster Descriptor Table (MEMDSC) */ /*************************************************** */ #define HWRPB_PMD$C_LENGTH 24 /* Length of HWRPB_PMD$ */ #define HWRPB_PMD$K_LENGTH 24 /* Length of HWRPB_PMD$ */ /* */ #define HWRPB_PMD$S_NULLPMDDEF 80 /* Size of NULL memory descr. */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _pmd { /* */ /* Checksum of Memory Descriptor from MEMDSC+8 through MEMDSC_END */ /**************************************************************** */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_pmd$iq_chksum; /* Checksum of PMD+8 to PMD+end */ __struct { unsigned int hwrpb_pmd$il_chksum_l; unsigned int hwrpb_pmd$il_chksum_h; } hwrpb_pmd$r_chksum_fields; } hwrpb_pmd$r_chksum_overlay; /* */ /* Optional Implementation-Specific Data */ /*************************************** */ __union { unsigned __int64 hwrpb_pmd$iq_opt_data; /* Optional data */ __struct { unsigned int hwrpb_pmd$il_opt_data_l; unsigned int hwrpb_pmd$il_opt_data_h; } hwrpb_pmd$r_opt_data_fields; } hwrpb_pmd$r_opt_data_overlay; /* */ /* Number of Memory Clusters in MEMDSC */ /************************************* */ __union { unsigned __int64 hwrpb_pmd$iq_cluster_count; /* Count of clusters present */ __struct { unsigned int hwrpb_pmd$il_cluster_count_l; unsigned int hwrpb_pmd$il_cluster_count_h; } hwrpb_pmd$r_cluster_count_fields; } hwrpb_pmd$r_cluster_count_overlay; /* */ /* Physical Memory Region (PMR) */ /****************************** */ __union { /* */ /* For system with PHYSICALLY DIS-CONTIGUOUS memory, PMR points to */ /* an array of Physical Memory Regions (PMR). */ /* */ __union { unsigned __int64 hwrpb_pmd$iq_pmr; /* Start of first region */ __struct { unsigned int hwrpb_pmd$il_pmr_l; unsigned int hwrpb_pmd$il_pmr_h; } hwrpb_pmd$r_pmr_fields; } hwrpb_pmd$r_pmr_overlay; /* */ /* For system with PHYSICALLY CONTIGUOUS memory, there are only two regions */ /* defined. The first region describes memory in use by the console, and the */ /* second region describes memory for use by the system. */ /* */ __union { unsigned __int64 hwrpb_pmd$iq_cn_pfn_start; /* Start PFN of console region */ __struct { unsigned int hwrpb_pmd$il_cn_pfn_start_l; unsigned int hwrpb_pmd$il_cn_pfn_start_h; } hwrpb_pmd$r_cn_pfn_start_fields; } hwrpb_pmd$r_cn_pfn_start_overlay; /* */ /* For system with DYNAMIC memory descriptors, there is only one region defined. It is a */ /* NULL cluster descriptor. It describes the listheads of shared and private memory cluster */ /* descriptors. The first field which is normally the PFN_START field, must be set to -1. */ __union { __int64 hwrpb_pmd$iq_null_mbmo; /* Must be minus one */ __struct { int hwrpb_pmd$il_null_mbmo_l; int hwrpb_pmd$il_null_mbmo_h; } hwrpb_pmd$r_null_mbmo_fields; } hwrpb_pmd$r_null_mbmo_overlay; } hwrpb_pmd$r_pmr_region_overlay; __union { /* */ /* Number of Page Frame Numbers (PFNs) in the region */ /*************************************************** */ unsigned __int64 hwrpb_pmd$iq_cn_pfn_count; /* Number of PFNs in region */ __struct { unsigned int hwrpb_pmd$il_cn_pfn_count_l; unsigned int hwrpb_pmd$il_cn_pfn_count_h; } hwrpb_pmd$r_cn_pfn_count_fields; /* */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ __int64 hwrpb_pmd$iq_null_mbz; /* Must be zero */ __struct { int hwrpb_pmd$il_null_mbz_l; int hwrpb_pmd$il_null_mbz_h; } hwrpb_pmd$r_null_mbz_fields; } hwrpb_pmd$r_cn_pfn_count_overlay; __union { /* */ /* Number of tested PFNs in the region */ /************************************* */ unsigned __int64 hwrpb_pmd$iq_cn_test_count; /* Num. of tested PFNs in region */ __struct { unsigned int hwrpb_pmd$il_cn_test_count_l; unsigned int hwrpb_pmd$il_cn_test_count_h; } hwrpb_pmd$r_cn_test_count_fields; /* */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ } hwrpb_pmd$r_cn_test_count_overlay; __union { /* */ /* Virtual Address of Memory bitmap */ /********************************** */ unsigned __int64 hwrpb_pmd$iq_cn_bitmap_va; /* VA of bitmap */ __struct { unsigned int hwrpb_pmd$il_cn_bitmap_va_l; unsigned int hwrpb_pmd$il_cn_bitmap_va_h; } hwrpb_pmd$r_cn_bitmap_va_fields; /* */ /* Physical offset to listhead of shared MCDs */ /* in NULL cluster descriptor */ /******************************************** */ unsigned __int64 hwrpb_pmd$iq_null_shr_lh; __struct { unsigned int hwrpb_pmd$il_null_shr_lh_l; unsigned int hwrpb_pmd$il_null_shr_lh_h; } hwrpb_pmd$r_null_shr_lh_fields; } hwrpb_pmd$r_cn_bitmap_va_overlay; __union { /* */ /* Physical Address of bitmap */ /**************************** */ unsigned __int64 hwrpb_pmd$iq_cn_bitmap_pa; /* PA of bitmap */ __struct { unsigned int hwrpb_pmd$il_cn_bitmap_pa_l; unsigned int hwrpb_pmd$il_cn_bitmap_pa_h; } hwrpb_pmd$r_cn_bitmap_pa_fields; /* */ /* Physical offset to first MCD in private list */ /* in NULL cluster descriptor */ /********************************************** */ unsigned __int64 hwrpb_pmd$iq_null_prv_offset; __struct { unsigned int hwrpb_pmd$il_null_prv_offset_l; unsigned int hwrpb_pmd$il_null_prv_offset_h; } hwrpb_pmd$r_null_prv_fields; } hwrpb_pmd$r_cn_bitmap_pa_overlay; __union { /* */ /* Checksum of bitmap */ /******************** */ unsigned __int64 hwrpb_pmd$iq_cn_bitmap_chksum; /* Checksum of bitmap */ __struct { unsigned int hwrpb_pmd$il_cn_bitmap_chksum_l; unsigned int hwrpb_pmd$il_cn_bitmap_chksum_h; } hwrpb_pmd$r_cn_bitmap_chksum_field; /* */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ } hwrpb_pmd$r_cn_bitmap_chksum_overl; __union { /* */ /* Cluster Usage Flags */ /********************* */ unsigned __int64 hwrpb_pmd$iq_cn_usage; /* Cluster usage flags */ __struct { unsigned int hwrpb_pmd$il_cn_usage_l; unsigned int hwrpb_pmd$il_cn_usage_h; } hwrpb_pmd$r_cn_usage_fields; /* */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ } hwrpb_pmd$r_cn_usage_overlay; /* Start PFN of system region */ /**************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_pfn_start; /* Start PFN of system region */ __struct { unsigned int hwrpb_pmd$il_sy_pfn_start_l; unsigned int hwrpb_pmd$il_sy_pfn_start_h; } hwrpb_pmd$r_sy_pfn_start_fields; } hwrpb_pmd$r_sy_pfn_start_overlay; /* */ /* Number of PFNs in region */ /************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_pfn_count; /* Number of PFNs in region */ __struct { unsigned int hwrpb_pmd$il_sy_pfn_count_l; unsigned int hwrpb_pmd$il_sy_pfn_count_h; } hwrpb_pmd$r_sy_pfn_count_fields; } hwrpb_pmd$r_sy_pfn_count_overlay; /* */ /* Number of tested PFNs in region */ /********************************* */ __union { unsigned __int64 hwrpb_pmd$iq_sy_test_count; /* Num. of tested PFNs in region */ __struct { unsigned int hwrpb_pmd$il_sy_test_count_l; unsigned int hwrpb_pmd$il_sy_test_count_h; } hwrpb_pmd$r_sy_test_count_fields; } hwrpb_pmd$r_sy_test_count_overlay; /* */ /* Virtual Address of bitmap */ /*************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_bitmap_va; /* VA of bitmap */ __struct { unsigned int hwrpb_pmd$il_sy_bitmap_va_l; unsigned int hwrpb_pmd$il_sy_bitmap_va_h; } hwrpb_pmd$r_sy_bitmap_va_fields; } hwrpb_pmd$r_sy_bitmap_va_overlay; /* */ /* Physical Address of bitmap */ /**************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_bitmap_pa; /* PA of bitmap */ __struct { unsigned int hwrpb_pmd$il_sy_bitmap_pa_l; unsigned int hwrpb_pmd$il_sy_bitmap_pa_h; } hwrpb_pmd$r_sy_bitmap_pa_fields; } hwrpb_pmd$r_sy_bitmap_pa_overlay; /* */ /* Checksum of bitmap */ /******************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_bitmap_chksum; /* Checksum of bitmap */ __struct { unsigned int hwrpb_pmd$il_sy_bitmap_chksum_l; unsigned int hwrpb_pmd$il_sy_bitmap_chksum_h; } hwrpb_pmd$r_sy_bitmap_chksum_field; } hwrpb_pmd$r_sy_bitmap_chksum_overl; /* */ /* Cluster Usage Flags */ /********************* */ __union { unsigned __int64 hwrpb_pmd$iq_sy_usage; /* Cluster usage flags */ __struct { unsigned int hwrpb_pmd$il_sy_usage_l; unsigned int hwrpb_pmd$il_sy_usage_h; } hwrpb_pmd$r_sy_usage_fields; } hwrpb_pmd$r_sy_usage_overlay; } PMD; #if !defined(__VAXC) #define hwrpb_pmd$iq_chksum hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$iq_chksum #define hwrpb_pmd$il_chksum_l hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$r_chksum_fields.hwrpb_pmd$il_chksum_l #define hwrpb_pmd$il_chksum_h hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$r_chksum_fields.hwrpb_pmd$il_chksum_h #define hwrpb_pmd$iq_opt_data hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$iq_opt_data #define hwrpb_pmd$il_opt_data_l hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$r_opt_data_fields.hwrpb_pmd$il_opt_data_l #define hwrpb_pmd$il_opt_data_h hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$r_opt_data_fields.hwrpb_pmd$il_opt_data_h #define hwrpb_pmd$iq_cluster_count hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$iq_cluster_count #define hwrpb_pmd$il_cluster_count_l hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$r_cluster_count_fields.hwrpb_pmd$il_cluster_count_l #define hwrpb_pmd$il_cluster_count_h hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$r_cluster_count_fields.hwrpb_pmd$il_cluster_count_h #define hwrpb_pmd$iq_pmr hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$iq_pmr #define hwrpb_pmd$il_pmr_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$r_pmr_fields.hwrpb_pmd$il_pmr_l #define hwrpb_pmd$il_pmr_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$r_pmr_fields.hwrpb_pmd$il_pmr_h #define hwrpb_pmd$iq_cn_pfn_start hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$iq_cn_pfn_start #define hwrpb_pmd$il_cn_pfn_start_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$r_cn_pfn_start_fields\ .hwrpb_pmd$il_cn_pfn_start_l #define hwrpb_pmd$il_cn_pfn_start_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$r_cn_pfn_start_fields\ .hwrpb_pmd$il_cn_pfn_start_h #define hwrpb_pmd$iq_null_mbmo hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$iq_null_mbmo #define hwrpb_pmd$il_null_mbmo_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$r_null_mbmo_fields.hwrpb_pm\ d$il_null_mbmo_l #define hwrpb_pmd$il_null_mbmo_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$r_null_mbmo_fields.hwrpb_pm\ d$il_null_mbmo_h #define hwrpb_pmd$iq_cn_pfn_count hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$iq_cn_pfn_count #define hwrpb_pmd$il_cn_pfn_count_l hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_cn_pfn_count_fields.hwrpb_pmd$il_cn_pfn_count_l #define hwrpb_pmd$il_cn_pfn_count_h hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_cn_pfn_count_fields.hwrpb_pmd$il_cn_pfn_count_h #define hwrpb_pmd$iq_null_mbz hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$iq_null_mbz #define hwrpb_pmd$il_null_mbz_l hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_null_mbz_fields.hwrpb_pmd$il_null_mbz_l #define hwrpb_pmd$il_null_mbz_h hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_null_mbz_fields.hwrpb_pmd$il_null_mbz_h #define hwrpb_pmd$iq_cn_test_count hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$iq_cn_test_count #define hwrpb_pmd$il_cn_test_count_l hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_cn_test_count_fields.hwrpb_pmd$il_cn_test_count_l #define hwrpb_pmd$il_cn_test_count_h hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_cn_test_count_fields.hwrpb_pmd$il_cn_test_count_h #define hwrpb_pmd$iq_cn_bitmap_va hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$iq_cn_bitmap_va #define hwrpb_pmd$il_cn_bitmap_va_l hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_cn_bitmap_va_fields.hwrpb_pmd$il_cn_bitmap_va_l #define hwrpb_pmd$il_cn_bitmap_va_h hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_cn_bitmap_va_fields.hwrpb_pmd$il_cn_bitmap_va_h #define hwrpb_pmd$iq_null_shr_lh hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$iq_null_shr_lh #define hwrpb_pmd$il_null_shr_lh_l hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_null_shr_lh_fields.hwrpb_pmd$il_null_shr_lh_l #define hwrpb_pmd$il_null_shr_lh_h hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_null_shr_lh_fields.hwrpb_pmd$il_null_shr_lh_h #define hwrpb_pmd$iq_cn_bitmap_pa hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$iq_cn_bitmap_pa #define hwrpb_pmd$il_cn_bitmap_pa_l hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_cn_bitmap_pa_fields.hwrpb_pmd$il_cn_bitmap_pa_l #define hwrpb_pmd$il_cn_bitmap_pa_h hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_cn_bitmap_pa_fields.hwrpb_pmd$il_cn_bitmap_pa_h #define hwrpb_pmd$iq_null_prv_offset hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$iq_null_prv_offset #define hwrpb_pmd$il_null_prv_offset_l hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_null_prv_fields.hwrpb_pmd$il_null_prv_offset_l #define hwrpb_pmd$il_null_prv_offset_h hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_null_prv_fields.hwrpb_pmd$il_null_prv_offset_h #define hwrpb_pmd$iq_cn_bitmap_chksum hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$iq_cn_bitmap_chksum #define hwrpb_pmd$il_cn_bitmap_chksum_l hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_cn_bitmap_chksum_field.hwrpb_pmd$il_cn_bitma\ p_chksum_l #define hwrpb_pmd$il_cn_bitmap_chksum_h hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_cn_bitmap_chksum_field.hwrpb_pmd$il_cn_bitma\ p_chksum_h #define hwrpb_pmd$iq_cn_usage hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$iq_cn_usage #define hwrpb_pmd$il_cn_usage_l hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_cn_usage_fields.hwrpb_pmd$il_cn_usage_l #define hwrpb_pmd$il_cn_usage_h hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_cn_usage_fields.hwrpb_pmd$il_cn_usage_h #define hwrpb_pmd$iq_sy_pfn_start hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$iq_sy_pfn_start #define hwrpb_pmd$il_sy_pfn_start_l hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$r_sy_pfn_start_fields.hwrpb_pmd$il_sy_pfn_start_l #define hwrpb_pmd$il_sy_pfn_start_h hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$r_sy_pfn_start_fields.hwrpb_pmd$il_sy_pfn_start_h #define hwrpb_pmd$iq_sy_pfn_count hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$iq_sy_pfn_count #define hwrpb_pmd$il_sy_pfn_count_l hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$r_sy_pfn_count_fields.hwrpb_pmd$il_sy_pfn_count_l #define hwrpb_pmd$il_sy_pfn_count_h hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$r_sy_pfn_count_fields.hwrpb_pmd$il_sy_pfn_count_h #define hwrpb_pmd$iq_sy_test_count hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$iq_sy_test_count #define hwrpb_pmd$il_sy_test_count_l hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$r_sy_test_count_fields.hwrpb_pmd$il_sy_test_count_l #define hwrpb_pmd$il_sy_test_count_h hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$r_sy_test_count_fields.hwrpb_pmd$il_sy_test_count_h #define hwrpb_pmd$iq_sy_bitmap_va hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$iq_sy_bitmap_va #define hwrpb_pmd$il_sy_bitmap_va_l hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$r_sy_bitmap_va_fields.hwrpb_pmd$il_sy_bitmap_va_l #define hwrpb_pmd$il_sy_bitmap_va_h hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$r_sy_bitmap_va_fields.hwrpb_pmd$il_sy_bitmap_va_h #define hwrpb_pmd$iq_sy_bitmap_pa hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$iq_sy_bitmap_pa #define hwrpb_pmd$il_sy_bitmap_pa_l hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$r_sy_bitmap_pa_fields.hwrpb_pmd$il_sy_bitmap_pa_l #define hwrpb_pmd$il_sy_bitmap_pa_h hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$r_sy_bitmap_pa_fields.hwrpb_pmd$il_sy_bitmap_pa_h #define hwrpb_pmd$iq_sy_bitmap_chksum hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$iq_sy_bitmap_chksum #define hwrpb_pmd$il_sy_bitmap_chksum_l hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$r_sy_bitmap_chksum_field.hwrpb_pmd$il_sy_bitma\ p_chksum_l #define hwrpb_pmd$il_sy_bitmap_chksum_h hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$r_sy_bitmap_chksum_field.hwrpb_pmd$il_sy_bitma\ p_chksum_h #define hwrpb_pmd$iq_sy_usage hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$iq_sy_usage #define hwrpb_pmd$il_sy_usage_l hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$r_sy_usage_fields.hwrpb_pmd$il_sy_usage_l #define hwrpb_pmd$il_sy_usage_h hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$r_sy_usage_fields.hwrpb_pmd$il_sy_usage_h #endif /* #if !defined(__VAXC) */ /* */ #define HWRPB_PMD$S_PMDDEF 136 /* Old size name - synonym */ /* */ /* Physical memory region descriptor */ /*********************************** */ #define HWRPB_PMR$M_CONSOLE 0x1 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _pmreg { /* */ /* Starting PFN in region */ /************************ */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_pmr$iq_pfn_start; /* Starting PFN in region */ __struct { unsigned int hwrpb_pmr$il_pfn_start_l; unsigned int hwrpb_pmr$il_pfn_start_h; } hwrpb_pmr$r_pfn_start_fields; } hwrpb_pmr$r_pfn_start_overlay; /* */ /* Number of PFNs in region */ /************************** */ __union { unsigned __int64 hwrpb_pmr$iq_pfn_count; /* Number of PFNs in region */ __struct { unsigned int hwrpb_pmr$il_pfn_count_l; unsigned int hwrpb_pmr$il_pfn_count_h; } hwrpb_pmr$r_pfn_count_fields; } hwrpb_pmr$r_pfn_count_overlay; /* */ /* Number of tested PFNs in region */ /********************************* */ __union { unsigned __int64 hwrpb_pmr$iq_test_count; /* Num. of tested PFNs in region */ __struct { unsigned int hwrpb_pmr$il_test_count_l; unsigned int hwrpb_pmr$il_test_count_h; } hwrpb_pmr$r_test_count_fields; } hwrpb_pmr$r_test_count_overlay; /* */ /* Virtual Address of bitmap */ /*************************** */ __union { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb_pmr$pq_bitmap_va; /* VA of bitmap */ #else unsigned __int64 hwrpb_pmr$pq_bitmap_va; #endif __struct { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif void *hwrpb_pmr$pl_bitmap_va_l; unsigned int hwrpb_pmr$il_bitmap_va_h; } hwrpb_pmr$r_bitmap_va_fields; } hwrpb_pmr$r_bitmap_va_overlay; /* */ /* Physical Address of bitmap */ /**************************** */ __union { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb_pmr$pq_bitmap_pa; /* PA of bitmap */ #else unsigned __int64 hwrpb_pmr$pq_bitmap_pa; #endif __struct { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif void *hwrpb_pmr$pl_bitmap_pa_l; unsigned int hwrpb_pmr$il_bitmap_pa_h; } hwrpb_pmr$r_bitmap_pa_fields; } hwrpb_pmr$r_bitmap_pa_overlay; /* */ /* Checksum of bitmap */ /******************** */ __union { unsigned __int64 hwrpb_pmr$iq_bitmap_chksum; /* Checksum of bitmap */ __struct { unsigned int hwrpb_pmr$il_bitmap_chksum_l; unsigned int hwrpb_pmr$il_bitmap_chksum_h; } hwrpb_pmr$r_bitmap_chksum_fields; } hwrpb_pmr$r_bitmap_chksum_overlay; /* */ /* Cluster Usage Flags */ /********************* */ __union { unsigned __int64 hwrpb_pmr$iq_usage; /* Cluster usage flags */ __struct { __union { unsigned int hwrpb_pmr$il_usage_l; __struct { unsigned hwrpb_pmr$v_console : 1; /* Cluster reserved by console */ unsigned hwrpb_pmr$v_fill1 : 31 /** WARNING: bitfield array has been reduced to a string **/ ; } hwrpb_pmr$r_usage_field1; } hwrpb_pmr$r_usage_fields_overlay; unsigned int hwrpb_pmr$il_usage_h; } hwrpb_pmr$r_usage_fields; } hwrpb_pmr$r_usage_overlay; } PMREG; #if !defined(__VAXC) #define hwrpb_pmr$iq_pfn_start hwrpb_pmr$r_pfn_start_overlay.hwrpb_pmr$iq_pfn_start #define hwrpb_pmr$il_pfn_start_l hwrpb_pmr$r_pfn_start_overlay.hwrpb_pmr$r_pfn_start_fields.hwrpb_pmr$il_pfn_start_l #define hwrpb_pmr$il_pfn_start_h hwrpb_pmr$r_pfn_start_overlay.hwrpb_pmr$r_pfn_start_fields.hwrpb_pmr$il_pfn_start_h #define hwrpb_pmr$iq_pfn_count hwrpb_pmr$r_pfn_count_overlay.hwrpb_pmr$iq_pfn_count #define hwrpb_pmr$il_pfn_count_l hwrpb_pmr$r_pfn_count_overlay.hwrpb_pmr$r_pfn_count_fields.hwrpb_pmr$il_pfn_count_l #define hwrpb_pmr$il_pfn_count_h hwrpb_pmr$r_pfn_count_overlay.hwrpb_pmr$r_pfn_count_fields.hwrpb_pmr$il_pfn_count_h #define hwrpb_pmr$iq_test_count hwrpb_pmr$r_test_count_overlay.hwrpb_pmr$iq_test_count #define hwrpb_pmr$il_test_count_l hwrpb_pmr$r_test_count_overlay.hwrpb_pmr$r_test_count_fields.hwrpb_pmr$il_test_count_l #define hwrpb_pmr$il_test_count_h hwrpb_pmr$r_test_count_overlay.hwrpb_pmr$r_test_count_fields.hwrpb_pmr$il_test_count_h #define hwrpb_pmr$pq_bitmap_va hwrpb_pmr$r_bitmap_va_overlay.hwrpb_pmr$pq_bitmap_va #define hwrpb_pmr$pl_bitmap_va_l hwrpb_pmr$r_bitmap_va_overlay.hwrpb_pmr$r_bitmap_va_fields.hwrpb_pmr$pl_bitmap_va_l #define hwrpb_pmr$il_bitmap_va_h hwrpb_pmr$r_bitmap_va_overlay.hwrpb_pmr$r_bitmap_va_fields.hwrpb_pmr$il_bitmap_va_h #define hwrpb_pmr$pq_bitmap_pa hwrpb_pmr$r_bitmap_pa_overlay.hwrpb_pmr$pq_bitmap_pa #define hwrpb_pmr$pl_bitmap_pa_l hwrpb_pmr$r_bitmap_pa_overlay.hwrpb_pmr$r_bitmap_pa_fields.hwrpb_pmr$pl_bitmap_pa_l #define hwrpb_pmr$il_bitmap_pa_h hwrpb_pmr$r_bitmap_pa_overlay.hwrpb_pmr$r_bitmap_pa_fields.hwrpb_pmr$il_bitmap_pa_h #define hwrpb_pmr$iq_bitmap_chksum hwrpb_pmr$r_bitmap_chksum_overlay.hwrpb_pmr$iq_bitmap_chksum #define hwrpb_pmr$il_bitmap_chksum_l hwrpb_pmr$r_bitmap_chksum_overlay.hwrpb_pmr$r_bitmap_chksum_fields.hwrpb_pmr$il_bitmap_chksum_l #define hwrpb_pmr$il_bitmap_chksum_h hwrpb_pmr$r_bitmap_chksum_overlay.hwrpb_pmr$r_bitmap_chksum_fields.hwrpb_pmr$il_bitmap_chksum_h #define hwrpb_pmr$iq_usage hwrpb_pmr$r_usage_overlay.hwrpb_pmr$iq_usage #define hwrpb_pmr$il_usage_l hwrpb_pmr$r_usage_overlay.hwrpb_pmr$r_usage_fields.hwrpb_pmr$r_usage_fields_overlay.hwrpb_pmr$il_usage\ _l #define hwrpb_pmr$v_console hwrpb_pmr$r_usage_overlay.hwrpb_pmr$r_usage_fields.hwrpb_pmr$r_usage_fields_overlay.hwrpb_pmr$r_usage_f\ ield1.hwrpb_pmr$v_console #define hwrpb_pmr$il_usage_h hwrpb_pmr$r_usage_overlay.hwrpb_pmr$r_usage_fields.hwrpb_pmr$il_usage_h #endif /* #if !defined(__VAXC) */ /* */ #define HWRPB_PMR$C_LENGTH 56 /* Size of region entry */ #define HWRPB_PMR$K_LENGTH 56 /* Size of region entry */ #define HWRPB_PMR$S_PMREGDEF 56 /* Old size name - synonym */ /* */ /* Console languages */ /******************* */ #define HWRPB_LANG$K_UNKNOWN 0 #define HWRPB_LANG$K_DANISH 48 #define HWRPB_LANG$K_GERMAN 50 #define HWRPB_LANG$K_SWISS 52 #define HWRPB_LANG$K_AMERICAN 54 #define HWRPB_LANG$K_BRITISH 56 #define HWRPB_LANG$K_SPANISH 58 #define HWRPB_LANG$K_FRENCH 60 #define HWRPB_LANG$K_CANADIAN 62 #define HWRPB_LANG$K_ROMANDE 64 #define HWRPB_LANG$K_ITALIAN 66 #define HWRPB_LANG$K_NETHERLANDS 68 #define HWRPB_LANG$K_NORSK 70 #define HWRPB_LANG$K_PORTUGUESE 72 #define HWRPB_LANG$K_SUOMI 74 #define HWRPB_LANG$K_SWEDISH 76 #define HWRPB_LANG$K_VLAAMS 78 /* */ /* Console Routine Block */ /*********************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hwrpb_crb { /* */ /* Virtual Address of DISPATCH Procedure Descriptor */ /************************************************** */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_crb$iq_va_dispatch_pd; /* Virt. Addr of Procedure Desc. */ __struct { unsigned int hwrpb_crb$il_va_dispatch_pd_l; unsigned int hwrpb_crb$il_va_dispatch_pd_h; } hwrpb_crb$r_va_dispatch_pd_fields; } hwrpb_crb$r_va_dispatch_pd_overlay; /* */ /* Physical Address of DISPATCH Procedure Descriptor */ /*************************************************** */ __union { unsigned __int64 hwrpb_crb$iq_pa_dispatch_pd; /* Phy. Addr of Procedure Desc. */ __struct { unsigned int hwrpb_crb$il_pa_dispatch_pd_l; unsigned int hwrpb_crb$il_pa_dispatch_pd_h; } hwrpb_crb$r_pa_dispatch_pd_fields; } hwrpb_crb$r_pa_dispatch_pd_overlay; /* */ /* Virtual Address of FIXUP Procedure Descriptor */ /*********************************************** */ __union { unsigned __int64 hwrpb_crb$iq_va_fixup_pd; /* Virt. Addr of Procedure Desc. */ __struct { unsigned int hwrpb_crb$il_va_fixup_pd_l; unsigned int hwrpb_crb$il_va_fixup_pd_h; } hwrpb_crb$r_va_fixup_pd_fields; } hwrpb_crb$r_va_fixup_pd_overlay; /* */ /* Physical Address of FIXUP Procedure Descriptor */ /*********************************************** */ __union { unsigned __int64 hwrpb_crb$iq_pa_fixup_pd; /* Phy. Addr of Procedure Desc. */ __struct { unsigned int hwrpb_crb$il_pa_fixup_pd_l; unsigned int hwrpb_crb$il_pa_fixup_pd_h; } hwrpb_crb$r_pa_fixup_pd_fields; } hwrpb_crb$r_pa_fixup_pd_overlay; /* */ /* Number of entries in VA/PA map */ /******************************** */ __union { unsigned __int64 hwrpb_crb$iq_map_count; /* Num. of entries in VA/PA map */ __struct { unsigned int hwrpb_crb$il_map_count_l; unsigned int hwrpb_crb$il_map_count_h; } hwrpb_crb$r_map_count_fields; } hwrpb_crb$r_map_count_overlay; /* */ /* Number of pages to be mapped */ /****************************** */ __union { unsigned __int64 hwrpb_crb$iq_page_count; /* Num. of pages to be map */ __struct { unsigned int hwrpb_crb$il_page_count_l; unsigned int hwrpb_crb$il_page_count_h; } hwrpb_crb$r_page_count_fields; } hwrpb_crb$r_page_count_overlay; /* */ /* Console VA/PA map */ /******************* */ __union { unsigned __int64 hwrpb_crb$iq_vapa_map; /* Console VA/PA map */ __struct { unsigned int hwrpb_crb$il_vapa_map_l; unsigned int hwrpb_crb$il_vapa_map_h; } hwrpb_crb$r_vapa_map_fields; } hwrpb_crb$r_vapa_map_overlay; } HWRPB_CRB; #if !defined(__VAXC) #define hwrpb_crb$iq_va_dispatch_pd hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$iq_va_dispatch_pd #define hwrpb_crb$il_va_dispatch_pd_l hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$r_va_dispatch_pd_fields.hwrpb_crb$il_va_dispatch\ _pd_l #define hwrpb_crb$il_va_dispatch_pd_h hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$r_va_dispatch_pd_fields.hwrpb_crb$il_va_dispatch\ _pd_h #define hwrpb_crb$iq_pa_dispatch_pd hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$iq_pa_dispatch_pd #define hwrpb_crb$il_pa_dispatch_pd_l hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$r_pa_dispatch_pd_fields.hwrpb_crb$il_pa_dispatch\ _pd_l #define hwrpb_crb$il_pa_dispatch_pd_h hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$r_pa_dispatch_pd_fields.hwrpb_crb$il_pa_dispatch\ _pd_h #define hwrpb_crb$iq_va_fixup_pd hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$iq_va_fixup_pd #define hwrpb_crb$il_va_fixup_pd_l hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$r_va_fixup_pd_fields.hwrpb_crb$il_va_fixup_pd_l #define hwrpb_crb$il_va_fixup_pd_h hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$r_va_fixup_pd_fields.hwrpb_crb$il_va_fixup_pd_h #define hwrpb_crb$iq_pa_fixup_pd hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$iq_pa_fixup_pd #define hwrpb_crb$il_pa_fixup_pd_l hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$r_pa_fixup_pd_fields.hwrpb_crb$il_pa_fixup_pd_l #define hwrpb_crb$il_pa_fixup_pd_h hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$r_pa_fixup_pd_fields.hwrpb_crb$il_pa_fixup_pd_h #define hwrpb_crb$iq_map_count hwrpb_crb$r_map_count_overlay.hwrpb_crb$iq_map_count #define hwrpb_crb$il_map_count_l hwrpb_crb$r_map_count_overlay.hwrpb_crb$r_map_count_fields.hwrpb_crb$il_map_count_l #define hwrpb_crb$il_map_count_h hwrpb_crb$r_map_count_overlay.hwrpb_crb$r_map_count_fields.hwrpb_crb$il_map_count_h #define hwrpb_crb$iq_page_count hwrpb_crb$r_page_count_overlay.hwrpb_crb$iq_page_count #define hwrpb_crb$il_page_count_l hwrpb_crb$r_page_count_overlay.hwrpb_crb$r_page_count_fields.hwrpb_crb$il_page_count_l #define hwrpb_crb$il_page_count_h hwrpb_crb$r_page_count_overlay.hwrpb_crb$r_page_count_fields.hwrpb_crb$il_page_count_h #define hwrpb_crb$iq_vapa_map hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$iq_vapa_map #define hwrpb_crb$il_vapa_map_l hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$r_vapa_map_fields.hwrpb_crb$il_vapa_map_l #define hwrpb_crb$il_vapa_map_h hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$r_vapa_map_fields.hwrpb_crb$il_vapa_map_h #endif /* #if !defined(__VAXC) */ /* */ #define HWRPB_CRB$C_LENGTH 56 /* Length of CRB */ #define HWRPB_CRB$K_LENGTH 56 /* Length of CRB */ #define HWRPB_CRB$S_CRBDEF 56 /* Old size name - synonym */ /* */ /* Virtual/Physical Address Map */ /****************************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _vapamap { /* */ /* Console Virtual Address */ /************************* */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_vapamap$iq_va; /* Console VA */ __struct { unsigned int hwrpb_vapamap$il_va_l; unsigned int hwrpb_vapamap$il_va_h; } hwrpb_vapamap$r_va_fields; } hwrpb_vapamap$r_va_overlay; /* */ /* Console Physical Address */ /************************* */ __union { unsigned __int64 hwrpb_vapamap$iq_pa; /* Console PA */ __struct { unsigned int hwrpb_vapamap$il_pa_l; unsigned int hwrpb_vapamap$il_pa_h; } hwrpb_vapamap$r_pa_fields; } hwrpb_vapamap$r_pa_overlay; /* */ /* Page Count of Entry */ /********************* */ __union { unsigned __int64 hwrpb_vapamap$iq_page_count; /* Page count of entry */ __struct { unsigned int hwrpb_vapamap$il_page_count_l; unsigned int hwrpb_vapamap$il_page_count_h; } hwrpb_vapamap$r_page_count_fields; } hwrpb_vapamap$r_page_count_overlay; } VAPAMAP; #if !defined(__VAXC) #define hwrpb_vapamap$iq_va hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$iq_va #define hwrpb_vapamap$il_va_l hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$r_va_fields.hwrpb_vapamap$il_va_l #define hwrpb_vapamap$il_va_h hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$r_va_fields.hwrpb_vapamap$il_va_h #define hwrpb_vapamap$iq_pa hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$iq_pa #define hwrpb_vapamap$il_pa_l hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$r_pa_fields.hwrpb_vapamap$il_pa_l #define hwrpb_vapamap$il_pa_h hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$r_pa_fields.hwrpb_vapamap$il_pa_h #define hwrpb_vapamap$iq_page_count hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$iq_page_count #define hwrpb_vapamap$il_page_count_l hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$r_page_count_fields.hwrpb_vapamap$il_page_co\ unt_l #define hwrpb_vapamap$il_page_count_h hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$r_page_count_fields.hwrpb_vapamap$il_page_co\ unt_h #endif /* #if !defined(__VAXC) */ /* */ #define HWRPB_VAPAMAP$S_VAPAMAPDEF 24 /* Old size name synonym */ /* Console terminal routines */ #define HWRPB_CRB$K_GETC 1 /* Get a character from console */ #define HWRPB_CRB$K_PUTS 2 /* Put a string to console term */ #define HWRPB_CRB$K_RESET_TERM 3 /* Reset console terminal */ #define HWRPB_CRB$K_SET_TERM_INTR 4 /* Set console terminal int. */ #define HWRPB_CRB$K_SET_TERM_CTL 5 /* Set console terminal controls */ #define HWRPB_CRB$K_PROCESS_KEYCODE 6 /* Process and translate keycode */ #define HWRPB_CRB$K_CONSOLE_OPEN 7 /* Open console for I/O */ #define HWRPB_CRB$K_CONSOLE_CLOSE 8 /* Close console for I/O */ /* Console Generic IO routines */ #define HWRPB_CRB$K_OPEN 16 /* Open access to I/O device */ #define HWRPB_CRB$K_CLOSE 17 /* Close access to I/O device */ #define HWRPB_CRB$K_IOCTL 18 #define HWRPB_CRB$K_READ 19 /* Perform read operation */ #define HWRPB_CRB$K_WRITE 20 /* Perform write operation */ /* Console Env. Variable Routines */ #define HWRPB_CRB$K_SET_ENV 32 /* Set an environment varible */ #define HWRPB_CRB$K_RESET_ENV 33 /* Reset an environment variable */ #define HWRPB_CRB$K_GET_ENV 34 /* Fetch an environment varible */ #define HWRPB_CRB$K_SAVE_ENV 35 /* Save an environment varible */ /* Write/Read FRU EEROM routines */ #define HWRPB_CRB$K_WRITE_EEROM 51 #define HWRPB_CRB$K_READ_EEROM 52 /* Required Environment Variables */ #define HWRPB_CRB$K_AUTO_ACTION 1 #define HWRPB_CRB$K_BOOT_DEV 2 #define HWRPB_CRB$K_BOOTCMD_DEV 3 #define HWRPB_CRB$K_BOOTED_DEV 4 #define HWRPB_CRB$K_BOOT_FILE 5 #define HWRPB_CRB$K_BOOTED_FILE 6 #define HWRPB_CRB$K_BOOT_OSFLAGS 7 #define HWRPB_CRB$K_BOOTED_OSFLAGS 8 #define HWRPB_CRB$K_BOOT_RESET 9 #define HWRPB_CRB$K_DUMP_DEV 10 #define HWRPB_CRB$K_ENABLE_AUDIT 11 #define HWRPB_CRB$K_LICENSE 12 #define HWRPB_CRB$K_CHAR_SET 13 #define HWRPB_CRB$K_LANGUAGE 14 #define HWRPB_CRB$K_TTY_DEV 15 #define HWRPB_CRB$K_PSWITCH 48 #define HWRPB_CRB$K_SAVE_ERROR_LOG 49 #define HWRPB_CRB$K_PARTITION 40 #define HWRPB_CRB$K_GALAXY 40 /* */ /* Console Terminal Block */ /************************ */ #define HWRPB_CTBG$K_LENGTH 256 #define HWRPB_CTBG$C_LENGTH 256 #define HWRPB_CTBT$K_LENGTH 144 #define HWRPB_CTBT$C_LENGTH 144 #define HWRPB_CTBWS$K_LENGTH 352 #define HWRPB_CTBWS$C_LENGTH 352 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _ctb { /* */ /* CTB - Common Section */ /*********************** */ /* */ /* Device Type */ /************* */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_ctb$iq_type; /* Device Type */ __struct { unsigned int hwrpb_ctb$il_type_l; unsigned int hwrpb_ctb$il_type_h; } hwrpb_ctb$r_type_fields; } hwrpb_ctb$r_type_overlay; /* */ /* Device ID */ /*********** */ __union { unsigned __int64 hwrpb_ctb$iq_device_id; /* Device ID */ __struct { unsigned int hwrpb_ctb$il_device_id_channel; unsigned int hwrpb_ctb$il_device_id_widget; } hwrpb_ctb$r_device_id_fields; } hwrpb_ctb$r_device_id_overlay; /* */ /* Reserved */ /********** */ __int64 hwrpb_ctb$q_fill1; /* Reserved for Future use */ /* */ /* Device-Specific Data */ __union { unsigned __int64 hwrpb_ctb$iq_dev_spec; /* Len of dev specific data */ __struct { unsigned int hwrpb_ctb$il_dev_spec_l; unsigned int hwrpb_ctb$il_dev_spec_h; } hwrpb_ctb$r_dev_spec_fields; } hwrpb_ctb$r_dev_spec_overlay; /* */ /* CTB - Device dependent section */ /* */ /* - Graphics device portion */ /* */ __union { __struct { /* */ /* Current ROw */ /************* */ __union { unsigned __int64 hwrpb_ctbg$iq_row; /* Current Row */ __struct { unsigned int hwrpb_ctbg$il_row_l; unsigned int hwrpb_ctbg$il_row_h; } hwrpb_ctbg$r_row_fields; } hwrpb_ctbg$r_row_overlay; /* */ /* Current Column */ /**************** */ __union { unsigned __int64 hwrpb_ctbg$iq_column; /* Current Column */ __struct { unsigned int hwrpb_ctbg$il_column_l; unsigned int hwrpb_ctbg$il_column_h; } hwrpb_ctbg$r_column_fields; } hwrpb_ctbg$r_column_overlay; /* */ /* Maximum Row */ /************* */ __union { unsigned __int64 hwrpb_ctbg$iq_max_row; /* Maximum Row */ __struct { unsigned int hwrpb_ctbg$il_max_row_l; unsigned int hwrpb_ctbg$il_max_row_h; } hwrpb_ctbg$r_max_row_fields; } hwrpb_ctbg$r_max_row_overlay; /* */ /* Character Cell Height */ /*********************** */ __union { unsigned __int64 hwrpb_ctbg$iq_char_height; /* Character Cell Height */ __struct { unsigned int hwrpb_ctbg$il_char_height_l; unsigned int hwrpb_ctbg$il_char_height_h; } hwrpb_ctbg$r_char_height_fields; } hwrpb_ctbg$r_char_height_overlay; /* */ /* Character Cell Width */ /********************** */ __union { unsigned __int64 hwrpb_ctbg$iq_char_width; /* Character Cell Width */ __struct { unsigned int hwrpb_ctbg$il_char_width_l; unsigned int hwrpb_ctbg$il_char_width_h; } hwrpb_ctbg$r_char_width_fields; } hwrpb_ctbg$r_char_width_overlay; /* */ /* Address of Display's Control and Status Register */ /************************************************** */ __union { unsigned __int64 hwrpb_ctbg$iq_display_csr; /* CSR addr. of Display */ __struct { unsigned int hwrpb_ctbg$il_display_csr_l; unsigned int hwrpb_ctbg$il_display_csr_h; } hwrpb_ctbg$r_display_csr_fields; } hwrpb_ctbg$r_display_csr_overlay; /* */ /* Address of Keyboard's Control and Status Register */ /*************************************************** */ __union { unsigned __int64 hwrpb_ctbg$iq_keyb_csr; /* CSR addr. of keyboard */ __struct { unsigned int hwrpb_ctbg$il_keyb_csr_l; unsigned int hwrpb_ctbg$il_keyb_csr_h; } hwrpb_ctbg$r_keyb_csr_fields; } hwrpb_ctbg$r_keyb_csr_overlay; /* */ /* LK Keyboard interrupt SCB offset */ /********************************** */ __union { unsigned __int64 hwrpb_ctbg$iq_keyb_vector; /* Lk keyboard inter. SCB offset */ __struct { unsigned int hwrpb_ctbg$il_keyb_vector_l; unsigned int hwrpb_ctbg$il_keyb_vector_h; } hwrpb_ctbg$r_keyb_vector_fields; } hwrpb_ctbg$r_keyb_vector_overlay; /* */ /* Keyboard State */ /**************** */ __union { unsigned __int64 hwrpb_ctbg$iq_keyb_state; /* Keyboard state */ __struct { unsigned int hwrpb_ctbg$il_keyb_state_l; unsigned int hwrpb_ctbg$il_keyb_state_h; } hwrpb_ctbg$r_keyb_state_fields; } hwrpb_ctbg$r_keyb_state_overlay; /* */ /* Keycode Buffer */ /**************** */ __union { unsigned __int64 hwrpb_ctbg$iq_keyc_buffer [6]; __struct { unsigned int hwrpb_ctbg$il_keyc_buffer_l; unsigned int hwrpb_ctbg$il_keyc_buffer_h; } hwrpb_ctbg$r_keyc_buffer_fields; } hwrpb_ctbg$r_keycode_buf_overlay; /* */ unsigned __int64 hwrpb_ctbg$iq_fill1 [13]; /* */ } hwrpb_ctb$q_ctbgdef; /* */ /* - Terminal device portion */ /* */ __struct { /* */ /* CSR Address */ /************* */ __union { unsigned __int64 hwrpb_ctbt$iq_csr_addr; /* CSR address */ __struct { unsigned int hwrpb_ctbt$il_csr_addr_l; unsigned int hwrpb_ctbt$il_csr_addr_h; } hwrpb_ctbt$r_csr_addr_fields; } hwrpb_ctbt$r_csr_addr_overlay; /* */ /* SCB Vector of Transmit Interrupts */ /******************************* */ __union { unsigned __int64 hwrpb_ctbt$iq_xmit_vector; /* SCB vec of Xmit interrupts */ __struct { unsigned int hwrpb_ctbt$il_xmit_vector_l; unsigned int hwrpb_ctbt$il_xmit_vector_h; } hwrpb_ctbt$r_xmit_vector_fields; } hwrpb_ctbt$r_xmit_vector_overlay; /* */ /* SCB Vector of Receive Interrupts */ /********************************** */ __union { unsigned __int64 hwrpb_ctbt$iq_rcv_vector; /* SCB vec of Receive interrupts */ __struct { unsigned int hwrpb_ctbt$il_rcv_vector_l; unsigned int hwrpb_ctbt$il_rcv_vector_h; } hwrpb_ctbt$r_rcv_vector_fields; } hwrpb_ctbt$r_rcv_vector_overlay; /* */ /* Terminal Baud Rate in Decimal */ /******************************* */ __union { unsigned __int64 hwrpb_ctbt$iq_baud; /* Terminal Baud Rate in decimal */ __struct { unsigned int hwrpb_ctbt$il_baud_l; unsigned int hwrpb_ctbt$il_baud_h; } hwrpb_ctbt$r_baud_fields; } hwrpb_ctbt$r_baud_overlay; /* */ /* Extended Error Status on last PUTS */ /************************************ */ __union { unsigned __int64 hwrpb_ctbt$iq_puts_status; /* Extended Error status on last PUTS */ __struct { unsigned int hwrpb_ctbt$il_puts_status_l; unsigned int hwrpb_ctbt$il_puts_status_h; } hwrpb_ctbt$r_puts_status_fields; } hwrpb_ctbt$r_puts_status_overlay; /* */ /* Extended Error status on last GETC */ /************************************ */ __union { unsigned __int64 hwrpb_ctbt$iq_getc_status; /* Extended Error status on last GETC */ __struct { unsigned int hwrpb_ctbt$il_getc_status_l; unsigned int hwrpb_ctbt$il_getc_status_h; } hwrpb_ctbt$r_getc_status_fields; } hwrpb_ctbt$r_getc_status_overlay; /* */ unsigned __int64 hwrpb_ctbt$iq_fill2 [8]; /* */ } hwrpb_ctb$r_ctbtdef; /* */ /* - Workstation portion */ /* */ __struct { /* */ /* Interrupt Priority Level (IPL) */ /******************************** */ __union { unsigned __int64 hwrpb_ctbws$iq_ipl; /* IPL */ __struct { unsigned int hwrpb_ctbws$il_ipl_l; unsigned int hwrpb_ctbws$il_ipl_h; } hwrpb_ctbws$r_ipl_fields; } hwrpb_ctbws$r_ipl_overlay; /* */ /* Transmit SCB Vector */ /********************* */ __union { unsigned __int64 hwrpb_ctbws$iq_xmit_vector; /* Transmit SCB vector */ __struct { unsigned int hwrpb_ctbws$il_xmit_vector_l; unsigned int hwrpb_ctbws$il_xmit_vector_h; } hwrpb_ctbws$r_xmit_vector_fields; } hwrpb_ctbws$r_xmit_vector_overlay; /* */ /* Receive SCB Vector */ /******************** */ __union { unsigned __int64 hwrpb_ctbws$iq_rec_vector; /* Recieve SCB vector */ __struct { unsigned int hwrpb_ctbws$il_rec_vector_l; unsigned int hwrpb_ctbws$il_rec_vector_h; } hwrpb_ctbws$r_rec_vector_fields; } hwrpb_ctbws$r_rcv_vector_overlay; /* */ /* Terminal Type */ /*************** */ __union { unsigned __int64 hwrpb_ctbws$iq_term_type; /* Terminal Type */ __struct { unsigned int hwrpb_ctbws$il_term_type_l; unsigned int hwrpb_ctbws$il_term_type_h; } hwrpb_ctbws$r_term_type_fields; } hwrpb_ctbws$r_term_type_overlay; /* */ /* Keyboard Type */ /*************** */ __union { unsigned __int64 hwrpb_ctbws$iq_kb_type; /* Keyboard type */ __struct { unsigned int hwrpb_ctbws$il_kb_type_l; unsigned int hwrpb_ctbws$il_kb_type_h; } hwrpb_ctbws$r_kb_type_fields; } hwrpb_ctbws$r_kb_type_overlay; /* */ /* Keyboard Translation Table pointer */ /************************************ */ __union { unsigned __int64 hwrpb_ctbws$iq_kb_trn_table; /* Keyboard Translation */ __struct { /* table pointer */ unsigned int hwrpb_ctbws$il_kb_trn_table_l; unsigned int hwrpb_ctbws$il_kb_trn_table_h; } hwrpb_ctbws$r_kb_trn_table_fields; } hwrpb_ctbws$r_kb_trn_table_overlay; /* */ /* Keyboard Map Table pointer */ /**************************** */ __union { unsigned __int64 hwrpb_ctbws$iq_kb_map_table; /* Keyboard Map Table */ __struct { /* table pointer */ unsigned int hwrpb_ctbws$il_kb_map_table_l; unsigned int hwrpb_ctbws$il_kb_map_table_h; } hwrpb_ctbws$r_kb_map_table_fields; } hwrpb_ctbws$r_kb_map_table_overlay; /* */ /* Keyboard State */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_keyb_state; /* Keyboard state */ __struct { unsigned int hwrpb_ctbws$il_keyb_state_l; unsigned int hwrpb_ctbws$il_keyb_state_h; } hwrpb_ctbws$r_keyb_state_fields; } hwrpb_ctbws$r_keyb_state_overlay; /* */ /* Last Key Down */ /*************** */ __union { unsigned __int64 hwrpb_ctbws$iq_last_key; /* Last key down */ __struct { unsigned int hwrpb_ctbws$il_last_key_l; unsigned int hwrpb_ctbws$il_last_key_h; } hwrpb_ctbws$r_last_key_fields; } hwrpb_ctbws$r_last_key_overlay; /* */ /* US font Table pointer */ /*********************** */ __union { unsigned __int64 hwrpb_ctbws$iq_usfnt_ptr; /* US font table pointer */ __struct { unsigned int hwrpb_ctbws$il_usfnt_ptr_l; unsigned int hwrpb_ctbws$il_usfnt_ptr_h; } hwrpb_ctbws$r_usfnt_ptr_fields; } hwrpb_ctbws$r_usfnt_ptr_overlay; /* */ /* DMCS Font Table pointer */ /************************* */ __union { unsigned __int64 hwrpb_ctbws$iq_dmfnt_ptr; /* DMCS font table pointer */ __struct { unsigned int hwrpb_ctbws$il_dmfnt_ptr_l; unsigned int hwrpb_ctbws$il_dmfnt_ptr_h; } hwrpb_ctbws$r_dmfnt_ptr_fields; } hwrpb_ctbws$r_dmfnt_ptr_overlay; /* */ /* Font Width in pixels */ /********************** */ __union { unsigned __int64 hwrpb_ctbws$iq_font_width; /* Font width in pixels */ __struct { unsigned int hwrpb_ctbws$il_font_width_l; unsigned int hwrpb_ctbws$il_font_width_h; } hwrpb_ctbws$r_font_width_fields; } hwrpb_ctbws$r_font_width_overlay; /* */ /* Font Height in pixels */ /*********************** */ __union { unsigned __int64 hwrpb_ctbws$iq_font_hght; /* Font height in pixels */ __struct { unsigned int hwrpb_ctbws$il_font_hght_l; unsigned int hwrpb_ctbws$il_font_hght_h; } hwrpb_ctbws$r_font_hght_fields; } hwrpb_ctbws$r_font_hght_overlay; /* */ /* Monitor Width in pixels - 1 */ /***************************** */ __union { unsigned __int64 hwrpb_ctbws$iq_mon_width; /* Monitor width in pixels -1 */ __struct { unsigned int hwrpb_ctbws$il_mon_width_l; unsigned int hwrpb_ctbws$il_mon_width_h; } hwrpb_ctbws$r_mon_width_fields; } hwrpb_ctbws$r_mon_width_overlay; /* */ /* Monitor Height in scanlines - 1 */ /********************************* */ __union { unsigned __int64 hwrpb_ctbws$iq_mon_hght; /* Monitor height in scanlines -1 */ __struct { unsigned int hwrpb_ctbws$il_mon_hght_l; unsigned int hwrpb_ctbws$il_mon_hght_h; } hwrpb_ctbws$r_mon_hght_fields; } hwrpb_ctbws$r_mon_hght_overlay; /* */ /* Monitor Density in pixels - 1 */ /******************************* */ __union { unsigned __int64 hwrpb_ctbws$iq_mon_dens; /* Monitor density in pixels -1 */ __struct { unsigned int hwrpb_ctbws$il_mon_dens_l; unsigned int hwrpb_ctbws$il_mon_dens_h; } hwrpb_ctbws$r_mon_dens_fields; } hwrpb_ctbws$r_mon_dens_overlay; /* */ /* Number of Planes */ /****************** */ __union { unsigned __int64 hwrpb_ctbws$iq_plane_count; /* Number of planes */ __struct { unsigned int hwrpb_ctbws$il_plane_count_l; unsigned int hwrpb_ctbws$il_plane_count_h; } hwrpb_ctbws$r_plane_count_fields; } hwrpb_ctbws$r_plane_count_overlay; /* */ /* Character Cell Width */ /********************** */ __union { unsigned __int64 hwrpb_ctbws$iq_cursor_width; /* Character Cell Width */ __struct { unsigned int hwrpb_ctbws$il_cursor_width_l; unsigned int hwrpb_ctbws$il_cursor_width_h; } hwrpb_ctbws$r_cursor_width_fields; } hwrpb_ctbws$r_cursor_width_overlay; /* */ /* Character Cell Height */ /*********************** */ __union { unsigned __int64 hwrpb_ctbws$iq_cursor_hght; /* Character Cell Height */ __struct { unsigned int hwrpb_ctbws$il_cursor_hght_l; unsigned int hwrpb_ctbws$il_cursor_hght_h; } hwrpb_ctbws$r_cursor_hght_fields; } hwrpb_ctbws$r_cursor_height_overla; /* */ /* Number of Heads Supported */ /*************************** */ __union { unsigned __int64 hwrpb_ctbws$iq_head_count; /* Number of heads supported */ __struct { unsigned int hwrpb_ctbws$il_head_count_l; unsigned int hwrpb_ctbws$il_head_count_h; } hwrpb_ctbws$r_head_count_fields; } hwrpb_ctbws$r_head_count_overlay; /* */ /* Window UP/DOWN */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_win_updwn; /* window up/down */ __struct { unsigned int hwrpb_ctbws$il_win_updwn_l; unsigned int hwrpb_ctbws$il_win_updwn_h; } hwrpb_ctbws$r_win_updwn_fields; } hwrpb_ctbws$r_win_updwn_overlay; /* */ /* Offset to Heads */ /***************** */ __union { unsigned __int64 hwrpb_ctbws$iq_head_offset; /* Offset to heads */ __struct { unsigned int hwrpb_ctbws$il_head_offset_l; unsigned int hwrpb_ctbws$il_head_offset_h; } hwrpb_ctbws$r_head_offset_fields; } hwrpb_ctbws$r_head_offset_overlay; /* */ /* Pointer to putchar routine */ /**************************** */ __union { unsigned __int64 hwrpb_ctbws$iq_put_char_rtn; /* pointer to putchar routine */ __struct { unsigned int hwrpb_ctbws$il_put_char_rtn_l; unsigned int hwrpb_ctbws$il_put_char_rtn_h; } hwrpb_ctbws$r_put_char_rtn_fields; } hwrpb_ctbws$r_put_char_rtn_overlay; /* */ /* Console I/O State */ /******************* */ __union { unsigned __int64 hwrpb_ctbws$iq_io_state; /* console I/O state */ __struct { unsigned int hwrpb_ctbws$il_io_state_l; unsigned int hwrpb_ctbws$il_io_state_h; } hwrpb_ctbws$r_io_state_fields; } hwrpb_ctbws$r_io_state_overlay; /* */ /* Listener State */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_lstnr_state; /* listener state */ __struct { unsigned int hwrpb_ctbws$il_lstnr_state_l; unsigned int hwrpb_ctbws$il_lstnr_state_h; } hwrpb_ctbws$r_lstnr_state_fields; } hwrpb_ctbws$r_lstnr_state_overlay; /* */ /* Address of Extended Information */ /********************************* */ __union { unsigned __int64 hwrpb_ctbws$iq_info_ext; /* address of Extended information */ __struct { unsigned int hwrpb_ctbws$il_info_ext_l; unsigned int hwrpb_ctbws$il_info_ext_h; } hwrpb_ctbws$r_info_ext_fields; } hwrpb_ctbws$r_info_ext_overlay; /* */ /* Terminal Output location (was OPT_CONS_LOC) */ /************************* */ __union { unsigned __int64 hwrpb_ctbws$iq_opt_cons_loc; /* Original name */ __struct { unsigned int hwrpb_ctbws$il_opt_cons_loc_l; unsigned int hwrpb_ctbws$il_opt_cons_loc_h; } hwrpb_ctbws$r_opt_cons_loc_fields; unsigned __int64 hwrpb_ctbws$iq_termout_loc; /* New name for ECO #130 */ __struct { unsigned int hwrpb_ctbws$il_termout_loc_l; unsigned int hwrpb_ctbws$il_termout_loc_h; } hwrpb_ctbws$r_termout_loc_fields; } hwrpb_ctbws$r_termout_loc_overlay; /* */ /* Server Offset */ /*************** */ __union { unsigned __int64 hwrpb_ctbws$iq_server_offset; /* server offset */ __struct { unsigned int hwrpb_ctbws$il_server_offset_l; unsigned int hwrpb_ctbws$il_server_offset_h; } hwrpb_ctbws$r_server_offset_fields; } hwrpb_ctbws$r_server_offset_overla; /* */ /* Line Parameter */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_line_param; /* line parameter */ __struct { unsigned int hwrpb_ctbws$il_line_param_l; unsigned int hwrpb_ctbws$il_line_param_h; } hwrpb_ctbws$r_line_param_fields; } hwrpb_ctbws$r_line_param_overlay; /* */ /* Terminal Input Location */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_termin_loc; __struct { unsigned int hwrpb_ctbws$il_termin_loc_l; unsigned int hwrpb_ctbws$il_termin_loc_h; } hwrpb_ctbws$r_termin_loc_fields; } hwrpb_ctbws$r_termin_loc_overlay; /* */ /* Terminal Input Extended Location */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_termin_locx; __struct { unsigned int hwrpb_ctbws$il_termin_locx_l; unsigned int hwrpb_ctbws$il_termin_locx_h; } hwrpb_ctbws$r_termin_locx_fields; } hwrpb_ctbws$r_termin_locx_overlay; /* */ /* Terminal Protocol */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_term_protocol; __struct { unsigned int hwrpb_ctbws$il_termin_protocol; unsigned int hwrpb_ctbws$il_termout_protocol; } hwrpb_ctbws$r_term_protocol_fields; } hwrpb_ctbws$r_term_protocol_overla; /* */ /* Terminal Output Extended Location */ /**************** */ __union { unsigned __int64 hwrpb_ctbws$iq_termout_locx; __struct { unsigned int hwrpb_ctbws$il_termout_locx_l; unsigned int hwrpb_ctbws$il_termout_locx_h; } hwrpb_ctbws$r_termout_locx_fields; } hwrpb_ctbws$r_termout_locx_overlay; /* */ unsigned char hwrpb_ctbws$b_fill3 [56]; } hwrpb_ctb$r_ctbwsdef; } hwrpb_ctb$r_dev_depend; } CTB; #if !defined(__VAXC) #define hwrpb_ctb$iq_type hwrpb_ctb$r_type_overlay.hwrpb_ctb$iq_type #define hwrpb_ctb$il_type_l hwrpb_ctb$r_type_overlay.hwrpb_ctb$r_type_fields.hwrpb_ctb$il_type_l #define hwrpb_ctb$il_type_h hwrpb_ctb$r_type_overlay.hwrpb_ctb$r_type_fields.hwrpb_ctb$il_type_h #define hwrpb_ctb$iq_device_id hwrpb_ctb$r_device_id_overlay.hwrpb_ctb$iq_device_id #define hwrpb_ctb$il_device_id_channel hwrpb_ctb$r_device_id_overlay.hwrpb_ctb$r_device_id_fields.hwrpb_ctb$il_device_id_channel #define hwrpb_ctb$il_device_id_widget hwrpb_ctb$r_device_id_overlay.hwrpb_ctb$r_device_id_fields.hwrpb_ctb$il_device_id_widget #define hwrpb_ctb$iq_dev_spec hwrpb_ctb$r_dev_spec_overlay.hwrpb_ctb$iq_dev_spec #define hwrpb_ctb$il_dev_spec_l hwrpb_ctb$r_dev_spec_overlay.hwrpb_ctb$r_dev_spec_fields.hwrpb_ctb$il_dev_spec_l #define hwrpb_ctb$il_dev_spec_h hwrpb_ctb$r_dev_spec_overlay.hwrpb_ctb$r_dev_spec_fields.hwrpb_ctb$il_dev_spec_h #define hwrpb_ctb$q_ctbgdef hwrpb_ctb$r_dev_depend.hwrpb_ctb$q_ctbgdef #define hwrpb_ctbg$iq_row hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_row_overlay.hwrpb_ctbg$iq_row #define hwrpb_ctbg$il_row_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_row_overlay.hwrpb_ctbg$r_row_fields.hwrpb_ctbg$il_row_l #define hwrpb_ctbg$il_row_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_row_overlay.hwrpb_ctbg$r_row_fields.hwrpb_ctbg$il_row_h #define hwrpb_ctbg$iq_column hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_column_overlay.hwrpb_ctbg$iq_column #define hwrpb_ctbg$il_column_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_column_overlay.hwrpb_ctbg$r_column_fields.hwrpb_ctbg$il_column_l #define hwrpb_ctbg$il_column_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_column_overlay.hwrpb_ctbg$r_column_fields.hwrpb_ctbg$il_column_h #define hwrpb_ctbg$iq_max_row hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_max_row_overlay.hwrpb_ctbg$iq_max_row #define hwrpb_ctbg$il_max_row_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_max_row_overlay.hwrpb_ctbg$r_max_row_fields.hwrpb_ctbg$il_max_row_l #define hwrpb_ctbg$il_max_row_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_max_row_overlay.hwrpb_ctbg$r_max_row_fields.hwrpb_ctbg$il_max_row_h #define hwrpb_ctbg$iq_char_height hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_char_height_overlay.hwrpb_ctbg$iq_char_height #define hwrpb_ctbg$il_char_height_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_char_height_overlay.hwrpb_ctbg$r_char_height_fields.hwrpb_ctbg\ $il_char_height_l #define hwrpb_ctbg$il_char_height_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_char_height_overlay.hwrpb_ctbg$r_char_height_fields.hwrpb_ctbg\ $il_char_height_h #define hwrpb_ctbg$iq_char_width hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_char_width_overlay.hwrpb_ctbg$iq_char_width #define hwrpb_ctbg$il_char_width_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_char_width_overlay.hwrpb_ctbg$r_char_width_fields.hwrpb_ctbg$il\ _char_width_l #define hwrpb_ctbg$il_char_width_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_char_width_overlay.hwrpb_ctbg$r_char_width_fields.hwrpb_ctbg$il\ _char_width_h #define hwrpb_ctbg$iq_display_csr hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_display_csr_overlay.hwrpb_ctbg$iq_display_csr #define hwrpb_ctbg$il_display_csr_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_display_csr_overlay.hwrpb_ctbg$r_display_csr_fields.hwrpb_ctbg\ $il_display_csr_l #define hwrpb_ctbg$il_display_csr_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_display_csr_overlay.hwrpb_ctbg$r_display_csr_fields.hwrpb_ctbg\ $il_display_csr_h #define hwrpb_ctbg$iq_keyb_csr hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_csr_overlay.hwrpb_ctbg$iq_keyb_csr #define hwrpb_ctbg$il_keyb_csr_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_csr_overlay.hwrpb_ctbg$r_keyb_csr_fields.hwrpb_ctbg$il_keyb_\ csr_l #define hwrpb_ctbg$il_keyb_csr_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_csr_overlay.hwrpb_ctbg$r_keyb_csr_fields.hwrpb_ctbg$il_keyb_\ csr_h #define hwrpb_ctbg$iq_keyb_vector hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_vector_overlay.hwrpb_ctbg$iq_keyb_vector #define hwrpb_ctbg$il_keyb_vector_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_vector_overlay.hwrpb_ctbg$r_keyb_vector_fields.hwrpb_ctbg\ $il_keyb_vector_l #define hwrpb_ctbg$il_keyb_vector_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_vector_overlay.hwrpb_ctbg$r_keyb_vector_fields.hwrpb_ctbg\ $il_keyb_vector_h #define hwrpb_ctbg$iq_keyb_state hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_state_overlay.hwrpb_ctbg$iq_keyb_state #define hwrpb_ctbg$il_keyb_state_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_state_overlay.hwrpb_ctbg$r_keyb_state_fields.hwrpb_ctbg$il\ _keyb_state_l #define hwrpb_ctbg$il_keyb_state_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keyb_state_overlay.hwrpb_ctbg$r_keyb_state_fields.hwrpb_ctbg$il\ _keyb_state_h #define hwrpb_ctbg$iq_keyc_buffer hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keycode_buf_overlay.hwrpb_ctbg$iq_keyc_buffer #define hwrpb_ctbg$il_keyc_buffer_l hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keycode_buf_overlay.hwrpb_ctbg$r_keyc_buffer_fields.hwrpb_ctbg\ $il_keyc_buffer_l #define hwrpb_ctbg$il_keyc_buffer_h hwrpb_ctb$q_ctbgdef.hwrpb_ctbg$r_keycode_buf_overlay.hwrpb_ctbg$r_keyc_buffer_fields.hwrpb_ctbg\ $il_keyc_buffer_h #define hwrpb_ctb$r_ctbtdef hwrpb_ctb$r_dev_depend.hwrpb_ctb$r_ctbtdef #define hwrpb_ctbt$iq_csr_addr hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_csr_addr_overlay.hwrpb_ctbt$iq_csr_addr #define hwrpb_ctbt$il_csr_addr_l hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_csr_addr_overlay.hwrpb_ctbt$r_csr_addr_fields.hwrpb_ctbt$il_csr_a\ ddr_l #define hwrpb_ctbt$il_csr_addr_h hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_csr_addr_overlay.hwrpb_ctbt$r_csr_addr_fields.hwrpb_ctbt$il_csr_a\ ddr_h #define hwrpb_ctbt$iq_xmit_vector hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_xmit_vector_overlay.hwrpb_ctbt$iq_xmit_vector #define hwrpb_ctbt$il_xmit_vector_l hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_xmit_vector_overlay.hwrpb_ctbt$r_xmit_vector_fields.hwrpb_ctbt\ $il_xmit_vector_l #define hwrpb_ctbt$il_xmit_vector_h hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_xmit_vector_overlay.hwrpb_ctbt$r_xmit_vector_fields.hwrpb_ctbt\ $il_xmit_vector_h #define hwrpb_ctbt$iq_rcv_vector hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_rcv_vector_overlay.hwrpb_ctbt$iq_rcv_vector #define hwrpb_ctbt$il_rcv_vector_l hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_rcv_vector_overlay.hwrpb_ctbt$r_rcv_vector_fields.hwrpb_ctbt$il\ _rcv_vector_l #define hwrpb_ctbt$il_rcv_vector_h hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_rcv_vector_overlay.hwrpb_ctbt$r_rcv_vector_fields.hwrpb_ctbt$il\ _rcv_vector_h #define hwrpb_ctbt$iq_baud hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_baud_overlay.hwrpb_ctbt$iq_baud #define hwrpb_ctbt$il_baud_l hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_baud_overlay.hwrpb_ctbt$r_baud_fields.hwrpb_ctbt$il_baud_l #define hwrpb_ctbt$il_baud_h hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_baud_overlay.hwrpb_ctbt$r_baud_fields.hwrpb_ctbt$il_baud_h #define hwrpb_ctbt$iq_puts_status hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_puts_status_overlay.hwrpb_ctbt$iq_puts_status #define hwrpb_ctbt$il_puts_status_l hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_puts_status_overlay.hwrpb_ctbt$r_puts_status_fields.hwrpb_ctbt\ $il_puts_status_l #define hwrpb_ctbt$il_puts_status_h hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_puts_status_overlay.hwrpb_ctbt$r_puts_status_fields.hwrpb_ctbt\ $il_puts_status_h #define hwrpb_ctbt$iq_getc_status hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_getc_status_overlay.hwrpb_ctbt$iq_getc_status #define hwrpb_ctbt$il_getc_status_l hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_getc_status_overlay.hwrpb_ctbt$r_getc_status_fields.hwrpb_ctbt\ $il_getc_status_l #define hwrpb_ctbt$il_getc_status_h hwrpb_ctb$r_ctbtdef.hwrpb_ctbt$r_getc_status_overlay.hwrpb_ctbt$r_getc_status_fields.hwrpb_ctbt\ $il_getc_status_h #define hwrpb_ctb$r_ctbwsdef hwrpb_ctb$r_dev_depend.hwrpb_ctb$r_ctbwsdef #define hwrpb_ctbws$iq_ipl hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_ipl_overlay.hwrpb_ctbws$iq_ipl #define hwrpb_ctbws$il_ipl_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_ipl_overlay.hwrpb_ctbws$r_ipl_fields.hwrpb_ctbws$il_ipl_l #define hwrpb_ctbws$il_ipl_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_ipl_overlay.hwrpb_ctbws$r_ipl_fields.hwrpb_ctbws$il_ipl_h #define hwrpb_ctbws$iq_xmit_vector hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_xmit_vector_overlay.hwrpb_ctbws$iq_xmit_vector #define hwrpb_ctbws$il_xmit_vector_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_xmit_vector_overlay.hwrpb_ctbws$r_xmit_vector_fields.hwrpb_\ ctbws$il_xmit_vector_l #define hwrpb_ctbws$il_xmit_vector_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_xmit_vector_overlay.hwrpb_ctbws$r_xmit_vector_fields.hwrpb_\ ctbws$il_xmit_vector_h #define hwrpb_ctbws$iq_rec_vector hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_rcv_vector_overlay.hwrpb_ctbws$iq_rec_vector #define hwrpb_ctbws$il_rec_vector_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_rcv_vector_overlay.hwrpb_ctbws$r_rec_vector_fields.hwrpb_ctb\ ws$il_rec_vector_l #define hwrpb_ctbws$il_rec_vector_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_rcv_vector_overlay.hwrpb_ctbws$r_rec_vector_fields.hwrpb_ctb\ ws$il_rec_vector_h #define hwrpb_ctbws$iq_term_type hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_term_type_overlay.hwrpb_ctbws$iq_term_type #define hwrpb_ctbws$il_term_type_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_term_type_overlay.hwrpb_ctbws$r_term_type_fields.hwrpb_ctbws$\ il_term_type_l #define hwrpb_ctbws$il_term_type_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_term_type_overlay.hwrpb_ctbws$r_term_type_fields.hwrpb_ctbws$\ il_term_type_h #define hwrpb_ctbws$iq_kb_type hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_type_overlay.hwrpb_ctbws$iq_kb_type #define hwrpb_ctbws$il_kb_type_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_type_overlay.hwrpb_ctbws$r_kb_type_fields.hwrpb_ctbws$il_kb_\ type_l #define hwrpb_ctbws$il_kb_type_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_type_overlay.hwrpb_ctbws$r_kb_type_fields.hwrpb_ctbws$il_kb_\ type_h #define hwrpb_ctbws$iq_kb_trn_table hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_trn_table_overlay.hwrpb_ctbws$iq_kb_trn_table #define hwrpb_ctbws$il_kb_trn_table_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_trn_table_overlay.hwrpb_ctbws$r_kb_trn_table_fields.hwr\ pb_ctbws$il_kb_trn_table_l #define hwrpb_ctbws$il_kb_trn_table_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_trn_table_overlay.hwrpb_ctbws$r_kb_trn_table_fields.hwr\ pb_ctbws$il_kb_trn_table_h #define hwrpb_ctbws$iq_kb_map_table hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_map_table_overlay.hwrpb_ctbws$iq_kb_map_table #define hwrpb_ctbws$il_kb_map_table_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_map_table_overlay.hwrpb_ctbws$r_kb_map_table_fields.hwr\ pb_ctbws$il_kb_map_table_l #define hwrpb_ctbws$il_kb_map_table_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_kb_map_table_overlay.hwrpb_ctbws$r_kb_map_table_fields.hwr\ pb_ctbws$il_kb_map_table_h #define hwrpb_ctbws$iq_keyb_state hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_keyb_state_overlay.hwrpb_ctbws$iq_keyb_state #define hwrpb_ctbws$il_keyb_state_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_keyb_state_overlay.hwrpb_ctbws$r_keyb_state_fields.hwrpb_ctb\ ws$il_keyb_state_l #define hwrpb_ctbws$il_keyb_state_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_keyb_state_overlay.hwrpb_ctbws$r_keyb_state_fields.hwrpb_ctb\ ws$il_keyb_state_h #define hwrpb_ctbws$iq_last_key hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_last_key_overlay.hwrpb_ctbws$iq_last_key #define hwrpb_ctbws$il_last_key_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_last_key_overlay.hwrpb_ctbws$r_last_key_fields.hwrpb_ctbws$il_\ last_key_l #define hwrpb_ctbws$il_last_key_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_last_key_overlay.hwrpb_ctbws$r_last_key_fields.hwrpb_ctbws$il_\ last_key_h #define hwrpb_ctbws$iq_usfnt_ptr hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_usfnt_ptr_overlay.hwrpb_ctbws$iq_usfnt_ptr #define hwrpb_ctbws$il_usfnt_ptr_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_usfnt_ptr_overlay.hwrpb_ctbws$r_usfnt_ptr_fields.hwrpb_ctbws$\ il_usfnt_ptr_l #define hwrpb_ctbws$il_usfnt_ptr_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_usfnt_ptr_overlay.hwrpb_ctbws$r_usfnt_ptr_fields.hwrpb_ctbws$\ il_usfnt_ptr_h #define hwrpb_ctbws$iq_dmfnt_ptr hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_dmfnt_ptr_overlay.hwrpb_ctbws$iq_dmfnt_ptr #define hwrpb_ctbws$il_dmfnt_ptr_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_dmfnt_ptr_overlay.hwrpb_ctbws$r_dmfnt_ptr_fields.hwrpb_ctbws$\ il_dmfnt_ptr_l #define hwrpb_ctbws$il_dmfnt_ptr_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_dmfnt_ptr_overlay.hwrpb_ctbws$r_dmfnt_ptr_fields.hwrpb_ctbws$\ il_dmfnt_ptr_h #define hwrpb_ctbws$iq_font_width hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_font_width_overlay.hwrpb_ctbws$iq_font_width #define hwrpb_ctbws$il_font_width_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_font_width_overlay.hwrpb_ctbws$r_font_width_fields.hwrpb_ctb\ ws$il_font_width_l #define hwrpb_ctbws$il_font_width_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_font_width_overlay.hwrpb_ctbws$r_font_width_fields.hwrpb_ctb\ ws$il_font_width_h #define hwrpb_ctbws$iq_font_hght hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_font_hght_overlay.hwrpb_ctbws$iq_font_hght #define hwrpb_ctbws$il_font_hght_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_font_hght_overlay.hwrpb_ctbws$r_font_hght_fields.hwrpb_ctbws$\ il_font_hght_l #define hwrpb_ctbws$il_font_hght_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_font_hght_overlay.hwrpb_ctbws$r_font_hght_fields.hwrpb_ctbws$\ il_font_hght_h #define hwrpb_ctbws$iq_mon_width hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_width_overlay.hwrpb_ctbws$iq_mon_width #define hwrpb_ctbws$il_mon_width_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_width_overlay.hwrpb_ctbws$r_mon_width_fields.hwrpb_ctbws$\ il_mon_width_l #define hwrpb_ctbws$il_mon_width_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_width_overlay.hwrpb_ctbws$r_mon_width_fields.hwrpb_ctbws$\ il_mon_width_h #define hwrpb_ctbws$iq_mon_hght hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_hght_overlay.hwrpb_ctbws$iq_mon_hght #define hwrpb_ctbws$il_mon_hght_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_hght_overlay.hwrpb_ctbws$r_mon_hght_fields.hwrpb_ctbws$il_\ mon_hght_l #define hwrpb_ctbws$il_mon_hght_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_hght_overlay.hwrpb_ctbws$r_mon_hght_fields.hwrpb_ctbws$il_\ mon_hght_h #define hwrpb_ctbws$iq_mon_dens hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_dens_overlay.hwrpb_ctbws$iq_mon_dens #define hwrpb_ctbws$il_mon_dens_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_dens_overlay.hwrpb_ctbws$r_mon_dens_fields.hwrpb_ctbws$il_\ mon_dens_l #define hwrpb_ctbws$il_mon_dens_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_mon_dens_overlay.hwrpb_ctbws$r_mon_dens_fields.hwrpb_ctbws$il_\ mon_dens_h #define hwrpb_ctbws$iq_plane_count hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_plane_count_overlay.hwrpb_ctbws$iq_plane_count #define hwrpb_ctbws$il_plane_count_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_plane_count_overlay.hwrpb_ctbws$r_plane_count_fields.hwrpb_\ ctbws$il_plane_count_l #define hwrpb_ctbws$il_plane_count_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_plane_count_overlay.hwrpb_ctbws$r_plane_count_fields.hwrpb_\ ctbws$il_plane_count_h #define hwrpb_ctbws$iq_cursor_width hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_cursor_width_overlay.hwrpb_ctbws$iq_cursor_width #define hwrpb_ctbws$il_cursor_width_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_cursor_width_overlay.hwrpb_ctbws$r_cursor_width_fields.hwr\ pb_ctbws$il_cursor_width_l #define hwrpb_ctbws$il_cursor_width_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_cursor_width_overlay.hwrpb_ctbws$r_cursor_width_fields.hwr\ pb_ctbws$il_cursor_width_h #define hwrpb_ctbws$iq_cursor_hght hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_cursor_height_overla.hwrpb_ctbws$iq_cursor_hght #define hwrpb_ctbws$il_cursor_hght_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_cursor_height_overla.hwrpb_ctbws$r_cursor_hght_fields.hwrpb\ _ctbws$il_cursor_hght_l #define hwrpb_ctbws$il_cursor_hght_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_cursor_height_overla.hwrpb_ctbws$r_cursor_hght_fields.hwrpb\ _ctbws$il_cursor_hght_h #define hwrpb_ctbws$iq_head_count hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_head_count_overlay.hwrpb_ctbws$iq_head_count #define hwrpb_ctbws$il_head_count_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_head_count_overlay.hwrpb_ctbws$r_head_count_fields.hwrpb_ctb\ ws$il_head_count_l #define hwrpb_ctbws$il_head_count_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_head_count_overlay.hwrpb_ctbws$r_head_count_fields.hwrpb_ctb\ ws$il_head_count_h #define hwrpb_ctbws$iq_win_updwn hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_win_updwn_overlay.hwrpb_ctbws$iq_win_updwn #define hwrpb_ctbws$il_win_updwn_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_win_updwn_overlay.hwrpb_ctbws$r_win_updwn_fields.hwrpb_ctbws$\ il_win_updwn_l #define hwrpb_ctbws$il_win_updwn_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_win_updwn_overlay.hwrpb_ctbws$r_win_updwn_fields.hwrpb_ctbws$\ il_win_updwn_h #define hwrpb_ctbws$iq_head_offset hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_head_offset_overlay.hwrpb_ctbws$iq_head_offset #define hwrpb_ctbws$il_head_offset_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_head_offset_overlay.hwrpb_ctbws$r_head_offset_fields.hwrpb_\ ctbws$il_head_offset_l #define hwrpb_ctbws$il_head_offset_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_head_offset_overlay.hwrpb_ctbws$r_head_offset_fields.hwrpb_\ ctbws$il_head_offset_h #define hwrpb_ctbws$iq_put_char_rtn hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_put_char_rtn_overlay.hwrpb_ctbws$iq_put_char_rtn #define hwrpb_ctbws$il_put_char_rtn_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_put_char_rtn_overlay.hwrpb_ctbws$r_put_char_rtn_fields.hwr\ pb_ctbws$il_put_char_rtn_l #define hwrpb_ctbws$il_put_char_rtn_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_put_char_rtn_overlay.hwrpb_ctbws$r_put_char_rtn_fields.hwr\ pb_ctbws$il_put_char_rtn_h #define hwrpb_ctbws$iq_io_state hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_io_state_overlay.hwrpb_ctbws$iq_io_state #define hwrpb_ctbws$il_io_state_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_io_state_overlay.hwrpb_ctbws$r_io_state_fields.hwrpb_ctbws$il_\ io_state_l #define hwrpb_ctbws$il_io_state_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_io_state_overlay.hwrpb_ctbws$r_io_state_fields.hwrpb_ctbws$il_\ io_state_h #define hwrpb_ctbws$iq_lstnr_state hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_lstnr_state_overlay.hwrpb_ctbws$iq_lstnr_state #define hwrpb_ctbws$il_lstnr_state_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_lstnr_state_overlay.hwrpb_ctbws$r_lstnr_state_fields.hwrpb_\ ctbws$il_lstnr_state_l #define hwrpb_ctbws$il_lstnr_state_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_lstnr_state_overlay.hwrpb_ctbws$r_lstnr_state_fields.hwrpb_\ ctbws$il_lstnr_state_h #define hwrpb_ctbws$iq_info_ext hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_info_ext_overlay.hwrpb_ctbws$iq_info_ext #define hwrpb_ctbws$il_info_ext_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_info_ext_overlay.hwrpb_ctbws$r_info_ext_fields.hwrpb_ctbws$il_\ info_ext_l #define hwrpb_ctbws$il_info_ext_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_info_ext_overlay.hwrpb_ctbws$r_info_ext_fields.hwrpb_ctbws$il_\ info_ext_h #define hwrpb_ctbws$iq_opt_cons_loc hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_loc_overlay.hwrpb_ctbws$iq_opt_cons_loc #define hwrpb_ctbws$il_opt_cons_loc_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_loc_overlay.hwrpb_ctbws$r_opt_cons_loc_fields.hwrp\ b_ctbws$il_opt_cons_loc_l #define hwrpb_ctbws$il_opt_cons_loc_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_loc_overlay.hwrpb_ctbws$r_opt_cons_loc_fields.hwrp\ b_ctbws$il_opt_cons_loc_h #define hwrpb_ctbws$iq_termout_loc hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_loc_overlay.hwrpb_ctbws$iq_termout_loc #define hwrpb_ctbws$il_termout_loc_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_loc_overlay.hwrpb_ctbws$r_termout_loc_fields.hwrpb_\ ctbws$il_termout_loc_l #define hwrpb_ctbws$il_termout_loc_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_loc_overlay.hwrpb_ctbws$r_termout_loc_fields.hwrpb_\ ctbws$il_termout_loc_h #define hwrpb_ctbws$iq_server_offset hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_server_offset_overla.hwrpb_ctbws$iq_server_offset #define hwrpb_ctbws$il_server_offset_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_server_offset_overla.hwrpb_ctbws$r_server_offset_fields.h\ wrpb_ctbws$il_server_offset_l #define hwrpb_ctbws$il_server_offset_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_server_offset_overla.hwrpb_ctbws$r_server_offset_fields.h\ wrpb_ctbws$il_server_offset_h #define hwrpb_ctbws$iq_line_param hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_line_param_overlay.hwrpb_ctbws$iq_line_param #define hwrpb_ctbws$il_line_param_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_line_param_overlay.hwrpb_ctbws$r_line_param_fields.hwrpb_ctb\ ws$il_line_param_l #define hwrpb_ctbws$il_line_param_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_line_param_overlay.hwrpb_ctbws$r_line_param_fields.hwrpb_ctb\ ws$il_line_param_h #define hwrpb_ctbws$iq_termin_loc hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termin_loc_overlay.hwrpb_ctbws$iq_termin_loc #define hwrpb_ctbws$il_termin_loc_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termin_loc_overlay.hwrpb_ctbws$r_termin_loc_fields.hwrpb_ctb\ ws$il_termin_loc_l #define hwrpb_ctbws$il_termin_loc_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termin_loc_overlay.hwrpb_ctbws$r_termin_loc_fields.hwrpb_ctb\ ws$il_termin_loc_h #define hwrpb_ctbws$iq_termin_locx hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termin_locx_overlay.hwrpb_ctbws$iq_termin_locx #define hwrpb_ctbws$il_termin_locx_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termin_locx_overlay.hwrpb_ctbws$r_termin_locx_fields.hwrpb_\ ctbws$il_termin_locx_l #define hwrpb_ctbws$il_termin_locx_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termin_locx_overlay.hwrpb_ctbws$r_termin_locx_fields.hwrpb_\ ctbws$il_termin_locx_h #define hwrpb_ctbws$iq_term_protocol hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_term_protocol_overla.hwrpb_ctbws$iq_term_protocol #define hwrpb_ctbws$il_termin_protocol hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_term_protocol_overla.hwrpb_ctbws$r_term_protocol_fields.h\ wrpb_ctbws$il_termin_protocol #define hwrpb_ctbws$il_termout_protocol hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_term_protocol_overla.hwrpb_ctbws$r_term_protocol_fields.\ hwrpb_ctbws$il_termout_protocol #define hwrpb_ctbws$iq_termout_locx hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_locx_overlay.hwrpb_ctbws$iq_termout_locx #define hwrpb_ctbws$il_termout_locx_l hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_locx_overlay.hwrpb_ctbws$r_termout_locx_fields.hwr\ pb_ctbws$il_termout_locx_l #define hwrpb_ctbws$il_termout_locx_h hwrpb_ctb$r_ctbwsdef.hwrpb_ctbws$r_termout_locx_overlay.hwrpb_ctbws$r_termout_locx_fields.hwr\ pb_ctbws$il_termout_locx_h #endif /* #if !defined(__VAXC) */ /* */ #define HWRPB_CTB$K_LENGTH 352 #define HWRPB_CTB$C_LENGTH 352 #define HWRPB_CTB$S_CTBDEF 352 /* Old size name - synonym */ /* Console types */ #define HWRPB_CTB$K_NO_CONSOLE 0 /* No console is present */ #define HWRPB_CTB$K_SERVICE_CPU 1 /* Service processor */ #define HWRPB_CTB$K_TERMINAL 2 /* Serial line UART */ #define HWRPB_CTB$K_GRAPHIC 3 /* Graphic processor */ #define HWRPB_CTB$K_WORKSTATION 4 /* Integrated Workstation */ #define HWRPB_CTB$K_MAXTYPE 4 /* */ /* Define data structures for Cobra (02) configuration data block */ /**************************************************************** */ #define CONFIG_02$K_CONFIG_VERSION 1 #define CONFIG_02$K_MAX_DEVICES 16 /* in device block */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _config_02 { #pragma __nomember_alignment unsigned __int64 config_02$q_size; /* Size of CONFIG block */ unsigned __int64 config_02$q_checksum; /* Checksum of CONFIG block */ unsigned int config_02$l_version; /* Version */ unsigned int config_02$l_num_devices; /* Number of devices present */ #if defined(__VAXC) char config_02$b_device_02[]; #else /* Warning: empty char[] member for config_02$b_device_02 at end of structure not created */ #endif /* #if defined(__VAXC) */ } CONFIG_02; #define CONFIG_02$K_LENGTH 24 /* Length of CONFIG block */ /* */ /* Define data structures for Cobra (02) device block */ /**************************************************** */ #define DEVICE_02$K_TYPE_NONE 0 #define DEVICE_02$K_TYPE_NCR53C710_SCSI 1 #define DEVICE_02$K_TYPE_TGEC 2 #define DEVICE_02$K_TYPE_PCD8584 9 #define DEVICE_02$K_TYPE_NCR53C710_DSSI 10 #define DEVICE_02$M_SA 0x1 #define DEVICE_02$M_SE 0x2 #define DEVICE_02$M_HW 0x4 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _device_02 { #pragma __nomember_alignment unsigned char device_02$b_hose; /* Hose number of this device */ unsigned char device_02$b_slot; /* Slot number of this device */ unsigned short int device_02$w_num_vector; /* Number of vector for device */ unsigned short int device_02$w_vms_vector; /* VMS SCB vector for device */ unsigned short int device_02$w_osf_vector; /* OSF SCB vector for device */ unsigned int device_02$l_type; /* Type of device */ unsigned int device_02$l_version; /* Version of device block */ __union { unsigned __int64 device_02$q_specific_max [2]; __struct { unsigned char device_02$b_scsi_id; /* SCSI bus id of controller */ unsigned char device_02$b_fast; /* Fast SCSI enable */ } device_02$r_scsi_specific; __struct { unsigned char device_02$b_dssi_id; /* DSSI bus id of controller */ } device_02$r_dssi_specific; __struct { unsigned char device_02$b_sa [6]; /* Ethernet hardware address */ __struct { unsigned device_02$v_sa : 1; /* Sync/Async enable */ unsigned device_02$v_se : 1; /* Single cycle enable */ unsigned device_02$v_hw : 1; /* Hexaword enable */ unsigned device_02$v_fill_0_ : 5; } device_02$r_mode; unsigned char device_02$b_burst; /* Burst length in bytes */ } device_02$r_tgec_specific; } device_02$r_specific; } DEVICE_02; #if !defined(__VAXC) #define device_02$q_specific_max device_02$r_specific.device_02$q_specific_max #define device_02$b_scsi_id device_02$r_specific.device_02$r_scsi_specific.device_02$b_scsi_id #define device_02$b_fast device_02$r_specific.device_02$r_scsi_specific.device_02$b_fast #define device_02$b_dssi_id device_02$r_specific.device_02$r_dssi_specific.device_02$b_dssi_id #define device_02$b_sa device_02$r_specific.device_02$r_tgec_specific.device_02$b_sa #define device_02$v_sa device_02$r_specific.device_02$r_tgec_specific.device_02$r_mode.device_02$v_sa #define device_02$v_se device_02$r_specific.device_02$r_tgec_specific.device_02$r_mode.device_02$v_se #define device_02$v_hw device_02$r_specific.device_02$r_tgec_specific.device_02$r_mode.device_02$v_hw #define device_02$b_burst device_02$r_specific.device_02$r_tgec_specific.device_02$b_burst #endif /* #if !defined(__VAXC) */ #define DEVICE_02$K_LENGTH 32 /*Alpha */ #ifndef __ALPHA #ifdef EFI64 #pragma pack(pop,hwrpbdef) #endif #endif /* */ /* FRU Table Header */ /* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _fru_hdr { #pragma __nomember_alignment unsigned __int64 fru$q_fruhdr_checksum; unsigned int fru$l_fruhdr_length; char fru$b_fill_1_ [4]; } FRU_HDR; /*Alpha */ /*IA64 */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __HWRPBDEF_LOADED */