/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:25:14 by OpenVMS SDL EV3-3 */ /* Source: 22-MAR-1993 14:38:24 $1$DGA7274:[LIB_H.SRC]FBUSDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $FBUSDEF ***/ #ifndef __FBUSDEF_LOADED #define __FBUSDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*+ */ /* This file describes the layout of Futurebus CSR space. The information is */ /* based on the IEEE Futurebus specification 896.2 and IEEE CSR Architecture */ /* specification P1212. */ /*- */ #define FBUS$M_TEST_STATUS_FAILED 0x1 #define FBUS$M_TEST_STATUS_TIMEOUT 0x2 #define FBUS$M_TEST_STATUS_IMPLEMENTED 0x4 #define FBUS$M_TEST_STATUS_LOOPING 0x8 #define FBUS$M_TEST_STATUS_ACTIVE 0x10 #define FBUS$M_TEST_STATUS_RESERVED 0x20 #define FBUS$M_TEST_STATUS_STEP 0x3FFFC0 #define FBUS$M_TEST_STATUS_FRU 0xFC00000 #define FBUS$M_TEST_STATUS_CAT 0xF0000000 #define FBUS$M_ROM_BASE_CRC_VALUE 0xFFFF #define FBUS$M_ROM_BASE_CRC_LENGTH 0xFF0000 #define FBUS$M_ROM_BASE_BUS_INFO_LENGTH 0xFF000000 #define FBUS$M_ROOT_DIR_BASE_CRC 0xFFFF #define FBUS$M_ROOT_DIR_BASE_LENGTH 0xFFFF0000 #define FBUS$K_NODE_SPACE_LENGTH 4096 #define FBUS$S_FBUSDEF 4096 /* Old size name, synonym for FBUS$S_FBUS */ typedef struct _fbus { /* The following definitions are for CORE CSR space, required by a all Futurebus */ /* nodes. */ #if defined(__VAXC) char fbus$l_csr_core[]; #else #define fbus$l_csr_core fbus$r_state_clear_overlay #endif /* #if defined(__VAXC) */ __union { /* State Clear register */ unsigned int fbus$l_state_clear; __struct { unsigned fbus$v_state_clear_fill : 32; } fbus$r_state_clear_fields; } fbus$r_state_clear_overlay; __union { /* State Set register */ unsigned int fbus$l_state_set; __struct { unsigned fbus$v_state_set_fill : 32; } fbus$r_state_set_fields; } fbus$r_state_set_overlay; __union { /* Node IDs register */ unsigned int fbus$l_node_ids; __struct { unsigned fbus$v_node_ids_fill : 32; } fbus$r_node_ids_fields; } fbus$r_node_ids_overlay; __union { /* Reset Start register */ unsigned int fbus$l_reset_start; __struct { unsigned fbus$v_reset_start_fill : 32; } fbus$r_reset_start_fields; } fbus$r_reset_start_overlay; __union { /* Indirect Address register */ unsigned int fbus$l_indirect_address; __struct { unsigned fbus$v_indirect_address_fill : 32; } fbus$r_indirect_address_fields; } fbus$r_indirect_address_overlay; __union { /* Indirect Data register */ unsigned int fbus$l_indirect_data; __struct { unsigned fbus$v_indirect_data_fill : 32; } fbus$r_indirect_data_fields; } fbus$r_indirect_data_overlay; __union { /* Split Timeout Hi register */ unsigned int fbus$l_split_timeout_hi; __struct { unsigned fbus$v_split_timeout_hi_fill : 32; } fbus$r_split_timeout_hi_fields; } fbus$r_split_timeout_hi_overlay; __union { /* Split Timeout Lo register */ unsigned int fbus$l_split_timeout_lo; __struct { unsigned fbus$v_split_timeout_lo_fill : 32; } fbus$r_split_timeout_lo_fields; } fbus$r_split_timeout_lo_overlay; __union { /* Argument Hi register */ unsigned int fbus$l_argument_hi; __struct { unsigned fbus$v_argument_hi_fill : 32; } fbus$r_argument_hi_fields; } fbus$r_argument_hi_overlay; __union { /* Argument Lo register */ unsigned int fbus$l_argument_lo; __struct { unsigned fbus$v_argument_lo_fill : 32; } fbus$r_argument_lo_fields; } fbus$r_argument_lo_overlay; __union { /* Test Start register */ unsigned int fbus$l_test_start; __struct { unsigned fbus$v_test_start_fill : 32; } fbus$r_test_start_fields; } fbus$r_test_start_overlay; __union { /* Test Status register */ unsigned int fbus$l_test_status; __struct { unsigned fbus$v_test_status_failed : 1; unsigned fbus$v_test_status_timeout : 1; unsigned fbus$v_test_status_implemented : 1; unsigned fbus$v_test_status_looping : 1; unsigned fbus$v_test_status_active : 1; unsigned fbus$v_test_status_reserved : 1; unsigned fbus$v_test_status_step : 16; unsigned fbus$v_test_status_fru : 6; unsigned fbus$v_test_status_cat : 4; } fbus$r_test_status_fields; } fbus$r_test_status_overlay; __union { /* Units Base Hi register */ unsigned int fbus$l_units_base_hi; __struct { unsigned fbus$v_units_base_hi_fill : 32; } fbus$r_units_base_hi_fields; } fbus$r_units_base_hi_overlay; __union { /* Units Base Lo register */ unsigned int fbus$l_units_base_lo; __struct { unsigned fbus$v_units_base_lo_fill : 32; } fbus$r_units_base_lo_fields; } fbus$r_units_base_lo_overlay; __union { /* Units Bound Hi register */ unsigned int fbus$l_units_bound_hi; __struct { unsigned fbus$v_units_bound_hi_fill : 32; } fbus$r_units_bound_hi_fields; } fbus$r_units_bound_hi_overlay; __union { /* Units Bound Lo register */ unsigned int fbus$l_units_bound_lo; __struct { unsigned fbus$v_units_bound_lo_fill : 32; } fbus$r_units_bound_lo_fields; } fbus$r_units_bound_lo_overlay; __union { /* Memory Base Hi register */ unsigned int fbus$l_memory_base_hi; __struct { unsigned fbus$v_memory_base_hi_fill : 32; } fbus$r_memory_base_hi_fields; } fbus$r_memory_base_hi_overlay; __union { /* Memory Base Lo register */ unsigned int fbus$l_memory_base_lo; __struct { unsigned fbus$v_memory_base_lo_fill : 32; } fbus$r_memory_base_lo_fields; } fbus$r_memory_base_lo_overlay; __union { /* Memory Bound Hi register */ unsigned int fbus$l_memory_bound_hi; __struct { unsigned fbus$v_memory_bound_hi_fill : 32; } fbus$r_memory_bound_hi_fields; } fbus$r_memory_bound_hi_overlay; __union { /* Memory Bound Lo register */ unsigned int fbus$l_memory_bound_lo; __struct { unsigned fbus$v_memory_bound_lo_fill : 32; } fbus$r_memory_bound_lo_fields; } fbus$r_memory_bound_lo_overlay; __union { /* Interrupt Target register */ unsigned int fbus$l_interrupt_target; __struct { unsigned fbus$v_interrupt_target_fill : 32; } fbus$r_interrupt_target_fields; } fbus$r_interrupt_target_overlay; __union { /* Interrupt Mask register */ unsigned int fbus$l_interrupt_mask; __struct { unsigned fbus$v_interrupt_mask_fill : 32; } fbus$r_interrupt_mask_fields; } fbus$r_interrupt_mask_overlay; __union { /* Clock Value Hi register */ unsigned int fbus$l_clock_value_hi; __struct { unsigned fbus$v_clock_value_hi_fill : 32; } fbus$r_clock_value_hi_fields; } fbus$r_clock_value_hi_overlay; __union { /* Clock Value Mid register */ unsigned int fbus$l_clock_value_mid; __struct { unsigned fbus$v_clock_value_mid_fill : 32; } fbus$r_clock_value_mid_fields; } fbus$r_clock_value_mid_overlay; __union { /* Clock Tick Period Mid register */ unsigned int fbus$l_clock_tick_period_mid; __struct { unsigned fbus$v_clock_tick_period_mid_fill : 32; } fbus$r_clock_tick_period_mid_field; } fbus$r_clock_tick_period_mid_overl; __union { /* Clock Tick Period Lo register */ unsigned int fbus$l_clock_tick_period_lo; __struct { unsigned fbus$v_clock_tick_period_lo_fill : 32; } fbus$r_clock_tick_period_lo_fields; } fbus$r_clock_tick_period_lo_overla; __union { /* Clock Strobe Arrived Hi register */ unsigned int fbus$l_clock_strobe_arrived_hi; __struct { unsigned fbus$v_clock_strobe_arrived_hi_fil : 32; } fbus$r_clock_strobe_arrived_hi_fie; } fbus$r_clock_strobe_arrived_hi_ove; __union { /* Clock Strobe Arrived Mid register */ unsigned int fbus$l_clock_strobe_arrived_mid; __struct { unsigned fbus$v_clock_strobe_arrived_mid_fi : 32; } fbus$r_clock_strobe_arrived_mid_fi; } fbus$r_clock_strobe_arrived_mid_ov; __union { /* Clock Strobe register */ unsigned int fbus$l_clock_strobe; __struct { unsigned fbus$v_clock_strobe_fill : 32; } fbus$r_clock_strobe_fields; } fbus$r_clock_strobe_overlay; __union { /* Clock Info1 register */ unsigned int fbus$l_clock_info1; __struct { unsigned fbus$v_clock_info1_fill : 32; } fbus$r_clock_info1_fields; } fbus$r_clock_info1_overlay; __union { /* Clock Reference register */ unsigned int fbus$l_clock_reference; __struct { unsigned fbus$v_clock_reference_fill : 32; } fbus$r_clock_reference_fields; } fbus$r_clock_reference_overlay; __union { /* Clock Info 3 register */ unsigned int fbus$l_clock_info3; __struct { unsigned fbus$v_clock_info3_fill : 32; } fbus$r_clock_info3_fields; } fbus$r_clock_info3_overlay; unsigned int fbus$l_message_request [16]; /* Message Request area */ unsigned int fbus$l_message_response [16]; /* Message Response area */ unsigned int fbus$l_p1212_reserved [32]; /* Reserved by P1212 */ __union { unsigned int fbus$l_error_hi; __struct { unsigned fbus$v_error_hi_fill : 32; } fbus$r_error_hi_fields; } fbus$r_error_hi_overlay; __union { unsigned int fbus$l_error_lo; __struct { unsigned fbus$v_error_lo_fill : 32; } fbus$r_error_lo_fields; } fbus$r_error_lo_overlay; __union { unsigned int fbus$l_fadr_hi; __struct { unsigned fbus$v_fadr_hi_fill : 32; } fbus$r_fadr_hi_fields; } fbus$r_fadr_hi_overlay; __union { unsigned int fbus$l_fadr_lo; __struct { unsigned fbus$v_fadr_lo_fill : 32; } fbus$r_fadr_lo_fields; } fbus$r_fadr_lo_overlay; unsigned int fbus$l_error_log_buffer [28]; /* The following definitions describe the Futurebus dependent CSR area */ #if defined(__VAXC) char fbus$l_bus_dependent[]; #else #define fbus$l_bus_dependent fbus$r_logical_common_control_over #endif /* #if defined(__VAXC) */ __union { /* Logical Common Control register */ unsigned int fbus$l_logical_common_control; __struct { unsigned fbus$v_logical_common_control_fill : 32; } fbus$r_logical_common_control_fiel; } fbus$r_logical_common_control_over; __union { /* Logical Module Control register */ unsigned int fbus$l_logical_module_control; __struct { unsigned fbus$v_logical_module_control_fill : 32; } fbus$r_logical_module_control_fiel; } fbus$r_logical_module_control_over; __union { /* Bus Propagation Delay register */ unsigned int fbus$l_bus_prop_delay; __struct { unsigned fbus$v_bus_prop_delay_fill : 32; } fbus$r_bus_prop_delay_fields; } fbus$r_bus_prop_delay_overlay; __union { /* Competition Settling Time register */ unsigned int fbus$l_comp_settling_time; __struct { unsigned fbus$v_comp_settling_time_fill : 32; } fbus$r_comp_settling_time_fields; } fbus$r_comp_settling_time_overlay; __union { /* Transaction Timeout register */ unsigned int fbus$l_transaction_timeout; __struct { unsigned fbus$v_transaction_timeout_fill : 32; } fbus$r_transaction_timeout_fields; } fbus$r_transaction_timeout_overlay; __union { /* Message Passing Select Mask */ unsigned int fbus$l_msg_select_mask_hi; __struct { unsigned fbus$v_msg_select_mask_hi_fill : 32; } fbus$r_msg_select_mask_hi_fields; } fbus$r_msg_select_mask_overlay_hi; __union { unsigned int fbus$l_msg_select_mask_lo; __struct { unsigned fbus$v_msg_select_mask_lo_fill : 32; } fbus$r_msg_select_mask_lo_fields; } fbus$r_msg_select_mask_overlay_lo; __union { /* Busy Retry Counter */ unsigned int fbus$l_bsy_rtry_counter; __struct { unsigned fbus$v_bsy_rtry_counter_fill : 32; } fbus$r_bsy_rtry_counter_fields; } fbus$r_bsy_rtry_counter_overlay; __union { /* Busy Retry Delay */ unsigned int fbus$l_bsy_rtry_delay; __struct { unsigned fbus$v_bsy_rtry_delay_fill : 32; } fbus$r_bsy_rtry_delay_fields; } fbus$r_bsy_rtry_delay_overlay; __union { /* Error Retry Counter */ unsigned int fbus$l_err_rtry_counter; __struct { unsigned fbus$v_err_rtry_counter_fill : 32; } fbus$r_err_rtry_counter_fields; } fbus$r_err_rtry_counter_overlay; __union { /* Error Retry Delay */ unsigned int fbus$l_err_rtry_delay; __struct { unsigned fbus$v_err_rtry_delay_fill : 32; } fbus$r_err_rtry_delay_fields; } fbus$r_err_rtry_delay_overlay; unsigned int fbus$l_bus_dependent_reserved [53]; unsigned int fbus$l_vendor_dependent [64]; /* The following definitions describe the Futurebus ROM area. */ __union { /* ROM Base starting location */ unsigned int fbus$l_rom_base; __struct { unsigned fbus$v_rom_base_crc_value : 16; unsigned fbus$v_rom_base_crc_length : 8; unsigned fbus$v_rom_base_bus_info_length : 8; } fbus$r_rom_base_fields; } fbus$r_rom_base_overlay; __union { /* Bus Id location */ unsigned int fbus$l_bus_id; __struct { unsigned fbus$v_bus_id_fill : 32; } fbus$r_bus_id_fields; } fbus$r_bus_id_overlay; __union { /* Profile ID */ unsigned int fbus$l_profile_id_hi; __struct { unsigned fbus$v_profile_id_hi_fill : 32; } fbus$r_profile_id_hi_fields; } fbus$r_profile_id_hi_overlay; __union { unsigned int fbus$l_profile_id_lo; __struct { unsigned fbus$v_profile_id_lo_fill : 32; } fbus$r_profile_id_lo_fields; } fbus$r_profile_id_lo_overlay; __union { /* Module Logical Capability */ unsigned int fbus$l_mod_log_cap; __struct { unsigned fbus$v_mod_log_cap_fill : 32; } fbus$r_mod_log_cap_fields; } fbus$r_mod_log_cap_overlay; __union { /* Node Capabilities Ext */ unsigned int fbus$l_node_cap_ext; __struct { unsigned fbus$v_node_cap_ext_fill : 32; } fbus$r_node_cap_ext_fields; } fbus$r_node_cap_ext_overlay; __union { /* Competition Internal Delay */ unsigned int fbus$l_comp_int_delay; __struct { unsigned fbus$v_comp_int_delay_fill : 32; } fbus$r_comp_int_delay_fields; } fbus$r_comp_int_delay_overlay; __union { /* Packet Speed register */ unsigned int fbus$l_packet_speed; __struct { unsigned fbus$v_packet_speed_fill : 32; } fbus$r_packet_speed_fields; } fbus$r_packet_speed_overlay; __union { /* Message Frame Size */ unsigned int fbus$l_msg_frame_size; __struct { unsigned fbus$v_msg_frame_size_fill : 32; } fbus$r_msg_frame_size_fields; } fbus$r_msg_frame_size_overlay; __union { /* Busy Retry Counter Capability */ unsigned int fbus$l_bsy_rtry_counter_cap; __struct { unsigned fbus$v_bsy_rtry_counter_cap_fill : 32; } fbus$r_bsy_rtry_counter_cap_fields; } fbus$r_bsy_rtry_counter_cap_overla; __union { /* Busy Retry Delay Capability */ unsigned int fbus$l_bsy_rtry_delay_cap; __struct { unsigned fbus$v_bsy_rtry_delay_cap_fill : 32; } fbus$r_bsy_rtry_delay_cap_fields; } fbus$r_bsy_rtry_delay_cap_overlay; __union { /* Error Retry Counter Capability */ unsigned int fbus$l_err_rtry_counter_cap; __struct { unsigned fbus$v_err_rtry_counter_cap_fill : 32; } fbus$r_err_rtry_counter_cap_fields; } fbus$r_err_rtry_counter_cap_overla; __union { /* Error Retry Delay Capability */ unsigned int fbus$l_err_rtry_delay_cap; __struct { unsigned fbus$v_err_rtry_delay_cap_fill : 32; } fbus$r_err_rtry_delay_cap_fields; } fbus$r_err_rtry_delay_cap_overlay; unsigned int fbus$l_bus_info_reserved [3]; __union { /* Root Directory base */ unsigned int fbus$l_root_dir_base; __struct { unsigned fbus$v_root_dir_base_crc : 16; unsigned fbus$v_root_dir_base_length : 16; } fbus$r_root_dir_base_fields; } fbus$r_root_dir_base_overlay; unsigned int fbus$l_rom_space_fill [239]; #if defined(__VAXC) char fbus$l_initial_units_space_base[]; #else #define fbus$l_initial_units_space_base fbus$l_initial_units_space_fill #endif /* #if defined(__VAXC) */ unsigned int fbus$l_initial_units_space_fill [512]; } FBUS; #if !defined(__VAXC) #define fbus$l_state_clear fbus$r_state_clear_overlay.fbus$l_state_clear #define fbus$l_state_set fbus$r_state_set_overlay.fbus$l_state_set #define fbus$l_node_ids fbus$r_node_ids_overlay.fbus$l_node_ids #define fbus$l_reset_start fbus$r_reset_start_overlay.fbus$l_reset_start #define fbus$l_indirect_address fbus$r_indirect_address_overlay.fbus$l_indirect_address #define fbus$l_indirect_data fbus$r_indirect_data_overlay.fbus$l_indirect_data #define fbus$l_split_timeout_hi fbus$r_split_timeout_hi_overlay.fbus$l_split_timeout_hi #define fbus$l_split_timeout_lo fbus$r_split_timeout_lo_overlay.fbus$l_split_timeout_lo #define fbus$l_argument_hi fbus$r_argument_hi_overlay.fbus$l_argument_hi #define fbus$l_argument_lo fbus$r_argument_lo_overlay.fbus$l_argument_lo #define fbus$l_test_start fbus$r_test_start_overlay.fbus$l_test_start #define fbus$l_test_status fbus$r_test_status_overlay.fbus$l_test_status #define fbus$v_test_status_failed fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_failed #define fbus$v_test_status_timeout fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_timeout #define fbus$v_test_status_implemented fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_implemented #define fbus$v_test_status_looping fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_looping #define fbus$v_test_status_active fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_active #define fbus$v_test_status_reserved fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_reserved #define fbus$v_test_status_step fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_step #define fbus$v_test_status_fru fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_fru #define fbus$v_test_status_cat fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_cat #define fbus$l_units_base_hi fbus$r_units_base_hi_overlay.fbus$l_units_base_hi #define fbus$l_units_base_lo fbus$r_units_base_lo_overlay.fbus$l_units_base_lo #define fbus$l_units_bound_hi fbus$r_units_bound_hi_overlay.fbus$l_units_bound_hi #define fbus$l_units_bound_lo fbus$r_units_bound_lo_overlay.fbus$l_units_bound_lo #define fbus$l_memory_base_hi fbus$r_memory_base_hi_overlay.fbus$l_memory_base_hi #define fbus$l_memory_base_lo fbus$r_memory_base_lo_overlay.fbus$l_memory_base_lo #define fbus$l_memory_bound_hi fbus$r_memory_bound_hi_overlay.fbus$l_memory_bound_hi #define fbus$l_memory_bound_lo fbus$r_memory_bound_lo_overlay.fbus$l_memory_bound_lo #define fbus$l_interrupt_target fbus$r_interrupt_target_overlay.fbus$l_interrupt_target #define fbus$l_interrupt_mask fbus$r_interrupt_mask_overlay.fbus$l_interrupt_mask #define fbus$l_clock_value_hi fbus$r_clock_value_hi_overlay.fbus$l_clock_value_hi #define fbus$l_clock_value_mid fbus$r_clock_value_mid_overlay.fbus$l_clock_value_mid #define fbus$l_clock_tick_period_mid fbus$r_clock_tick_period_mid_overl.fbus$l_clock_tick_period_mid #define fbus$l_clock_tick_period_lo fbus$r_clock_tick_period_lo_overla.fbus$l_clock_tick_period_lo #define fbus$l_clock_strobe_arrived_hi fbus$r_clock_strobe_arrived_hi_ove.fbus$l_clock_strobe_arrived_hi #define fbus$l_clock_strobe_arrived_mid fbus$r_clock_strobe_arrived_mid_ov.fbus$l_clock_strobe_arrived_mid #define fbus$l_clock_strobe fbus$r_clock_strobe_overlay.fbus$l_clock_strobe #define fbus$l_clock_info1 fbus$r_clock_info1_overlay.fbus$l_clock_info1 #define fbus$l_clock_reference fbus$r_clock_reference_overlay.fbus$l_clock_reference #define fbus$l_clock_info3 fbus$r_clock_info3_overlay.fbus$l_clock_info3 #define fbus$l_error_hi fbus$r_error_hi_overlay.fbus$l_error_hi #define fbus$l_error_lo fbus$r_error_lo_overlay.fbus$l_error_lo #define fbus$l_fadr_hi fbus$r_fadr_hi_overlay.fbus$l_fadr_hi #define fbus$l_fadr_lo fbus$r_fadr_lo_overlay.fbus$l_fadr_lo #define fbus$l_logical_common_control fbus$r_logical_common_control_over.fbus$l_logical_common_control #define fbus$l_logical_module_control fbus$r_logical_module_control_over.fbus$l_logical_module_control #define fbus$l_bus_prop_delay fbus$r_bus_prop_delay_overlay.fbus$l_bus_prop_delay #define fbus$l_comp_settling_time fbus$r_comp_settling_time_overlay.fbus$l_comp_settling_time #define fbus$l_transaction_timeout fbus$r_transaction_timeout_overlay.fbus$l_transaction_timeout #define fbus$l_msg_select_mask_hi fbus$r_msg_select_mask_overlay_hi.fbus$l_msg_select_mask_hi #define fbus$l_msg_select_mask_lo fbus$r_msg_select_mask_overlay_lo.fbus$l_msg_select_mask_lo #define fbus$l_bsy_rtry_counter fbus$r_bsy_rtry_counter_overlay.fbus$l_bsy_rtry_counter #define fbus$l_bsy_rtry_delay fbus$r_bsy_rtry_delay_overlay.fbus$l_bsy_rtry_delay #define fbus$l_err_rtry_counter fbus$r_err_rtry_counter_overlay.fbus$l_err_rtry_counter #define fbus$l_err_rtry_delay fbus$r_err_rtry_delay_overlay.fbus$l_err_rtry_delay #define fbus$l_rom_base fbus$r_rom_base_overlay.fbus$l_rom_base #define fbus$v_rom_base_crc_value fbus$r_rom_base_overlay.fbus$r_rom_base_fields.fbus$v_rom_base_crc_value #define fbus$v_rom_base_crc_length fbus$r_rom_base_overlay.fbus$r_rom_base_fields.fbus$v_rom_base_crc_length #define fbus$v_rom_base_bus_info_length fbus$r_rom_base_overlay.fbus$r_rom_base_fields.fbus$v_rom_base_bus_info_length #define fbus$l_bus_id fbus$r_bus_id_overlay.fbus$l_bus_id #define fbus$l_profile_id_hi fbus$r_profile_id_hi_overlay.fbus$l_profile_id_hi #define fbus$l_profile_id_lo fbus$r_profile_id_lo_overlay.fbus$l_profile_id_lo #define fbus$l_mod_log_cap fbus$r_mod_log_cap_overlay.fbus$l_mod_log_cap #define fbus$l_node_cap_ext fbus$r_node_cap_ext_overlay.fbus$l_node_cap_ext #define fbus$l_comp_int_delay fbus$r_comp_int_delay_overlay.fbus$l_comp_int_delay #define fbus$l_packet_speed fbus$r_packet_speed_overlay.fbus$l_packet_speed #define fbus$l_msg_frame_size fbus$r_msg_frame_size_overlay.fbus$l_msg_frame_size #define fbus$l_bsy_rtry_counter_cap fbus$r_bsy_rtry_counter_cap_overla.fbus$l_bsy_rtry_counter_cap #define fbus$l_bsy_rtry_delay_cap fbus$r_bsy_rtry_delay_cap_overlay.fbus$l_bsy_rtry_delay_cap #define fbus$l_err_rtry_counter_cap fbus$r_err_rtry_counter_cap_overla.fbus$l_err_rtry_counter_cap #define fbus$l_err_rtry_delay_cap fbus$r_err_rtry_delay_cap_overlay.fbus$l_err_rtry_delay_cap #define fbus$l_root_dir_base fbus$r_root_dir_base_overlay.fbus$l_root_dir_base #define fbus$v_root_dir_base_crc fbus$r_root_dir_base_overlay.fbus$r_root_dir_base_fields.fbus$v_root_dir_base_crc #define fbus$v_root_dir_base_length fbus$r_root_dir_base_overlay.fbus$r_root_dir_base_fields.fbus$v_root_dir_base_length #endif /* #if !defined(__VAXC) */ /* The following definitions describe the format of entries in root directories, */ /* subdirectories, and leaves. Root directories, subdirectories, and leaves are */ /* basically all the same thing -- an area of ROM space containing information */ /* about the module, node, or unit. See P1212 for the gory details on directory entry */ /* specification. Briefly, each type of directory contains an initial entry which */ /* indicates the size of the directory followed by one or more entries. */ /* All entries in a directory contain a key in byte 0, which identifies */ /* the type of entry, and a value in bytes 1, 2, and 3. The value can be an */ /* immediate value or a pointer, depending on the key value. */ /* Directory base entry format */ #define FBUS$M_DIR_BASE_CRC 0xFFFF #define FBUS$M_DIR_BASE_LENGTH 0xFFFF0000 #define FBUS$S_DIR_BASE_DEF 4 /* Old size name, synonym for FBUS$S_DIR_BASE */ typedef struct _dir_base { __union { unsigned int fbus$l_dir_base; __struct { unsigned fbus$v_dir_base_crc : 16; unsigned fbus$v_dir_base_length : 16; } fbus$r_dir_base_fields; } fbus$r_dir_base_overlay; } DIR_BASE; #if !defined(__VAXC) #define fbus$l_dir_base fbus$r_dir_base_overlay.fbus$l_dir_base #define fbus$v_dir_base_crc fbus$r_dir_base_overlay.fbus$r_dir_base_fields.fbus$v_dir_base_crc #define fbus$v_dir_base_length fbus$r_dir_base_overlay.fbus$r_dir_base_fields.fbus$v_dir_base_length #endif /* #if !defined(__VAXC) */ #define FBUS$M_DIR_ENTRY_VALUE 0xFFFFFF #define FBUS$M_DIR_ENTRY_KEY 0xFF000000 #define FBUS$S_DIR_ENTRY_DEF 4 /* Old size name, synonym for FBUS$S_DIR_ENTRY */ typedef struct _dir_entry { /* Directory entry format */ __union { unsigned int fbus$l_dir_entry; __struct { unsigned fbus$v_dir_entry_value : 24; unsigned fbus$v_dir_entry_key : 8; } fbus$r_dir_entry_fields; } fbus$r_dir_entry_overlay; } DIR_ENTRY; #if !defined(__VAXC) #define fbus$l_dir_entry fbus$r_dir_entry_overlay.fbus$l_dir_entry #define fbus$v_dir_entry_value fbus$r_dir_entry_overlay.fbus$r_dir_entry_fields.fbus$v_dir_entry_value #define fbus$v_dir_entry_key fbus$r_dir_entry_overlay.fbus$r_dir_entry_fields.fbus$v_dir_entry_key #endif /* #if !defined(__VAXC) */ /* The following definition describes the Digital implementation of ROM */ /* directory entry MODULE_SW_VERSION */ #define FBUS$M_DIGITAL_SW_VERSION_NODE 0x1 #define FBUS$M_DIGITAL_SW_VERSION_UNIT 0x3E #define FBUS$M_DIGITAL_SW_VERSION_VAR 0x3FC0 #define FBUS$M_DIGITAL_SW_VERSION_NUM 0xFFC000 #define FBUS$M_DIGITAL_SW_VERSION_KEY 0xFF000000 #define FBUS$S_DIGITAL_SW_VERSION_DEF 4 /* Old size name, synonym for FBUS$S_DIGITAL_SW_VERSION */ typedef struct _digital_sw_version { __union { unsigned int fbus$l_digital_sw_version; __struct { unsigned fbus$v_digital_sw_version_node : 1; unsigned fbus$v_digital_sw_version_unit : 5; unsigned fbus$v_digital_sw_version_var : 8; unsigned fbus$v_digital_sw_version_num : 10; unsigned fbus$v_digital_sw_version_key : 8; } fbus$r_digital_sw_version_fields; } fbus$r_digital_sw_version_overlay; } DIGITAL_SW_VERSION; #if !defined(__VAXC) #define fbus$l_digital_sw_version fbus$r_digital_sw_version_overlay.fbus$l_digital_sw_version #define fbus$v_digital_sw_version_node fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version\ _node #define fbus$v_digital_sw_version_unit fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version\ _unit #define fbus$v_digital_sw_version_var fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version_\ var #define fbus$v_digital_sw_version_num fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version_\ num #define fbus$v_digital_sw_version_key fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version_\ key #endif /* #if !defined(__VAXC) */ /* Format of Bus Array entry hardware_id quadword. When we probe the */ /* Futurebus, we concatenate the vendor_id and the sw_version (which are both */ /* read from the Fbus ROM area) and store the resulting quadword in a bus array */ /* entry. The following structure defines the format of the hardware id */ /* quadword in the bus array entry. */ #define DEC_FBUS$S_HW_ID_DEF 8 /* Old size name, synonym for DEC_FBUS$S_HW_ID */ typedef struct _fbus_hw_id { __union { unsigned __int64 dec_fbus$q_hw_id; __struct { unsigned int dec_fbus$l_hw_id_sw_version; unsigned int dec_fbus$l_hw_id_vendor_id; } dec_fbus$r_hw_id_fields; } dec_fbus$r_hw_id_overlay; } FBUS_HW_ID; #if !defined(__VAXC) #define dec_fbus$q_hw_id dec_fbus$r_hw_id_overlay.dec_fbus$q_hw_id #define dec_fbus$l_hw_id_sw_version dec_fbus$r_hw_id_overlay.dec_fbus$r_hw_id_fields.dec_fbus$l_hw_id_sw_version #define dec_fbus$l_hw_id_vendor_id dec_fbus$r_hw_id_overlay.dec_fbus$r_hw_id_fields.dec_fbus$l_hw_id_vendor_id #endif /* #if !defined(__VAXC) */ /* The following key types are defined by IEEE 1212. */ #define FBUS_KEY$K_TEX_LEAF 129 #define FBUS_KEY$K_TEX_SUBD 193 #define FBUS_KEY$K_BUS_DEP_INFO_LEAF 130 #define FBUS_KEY$K_BUS_DEP_INFO_SUBD 194 #define FBUS_KEY$K_MODULE_VENDOR_ID 3 #define FBUS_KEY$K_MODULE_HW_VERSION 4 #define FBUS_KEY$K_MODULE_SPEC_ID 5 #define FBUS_KEY$K_MODULE_SW_VERSION 6 #define FBUS_KEY$K_MODULE_DEP_INFO_LEAF 135 #define FBUS_KEY$K_MODULE_DEP_INFO_SUBD 199 #define FBUS_KEY$K_NODE_VENDOR_ID 8 #define FBUS_KEY$K_NODE_HW_VERSION 9 #define FBUS_KEY$K_NODE_SPEC_ID 10 #define FBUS_KEY$K_NODE_SW_VERSION 11 #define FBUS_KEY$K_NODE_CAPABILITIES 12 #define FBUS_KEY$K_NODE_UNIQUE_ID_LEAF 141 #define FBUS_KEY$K_NODE_UNITS_EXTENT 14 #define FBUS_KEY$K_NODE_UNITS_EXTENT_OF 78 #define FBUS_KEY$K_NODE_MEM_EXTENT 15 #define FBUS_KEY$K_NODE_MEM_EXTENT_OF 79 #define FBUS_KEY$K_NODE_DEP_INFO_LEAF 144 #define FBUS_KEY$K_NODE_DEP_INFO_SUBD 208 #define FBUS_KEY$K_UNIT_SUB 209 #define FBUS_KEY$K_UNIT_SPEC_ID 18 #define FBUS_KEY$K_UNIT_SW_VERSION 19 #define FBUS_KEY$K_UNIT_DEP_INFO_LEAF 148 #define FBUS_KEY$K_UNIT_DEP_INFO_SUBD 212 #define FBUS_KEY$K_UNIT_LOCATION 149 #define FBUS_KEY$K_UNIT_POLL_MASK 149 /* The following constants are useful for bus probing */ #define FBUS$K_NODE0_BASE_CSR -262144 #define FBUS$K_MAX_NODE_NUMBER 63 #define FBUS$K_DIGITAL_VENDOR_ID 524331 /* Create constants to represent Futurebus commands. These are the */ /* values that will be copied to the command field of the hardware mailbox */ /* for Futurebus register access. */ /* */ /* The following encodings for the Futurebus command field are taken */ /* from the Cobra I/O Module spec. These encodings should be the same */ /* for a Futurebus on any platform. */ /* */ /* 7 6 5 4 3 2 1 0 */ /* +---+---+---+---+---+---+---+---+ */ /* |AW | 0 |DW |WR | transaction | */ /* +---+---+---+---+---+---+---+---+ */ /* */ /* Bit Meaning */ /* --- ------- */ /* AW = 0 32 bit addressing */ /* AW = 1 64 bit addressing */ /* DW = 0 32 bit data width */ /* DW = 1 64 bit data width */ /* WR = 0 read transaction */ /* WR = 1 write transaction */ /* transaction = 0 unlocked transaction */ /* transaction = 2 partial (masked) transaction */ /* */ /* Bit 31 of the mailbox command field is defined by the Alpha SRM to */ /* mean that the command is a write. This bit is not passed onto the */ /* Futurebus--it is intended as a performance assist for a local side */ /* module. */ /* */ #define FBUS$K_RDQUAD32 32 /* Read, unlocked, AW=32, DW=64 */ #define FBUS$K_RDLONG32 0 /* Read, unlocked, AW=32, DW=32 */ #define FBUS$K_RDWORD32 2 /* Read, partial, AW=32, DW=32 */ #define FBUS$K_RDBYTE32 2 /* Read, partial, AW=32, DW=32 */ #define FBUS$K_WTQUAD32 48 /* write, unlocked, AW=32, DW=64 */ #define FBUS$K_WTLONG32 16 /* write, unlocked, AW=32, DW=32 */ #define FBUS$K_WTWORD32 18 /* write, partial, AW=32, DW=32 */ #define FBUS$K_WTBYTE32 18 /* write, partial, AW=32, DW=32 */ #define FBUS$K_RDQUAD64 160 /* Read, unlocked, AW=64, DW=64 */ #define FBUS$K_RDLONG64 128 /* Read, unlocked, AW=64, DW=32 */ #define FBUS$K_RDWORD64 130 /* Read, partial, AW=64, DW=32 */ #define FBUS$K_RDBYTE64 130 /* Read, partial, AW=64, DW=32 */ #define FBUS$K_WTQUAD64 176 /* Write, unlocked, AW=64, DW=64 */ #define FBUS$K_WTLONG64 144 /* Write, unlocked, AW=64, DW=32 */ #define FBUS$K_WTWORD64 146 /* Write, partial, AW=64, DW=32 */ #define FBUS$K_WTBYTE64 146 /* Write, partial , AW=64, DW=32 */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __FBUSDEF_LOADED */