/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:25:08 by OpenVMS SDL EV3-3 */ /* Source: 11-MAY-1993 13:18:10 $1$DGA7274:[LIB_H.SRC]FBICDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $FBICDEF ***/ #ifndef __FBICDEF_LOADED #define __FBICDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*++ */ /* Define FBIC offsets and registers for Firefox systems */ /*-- */ #define FBIC$L_MODTYPE 508 /*Module type */ #define FBIC$L_BUSCSR 504 /*MBUS error status */ #define FBIC$L_BUSCTL 500 /*MBUS error control signal log */ #define FBIC$L_BUSADR 496 /*MBUS error address signal log */ #define FBIC$L_BUSDAT 492 /*MBUS error data signal log */ #define FBIC$L_FBICSR 488 /*FBIC CSR */ #define FBIC$L_RANGE 484 /*I/O Space range deco=e */ #define FBIC$L_IPDVINT 480 /*IP/Device interrupt */ #define FBIC$L_WHAMI 476 /*Unique software ID */ #define FBIC$L_CPUID 472 /*Unique hardware ID */ #define FBIC$L_IADR1 468 /*Interlock 1 address */ #define FBIC$L_IADR2 464 /*Interlock 2 address */ #define FBIC$L_SAVGPR 452 /*Scratch register */ #define FMDC$L_FMDCSR 488 /*FMDC CSR */ #define FMDC$L_BASEADDR 484 /*Memory space base address */ #define FMDC$L_ECCADDR0 480 /*ECC error address (QW0) */ #define FMDC$L_ECCADDR1 476 /*ECC error address (QW1) */ #define FMDC$L_ECCSYND0 472 /*ECC error status (QW0) */ #define FMDC$L_ECCSYND1 468 /*ECC error status (QW1) */ #define FMDC$L_MSECTERR 464 /*Memory section */ #define FMDC$L_MBUSSIG 460 /*MBUS control signature */ #define FMDC$L_DRAMSIG 456 /*DRAM control signature */ #define FMDC$L_SELFSIG 452 /*Self test signature */ #define FMDC$L_LEDLATCH 448 /*Diagnostic LED latch */ typedef struct _modtype { unsigned fbic$v_modtype_class : 8; /* Class of module */ unsigned fbic$v_modtype_subclass : 8; /* Low bit echoes TYPDUAL */ unsigned fbic$v_modtype_interface : 8; /* FBIC interface == 1 */ unsigned fbic$v_modtype_revision : 8; /* FBIC hardware revision */ } MODTYPE; #define KA60$K_MODTYPE_FBIC 1 /* 1 FBIC interface */ #define KA60$K_MODTYPE_FMDC 2 /* 2 FMDC interface */ #define KA60$K_MODTYPE_FMCM 254 #define FBIC$M_BUSCSR_DBLE 0x10000 #define FBIC$M_BUSCSR_SERR 0x20000 #define FBIC$M_BUSCSR_CTPE 0x40000 #define FBIC$M_BUSCSR_CDPE 0x80000 #define FBIC$M_BUSCSR_CTO 0x100000 #define FBIC$M_BUSCSR_NOS 0x200000 #define FBIC$M_BUSCSR_MTO 0x400000 #define FBIC$M_BUSCSR_ILCK 0x800000 #define FBIC$M_BUSCSR_MCPE 0x1000000 #define FBIC$M_BUSCSR_MSPE 0x2000000 #define FBIC$M_BUSCSR_MDPE 0x4000000 #define FBIC$M_BUSCSR_MTPE 0x8000000 #define FBIC$M_BUSCSR_IDAT 0x10000000 #define FBIC$M_BUSCSR_ICMD 0x20000000 #define FBIC$M_BUSCSR_ARB 0x40000000 #define FBIC$M_BUSCSR_FRZN 0x80000000 typedef struct _buscsr { unsigned fbic$v_buscsr_mbz : 16; unsigned fbic$v_buscsr_dble : 1; /*MBUS double error bit */ unsigned fbic$v_buscsr_serr : 1; /*SERR */ unsigned fbic$v_buscsr_ctpe : 1; /*CDAL tag store parity error */ unsigned fbic$v_buscsr_cdpe : 1; /*CDAL parity error */ unsigned fbic$v_buscsr_cto : 1; /*CDAL timeout */ unsigned fbic$v_buscsr_nos : 1; /*MBUS no slave response */ unsigned fbic$v_buscsr_mto : 1; /*MBUS slave timeout */ unsigned fbic$v_buscsr_ilck : 1; /*MBUS interlock violation */ unsigned fbic$v_buscsr_mcpe : 1; /*MBUS MCMD parity error */ unsigned fbic$v_buscsr_mspe : 1; /*MBUS MSTATUS parity error */ unsigned fbic$v_buscsr_mdpe : 1; /*MBUS MDAL parity error */ unsigned fbic$v_buscsr_mtpe : 1; /*MBUS tag parity error */ unsigned fbic$v_buscsr_idat : 1; /*MBUS invalid data supplied */ unsigned fbic$v_buscsr_icmd : 1; /*MBUS invalid MCMD encoding */ unsigned fbic$v_buscsr_arb : 1; /*MBUS arbitration error */ unsigned fbic$v_buscsr_frzn : 1; /*MBUS error logging frozen */ } BUSCSR; #define FBIC$M_BUSCTL_MBRM 0x7F #define FBIC$M_BUSCTL_MBRP 0x80 #define FBIC$M_BUSCTL_MBRQ 0x100 #define FBIC$M_BUSCTL_MCMD 0x1E00 #define FBIC$M_BUSCTL_MCPAR 0x2000 #define FBIC$M_BUSCTL_MSTATUS 0xC000 #define FBIC$M_BUSCTL_MSPAR 0x10000 #define FBIC$M_BUSCTL_MDPAR 0x20000 #define FBIC$M_BUSCTL_MBUSY 0x40000 #define FBIC$M_BUSCTL_MSHARED 0x80000 #define FBIC$M_BUSCTL_MDATINV 0x100000 #define FBIC$M_BUSCTL_MABORT 0x200000 #define FBIC$M_BUSCTL_MHALT 0x400000 #define FBIC$M_BUSCTL_PHASE 0x3800000 #define FBIC$M_BUSCTL_SLAVE 0x4000000 #define FBIC$M_BUSCTL_MASTER 0x8000000 #define FBIC$M_BUSCTL_SVDMCMD 0xF0000000 typedef struct _busctl { unsigned fbic$v_busctl_mbrm : 7; /* MBRM signals */ unsigned fbic$v_busctl_mbrp : 1; /* MBRP signal */ unsigned fbic$v_busctl_mbrq : 1; /* MBRQ signal */ unsigned fbic$v_busctl_mcmd : 4; /* MCMD signals */ unsigned fbic$v_busctl_mcpar : 1; /* MCPAR signal */ unsigned fbic$v_busctl_mstatus : 2; /* MSTATUS signal */ unsigned fbic$v_busctl_mspar : 1; /* MSPAR */ unsigned fbic$v_busctl_mdpar : 1; /* MDPAR */ unsigned fbic$v_busctl_mbusy : 1; /* MBUSY */ unsigned fbic$v_busctl_mshared : 1; /* MSHARED */ unsigned fbic$v_busctl_mdatinv : 1; /* MDATINV */ unsigned fbic$v_busctl_mabort : 1; /* MABORT */ unsigned fbic$v_busctl_mhalt : 1; /* MHALT */ unsigned fbic$v_busctl_phase : 3; /* BUS PHASE */ unsigned fbic$v_busctl_slave : 1; /* SLAVE */ unsigned fbic$v_busctl_master : 1; /* MASTER */ unsigned fbic$v_busctl_svdmcmd : 4; /* MCMD signal */ } BUSCTL; #define FBIC$M_FBICSR_CDPE 0x1 #define FBIC$M_FBICSR_TSTFNC 0x3E #define FBIC$M_FBICSR_HALTEN 0x80 #define FBIC$M_FBICSR_LEDS 0x3F00 #define FBIC$M_FBICSR_IRQC2M 0xF0000 #define FBIC$M_FBICSR_IRQEN 0xF00000 #define FBIC$M_FBICSR_RESET 0x1000000 #define FBIC$M_FBICSR_HALTCPU 0x2000000 #define FBIC$M_FBICSR_EXCAEN 0x4000000 #define FBIC$M_FBICSR_CMISS 0x8000000 #define FBIC$M_FBICSR_MFMD 0xC0000000 typedef struct _fbicsr { unsigned fbic$v_fbicsr_cdpe : 1; /*CBUS parity check enable */ unsigned fbic$v_fbicsr_tstfnc : 5; /*Diagnostic test function */ unsigned fbic$v_fbicsr_mbz0 : 1; /* Must be zero */ unsigned fbic$v_fbicsr_halten : 1; /*Enable CPU halts */ unsigned fbic$v_fbicsr_leds : 6; /*FBIC LED output */ unsigned fbic$v_fbicsr_mbz1 : 2; /* Must be zero */ unsigned fbic$v_fbicsr_irqc2m : 4; /*Interrupt request direction */ unsigned fbic$v_fbicsr_irqen : 4; /*Interrupt request enable */ unsigned fbic$v_fbicsr_reset : 1; /*CBUS RESET */ unsigned fbic$v_fbicsr_haltcpu : 1; /*CBUS halt control */ unsigned fbic$v_fbicsr_excaen : 1; /*External cache enable */ unsigned fbic$v_fbicsr_cmiss : 1; /*CBUS cache miss occurred */ unsigned fbic$v_fbicsr_mbz2 : 2; /* Must be zero */ unsigned fbic$v_fbicsr_mfmd : 2; /*Manufacturing mode */ } FBICSR; #define FBIC$M_RANGE_MASK 0x7FFF #define FBIC$M_RANGE_ENABLE 0x8000 #define FBIC$M_RANGE_MATCH 0xFFFF0000 typedef struct _range { unsigned fbic$v_range_mask : 15; /*I/O space address range mask */ unsigned fbic$v_range_enable : 1; /*I/O space address range enable */ unsigned fbic$v_range_match : 16; /*I/O space address range match */ } RANGE; #define FBIC$M_IPDVINT_VECTOR 0xFFFF #define FBIC$M_IPDVINT_DEVUNIT 0x10000 #define FBIC$M_IPDVINT_IPUNIT 0x20000 #define FBIC$M_IPDVINT_IPL14 0x1000000 #define FBIC$M_IPDVINT_IPL15 0x2000000 #define FBIC$M_IPDVINT_IPL16 0x4000000 #define FBIC$M_IPDVINT_IPL17 0x8000000 typedef struct _ipdvint { unsigned fbic$v_ipdvint_vector : 16; /*Interrupt vector */ unsigned fbic$v_ipdvint_devunit : 1; /*Device interrupt unit */ unsigned fbic$v_ipdvint_ipunit : 1; /*I/P interrupt unit */ unsigned fbic$v_ipdvint_mbz : 6; unsigned fbic$v_ipdvint_ipl14 : 1; /*Generate IPL 14 interrupt */ unsigned fbic$v_ipdvint_ipl15 : 1; /*Generate IPL 15 interrupt */ unsigned fbic$v_ipdvint_ipl16 : 1; /*Generate IPL 16 interrupt */ unsigned fbic$v_ipdvint_ipl17 : 1; /*Generate IPL 17 interrupt */ unsigned fbic$v_fill_0_ : 4; } IPDVINT; #define FBIC$M_CPUID_PROC 0x3 #define FBIC$M_CPUID_MID 0xC typedef struct _cpuid { unsigned fbic$v_cpuid_proc : 2; /*Processor identifier */ unsigned fbic$v_cpuid_mid : 2; /*Module slot identifier */ unsigned fbic$v_fill_1_ : 4; } CPUID; #define FMDC$M_FMDCSR_RAS_CNT 0xFF #define FMDC$M_FMDCSR_ST_START 0x100 #define FMDC$M_FMDCSR_ST_DONE 0x200 #define FMDC$M_FMDCSR_DTCB 0x400 #define FMDC$M_FMDCSR_DIS_REFRESH 0x1000 #define FMDC$M_FMDCSR_RPS 0x2000 #define FMDC$M_FMDCSR_DRS 0x4000 #define FMDC$M_FMDCSR_EDM 0x18000 #define FMDC$M_FMDCSR_FESC 0x60000 #define FMDC$M_FMDCSR_FEC 0x380000 #define FMDC$M_FMDCSR_ISR 0x400000 #define FMDC$M_FMDCSR_ISML 0x800000 #define FMDC$M_FMDCSR_MOL 0x40000000 #define FMDC$M_FMDCSR_EFS 0x80000000 typedef struct _fmdcsr { unsigned fmdc$v_fmdcsr_ras_cnt : 8; /* Refresh counter */ unsigned fmdc$v_fmdcsr_st_start : 1; /* Self test start */ unsigned fmdc$v_fmdcsr_st_done : 1; /* Self test complete */ unsigned fmdc$v_fmdcsr_dtcb : 1; /* Data to check bits */ unsigned fmdc$v_fmdcsr_mbz1 : 1; unsigned fmdc$v_fmdcsr_dis_refresh : 1; /* Disable refresh */ unsigned fmdc$v_fmdcsr_rps : 1; /* Refresh period select */ unsigned fmdc$v_fmdcsr_drs : 1; /* Diagnostic refresh start */ unsigned fmdc$v_fmdcsr_edm : 2; /* ECC diagnostic mode */ unsigned fmdc$v_fmdcsr_fesc : 2; /* Force error sub category */ unsigned fmdc$v_fmdcsr_fec : 3; /* Force error category */ unsigned fmdc$v_fmdcsr_isr : 1; /* Inhibit SBE reporting */ unsigned fmdc$v_fmdcsr_isml : 1; /* Inhibit SBE MSECTERR log */ unsigned fmdc$v_fmdcsr_mbz2 : 6; unsigned fmdc$v_fmdcsr_mol : 1; /* Module on-line */ unsigned fmdc$v_fmdcsr_efs : 1; /* Error flag summary */ } FMDCSR; #define FMDC$M_BASEADDR_STARTADDR 0x7FF00000 #define FMDC$M_BASEADDR_MEMSPEN 0x80000000 typedef struct _baseaddr { unsigned fmdc$v_baseaddr_mbz : 20; unsigned fmdc$v_baseaddr_startaddr : 11; /* Starting memory address */ unsigned fmdc$v_baseaddr_memspen : 1; /* Memory space enable */ } BASEADDR; #define FMDC$M_ECCADDR_RAMERRADDR0 0x7FFFFF0 typedef struct _eccaddr { unsigned fmdc$v_eccaddr_mbz : 4; unsigned fmdc$v_eccaddr_ramerraddr0 : 23; /* ECC Error address */ unsigned fmdc$v_fill_2_ : 5; } ECCADDR; #define FMDC$M_ECCSYND_SYND0 0xFF #define FMDC$M_ECCSYND_SBE 0x100 #define FMDC$M_ECCSYND_MBE 0x200 #define FMDC$M_ECCSYND_ERROVFL 0x1C00 #define FMDC$M_ECCSYND_SUBCB 0xFF0000 #define FMDC$M_ECCSYND_READCB 0xFF000000 typedef struct _eccsynd { unsigned fmdc$v_eccsynd_synd0 : 8; /* ECC syndronme */ unsigned fmdc$v_eccsynd_sbe : 1; /* Single bit error */ unsigned fmdc$v_eccsynd_mbe : 1; /* Multiple bit error */ unsigned fmdc$v_eccsynd_errovfl : 3; /* Error overflow field */ unsigned fmdc$v_eccsynd_mbz : 3; unsigned fmdc$v_eccsynd_subcb : 8; /* Substitute check bits */ unsigned fmdc$v_eccsynd_readcb : 8; /* Read check bits */ } ECCSYND; #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __FBICDEF_LOADED */