/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:25 by OpenVMS SDL EV3-3 */ /* Source: 13-APR-1996 16:32:46 $1$DGA7274:[LIB_H.SRC]EISABUSDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $EISABUSDEF ***/ #ifndef __EISABUSDEF_LOADED #define __EISABUSDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* This file describes the layout of EISA CSR space. It is based */ /* on the EISA spec, V3.10 BCPR Service, INC. */ /* */ #define EISA$M_PIC_L_ICW1_ICW4 0x1 #define EISA$M_PIC_L_ICW1_SNGL 0x2 #define EISA$M_PIC_L_OCW2_L0 0x1 #define EISA$M_PIC_L_OCW2_L1 0x2 #define EISA$M_PIC_L_OCW2_L2 0x4 #define EISA$M_PIC_L_OCW2_EOI 0x20 #define EISA$M_PIC_L_OCW2_SL 0x40 #define EISA$M_PIC_L_OCW2_R 0x80 #define EISA$M_PIC_L_OCW3_RIS 0x1 #define EISA$M_PIC_L_OCW3_RR 0x2 #define EISA$M_PIC_L_OCW3_P 0x4 #define EISA$M_PIC_L_OCW3_SMM 0x20 #define EISA$M_PIC_L_OCW3_ESMM 0x40 #define EISA$M_PIC_L_ICW2_ZEROES 0x7 #define EISA$M_PIC_L_ICW2_VEC 0xF8 #define EISA$M_PIC_L_ICW3_IRQ0_SLAVE 0x1 #define EISA$M_PIC_L_ICW3_IRQ1_SLAVE 0x2 #define EISA$M_PIC_L_ICW3_IRQ2_SLAVE 0x4 #define EISA$M_PIC_L_ICW3_IRQ3_SLAVE 0x8 #define EISA$M_PIC_L_ICW3_IRQ4_SLAVE 0x10 #define EISA$M_PIC_L_ICW3_IRQ5_SLAVE 0x20 #define EISA$M_PIC_L_ICW3_IRQ6_SLAVE 0x40 #define EISA$M_PIC_L_ICW3_IRQ7_SLAVE 0x80 #define EISA$M_PIC_L_ICW4_MODE 0x1 #define EISA$M_PIC_L_ICW4_AEOI 0x2 #define EISA$M_PIC_L_ICW4_BUFF 0x18 #define EISA$M_PIC_L_ICW4_NEST 0x20 #define EISA$M_PIC_L_OCW1_MASK 0xFF #define EISA$M_PIC_L_T1_SYSTIM_BCD 0x1 #define EISA$M_PIC_L_T1_SYSTIM_MODE 0xE #define EISA$M_PIC_L_T1_SYSTIM_RW 0x30 #define EISA$M_PIC_L_T1_SYSTIM_STAT 0x40 #define EISA$M_PIC_L_T1_SYSTIM_OUT 0x80 #define EISA$M_PIC_L_T1_REF_BCD 0x1 #define EISA$M_PIC_L_T1_REF_MODE 0xE #define EISA$M_PIC_L_T1_REF_RW 0x30 #define EISA$M_PIC_L_T1_REF_STAT 0x40 #define EISA$M_PIC_L_T1_REF_OUT 0x80 #define EISA$M_PIC_L_T1_SPKR_BCD 0x1 #define EISA$M_PIC_L_T1_SPKR_MODE 0xE #define EISA$M_PIC_L_T1_SPKR_RW 0x30 #define EISA$M_PIC_L_T1_SPKR_STAT 0x40 #define EISA$M_PIC_L_T1_SPKR_OUT 0x80 #define EISA$M_PIC_L_T1_CTRL_BCD 0x1 #define EISA$M_PIC_L_T1_CTRL_MODE 0xE #define EISA$M_PIC_L_T1_CTRL_CNTLAT 0x30 #define EISA$M_PIC_L_T1_CTRL_CNTSEL 0xC0 #define EISA$M_PIC_L_T2_FLSF_BCD 0x1 #define EISA$M_PIC_L_T2_FLSF_MODE 0xE #define EISA$M_PIC_L_T2_FLSF_RW 0x30 #define EISA$M_PIC_L_T2_FLSF_STAT 0x40 #define EISA$M_PIC_L_T2_FLSF_OUT 0x80 #define EISA$M_PIC_L_T2_CPUSPD_BCD 0x1 #define EISA$M_PIC_L_T2_CPUSPD_MODE 0xE #define EISA$M_PIC_L_T2_CPUSPD_RW 0x30 #define EISA$M_PIC_L_T2_CPUSPD_STAT 0x40 #define EISA$M_PIC_L_T2_CPUSPD_OUT 0x80 #define EISA$M_PIC_L_T2_CTRL_BCD 0x1 #define EISA$M_PIC_L_T2_CTRL_MODE 0xE #define EISA$M_PIC_L_T2_CTRL_CNTLAT 0x30 #define EISA$M_PIC_L_T2_CTRL_CNTSEL 0xC0 #define EISA$M_PIC_L_NMICSR_T1 0x1 #define EISA$M_PIC_L_NMICSR_SPKR 0x2 #define EISA$M_PIC_L_NMICSR_PE 0x4 #define EISA$M_PIC_L_NMICSR_IOCHK 0x8 #define EISA$M_PIC_L_NMICSR_REF 0x10 #define EISA$M_PIC_L_NMICSR_INTM1 0x20 #define EISA$M_PIC_L_NMICSR_NMIINT 0x40 #define EISA$M_PIC_L_NMICSR_PAR 0x80 #define EISA$M_PIC_L_NMIRTC_CLKADR 0x7F #define EISA$M_PIC_L_NMIRTC_ENDIS 0x80 #define EISA$M_PIC_H_ICW1_ICW4 0x1 #define EISA$M_PIC_H_ICW1_SNGL 0x2 #define EISA$M_PIC_H_OCW2_L0 0x1 #define EISA$M_PIC_H_OCW2_L1 0x2 #define EISA$M_PIC_H_OCW2_L2 0x4 #define EISA$M_PIC_H_OCW2_EOI 0x20 #define EISA$M_PIC_H_OCW2_SL 0x40 #define EISA$M_PIC_H_OCW2_R 0x80 #define EISA$M_PIC_H_OCW3_RIS 0x1 #define EISA$M_PIC_H_OCW3_RR 0x2 #define EISA$M_PIC_H_OCW3_P 0x4 #define EISA$M_PIC_H_OCW3_SMM 0x20 #define EISA$M_PIC_H_OCW3_ESMM 0x40 #define EISA$M_PIC_H_ICW2_ZEROES 0x7 #define EISA$M_PIC_H_ICW2_VEC 0xF8 #define EISA$M_PIC_H_ICW3_IRQ0_SLAVE 0x1 #define EISA$M_PIC_H_ICW3_IRQ1_SLAVE 0x2 #define EISA$M_PIC_H_ICW3_IRQ2_SLAVE 0x4 #define EISA$M_PIC_H_ICW3_IRQ3_SLAVE 0x8 #define EISA$M_PIC_H_ICW3_IRQ4_SLAVE 0x10 #define EISA$M_PIC_H_ICW3_IRQ5_SLAVE 0x20 #define EISA$M_PIC_H_ICW3_IRQ6_SLAVE 0x40 #define EISA$M_PIC_H_ICW3_IRQ7_SLAVE 0x80 #define EISA$M_PIC_H_ICW4_MODE 0x1 #define EISA$M_PIC_H_ICW4_AEOI 0x2 #define EISA$M_PIC_H_ICW4_BUFF 0x18 #define EISA$M_PIC_H_ICW4_NEST 0x20 #define EISA$M_PIC_H_OCW1_MASK 0xFF #define EISA$M_PIC_EXNMICSR_BUSRST 0x1 #define EISA$M_PIC_EXNMICSR_ENIO 0x2 #define EISA$M_PIC_EXNMICSR_FSEN 0x4 #define EISA$M_PIC_EXNMICSR_TOEN 0x8 #define EISA$M_PIC_EXNMICSR_IOP 0x20 #define EISA$M_PIC_EXNMICSR_BT 0x40 #define EISA$M_PIC_EXNMICSR_FSINT 0x80 #define EISA$M_PIC_EISA_BUSMAS_SL1 0x1 #define EISA$M_PIC_EISA_BUSMAS_SL2 0x2 #define EISA$M_PIC_EISA_BUSMAS_SL3 0x4 #define EISA$M_PIC_EISA_BUSMAS_SL4 0x8 #define EISA$M_PIC_EISA_BUSMAS_SL5 0x10 #define EISA$M_PIC_EISA_BUSMAS_SL6 0x20 #define EISA$M_PIC_EISA_BUSMAS_SL7 0x40 #define EISA$M_PIC_CTRL1_EDGE_INT3 0x8 #define EISA$M_PIC_CTRL1_EDGE_INT4 0x10 #define EISA$M_PIC_CTRL1_EDGE_INT5 0x20 #define EISA$M_PIC_CTRL1_EDGE_INT6 0x40 #define EISA$M_PIC_CTRL1_EDGE_INT7 0x80 #define EISA$M_PIC_CTRL2_EDGE_INT9 0x2 #define EISA$M_PIC_CTRL2_EDGE_INT10 0x4 #define EISA$M_PIC_CTRL2_EDGE_INT11 0x8 #define EISA$M_PIC_CTRL2_EDGE_INT12 0x10 #define EISA$M_PIC_CTRL2_EDGE_INT14 0x40 #define EISA$M_PIC_CTRL2_EDGE_INT15 0x80 #define EISA$M_SLOT1_PID_CHAR2 0x3 #define EISA$M_SLOT1_PID_CHAR1 0x7C #define EISA$M_SLOT1_PID_CHAR3 0x1F00 #define EISA$M_SLOT1_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT1_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT1_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT1_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT1_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT2_PID_CHAR2 0x3 #define EISA$M_SLOT2_PID_CHAR1 0x7C #define EISA$M_SLOT2_PID_CHAR3 0x1F00 #define EISA$M_SLOT2_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT2_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT2_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT2_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT2_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT3_PID_CHAR2 0x3 #define EISA$M_SLOT3_PID_CHAR1 0x7C #define EISA$M_SLOT3_PID_CHAR3 0x1F00 #define EISA$M_SLOT3_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT3_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT3_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT3_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT3_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT4_PID_CHAR2 0x3 #define EISA$M_SLOT4_PID_CHAR1 0x7C #define EISA$M_SLOT4_PID_CHAR3 0x1F00 #define EISA$M_SLOT4_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT4_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT4_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT4_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT4_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT5_PID_CHAR2 0x3 #define EISA$M_SLOT5_PID_CHAR1 0x7C #define EISA$M_SLOT5_PID_CHAR3 0x1F00 #define EISA$M_SLOT5_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT5_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT5_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT5_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT5_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT6_PID_CHAR2 0x3 #define EISA$M_SLOT6_PID_CHAR1 0x7C #define EISA$M_SLOT6_PID_CHAR3 0x1F00 #define EISA$M_SLOT6_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT6_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT6_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT6_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT6_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT7_PID_CHAR2 0x3 #define EISA$M_SLOT7_PID_CHAR1 0x7C #define EISA$M_SLOT7_PID_CHAR3 0x1F00 #define EISA$M_SLOT7_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT7_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT7_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT7_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT7_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT8_PID_CHAR2 0x3 #define EISA$M_SLOT8_PID_CHAR1 0x7C #define EISA$M_SLOT8_PID_CHAR3 0x1F00 #define EISA$M_SLOT8_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT8_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT8_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT8_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT8_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT9_PID_CHAR2 0x3 #define EISA$M_SLOT9_PID_CHAR1 0x7C #define EISA$M_SLOT9_PID_CHAR3 0x1F00 #define EISA$M_SLOT9_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT9_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT9_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT9_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT9_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT10_PID_CHAR2 0x3 #define EISA$M_SLOT10_PID_CHAR1 0x7C #define EISA$M_SLOT10_PID_CHAR3 0x1F00 #define EISA$M_SLOT10_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT10_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT10_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT10_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT10_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT11_PID_CHAR2 0x3 #define EISA$M_SLOT11_PID_CHAR1 0x7C #define EISA$M_SLOT11_PID_CHAR3 0x1F00 #define EISA$M_SLOT11_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT11_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT11_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT11_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT11_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT12_PID_CHAR2 0x3 #define EISA$M_SLOT12_PID_CHAR1 0x7C #define EISA$M_SLOT12_PID_CHAR3 0x1F00 #define EISA$M_SLOT12_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT12_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT12_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT12_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT12_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT13_PID_CHAR2 0x3 #define EISA$M_SLOT13_PID_CHAR1 0x7C #define EISA$M_SLOT13_PID_CHAR3 0x1F00 #define EISA$M_SLOT13_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT13_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT13_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT13_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT13_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT14_PID_CHAR2 0x3 #define EISA$M_SLOT14_PID_CHAR1 0x7C #define EISA$M_SLOT14_PID_CHAR3 0x1F00 #define EISA$M_SLOT14_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT14_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT14_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT14_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT14_PID_PROD_NUM3 0xF0000000 #define EISA$M_SLOT15_PID_CHAR2 0x3 #define EISA$M_SLOT15_PID_CHAR1 0x7C #define EISA$M_SLOT15_PID_CHAR3 0x1F00 #define EISA$M_SLOT15_PID_CHAR2_CONT 0xE000 #define EISA$M_SLOT15_PID_PROD_NUM1 0xF0000 #define EISA$M_SLOT15_PID_PROD_NUM2 0xF00000 #define EISA$M_SLOT15_PID_REV_NUM1 0xF000000 #define EISA$M_SLOT15_PID_PROD_NUM3 0xF0000000 #define EISA$K_NODE_SPACE_LENGTH 131072 #define EISA$S_EISABUSDEF 131072 /* Old size name - synonym */ typedef struct _eisabus { __union { unsigned char eisa$b_dma1_ch0_base_addr; } eisa$r_dma1_ch0_base_addr_overlay; __union { unsigned char eisa$b_dma1_ch0_base_cnt; } eisa$r_dma1_ch0_base_cnt_overlay; __union { unsigned char eisa$b_dma1_ch1_base_addr; } eisa$r_dma1_ch1_base_addr_overlay; __union { unsigned char eisa$b_dma1_ch1_base_cnt; } eisa$r_dma1_ch1_base_cnt_overlay; __union { unsigned char eisa$b_dma1_ch2_base_addr; } eisa$r_dma1_ch2_base_addr_overlay; __union { unsigned char eisa$b_dma1_ch2_base_cnt; } eisa$r_dma1_ch2_base_cnt_overlay; __union { unsigned char eisa$b_dma1_ch3_base_addr; } eisa$r_dma1_ch3_base_addr_overlay; __union { unsigned char eisa$b_dma1_ch3_base_cnt; } eisa$r_dma1_ch3_base_cnt_overlay; __union { unsigned char eisa$b_dma1_stat_cmd; } eisa$r_dma1_stat_cmd_overlay; __union { unsigned char eisa$b_dma1_wrreq; } eisa$r_dma1_wrreq_overlay; __union { unsigned char eisa$b_dma1_wrmask; } eisa$r_dma1_wrmask_overlay; __union { unsigned char eisa$b_dma1_wrmode; } eisa$r_dma1_wrmode_overlay; __union { unsigned char eisa$b_dma1_clrbyt; } eisa$r_dma1_clrbyt_overlay; __union { unsigned char eisa$b_dma1_master_clr; } eisa$r_dma1_master_clr_overlay; __union { unsigned char eisa$b_dma1_clr_mask; } eisa$r_dma1_clr_mask_overlay; __union { unsigned char eisa$b_dma1_mask_reg; } eisa$r_dma1_mask_reg_overlay; char eisa$b_fill4 [16]; __union { unsigned char eisa$b_pic_l_icw1; __struct { unsigned eisa$v_pic_l_icw1_icw4 : 1; unsigned eisa$v_pic_l_icw1_sngl : 1; unsigned eisa$v_pic_l_icw1_fill1 : 6; } eisa$r_pic_l_icw1_bits; __struct { unsigned eisa$v_pic_l_ocw2_l0 : 1; unsigned eisa$v_pic_l_ocw2_l1 : 1; unsigned eisa$v_pic_l_ocw2_l2 : 1; unsigned eisa$v_pic_l_ocw2_fill1 : 2; unsigned eisa$v_pic_l_ocw2_eoi : 1; unsigned eisa$v_pic_l_ocw2_sl : 1; unsigned eisa$v_pic_l_ocw2_r : 1; } eisa$r_pic_l_ocw2_bits; __struct { unsigned eisa$v_pic_l_ocw3_ris : 1; unsigned eisa$v_pic_l_ocw3_rr : 1; unsigned eisa$v_pic_l_ocw3_p : 1; unsigned eisa$v_pic_l_ocw3_fill1 : 2; unsigned eisa$v_pic_l_ocw3_smm : 1; unsigned eisa$v_pic_l_ocw3_esmm : 1; unsigned eisa$v_pic_l_ocw3_fill2 : 1; } eisa$r_pic_l_ocw3_bits; } eisa$r_pic_l_icw1_ocw23_overlay; __union { unsigned char eisa$b_pic_l_icw2; __struct { unsigned eisa$v_pic_l_icw2_zeroes : 3; unsigned eisa$v_pic_l_icw2_vec : 5; } eisa$r_pic_l_icw2_bits; __struct { unsigned eisa$v_pic_l_icw3_irq0_slave : 1; unsigned eisa$v_pic_l_icw3_irq1_slave : 1; unsigned eisa$v_pic_l_icw3_irq2_slave : 1; unsigned eisa$v_pic_l_icw3_irq3_slave : 1; unsigned eisa$v_pic_l_icw3_irq4_slave : 1; unsigned eisa$v_pic_l_icw3_irq5_slave : 1; unsigned eisa$v_pic_l_icw3_irq6_slave : 1; unsigned eisa$v_pic_l_icw3_irq7_slave : 1; } eisa$r_pic_l_icw3_bits; __struct { unsigned eisa$v_pic_l_icw4_mode : 1; unsigned eisa$v_pic_l_icw4_aeoi : 1; unsigned eisa$v_pic_l_icw4_fill1 : 1; unsigned eisa$v_pic_l_icw4_buff : 2; unsigned eisa$v_pic_l_icw4_nest : 1; unsigned eisa$v_pic_l_icw4_fill2 : 3; unsigned eisa$v_fill_0_ : 7; } eisa$r_pic_l_icw4_bits; __struct { unsigned eisa$v_pic_l_ocw1_mask : 8; } eisa$r_pic_l_ocw1_bits; } eisa$r_pic_l_icw234_ocw1_overlay; char eisa$b_fill5 [29]; __union { unsigned char eisa$b_pic_l_t1_systim; __struct { unsigned eisa$v_pic_l_t1_systim_bcd : 1; unsigned eisa$v_pic_l_t1_systim_mode : 3; unsigned eisa$v_pic_l_t1_systim_rw : 2; unsigned eisa$v_pic_l_t1_systim_stat : 1; unsigned eisa$v_pic_l_t1_systim_out : 1; } eisa$r_pic_l_t1_systim_bits; } eisa$r_pic_l_t1_systim_overlay; __union { unsigned char eisa$b_pic_l_t1_ref; __struct { unsigned eisa$v_pic_l_t1_ref_bcd : 1; unsigned eisa$v_pic_l_t1_ref_mode : 3; unsigned eisa$v_pic_l_t1_ref_rw : 2; unsigned eisa$v_pic_l_t1_ref_stat : 1; unsigned eisa$v_pic_l_t1_ref_out : 1; } eisa$r_pic_l_t1_ref_bits; } eisa$r_pic_l_t1_ref_overlay; __union { unsigned char eisa$b_pic_l_t1_spkr; __struct { unsigned eisa$v_pic_l_t1_spkr_bcd : 1; unsigned eisa$v_pic_l_t1_spkr_mode : 3; unsigned eisa$v_pic_l_t1_spkr_rw : 2; unsigned eisa$v_pic_l_t1_spkr_stat : 1; unsigned eisa$v_pic_l_t1_spkr_out : 1; } eisa$r_pic_l_t1_spkr_bits; } eisa$r_pic_l_t1_spkr_overlay; __union { unsigned char eisa$b_pic_l_t1_ctrl; __struct { unsigned eisa$v_pic_l_t1_ctrl_bcd : 1; unsigned eisa$v_pic_l_t1_ctrl_mode : 3; unsigned eisa$v_pic_l_t1_ctrl_cntlat : 2; unsigned eisa$v_pic_l_t1_ctrl_cntsel : 2; } eisa$r_pic_l_t1_ctrl_bits; } eisa$r_pic_l_t1_ctrl_overlay; char eisa$b_fill6 [4]; __union { unsigned char eisa$b_pic_l_t2_flsf; __struct { unsigned eisa$v_pic_l_t2_flsf_bcd : 1; unsigned eisa$v_pic_l_t2_flsf_mode : 3; unsigned eisa$v_pic_l_t2_flsf_rw : 2; unsigned eisa$v_pic_l_t2_flsf_stat : 1; unsigned eisa$v_pic_l_t2_flsf_out : 1; } eisa$r_pic_l_t2_flsf_bits; } eisa$r_pic_l_t2_flsf_overlay; char eisa$b_fill7 [1]; __union { unsigned char eisa$b_pic_l_t2_cpuspd; __struct { unsigned eisa$v_pic_l_t2_cpuspd_bcd : 1; unsigned eisa$v_pic_l_t2_cpuspd_mode : 3; unsigned eisa$v_pic_l_t2_cpuspd_rw : 2; unsigned eisa$v_pic_l_t2_cpuspd_stat : 1; unsigned eisa$v_pic_l_t2_cpuspd_out : 1; } eisa$r_pic_l_t2_cpuspd_bits; } eisa$r_pic_l_t2_cpuspd_overlay; __union { unsigned char eisa$b_pic_l_t2_ctrl; __struct { unsigned eisa$v_pic_l_t2_ctrl_bcd : 1; unsigned eisa$v_pic_l_t2_ctrl_mode : 3; unsigned eisa$v_pic_l_t2_ctrl_cntlat : 2; unsigned eisa$v_pic_l_t2_ctrl_cntsel : 2; } eisa$r_pic_l_t2_ctrl_bits; } eisa$r_pic_l_t2_ctrl_overlay; char eisa$b_fill8 [21]; __union { unsigned char eisa$b_pic_l_nmicsr; __struct { unsigned eisa$v_pic_l_nmicsr_t1 : 1; unsigned eisa$v_pic_l_nmicsr_spkr : 1; unsigned eisa$v_pic_l_nmicsr_pe : 1; unsigned eisa$v_pic_l_nmicsr_iochk : 1; unsigned eisa$v_pic_l_nmicsr_ref : 1; unsigned eisa$v_pic_l_nmicsr_intm1 : 1; unsigned eisa$v_pic_l_nmicsr_nmiint : 1; unsigned eisa$v_pic_l_nmicsr_par : 1; } eisa$r_pic_l_nmicsr_bits; } eisa$r_pic_l_nmicsr_overlay; char eisa$b_fill9 [14]; __union { unsigned char eisa$b_pic_l_nmirtc; __struct { unsigned eisa$v_pic_l_nmirtc_clkadr : 7; unsigned eisa$v_pic_l_nmirtc_endis : 1; } eisa$r_pic_l_nmirtc_bits; } eisa$r_pic_l_nmirtc_overlay; char eisa$b_fill10 [16]; __union { unsigned char eisa$b_dma_page_ch2; } eisa$r_dma_page_ch2_overlay; __union { unsigned char eisa$b_dma_page_ch3; } eisa$r_dma_page_ch3_overlay; __union { unsigned char eisa$b_dma_page_ch1; } eisa$r_dma_page_ch1_overlay; char eisa$b_fill10a [3]; __union { unsigned char eisa$b_dma_page_ch0; } eisa$r_dma_page_ch0_overlay; char eisa$b_fill10b [1]; __union { unsigned char eisa$b_dma_page_ch6; } eisa$r_dma_page_ch6_overlay; __union { unsigned char eisa$b_dma_page_ch7; } eisa$r_dma_page_ch7_overlay; __union { unsigned char eisa$b_dma_page_ch5; } eisa$r_dma_page_ch5_overlay; char eisa$b_fill10c [3]; __union { unsigned char eisa$b_dma_page_ref; } eisa$r_dma_page_ref_overlay; char eisa$b_fill10d [16]; __union { unsigned char eisa$b_pic_h_icw1; __struct { unsigned eisa$v_pic_h_icw1_icw4 : 1; unsigned eisa$v_pic_h_icw1_sngl : 1; unsigned eisa$v_pic_h_icw1_fill1 : 5; unsigned eisa$v_fill_1_ : 1; } eisa$r_pic_h_icw1_bits; __struct { unsigned eisa$v_pic_h_ocw2_l0 : 1; unsigned eisa$v_pic_h_ocw2_l1 : 1; unsigned eisa$v_pic_h_ocw2_l2 : 1; unsigned eisa$v_pic_h_ocw2_fill1 : 2; unsigned eisa$v_pic_h_ocw2_eoi : 1; unsigned eisa$v_pic_h_ocw2_sl : 1; unsigned eisa$v_pic_h_ocw2_r : 1; } eisa$r_pic_h_ocw2_bits; __struct { unsigned eisa$v_pic_h_ocw3_ris : 1; unsigned eisa$v_pic_h_ocw3_rr : 1; unsigned eisa$v_pic_h_ocw3_p : 1; unsigned eisa$v_pic_h_ocw3_fill1 : 2; unsigned eisa$v_pic_h_ocw3_smm : 1; unsigned eisa$v_pic_h_ocw3_esmm : 1; unsigned eisa$v_pic_h_ocw3_fill2 : 1; } eisa$r_pic_h_ocw3_bits; } eisa$r_pic_h_icw1_ocw23_overlay; __union { unsigned char eisa$b_pic_h_icw2; __struct { unsigned eisa$v_pic_h_icw2_zeroes : 3; unsigned eisa$v_pic_h_icw2_vec : 5; } eisa$r_pic_h_icw2_bits; __struct { unsigned eisa$v_pic_h_icw3_irq0_slave : 1; unsigned eisa$v_pic_h_icw3_irq1_slave : 1; unsigned eisa$v_pic_h_icw3_irq2_slave : 1; unsigned eisa$v_pic_h_icw3_irq3_slave : 1; unsigned eisa$v_pic_h_icw3_irq4_slave : 1; unsigned eisa$v_pic_h_icw3_irq5_slave : 1; unsigned eisa$v_pic_h_icw3_irq6_slave : 1; unsigned eisa$v_pic_h_icw3_irq7_slave : 1; } eisa$r_pic_h_icw3_bits; __struct { unsigned eisa$v_pic_h_icw4_mode : 1; unsigned eisa$v_pic_h_icw4_aeoi : 1; unsigned eisa$v_pic_h_icw4_fill1 : 1; unsigned eisa$v_pic_h_icw4_buff : 2; unsigned eisa$v_pic_h_icw4_nest : 1; unsigned eisa$v_pic_h_icw4_fill2 : 2; } eisa$r_pic_h_icw4_bits; __struct { unsigned eisa$v_pic_h_ocw1_mask : 8; } eisa$r_pic_h_ocw1_bits; } eisa$r_pic_h_icw234_ocw1_overlay; char eisa$b_fill10e [30]; __union { unsigned char eisa$b_dma2_ch0_base_addr; } eisa$r_dma2_ch0_base_addr_overlay; char eisa$b_fill010 [1]; __union { unsigned char eisa$b_dma2_ch0_base_cnt; } eisa$r_dma2_ch0_base_cnt_overlay; char eisa$b_fill010a [1]; __union { unsigned char eisa$b_dma2_ch1_base_addr; } eisa$r_dma2_ch1_base_addr_overlay; char eisa$b_fill010b [1]; __union { unsigned char eisa$b_dma2_ch1_base_cnt; } eisa$r_dma2_ch1_base_cnt_overlay; char eisa$b_fill110 [1]; __union { unsigned char eisa$b_dma2_ch2_base_addr; } eisa$r_dma2_ch2_base_addr_overlay; char eisa$b_fill210 [1]; __union { unsigned char eisa$b_dma2_ch2_base_cnt; } eisa$r_dma2_ch2_base_cnt_overlay; char eisa$b_fill210a [1]; __union { unsigned char eisa$b_dma2_ch3_base_addr; } eisa$r_dma2_ch3_base_addr_overlay; char eisa$b_fill310 [1]; __union { unsigned char eisa$b_dma2_ch3_base_cnt; } eisa$r_dma2_ch3_base_cnt_overlay; char eisa$b_fill310a [1]; __union { unsigned char eisa$b_dma2_stat_wr; } eisa$r_dma2_stat_wr_overlay; char eisa$b_fill410 [1]; __union { unsigned char eisa$b_dma2_wr_req; } eisa$r_dma2_wr_req_overlay; char eisa$b_fill410a [1]; __union { unsigned char eisa$b_dma2_smask; } eisa$r_dma2_wr_smask_overlay; char eisa$b_fill410b [1]; __union { unsigned char eisa$b_dma2_wrmode; } eisa$r_dma2_wrmode_overlay; char eisa$b_fill510 [1]; __union { unsigned char eisa$b_dma2_clrbyt; } eisa$r_dma2_clrbyt_overlay; char eisa$b_fill610 [1]; __union { unsigned char eisa$b_dma2_master_clr; } eisa$r_dma2_master_clr_overlay; char eisa$b_fill710 [1]; __union { unsigned char eisa$b_dma2_clr_mask; } eisa$r_dma2_clr_mask_overlay; char eisa$b_fill810 [1]; __union { unsigned char eisa$b_dma2_mask_reg; } eisa$r_dma2_mask_reg_overlay; char eisa$b_fill910 [802]; __union { unsigned char eisa$b_dma1_ch0_cnt; } eisa$r_dma1_ch0_cnt_overlay; char eisa$b_fillabc [1]; __union { unsigned char eisa$b_dma1_ch1_cnt; } eisa$r_dma1_ch1_cnt_overlay; char eisa$b_fillabc1 [1]; __union { unsigned char eisa$b_dma1_ch2_cnt; } eisa$r_dma1_ch2_cnt_overlay; char eisa$b_fillabc2 [1]; __union { unsigned char eisa$b_dma1_ch3_cnt; } eisa$r_dma1_ch3_cnt_overlay; char eisa$b_fillabc21 [2]; __union { unsigned char eisa$b_dma1_chn_mode; } eisa$r_dma1_chn_mode_overlay; __union { unsigned char eisa$b_dma1_wrt_mode; } eisa$r_dma1_wrt_mode_overlay; __union { unsigned char eisa$b_dma1_buf_ctrl; } eisa$r_dma1_buf_ctrl_overlay; __union { unsigned char eisa$b_dma1_stp_lvl; } eisa$r_dma1_stp_lvl_overlay; char eisa$b_fillabc3 [83]; __union { unsigned char eisa$b_pic_exnmicsr; __struct { unsigned eisa$v_pic_exnmicsr_busrst : 1; unsigned eisa$v_pic_exnmicsr_enio : 1; unsigned eisa$v_pic_exnmicsr_fsen : 1; unsigned eisa$v_pic_exnmicsr_toen : 1; unsigned eisa$v_pic_fill1 : 1; unsigned eisa$v_pic_exnmicsr_iop : 1; unsigned eisa$v_pic_exnmicsr_bt : 1; unsigned eisa$v_pic_exnmicsr_fsint : 1; } eisa$r_pic_exnmicsr_bits; } eisa$r_pic_exnmicsr_overlay; __union { unsigned char eisa$b_pic_nmigen; } eisa$r_pic_nmigen_overlay; char eisa$b_fill11 [1]; __union { unsigned char eisa$b_pic_eisa_busmas; __struct { unsigned eisa$v_pic_eisa_busmas_sl1 : 1; unsigned eisa$v_pic_eisa_busmas_sl2 : 1; unsigned eisa$v_pic_eisa_busmas_sl3 : 1; unsigned eisa$v_pic_eisa_busmas_sl4 : 1; unsigned eisa$v_pic_eisa_busmas_sl5 : 1; unsigned eisa$v_pic_eisa_busmas_sl6 : 1; unsigned eisa$v_pic_eisa_busmas_sl7 : 1; unsigned eisa$v_fill_2_ : 1; } eisa$r_pic_eisa_busmas_bits; } eisa$r_pic_eisa_busmas_overlay; char eisa$b_fill12 [28]; __union { unsigned char eisa$b_dma_ch2_page_high; } eisa$r_dma_ch2_page_high_overlay; __union { unsigned char eisa$b_dma_ch3_page_high; } eisa$r_dma_ch3_page_high_overlay; __union { unsigned char eisa$b_dma_ch1_page_high; } eisa$r_dma_ch1_page_high_overlay; char eisa$b_fill12a [3]; __union { unsigned char eisa$b_dma_ch0_page_high; } eisa$r_dma_ch0_page_high_overlay; char eisa$b_fill12b [1]; __union { unsigned char eisa$b_dma_ch6_page_high; } eisa$r_dma_ch6_page_high_overlay; __union { unsigned char eisa$b_dma_ch7_page_high; } eisa$r_dma_ch7_page_high_overlay; __union { unsigned char eisa$b_dma_ch5_page_high; } eisa$r_dma_ch5_page_high_overlay; char eisa$b_fill12c [3]; __union { unsigned char eisa$b_dma_reg_ref_high; } eisa$r_dma_reg_ref_high_overlay; char eisa$b_fill12d [54]; __union { unsigned char eisa$b_dma2_ch5_cnt; } eisa$r_dma2_ch5_cnt_overlay; char eisa$b_fill12e [3]; __union { unsigned char eisa$b_dma2_ch6_cnt; } eisa$r_dma2_ch6_cnt_overlay; char eisa$b_fill12e1 [3]; __union { unsigned char eisa$b_dma2_ch7_cnt; } eisa$r_dma2_ch7_cnt_overlay; char eisa$b_fill12f [1]; __union { unsigned char eisa$b_pic_ctrl1_edge; __struct { unsigned eisa$v_pic_ctrl1_edge_fill1 : 3; unsigned eisa$v_pic_ctrl1_edge_int3 : 1; unsigned eisa$v_pic_ctrl1_edge_int4 : 1; unsigned eisa$v_pic_ctrl1_edge_int5 : 1; unsigned eisa$v_pic_ctrl1_edge_int6 : 1; unsigned eisa$v_pic_ctrl1_edge_int7 : 1; } eisa$r_pic_ctrl1_edge_bits; } eisa$r_pic_ctrl1_edge_overlay; __union { unsigned char eisa$b_pic_ctrl2_edge; __struct { unsigned eisa$v_pic_ctrl2_edge_fill1 : 1; unsigned eisa$v_pic_ctrl2_edge_int9 : 1; unsigned eisa$v_pic_ctrl2_edge_int10 : 1; unsigned eisa$v_pic_ctrl2_edge_int11 : 1; unsigned eisa$v_pic_ctrl2_edge_int12 : 1; unsigned eisa$v_pic_ctrl2_edge_fill2 : 1; unsigned eisa$v_pic_ctrl2_edge_int14 : 1; unsigned eisa$v_pic_ctrl2_edge_int15 : 1; } eisa$r_pic_ctrl2_edge_bits; } eisa$r_pic_ctrl2_edge_overlay; char eisa$b_fill13 [2]; __union { unsigned char eisa$b_dma2_chn_mode; } eisa$r_dma2_chn_mode_overlay; char eisa$b_fill13a [1]; __union { unsigned char eisa$b_dma2_wrt_mode; } eisa$r_dma2_wrt_mode_overlay; char eisa$b_fill13b [9]; __union { unsigned char eisa$b_dma_ch0_srb7_2; } eisa$r_dma_ch0_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch0_srb15_8; } eisa$r_dma_ch0_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch0_srb23_16; } eisa$r_dma_ch0_srb23_16_overlay; char eisa$b_fill13c [1]; __union { unsigned char eisa$b_dma_ch1_srb7_2; } eisa$r_dma_ch1_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch1_srb15_8; } eisa$r_dma_ch1_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch1_srb23_16; } eisa$r_dma_ch1_srb23_16_overlay; char eisa$b_fill13d [1]; __union { unsigned char eisa$b_dma_ch2_srb7_2; } eisa$r_dma_ch2_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch2_srb15_8; } eisa$r_dma_ch2_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch2_srb23_16; } eisa$r_dma_ch2_srb23_16_overlay; char eisa$b_fill13e [1]; __union { unsigned char eisa$b_dma_ch3_srb7_2; } eisa$r_dma_ch3_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch3_srb15_8; } eisa$r_dma_ch3_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch3_srb23_16; } eisa$r_dma_ch3_srb23_16_overlay; char eisa$b_fill13f [5]; __union { unsigned char eisa$b_dma_ch5_srb7_2; } eisa$r_dma_ch5_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch5_srb15_8; } eisa$r_dma_ch5_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch5_srb23_16; } eisa$r_dma_ch5_srb23_16_overlay; char eisa$b_fill13f1 [1]; __union { unsigned char eisa$b_dma_ch6_srb7_2; } eisa$r_dma_ch6_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch6_srb15_8; } eisa$r_dma_ch6_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch6_srb23_16; } eisa$r_dma_ch6_srb23_16_overlay; char eisa$b_fill13f2 [1]; __union { unsigned char eisa$b_dma_ch7_srb7_2; } eisa$r_dma_ch7_srb7_2_overlay; __union { unsigned char eisa$b_dma_ch7_srb15_8; } eisa$r_dma_ch7_srb15_8_overlay; __union { unsigned char eisa$b_dma_ch7_srb23_16; } eisa$r_dma_ch7_srb23_16_overlay; char eisa$b_fill13g [6913]; unsigned char eisa$b_slot1_base; char eisa$b_fill14 [3199]; __union { unsigned int eisa$l_slot1_pid; __struct { unsigned eisa$v_slot1_pid_char2 : 2; unsigned eisa$v_slot1_pid_char1 : 5; unsigned eisa$v_slot1_pid_fill1 : 1; unsigned eisa$v_slot1_pid_char3 : 5; unsigned eisa$v_slot1_pid_char2_cont : 3; unsigned eisa$v_slot1_pid_prod_num1 : 4; unsigned eisa$v_slot1_pid_prod_num2 : 4; unsigned eisa$v_slot1_pid_rev_num1 : 4; unsigned eisa$v_slot1_pid_prod_num3 : 4; } eisa$r_slot1_pid_bits; } eisa$r_slot1_pid_overlay; char eisa$b_fill14a [4988]; unsigned char eisa$b_slot2_base; char eisa$b_fill15 [3199]; __union { unsigned int eisa$l_slot2_pid; __struct { unsigned eisa$v_slot2_pid_char2 : 2; unsigned eisa$v_slot2_pid_char1 : 5; unsigned eisa$v_slot2_pid_fill1 : 1; unsigned eisa$v_slot2_pid_char3 : 5; unsigned eisa$v_slot2_pid_char2_cont : 3; unsigned eisa$v_slot2_pid_prod_num1 : 4; unsigned eisa$v_slot2_pid_prod_num2 : 4; unsigned eisa$v_slot2_pid_rev_num1 : 4; unsigned eisa$v_slot2_pid_prod_num3 : 4; } eisa$r_slot2_pid_bits; } eisa$r_slot2_pid_overlay; char eisa$b_fill15a [4988]; unsigned char eisa$b_slot3_base; char eisa$b_fill16 [3199]; __union { unsigned int eisa$l_slot3_pid; __struct { unsigned eisa$v_slot3_pid_char2 : 2; unsigned eisa$v_slot3_pid_char1 : 5; unsigned eisa$v_slot3_pid_fill1 : 1; unsigned eisa$v_slot3_pid_char3 : 5; unsigned eisa$v_slot3_pid_char2_cont : 3; unsigned eisa$v_slot3_pid_prod_num1 : 4; unsigned eisa$v_slot3_pid_prod_num2 : 4; unsigned eisa$v_slot3_pid_rev_num1 : 4; unsigned eisa$v_slot3_pid_prod_num3 : 4; } eisa$r_slot3_pid_bits; } eisa$r_slot3_pid_overlay; char eisa$b_fill16a [4988]; unsigned char eisa$b_slot4_base; char eisa$b_fill17 [3199]; __union { unsigned int eisa$l_slot4_pid; __struct { unsigned eisa$v_slot4_pid_char2 : 2; unsigned eisa$v_slot4_pid_char1 : 5; unsigned eisa$v_slot4_pid_fill1 : 1; unsigned eisa$v_slot4_pid_char3 : 5; unsigned eisa$v_slot4_pid_char2_cont : 3; unsigned eisa$v_slot4_pid_prod_num1 : 4; unsigned eisa$v_slot4_pid_prod_num2 : 4; unsigned eisa$v_slot4_pid_rev_num1 : 4; unsigned eisa$v_slot4_pid_prod_num3 : 4; } eisa$r_slot4_pid_bits; } eisa$r_slot4_pid_overlay; char eisa$b_fill17a [4988]; unsigned char eisa$b_slot5_base; char eisa$b_fill18 [3199]; __union { unsigned int eisa$l_slot5_pid; __struct { unsigned eisa$v_slot5_pid_char2 : 2; unsigned eisa$v_slot5_pid_char1 : 5; unsigned eisa$v_slot5_pid_fill1 : 1; unsigned eisa$v_slot5_pid_char3 : 5; unsigned eisa$v_slot5_pid_char2_cont : 3; unsigned eisa$v_slot5_pid_prod_num1 : 4; unsigned eisa$v_slot5_pid_prod_num2 : 4; unsigned eisa$v_slot5_pid_rev_num1 : 4; unsigned eisa$v_slot5_pid_prod_num3 : 4; } eisa$r_slot5_pid_bits; } eisa$r_slot5_pid_overlay; char eisa$b_fill18a [4988]; unsigned char eisa$b_slot6_base; char eisa$b_fill19 [3199]; __union { unsigned int eisa$l_slot6_pid; __struct { unsigned eisa$v_slot6_pid_char2 : 2; unsigned eisa$v_slot6_pid_char1 : 5; unsigned eisa$v_slot6_pid_fill1 : 1; unsigned eisa$v_slot6_pid_char3 : 5; unsigned eisa$v_slot6_pid_char2_cont : 3; unsigned eisa$v_slot6_pid_prod_num1 : 4; unsigned eisa$v_slot6_pid_prod_num2 : 4; unsigned eisa$v_slot6_pid_rev_num1 : 4; unsigned eisa$v_slot6_pid_prod_num3 : 4; } eisa$r_slot6_pid_bits; } eisa$r_slot6_pid_overlay; char eisa$b_fill19a [4988]; unsigned char eisa$b_slot7_base; char eisa$b_fill19a01 [3199]; __union { unsigned int eisa$l_slot7_pid; __struct { unsigned eisa$v_slot7_pid_char2 : 2; unsigned eisa$v_slot7_pid_char1 : 5; unsigned eisa$v_slot7_pid_fill1 : 1; unsigned eisa$v_slot7_pid_char3 : 5; unsigned eisa$v_slot7_pid_char2_cont : 3; unsigned eisa$v_slot7_pid_prod_num1 : 4; unsigned eisa$v_slot7_pid_prod_num2 : 4; unsigned eisa$v_slot7_pid_rev_num1 : 4; unsigned eisa$v_slot7_pid_prod_num3 : 4; } eisa$r_slot7_pid_bits; } eisa$r_slot7_pid_overlay; char eisa$b_fill19a1 [4988]; unsigned char eisa$b_slot8_base; char eisa$b_fill19b [3199]; __union { unsigned int eisa$l_slot8_pid; __struct { unsigned eisa$v_slot8_pid_char2 : 2; unsigned eisa$v_slot8_pid_char1 : 5; unsigned eisa$v_slot8_pid_fill1 : 1; unsigned eisa$v_slot8_pid_char3 : 5; unsigned eisa$v_slot8_pid_char2_cont : 3; unsigned eisa$v_slot8_pid_prod_num1 : 4; unsigned eisa$v_slot8_pid_prod_num2 : 4; unsigned eisa$v_slot8_pid_rev_num1 : 4; unsigned eisa$v_slot8_pid_prod_num3 : 4; } eisa$r_slot8_pid_bits; } eisa$r_slot8_pid_overlay; char eisa$b_fill19b1 [4988]; unsigned char eisa$b_slot9_base; char eisa$b_fill19c [3199]; __union { unsigned int eisa$l_slot9_pid; __struct { unsigned eisa$v_slot9_pid_char2 : 2; unsigned eisa$v_slot9_pid_char1 : 5; unsigned eisa$v_slot9_pid_fill1 : 1; unsigned eisa$v_slot9_pid_char3 : 5; unsigned eisa$v_slot9_pid_char2_cont : 3; unsigned eisa$v_slot9_pid_prod_num1 : 4; unsigned eisa$v_slot9_pid_prod_num2 : 4; unsigned eisa$v_slot9_pid_rev_num1 : 4; unsigned eisa$v_slot9_pid_prod_num3 : 4; } eisa$r_slot9_pid_bits; } eisa$r_slot9_pid_overlay; char eisa$b_fill19c1 [4988]; unsigned char eisa$b_slot10_base; char eisa$b_fill19d [3199]; __union { unsigned int eisa$l_slot10_pid; __struct { unsigned eisa$v_slot10_pid_char2 : 2; unsigned eisa$v_slot10_pid_char1 : 5; unsigned eisa$v_slot10_pid_fill1 : 1; unsigned eisa$v_slot10_pid_char3 : 5; unsigned eisa$v_slot10_pid_char2_cont : 3; unsigned eisa$v_slot10_pid_prod_num1 : 4; unsigned eisa$v_slot10_pid_prod_num2 : 4; unsigned eisa$v_slot10_pid_rev_num1 : 4; unsigned eisa$v_slot10_pid_prod_num3 : 4; } eisa$r_slot10_pid_bits; } eisa$r_slot10_pid_overlay; char eisa$b_fill19d1 [4988]; unsigned char eisa$b_slot11_base; char eisa$b_fill19e [3199]; __union { unsigned int eisa$l_slot11_pid; __struct { unsigned eisa$v_slot11_pid_char2 : 2; unsigned eisa$v_slot11_pid_char1 : 5; unsigned eisa$v_slot11_pid_fill1 : 1; unsigned eisa$v_slot11_pid_char3 : 5; unsigned eisa$v_slot11_pid_char2_cont : 3; unsigned eisa$v_slot11_pid_prod_num1 : 4; unsigned eisa$v_slot11_pid_prod_num2 : 4; unsigned eisa$v_slot11_pid_rev_num1 : 4; unsigned eisa$v_slot11_pid_prod_num3 : 4; } eisa$r_slot11_pid_bits; } eisa$r_slot11_pid_overlay; char eisa$b_fill19e1 [4988]; unsigned char eisa$b_slot12_base; char eisa$b_fill19f [3199]; __union { unsigned int eisa$l_slot12_pid; __struct { unsigned eisa$v_slot12_pid_char2 : 2; unsigned eisa$v_slot12_pid_char1 : 5; unsigned eisa$v_slot12_pid_fill1 : 1; unsigned eisa$v_slot12_pid_char3 : 5; unsigned eisa$v_slot12_pid_char2_cont : 3; unsigned eisa$v_slot12_pid_prod_num1 : 4; unsigned eisa$v_slot12_pid_prod_num2 : 4; unsigned eisa$v_slot12_pid_rev_num1 : 4; unsigned eisa$v_slot12_pid_prod_num3 : 4; } eisa$r_slot12_pid_bits; } eisa$r_slot12_pid_overlay; char eisa$b_fill19f1 [4988]; unsigned char eisa$b_slot13_base; char eisa$b_fill19aa [3199]; __union { unsigned int eisa$l_slot13_pid; __struct { unsigned eisa$v_slot13_pid_char2 : 2; unsigned eisa$v_slot13_pid_char1 : 5; unsigned eisa$v_slot13_pid_fill1 : 1; unsigned eisa$v_slot13_pid_char3 : 5; unsigned eisa$v_slot13_pid_char2_cont : 3; unsigned eisa$v_slot13_pid_prod_num1 : 4; unsigned eisa$v_slot13_pid_prod_num2 : 4; unsigned eisa$v_slot13_pid_rev_num1 : 4; unsigned eisa$v_slot13_pid_prod_num3 : 4; } eisa$r_slot13_pid_bits; } eisa$r_slot13_pid_overlay; char eisa$b_fill19aa1 [4988]; unsigned char eisa$b_slot14_base; char eisa$b_fill19ab [3199]; __union { unsigned int eisa$l_slot14_pid; __struct { unsigned eisa$v_slot14_pid_char2 : 2; unsigned eisa$v_slot14_pid_char1 : 5; unsigned eisa$v_slot14_pid_fill1 : 1; unsigned eisa$v_slot14_pid_char3 : 5; unsigned eisa$v_slot14_pid_char2_cont : 3; unsigned eisa$v_slot14_pid_prod_num1 : 4; unsigned eisa$v_slot14_pid_prod_num2 : 4; unsigned eisa$v_slot14_pid_rev_num1 : 4; unsigned eisa$v_slot14_pid_prod_num3 : 4; } eisa$r_slot14_pid_bits; } eisa$r_slot14_pid_overlay; char eisa$b_fill19ab1 [4988]; unsigned char eisa$b_slot15_base; char eisa$b_fill19ac [3199]; __union { unsigned int eisa$l_slot15_pid; __struct { unsigned eisa$v_slot15_pid_char2 : 2; unsigned eisa$v_slot15_pid_char1 : 5; unsigned eisa$v_slot15_pid_fill1 : 1; unsigned eisa$v_slot15_pid_char3 : 5; unsigned eisa$v_slot15_pid_char2_cont : 3; unsigned eisa$v_slot15_pid_prod_num1 : 4; unsigned eisa$v_slot15_pid_prod_num2 : 4; unsigned eisa$v_slot15_pid_rev_num1 : 4; unsigned eisa$v_slot15_pid_prod_num3 : 4; } eisa$r_slot15_pid_bits; } eisa$r_slot15_pid_overlay; char eisa$b_fill19ac1 [4988]; } EISABUS; #if !defined(__VAXC) #define eisa$b_dma1_ch0_base_addr eisa$r_dma1_ch0_base_addr_overlay.eisa$b_dma1_ch0_base_addr #define eisa$b_dma1_ch0_base_cnt eisa$r_dma1_ch0_base_cnt_overlay.eisa$b_dma1_ch0_base_cnt #define eisa$b_dma1_ch1_base_addr eisa$r_dma1_ch1_base_addr_overlay.eisa$b_dma1_ch1_base_addr #define eisa$b_dma1_ch1_base_cnt eisa$r_dma1_ch1_base_cnt_overlay.eisa$b_dma1_ch1_base_cnt #define eisa$b_dma1_ch2_base_addr eisa$r_dma1_ch2_base_addr_overlay.eisa$b_dma1_ch2_base_addr #define eisa$b_dma1_ch2_base_cnt eisa$r_dma1_ch2_base_cnt_overlay.eisa$b_dma1_ch2_base_cnt #define eisa$b_dma1_ch3_base_addr eisa$r_dma1_ch3_base_addr_overlay.eisa$b_dma1_ch3_base_addr #define eisa$b_dma1_ch3_base_cnt eisa$r_dma1_ch3_base_cnt_overlay.eisa$b_dma1_ch3_base_cnt #define eisa$b_dma1_stat_cmd eisa$r_dma1_stat_cmd_overlay.eisa$b_dma1_stat_cmd #define eisa$b_dma1_wrreq eisa$r_dma1_wrreq_overlay.eisa$b_dma1_wrreq #define eisa$b_dma1_wrmask eisa$r_dma1_wrmask_overlay.eisa$b_dma1_wrmask #define eisa$b_dma1_wrmode eisa$r_dma1_wrmode_overlay.eisa$b_dma1_wrmode #define eisa$b_dma1_clrbyt eisa$r_dma1_clrbyt_overlay.eisa$b_dma1_clrbyt #define eisa$b_dma1_master_clr eisa$r_dma1_master_clr_overlay.eisa$b_dma1_master_clr #define eisa$b_dma1_clr_mask eisa$r_dma1_clr_mask_overlay.eisa$b_dma1_clr_mask #define eisa$b_dma1_mask_reg eisa$r_dma1_mask_reg_overlay.eisa$b_dma1_mask_reg #define eisa$b_pic_l_icw1 eisa$r_pic_l_icw1_ocw23_overlay.eisa$b_pic_l_icw1 #define eisa$v_pic_l_icw1_icw4 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_icw1_bits.eisa$v_pic_l_icw1_icw4 #define eisa$v_pic_l_icw1_sngl eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_icw1_bits.eisa$v_pic_l_icw1_sngl #define eisa$v_pic_l_ocw2_l0 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_l0 #define eisa$v_pic_l_ocw2_l1 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_l1 #define eisa$v_pic_l_ocw2_l2 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_l2 #define eisa$v_pic_l_ocw2_eoi eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_eoi #define eisa$v_pic_l_ocw2_sl eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_sl #define eisa$v_pic_l_ocw2_r eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_r #define eisa$v_pic_l_ocw3_ris eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_ris #define eisa$v_pic_l_ocw3_rr eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_rr #define eisa$v_pic_l_ocw3_p eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_p #define eisa$v_pic_l_ocw3_smm eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_smm #define eisa$v_pic_l_ocw3_esmm eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_esmm #define eisa$b_pic_l_icw2 eisa$r_pic_l_icw234_ocw1_overlay.eisa$b_pic_l_icw2 #define eisa$v_pic_l_icw2_zeroes eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw2_bits.eisa$v_pic_l_icw2_zeroes #define eisa$v_pic_l_icw2_vec eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw2_bits.eisa$v_pic_l_icw2_vec #define eisa$v_pic_l_icw3_irq0_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq0_slave #define eisa$v_pic_l_icw3_irq1_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq1_slave #define eisa$v_pic_l_icw3_irq2_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq2_slave #define eisa$v_pic_l_icw3_irq3_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq3_slave #define eisa$v_pic_l_icw3_irq4_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq4_slave #define eisa$v_pic_l_icw3_irq5_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq5_slave #define eisa$v_pic_l_icw3_irq6_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq6_slave #define eisa$v_pic_l_icw3_irq7_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq7_slave #define eisa$v_pic_l_icw4_mode eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_mode #define eisa$v_pic_l_icw4_aeoi eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_aeoi #define eisa$v_pic_l_icw4_buff eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_buff #define eisa$v_pic_l_icw4_nest eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_nest #define eisa$v_pic_l_ocw1_mask eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_ocw1_bits.eisa$v_pic_l_ocw1_mask #define eisa$b_pic_l_t1_systim eisa$r_pic_l_t1_systim_overlay.eisa$b_pic_l_t1_systim #define eisa$v_pic_l_t1_systim_bcd eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_bcd #define eisa$v_pic_l_t1_systim_mode eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_mode #define eisa$v_pic_l_t1_systim_rw eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_rw #define eisa$v_pic_l_t1_systim_stat eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_stat #define eisa$v_pic_l_t1_systim_out eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_out #define eisa$b_pic_l_t1_ref eisa$r_pic_l_t1_ref_overlay.eisa$b_pic_l_t1_ref #define eisa$v_pic_l_t1_ref_bcd eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_bcd #define eisa$v_pic_l_t1_ref_mode eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_mode #define eisa$v_pic_l_t1_ref_rw eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_rw #define eisa$v_pic_l_t1_ref_stat eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_stat #define eisa$v_pic_l_t1_ref_out eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_out #define eisa$b_pic_l_t1_spkr eisa$r_pic_l_t1_spkr_overlay.eisa$b_pic_l_t1_spkr #define eisa$v_pic_l_t1_spkr_bcd eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_bcd #define eisa$v_pic_l_t1_spkr_mode eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_mode #define eisa$v_pic_l_t1_spkr_rw eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_rw #define eisa$v_pic_l_t1_spkr_stat eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_stat #define eisa$v_pic_l_t1_spkr_out eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_out #define eisa$b_pic_l_t1_ctrl eisa$r_pic_l_t1_ctrl_overlay.eisa$b_pic_l_t1_ctrl #define eisa$v_pic_l_t1_ctrl_bcd eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_bcd #define eisa$v_pic_l_t1_ctrl_mode eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_mode #define eisa$v_pic_l_t1_ctrl_cntlat eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_cntlat #define eisa$v_pic_l_t1_ctrl_cntsel eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_cntsel #define eisa$b_pic_l_t2_flsf eisa$r_pic_l_t2_flsf_overlay.eisa$b_pic_l_t2_flsf #define eisa$v_pic_l_t2_flsf_bcd eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_bcd #define eisa$v_pic_l_t2_flsf_mode eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_mode #define eisa$v_pic_l_t2_flsf_rw eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_rw #define eisa$v_pic_l_t2_flsf_stat eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_stat #define eisa$v_pic_l_t2_flsf_out eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_out #define eisa$b_pic_l_t2_cpuspd eisa$r_pic_l_t2_cpuspd_overlay.eisa$b_pic_l_t2_cpuspd #define eisa$v_pic_l_t2_cpuspd_bcd eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_bcd #define eisa$v_pic_l_t2_cpuspd_mode eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_mode #define eisa$v_pic_l_t2_cpuspd_rw eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_rw #define eisa$v_pic_l_t2_cpuspd_stat eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_stat #define eisa$v_pic_l_t2_cpuspd_out eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_out #define eisa$b_pic_l_t2_ctrl eisa$r_pic_l_t2_ctrl_overlay.eisa$b_pic_l_t2_ctrl #define eisa$v_pic_l_t2_ctrl_bcd eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_bcd #define eisa$v_pic_l_t2_ctrl_mode eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_mode #define eisa$v_pic_l_t2_ctrl_cntlat eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_cntlat #define eisa$v_pic_l_t2_ctrl_cntsel eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_cntsel #define eisa$b_pic_l_nmicsr eisa$r_pic_l_nmicsr_overlay.eisa$b_pic_l_nmicsr #define eisa$v_pic_l_nmicsr_t1 eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_t1 #define eisa$v_pic_l_nmicsr_spkr eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_spkr #define eisa$v_pic_l_nmicsr_pe eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_pe #define eisa$v_pic_l_nmicsr_iochk eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_iochk #define eisa$v_pic_l_nmicsr_ref eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_ref #define eisa$v_pic_l_nmicsr_intm1 eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_intm1 #define eisa$v_pic_l_nmicsr_nmiint eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_nmiint #define eisa$v_pic_l_nmicsr_par eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_par #define eisa$b_pic_l_nmirtc eisa$r_pic_l_nmirtc_overlay.eisa$b_pic_l_nmirtc #define eisa$v_pic_l_nmirtc_clkadr eisa$r_pic_l_nmirtc_overlay.eisa$r_pic_l_nmirtc_bits.eisa$v_pic_l_nmirtc_clkadr #define eisa$v_pic_l_nmirtc_endis eisa$r_pic_l_nmirtc_overlay.eisa$r_pic_l_nmirtc_bits.eisa$v_pic_l_nmirtc_endis #define eisa$b_dma_page_ch2 eisa$r_dma_page_ch2_overlay.eisa$b_dma_page_ch2 #define eisa$b_dma_page_ch3 eisa$r_dma_page_ch3_overlay.eisa$b_dma_page_ch3 #define eisa$b_dma_page_ch1 eisa$r_dma_page_ch1_overlay.eisa$b_dma_page_ch1 #define eisa$b_dma_page_ch0 eisa$r_dma_page_ch0_overlay.eisa$b_dma_page_ch0 #define eisa$b_dma_page_ch6 eisa$r_dma_page_ch6_overlay.eisa$b_dma_page_ch6 #define eisa$b_dma_page_ch7 eisa$r_dma_page_ch7_overlay.eisa$b_dma_page_ch7 #define eisa$b_dma_page_ch5 eisa$r_dma_page_ch5_overlay.eisa$b_dma_page_ch5 #define eisa$b_dma_page_ref eisa$r_dma_page_ref_overlay.eisa$b_dma_page_ref #define eisa$b_pic_h_icw1 eisa$r_pic_h_icw1_ocw23_overlay.eisa$b_pic_h_icw1 #define eisa$v_pic_h_icw1_icw4 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_icw1_bits.eisa$v_pic_h_icw1_icw4 #define eisa$v_pic_h_icw1_sngl eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_icw1_bits.eisa$v_pic_h_icw1_sngl #define eisa$v_pic_h_ocw2_l0 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_l0 #define eisa$v_pic_h_ocw2_l1 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_l1 #define eisa$v_pic_h_ocw2_l2 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_l2 #define eisa$v_pic_h_ocw2_eoi eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_eoi #define eisa$v_pic_h_ocw2_sl eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_sl #define eisa$v_pic_h_ocw2_r eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_r #define eisa$v_pic_h_ocw3_ris eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_ris #define eisa$v_pic_h_ocw3_rr eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_rr #define eisa$v_pic_h_ocw3_p eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_p #define eisa$v_pic_h_ocw3_smm eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_smm #define eisa$v_pic_h_ocw3_esmm eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_esmm #define eisa$b_pic_h_icw2 eisa$r_pic_h_icw234_ocw1_overlay.eisa$b_pic_h_icw2 #define eisa$v_pic_h_icw2_zeroes eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw2_bits.eisa$v_pic_h_icw2_zeroes #define eisa$v_pic_h_icw2_vec eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw2_bits.eisa$v_pic_h_icw2_vec #define eisa$v_pic_h_icw3_irq0_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq0_slave #define eisa$v_pic_h_icw3_irq1_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq1_slave #define eisa$v_pic_h_icw3_irq2_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq2_slave #define eisa$v_pic_h_icw3_irq3_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq3_slave #define eisa$v_pic_h_icw3_irq4_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq4_slave #define eisa$v_pic_h_icw3_irq5_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq5_slave #define eisa$v_pic_h_icw3_irq6_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq6_slave #define eisa$v_pic_h_icw3_irq7_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq7_slave #define eisa$v_pic_h_icw4_mode eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_mode #define eisa$v_pic_h_icw4_aeoi eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_aeoi #define eisa$v_pic_h_icw4_buff eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_buff #define eisa$v_pic_h_icw4_nest eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_nest #define eisa$v_pic_h_ocw1_mask eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_ocw1_bits.eisa$v_pic_h_ocw1_mask #define eisa$b_dma2_ch0_base_addr eisa$r_dma2_ch0_base_addr_overlay.eisa$b_dma2_ch0_base_addr #define eisa$b_dma2_ch0_base_cnt eisa$r_dma2_ch0_base_cnt_overlay.eisa$b_dma2_ch0_base_cnt #define eisa$b_dma2_ch1_base_addr eisa$r_dma2_ch1_base_addr_overlay.eisa$b_dma2_ch1_base_addr #define eisa$b_dma2_ch1_base_cnt eisa$r_dma2_ch1_base_cnt_overlay.eisa$b_dma2_ch1_base_cnt #define eisa$b_dma2_ch2_base_addr eisa$r_dma2_ch2_base_addr_overlay.eisa$b_dma2_ch2_base_addr #define eisa$b_dma2_ch2_base_cnt eisa$r_dma2_ch2_base_cnt_overlay.eisa$b_dma2_ch2_base_cnt #define eisa$b_dma2_ch3_base_addr eisa$r_dma2_ch3_base_addr_overlay.eisa$b_dma2_ch3_base_addr #define eisa$b_dma2_ch3_base_cnt eisa$r_dma2_ch3_base_cnt_overlay.eisa$b_dma2_ch3_base_cnt #define eisa$b_dma2_stat_wr eisa$r_dma2_stat_wr_overlay.eisa$b_dma2_stat_wr #define eisa$b_dma2_wr_req eisa$r_dma2_wr_req_overlay.eisa$b_dma2_wr_req #define eisa$b_dma2_smask eisa$r_dma2_wr_smask_overlay.eisa$b_dma2_smask #define eisa$b_dma2_wrmode eisa$r_dma2_wrmode_overlay.eisa$b_dma2_wrmode #define eisa$b_dma2_clrbyt eisa$r_dma2_clrbyt_overlay.eisa$b_dma2_clrbyt #define eisa$b_dma2_master_clr eisa$r_dma2_master_clr_overlay.eisa$b_dma2_master_clr #define eisa$b_dma2_clr_mask eisa$r_dma2_clr_mask_overlay.eisa$b_dma2_clr_mask #define eisa$b_dma2_mask_reg eisa$r_dma2_mask_reg_overlay.eisa$b_dma2_mask_reg #define eisa$b_dma1_ch0_cnt eisa$r_dma1_ch0_cnt_overlay.eisa$b_dma1_ch0_cnt #define eisa$b_dma1_ch1_cnt eisa$r_dma1_ch1_cnt_overlay.eisa$b_dma1_ch1_cnt #define eisa$b_dma1_ch2_cnt eisa$r_dma1_ch2_cnt_overlay.eisa$b_dma1_ch2_cnt #define eisa$b_dma1_ch3_cnt eisa$r_dma1_ch3_cnt_overlay.eisa$b_dma1_ch3_cnt #define eisa$b_dma1_chn_mode eisa$r_dma1_chn_mode_overlay.eisa$b_dma1_chn_mode #define eisa$b_dma1_wrt_mode eisa$r_dma1_wrt_mode_overlay.eisa$b_dma1_wrt_mode #define eisa$b_dma1_buf_ctrl eisa$r_dma1_buf_ctrl_overlay.eisa$b_dma1_buf_ctrl #define eisa$b_dma1_stp_lvl eisa$r_dma1_stp_lvl_overlay.eisa$b_dma1_stp_lvl #define eisa$b_pic_exnmicsr eisa$r_pic_exnmicsr_overlay.eisa$b_pic_exnmicsr #define eisa$v_pic_exnmicsr_busrst eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_busrst #define eisa$v_pic_exnmicsr_enio eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_enio #define eisa$v_pic_exnmicsr_fsen eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_fsen #define eisa$v_pic_exnmicsr_toen eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_toen #define eisa$v_pic_exnmicsr_iop eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_iop #define eisa$v_pic_exnmicsr_bt eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_bt #define eisa$v_pic_exnmicsr_fsint eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_fsint #define eisa$b_pic_nmigen eisa$r_pic_nmigen_overlay.eisa$b_pic_nmigen #define eisa$b_pic_eisa_busmas eisa$r_pic_eisa_busmas_overlay.eisa$b_pic_eisa_busmas #define eisa$v_pic_eisa_busmas_sl1 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl1 #define eisa$v_pic_eisa_busmas_sl2 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl2 #define eisa$v_pic_eisa_busmas_sl3 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl3 #define eisa$v_pic_eisa_busmas_sl4 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl4 #define eisa$v_pic_eisa_busmas_sl5 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl5 #define eisa$v_pic_eisa_busmas_sl6 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl6 #define eisa$v_pic_eisa_busmas_sl7 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl7 #define eisa$b_dma_ch2_page_high eisa$r_dma_ch2_page_high_overlay.eisa$b_dma_ch2_page_high #define eisa$b_dma_ch3_page_high eisa$r_dma_ch3_page_high_overlay.eisa$b_dma_ch3_page_high #define eisa$b_dma_ch1_page_high eisa$r_dma_ch1_page_high_overlay.eisa$b_dma_ch1_page_high #define eisa$b_dma_ch0_page_high eisa$r_dma_ch0_page_high_overlay.eisa$b_dma_ch0_page_high #define eisa$b_dma_ch6_page_high eisa$r_dma_ch6_page_high_overlay.eisa$b_dma_ch6_page_high #define eisa$b_dma_ch7_page_high eisa$r_dma_ch7_page_high_overlay.eisa$b_dma_ch7_page_high #define eisa$b_dma_ch5_page_high eisa$r_dma_ch5_page_high_overlay.eisa$b_dma_ch5_page_high #define eisa$b_dma_reg_ref_high eisa$r_dma_reg_ref_high_overlay.eisa$b_dma_reg_ref_high #define eisa$b_dma2_ch5_cnt eisa$r_dma2_ch5_cnt_overlay.eisa$b_dma2_ch5_cnt #define eisa$b_dma2_ch6_cnt eisa$r_dma2_ch6_cnt_overlay.eisa$b_dma2_ch6_cnt #define eisa$b_dma2_ch7_cnt eisa$r_dma2_ch7_cnt_overlay.eisa$b_dma2_ch7_cnt #define eisa$b_pic_ctrl1_edge eisa$r_pic_ctrl1_edge_overlay.eisa$b_pic_ctrl1_edge #define eisa$v_pic_ctrl1_edge_int3 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int3 #define eisa$v_pic_ctrl1_edge_int4 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int4 #define eisa$v_pic_ctrl1_edge_int5 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int5 #define eisa$v_pic_ctrl1_edge_int6 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int6 #define eisa$v_pic_ctrl1_edge_int7 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int7 #define eisa$b_pic_ctrl2_edge eisa$r_pic_ctrl2_edge_overlay.eisa$b_pic_ctrl2_edge #define eisa$v_pic_ctrl2_edge_int9 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int9 #define eisa$v_pic_ctrl2_edge_int10 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int10 #define eisa$v_pic_ctrl2_edge_int11 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int11 #define eisa$v_pic_ctrl2_edge_int12 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int12 #define eisa$v_pic_ctrl2_edge_int14 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int14 #define eisa$v_pic_ctrl2_edge_int15 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int15 #define eisa$b_dma2_chn_mode eisa$r_dma2_chn_mode_overlay.eisa$b_dma2_chn_mode #define eisa$b_dma2_wrt_mode eisa$r_dma2_wrt_mode_overlay.eisa$b_dma2_wrt_mode #define eisa$b_dma_ch0_srb7_2 eisa$r_dma_ch0_srb7_2_overlay.eisa$b_dma_ch0_srb7_2 #define eisa$b_dma_ch0_srb15_8 eisa$r_dma_ch0_srb15_8_overlay.eisa$b_dma_ch0_srb15_8 #define eisa$b_dma_ch0_srb23_16 eisa$r_dma_ch0_srb23_16_overlay.eisa$b_dma_ch0_srb23_16 #define eisa$b_dma_ch1_srb7_2 eisa$r_dma_ch1_srb7_2_overlay.eisa$b_dma_ch1_srb7_2 #define eisa$b_dma_ch1_srb15_8 eisa$r_dma_ch1_srb15_8_overlay.eisa$b_dma_ch1_srb15_8 #define eisa$b_dma_ch1_srb23_16 eisa$r_dma_ch1_srb23_16_overlay.eisa$b_dma_ch1_srb23_16 #define eisa$b_dma_ch2_srb7_2 eisa$r_dma_ch2_srb7_2_overlay.eisa$b_dma_ch2_srb7_2 #define eisa$b_dma_ch2_srb15_8 eisa$r_dma_ch2_srb15_8_overlay.eisa$b_dma_ch2_srb15_8 #define eisa$b_dma_ch2_srb23_16 eisa$r_dma_ch2_srb23_16_overlay.eisa$b_dma_ch2_srb23_16 #define eisa$b_dma_ch3_srb7_2 eisa$r_dma_ch3_srb7_2_overlay.eisa$b_dma_ch3_srb7_2 #define eisa$b_dma_ch3_srb15_8 eisa$r_dma_ch3_srb15_8_overlay.eisa$b_dma_ch3_srb15_8 #define eisa$b_dma_ch3_srb23_16 eisa$r_dma_ch3_srb23_16_overlay.eisa$b_dma_ch3_srb23_16 #define eisa$b_dma_ch5_srb7_2 eisa$r_dma_ch5_srb7_2_overlay.eisa$b_dma_ch5_srb7_2 #define eisa$b_dma_ch5_srb15_8 eisa$r_dma_ch5_srb15_8_overlay.eisa$b_dma_ch5_srb15_8 #define eisa$b_dma_ch5_srb23_16 eisa$r_dma_ch5_srb23_16_overlay.eisa$b_dma_ch5_srb23_16 #define eisa$b_dma_ch6_srb7_2 eisa$r_dma_ch6_srb7_2_overlay.eisa$b_dma_ch6_srb7_2 #define eisa$b_dma_ch6_srb15_8 eisa$r_dma_ch6_srb15_8_overlay.eisa$b_dma_ch6_srb15_8 #define eisa$b_dma_ch6_srb23_16 eisa$r_dma_ch6_srb23_16_overlay.eisa$b_dma_ch6_srb23_16 #define eisa$b_dma_ch7_srb7_2 eisa$r_dma_ch7_srb7_2_overlay.eisa$b_dma_ch7_srb7_2 #define eisa$b_dma_ch7_srb15_8 eisa$r_dma_ch7_srb15_8_overlay.eisa$b_dma_ch7_srb15_8 #define eisa$b_dma_ch7_srb23_16 eisa$r_dma_ch7_srb23_16_overlay.eisa$b_dma_ch7_srb23_16 #define eisa$l_slot1_pid eisa$r_slot1_pid_overlay.eisa$l_slot1_pid #define eisa$v_slot1_pid_char2 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char2 #define eisa$v_slot1_pid_char1 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char1 #define eisa$v_slot1_pid_char3 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char3 #define eisa$v_slot1_pid_char2_cont eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char2_cont #define eisa$v_slot1_pid_prod_num1 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_prod_num1 #define eisa$v_slot1_pid_prod_num2 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_prod_num2 #define eisa$v_slot1_pid_rev_num1 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_rev_num1 #define eisa$v_slot1_pid_prod_num3 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_prod_num3 #define eisa$l_slot2_pid eisa$r_slot2_pid_overlay.eisa$l_slot2_pid #define eisa$v_slot2_pid_char2 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char2 #define eisa$v_slot2_pid_char1 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char1 #define eisa$v_slot2_pid_char3 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char3 #define eisa$v_slot2_pid_char2_cont eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char2_cont #define eisa$v_slot2_pid_prod_num1 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_prod_num1 #define eisa$v_slot2_pid_prod_num2 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_prod_num2 #define eisa$v_slot2_pid_rev_num1 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_rev_num1 #define eisa$v_slot2_pid_prod_num3 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_prod_num3 #define eisa$l_slot3_pid eisa$r_slot3_pid_overlay.eisa$l_slot3_pid #define eisa$v_slot3_pid_char2 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char2 #define eisa$v_slot3_pid_char1 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char1 #define eisa$v_slot3_pid_char3 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char3 #define eisa$v_slot3_pid_char2_cont eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char2_cont #define eisa$v_slot3_pid_prod_num1 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_prod_num1 #define eisa$v_slot3_pid_prod_num2 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_prod_num2 #define eisa$v_slot3_pid_rev_num1 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_rev_num1 #define eisa$v_slot3_pid_prod_num3 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_prod_num3 #define eisa$l_slot4_pid eisa$r_slot4_pid_overlay.eisa$l_slot4_pid #define eisa$v_slot4_pid_char2 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char2 #define eisa$v_slot4_pid_char1 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char1 #define eisa$v_slot4_pid_char3 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char3 #define eisa$v_slot4_pid_char2_cont eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char2_cont #define eisa$v_slot4_pid_prod_num1 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_prod_num1 #define eisa$v_slot4_pid_prod_num2 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_prod_num2 #define eisa$v_slot4_pid_rev_num1 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_rev_num1 #define eisa$v_slot4_pid_prod_num3 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_prod_num3 #define eisa$l_slot5_pid eisa$r_slot5_pid_overlay.eisa$l_slot5_pid #define eisa$v_slot5_pid_char2 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char2 #define eisa$v_slot5_pid_char1 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char1 #define eisa$v_slot5_pid_char3 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char3 #define eisa$v_slot5_pid_char2_cont eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char2_cont #define eisa$v_slot5_pid_prod_num1 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_prod_num1 #define eisa$v_slot5_pid_prod_num2 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_prod_num2 #define eisa$v_slot5_pid_rev_num1 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_rev_num1 #define eisa$v_slot5_pid_prod_num3 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_prod_num3 #define eisa$l_slot6_pid eisa$r_slot6_pid_overlay.eisa$l_slot6_pid #define eisa$v_slot6_pid_char2 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char2 #define eisa$v_slot6_pid_char1 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char1 #define eisa$v_slot6_pid_char3 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char3 #define eisa$v_slot6_pid_char2_cont eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char2_cont #define eisa$v_slot6_pid_prod_num1 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_prod_num1 #define eisa$v_slot6_pid_prod_num2 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_prod_num2 #define eisa$v_slot6_pid_rev_num1 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_rev_num1 #define eisa$v_slot6_pid_prod_num3 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_prod_num3 #define eisa$l_slot7_pid eisa$r_slot7_pid_overlay.eisa$l_slot7_pid #define eisa$v_slot7_pid_char2 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char2 #define eisa$v_slot7_pid_char1 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char1 #define eisa$v_slot7_pid_char3 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char3 #define eisa$v_slot7_pid_char2_cont eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char2_cont #define eisa$v_slot7_pid_prod_num1 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_prod_num1 #define eisa$v_slot7_pid_prod_num2 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_prod_num2 #define eisa$v_slot7_pid_rev_num1 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_rev_num1 #define eisa$v_slot7_pid_prod_num3 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_prod_num3 #define eisa$l_slot8_pid eisa$r_slot8_pid_overlay.eisa$l_slot8_pid #define eisa$v_slot8_pid_char2 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char2 #define eisa$v_slot8_pid_char1 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char1 #define eisa$v_slot8_pid_char3 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char3 #define eisa$v_slot8_pid_char2_cont eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char2_cont #define eisa$v_slot8_pid_prod_num1 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_prod_num1 #define eisa$v_slot8_pid_prod_num2 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_prod_num2 #define eisa$v_slot8_pid_rev_num1 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_rev_num1 #define eisa$v_slot8_pid_prod_num3 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_prod_num3 #define eisa$l_slot9_pid eisa$r_slot9_pid_overlay.eisa$l_slot9_pid #define eisa$v_slot9_pid_char2 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char2 #define eisa$v_slot9_pid_char1 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char1 #define eisa$v_slot9_pid_char3 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char3 #define eisa$v_slot9_pid_char2_cont eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char2_cont #define eisa$v_slot9_pid_prod_num1 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_prod_num1 #define eisa$v_slot9_pid_prod_num2 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_prod_num2 #define eisa$v_slot9_pid_rev_num1 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_rev_num1 #define eisa$v_slot9_pid_prod_num3 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_prod_num3 #define eisa$l_slot10_pid eisa$r_slot10_pid_overlay.eisa$l_slot10_pid #define eisa$v_slot10_pid_char2 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char2 #define eisa$v_slot10_pid_char1 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char1 #define eisa$v_slot10_pid_char3 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char3 #define eisa$v_slot10_pid_char2_cont eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char2_cont #define eisa$v_slot10_pid_prod_num1 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_prod_num1 #define eisa$v_slot10_pid_prod_num2 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_prod_num2 #define eisa$v_slot10_pid_rev_num1 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_rev_num1 #define eisa$v_slot10_pid_prod_num3 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_prod_num3 #define eisa$l_slot11_pid eisa$r_slot11_pid_overlay.eisa$l_slot11_pid #define eisa$v_slot11_pid_char2 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char2 #define eisa$v_slot11_pid_char1 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char1 #define eisa$v_slot11_pid_char3 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char3 #define eisa$v_slot11_pid_char2_cont eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char2_cont #define eisa$v_slot11_pid_prod_num1 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_prod_num1 #define eisa$v_slot11_pid_prod_num2 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_prod_num2 #define eisa$v_slot11_pid_rev_num1 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_rev_num1 #define eisa$v_slot11_pid_prod_num3 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_prod_num3 #define eisa$l_slot12_pid eisa$r_slot12_pid_overlay.eisa$l_slot12_pid #define eisa$v_slot12_pid_char2 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char2 #define eisa$v_slot12_pid_char1 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char1 #define eisa$v_slot12_pid_char3 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char3 #define eisa$v_slot12_pid_char2_cont eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char2_cont #define eisa$v_slot12_pid_prod_num1 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_prod_num1 #define eisa$v_slot12_pid_prod_num2 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_prod_num2 #define eisa$v_slot12_pid_rev_num1 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_rev_num1 #define eisa$v_slot12_pid_prod_num3 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_prod_num3 #define eisa$l_slot13_pid eisa$r_slot13_pid_overlay.eisa$l_slot13_pid #define eisa$v_slot13_pid_char2 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char2 #define eisa$v_slot13_pid_char1 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char1 #define eisa$v_slot13_pid_char3 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char3 #define eisa$v_slot13_pid_char2_cont eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char2_cont #define eisa$v_slot13_pid_prod_num1 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_prod_num1 #define eisa$v_slot13_pid_prod_num2 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_prod_num2 #define eisa$v_slot13_pid_rev_num1 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_rev_num1 #define eisa$v_slot13_pid_prod_num3 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_prod_num3 #define eisa$l_slot14_pid eisa$r_slot14_pid_overlay.eisa$l_slot14_pid #define eisa$v_slot14_pid_char2 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char2 #define eisa$v_slot14_pid_char1 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char1 #define eisa$v_slot14_pid_char3 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char3 #define eisa$v_slot14_pid_char2_cont eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char2_cont #define eisa$v_slot14_pid_prod_num1 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_prod_num1 #define eisa$v_slot14_pid_prod_num2 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_prod_num2 #define eisa$v_slot14_pid_rev_num1 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_rev_num1 #define eisa$v_slot14_pid_prod_num3 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_prod_num3 #define eisa$l_slot15_pid eisa$r_slot15_pid_overlay.eisa$l_slot15_pid #define eisa$v_slot15_pid_char2 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char2 #define eisa$v_slot15_pid_char1 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char1 #define eisa$v_slot15_pid_char3 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char3 #define eisa$v_slot15_pid_char2_cont eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char2_cont #define eisa$v_slot15_pid_prod_num1 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_prod_num1 #define eisa$v_slot15_pid_prod_num2 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_prod_num2 #define eisa$v_slot15_pid_rev_num1 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_rev_num1 #define eisa$v_slot15_pid_prod_num3 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_prod_num3 #endif /* #if !defined(__VAXC) */ /* the following constants are useful for bus probing. */ #define EISA$K_NODE0_BASE_CSR 0 /* this is the system */ /* board slot. */ #define EISA$K_NODE1_BASE_CSR 4096 /* this is slot 1 */ #define EISA$K_NODE2_BASE_CSR 8192 /* this is slot 2 */ #define EISA$K_NODE3_BASE_CSR 12288 /* this is slot 3 */ #define EISA$K_NODE4_BASE_CSR 16384 /* this is slot 4 */ #define EISA$K_NODE5_BASE_CSR 20480 /* this is slot 5 */ #define EISA$K_NODE6_BASE_CSR 24576 /* this is slot 6 */ #define EISA$K_NODE7_BASE_CSR 28672 /* this is slot 7 */ #define EISA$K_NODE8_BASE_CSR 32768 /* this is slot 8 */ #define EISA$K_NODE9_BASE_CSR 36864 /* this is slot 9 */ #define EISA$K_NODE10_BASE_CSR 40960 /* this is slot 10 */ #define EISA$K_NODE11_BASE_CSR 45056 /* this is slot 11 */ #define EISA$K_NODE12_BASE_CSR 49152 /* this is slot 12 */ #define EISA$K_NODE13_BASE_CSR 53248 /* this is slot 13 */ #define EISA$K_NODE14_BASE_CSR 57344 /* this is slot 14 */ #define EISA$K_NODE15_BASE_CSR 61440 /* this is slot 15 */ #define EISA$K_PRODUCT_ID_REG_OFFSET 3200 /* offset from the slot base */ /* to the PID reg */ #define EISA$K_MAX_NODE_NUMBER 15 /* max slots is 15 */ #define EISA$K_DIGITAL_VENDOR_ID 524331 /* enet prefix */ typedef struct _configdataheader { __union { unsigned short int eisacfghdr$w_version; } eisacfghdr$r_version_overlay; __union { unsigned short int eisacfghdr$w_revision; } eisacfghdr$r_revision_overlay; __union { int eisacfghdr$l_ptype; } eisacfghdr$r_ptype_overlay; __union { int eisacfghdr$l_pvendor; } eisacfghdr$r_pvendor_overlay; __union { int eisacfghdr$l_pname; } eisacfghdr$r_pname_overlay; __union { int eisacfghdr$l_pserial_num; } eisacfghdr$r_pserial_overlay; } CONFIGDATAHEADER; #if !defined(__VAXC) #define eisacfghdr$w_version eisacfghdr$r_version_overlay.eisacfghdr$w_version #define eisacfghdr$w_revision eisacfghdr$r_revision_overlay.eisacfghdr$w_revision #define eisacfghdr$l_ptype eisacfghdr$r_ptype_overlay.eisacfghdr$l_ptype #define eisacfghdr$l_pvendor eisacfghdr$r_pvendor_overlay.eisacfghdr$l_pvendor #define eisacfghdr$l_pname eisacfghdr$r_pname_overlay.eisacfghdr$l_pname #define eisacfghdr$l_pserial_num eisacfghdr$r_pserial_overlay.eisacfghdr$l_pserial_num #endif /* #if !defined(__VAXC) */ #define EISASLOTINFO$M_CFG_REV 0xF #define EISASLOTINFO$M_SLOT_TYPE 0x30 #define EISASLOTINFO$M_READ_ID 0x40 #define EISASLOTINFO$M_DUP_ID 0x80 #define EISASLOTINFO$M_TYPE_ENTRY 0x1 #define EISASLOTINFO$M_MEM_ENTRY 0x2 #define EISASLOTINFO$M_IRQ_ENTRY 0x4 #define EISASLOTINFO$M_DMA_ENTRY 0x8 #define EISASLOTINFO$M_PORT_RANGE_ENTRY 0x10 #define EISASLOTINFO$M_PORT_INIT_ENTRY 0x20 #define EISASLOTINFO$M_CHAR_2_MSB 0x3 #define EISASLOTINFO$M_CHAR_1 0x7C #define EISASLOTINFO$M_CHAR_3_MSB 0x1F #define EISASLOTINFO$M_CHAR_2_LSB 0xE0 #define EISASLOTINFO$M_HEX_2 0xF #define EISASLOTINFO$M_HEX_1 0xF0 #define EISASLOTINFO$M_HEX_4 0xF #define EISASLOTINFO$M_HEX_3 0xF0 typedef struct _eisaslotinfo { __union { unsigned char eisaslotinfo$b_slotid; __struct { unsigned eisaslotinfo$v_cfg_rev : 4; unsigned eisaslotinfo$v_slot_type : 2; unsigned eisaslotinfo$v_read_id : 1; unsigned eisaslotinfo$v_dup_id : 1; } eisaslotinfo$r_slotid_bits; } eisaslotinfo$r_slotid_overlay; unsigned char eisaslotinfo$b_major_cfg_rev; unsigned char eisaslotinfo$b_minor_cfg_rev; unsigned char eisaslotinfo$b_cfg_chksum_1; unsigned char eisaslotinfo$b_cfg_chksum_2; unsigned char eisaslotinfo$b_num_dev_func; __union { unsigned char eisaslotinfo$b_func_info; __struct { unsigned eisaslotinfo$v_type_entry : 1; unsigned eisaslotinfo$v_mem_entry : 1; unsigned eisaslotinfo$v_irq_entry : 1; unsigned eisaslotinfo$v_dma_entry : 1; unsigned eisaslotinfo$v_port_range_entry : 1; unsigned eisaslotinfo$v_port_init_entry : 1; unsigned eisaslotinfo$v_fillit : 2; } eisaslotinfo$r_func_info_bits; } eisaslotinfo$r_func_info_overlay; __union { unsigned char eisaslotinfo$b_pid_byte; __struct { unsigned eisaslotinfo$v_char_2_msb : 2; /* bits <1:0> (2 msb's) */ unsigned eisaslotinfo$v_char_1 : 5; /* bits <6:2> */ unsigned eisaslotinfo$v_rsvd1 : 1; /* bit <7> */ } eisaslotinfo$r_pid_byte0_bits; } eisaslotinfo$r_pid0_overlay; __union { unsigned char eisaslotinfo$b_pid_byte1; __struct { unsigned eisaslotinfo$v_char_3_msb : 5; /* bits <4:0> */ unsigned eisaslotinfo$v_char_2_lsb : 3; /* bits <7:5> */ } eisaslotinfo$r_pid_byte1_bits; } eisaslotinfo$r_pid1_overlay; __union { unsigned char eisaslotinfo$b_pid_byte2; __struct { unsigned eisaslotinfo$v_hex_2 : 4; unsigned eisaslotinfo$v_hex_1 : 4; } eisaslotinfo$r_pid_byte2_bits; } eisaslotinfo$r_pid2_overlay; __union { unsigned char eisaslotinfo$b_pid_byte3; __struct { unsigned eisaslotinfo$v_hex_4 : 4; unsigned eisaslotinfo$v_hex_3 : 4; } eisaslotinfo$r_pid_byte3_bits; } eisaslotinfo$r_pid3_overlay; } EISASLOTINFO; #if !defined(__VAXC) #define eisaslotinfo$b_slotid eisaslotinfo$r_slotid_overlay.eisaslotinfo$b_slotid #define eisaslotinfo$v_cfg_rev eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_cfg_rev #define eisaslotinfo$v_slot_type eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_slot_type #define eisaslotinfo$v_read_id eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_read_id #define eisaslotinfo$v_dup_id eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_dup_id #define eisaslotinfo$b_func_info eisaslotinfo$r_func_info_overlay.eisaslotinfo$b_func_info #define eisaslotinfo$v_type_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_type_entry #define eisaslotinfo$v_mem_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_mem_entry #define eisaslotinfo$v_irq_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_irq_entry #define eisaslotinfo$v_dma_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_dma_entry #define eisaslotinfo$v_port_range_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_port_range_en\ try #define eisaslotinfo$v_port_init_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_port_init_entry #define eisaslotinfo$b_pid_byte eisaslotinfo$r_pid0_overlay.eisaslotinfo$b_pid_byte #define eisaslotinfo$v_char_2_msb eisaslotinfo$r_pid0_overlay.eisaslotinfo$r_pid_byte0_bits.eisaslotinfo$v_char_2_msb #define eisaslotinfo$v_char_1 eisaslotinfo$r_pid0_overlay.eisaslotinfo$r_pid_byte0_bits.eisaslotinfo$v_char_1 #define eisaslotinfo$b_pid_byte1 eisaslotinfo$r_pid1_overlay.eisaslotinfo$b_pid_byte1 #define eisaslotinfo$v_char_3_msb eisaslotinfo$r_pid1_overlay.eisaslotinfo$r_pid_byte1_bits.eisaslotinfo$v_char_3_msb #define eisaslotinfo$v_char_2_lsb eisaslotinfo$r_pid1_overlay.eisaslotinfo$r_pid_byte1_bits.eisaslotinfo$v_char_2_lsb #define eisaslotinfo$b_pid_byte2 eisaslotinfo$r_pid2_overlay.eisaslotinfo$b_pid_byte2 #define eisaslotinfo$v_hex_2 eisaslotinfo$r_pid2_overlay.eisaslotinfo$r_pid_byte2_bits.eisaslotinfo$v_hex_2 #define eisaslotinfo$v_hex_1 eisaslotinfo$r_pid2_overlay.eisaslotinfo$r_pid_byte2_bits.eisaslotinfo$v_hex_1 #define eisaslotinfo$b_pid_byte3 eisaslotinfo$r_pid3_overlay.eisaslotinfo$b_pid_byte3 #define eisaslotinfo$v_hex_4 eisaslotinfo$r_pid3_overlay.eisaslotinfo$r_pid_byte3_bits.eisaslotinfo$v_hex_4 #define eisaslotinfo$v_hex_3 eisaslotinfo$r_pid3_overlay.eisaslotinfo$r_pid_byte3_bits.eisaslotinfo$v_hex_3 #endif /* #if !defined(__VAXC) */ #define EISACONFIG$M_CHAR_2_MSB 0x3 #define EISACONFIG$M_CHAR_1 0x7C #define EISACONFIG$M_CHAR_3_MSB 0x1F #define EISACONFIG$M_CHAR_2_LSB 0xE0 #define EISACONFIG$M_HEX_2 0xF #define EISACONFIG$M_HEX_1 0xF0 #define EISACONFIG$M_HEX_4 0xF #define EISACONFIG$M_HEX_3 0xF0 #define EISACONFIG$M_CFG_REV 0xF #define EISACONFIG$M_SLOT_TYPE 0x30 #define EISACONFIG$M_READ_ID 0x40 #define EISACONFIG$M_DUP_ID 0x80 #define EISACONFIG$M_EISA_ENABLE 0x1 #define EISACONFIG$M_IOCHKERR 0x2 #define EISACONFIG$M_CFG_DONE 0x80 #define EISACONFIG$M_TYPE_ENTRY 0x1 #define EISACONFIG$M_MEM_ENTRY 0x2 #define EISACONFIG$M_IRQ_ENTRY 0x4 #define EISACONFIG$M_DMA_ENTRY 0x8 #define EISACONFIG$M_PORT_RANGE_ENTRY 0x10 #define EISACONFIG$M_PORT_INIT_ENTRY 0x20 #define EISACONFIG$M_CFG_FREE_FORM 0x40 #define EISACONFIG$M_FUNC_ENB 0x80 #define EISACONFIG$M_ROM_RAM 0x1 #define EISACONFIG$M_MEM_CACHED 0x2 #define EISACONFIG$M_MEM_TYPE 0x18 #define EISACONFIG$M_SHARED_MEM 0x20 #define EISACONFIG$M_MORE_MEM_ENTRIES 0x80 #define EISACONFIG$M_MEM_ACCESS_SIZE 0x3 #define EISACONFIG$M_MEM_DECODE_SIZE 0xC #define EISACONFIG$M_INT_0_F 0xF #define EISACONFIG$M_INT_EDGE_LVL 0x20 #define EISACONFIG$M_INT_SHARED 0x40 #define EISACONFIG$M_INT_LAST_ENTRY 0x80 #define EISACONFIG$M_DMA_LAST_ENTRY 0x1 #define EISACONFIG$M_DMA_SHARED 0x2 #define EISACONFIG$M_DMA_CHAN 0xE0 #define EISACONFIG$M_DMA_TIMING 0xC #define EISACONFIG$M_DMA_XFER_SIZE 0x30 #define EISACONFIG$M_PORT_IO_LAST_ENTRY 0x1 #define EISACONFIG$M_PORT_IO_SHARED 0x2 #define EISACONFIG$M_NUM_IO_PORT_BYTES 0xF8 typedef struct _eisaconfigdef { __union { unsigned char eisaconfig$b_pid_byte; __struct { unsigned eisaconfig$v_char_2_msb : 2; /* bits <1:0> (2 msb's) */ unsigned eisaconfig$v_char_1 : 5; /* bits <6:2> */ unsigned eisaconfig$v_rsvd1 : 1; /* bit <7> */ } eisaconfig$r_pid_byte0_bits; } eisaconfig$r_pid0_overlay; __union { unsigned char eisaconfig$b_pid_byte1; __struct { unsigned eisaconfig$v_char_3_msb : 5; /* bits <4:0> */ unsigned eisaconfig$v_char_2_lsb : 3; /* bits <7:5> */ } eisaconfig$r_pid_byte1_bits; } eisaconfig$r_pid1_overlay; __union { unsigned char eisaconfig$b_pid_byte2; __struct { unsigned eisaconfig$v_hex_2 : 4; unsigned eisaconfig$v_hex_1 : 4; } eisaconfig$r_pid_byte2_bits; } eisaconfig$r_pid2_overlay; __union { unsigned char eisaconfig$b_pid_byte3; __struct { unsigned eisaconfig$v_hex_4 : 4; unsigned eisaconfig$v_hex_3 : 4; } eisaconfig$r_pid_byte3_bits; } eisaconfig$r_pid3_overlay; __union { unsigned char eisaconfig$b_slotid; __struct { unsigned eisaconfig$v_cfg_rev : 4; unsigned eisaconfig$v_slot_type : 2; unsigned eisaconfig$v_read_id : 1; unsigned eisaconfig$v_dup_id : 1; } eisaconfig$r_slotid_bits; } eisaconfig$r_slot_id_overlay; __union { unsigned char eisaconfig$b_config_err; __struct { unsigned eisaconfig$v_eisa_enable : 1; unsigned eisaconfig$v_iochkerr : 1; unsigned eisaconfig$v_fill3 : 5; unsigned eisaconfig$v_cfg_done : 1; } eisaconfig$r_config_err_bits; } eisaconfig$r_config_err_overlay; unsigned char eisaconfig$b_minor_cfg_rev; unsigned char eisaconfig$b_major_cfg_rev; char eisaconfig$b_selection_field [26]; __union { unsigned char eisaconfig$b_func_info; __struct { unsigned eisaconfig$v_type_entry : 1; unsigned eisaconfig$v_mem_entry : 1; unsigned eisaconfig$v_irq_entry : 1; unsigned eisaconfig$v_dma_entry : 1; unsigned eisaconfig$v_port_range_entry : 1; unsigned eisaconfig$v_port_init_entry : 1; unsigned eisaconfig$v_cfg_free_form : 1; unsigned eisaconfig$v_func_enb : 1; } eisaconfig$r_func_info_bits; } eisaconfig$r_func_info_overlay; unsigned char eisaconfig$b_type_stype_string [80]; /* the memory config region can contain up to 9 7 byte descriptions of */ /* assigned memory regions. In general, only */ /* one of the regions is used, but, for instance, some VGA cards require */ /* 4 buffers. These buffers would be specified in the first 4 7-byte blocks. */ /* Only one of the 7 byte regions has offsets defined here, the remaining 56 */ /* bytes of memory config information should be accessed using the defined offsets */ /* plus an offset of 7*#mem_config_block_being_returned. ie, to access the 1st byte */ /* of the ith config block being returned for this card, the bliss code would be */ /* mem_config_byte = .ptr_to_1st_mem_config_block[$byteoffset(eisaconfig$b_mem_config)+(i*7),0,8,0]; */ /* In order to reference the interior bits of these bytes, use the $bitposition macro similarly. */ /* these macros are all defined in starlet. */ /* */ __union { unsigned char eisaconfig$b_mem_config; __struct { unsigned eisaconfig$v_rom_ram : 1; unsigned eisaconfig$v_mem_cached : 1; unsigned eisaconfig$v_fill2a : 1; unsigned eisaconfig$v_mem_type : 2; unsigned eisaconfig$v_shared_mem : 1; unsigned eisaconfig$v_fill2a1 : 1; unsigned eisaconfig$v_more_mem_entries : 1; } eisaconfig$r_mem_config_bits; } eisaconfig$r_mem_config_overlay; __union { unsigned char eisaconfig$b_mem_data_size; __struct { unsigned eisaconfig$v_mem_access_size : 2; unsigned eisaconfig$v_mem_decode_size : 2; unsigned eisaconfig$v_fill2a : 4; } eisaconfig$r_mem_data_size_bits; } eisaconfig$r_mem_data_size_overlay; unsigned char eisaconfig$b_mem_addr_byte1; /*this 3 byte field should be multiplied */ unsigned char eisaconfig$b_mem_addr_byte2; /*by 100h to get the true starting address */ unsigned char eisaconfig$b_mem_addr_byte3; unsigned char eisaconfig$b_mem_size_byte1; /*this field needs to be multiplied by 400h */ unsigned char eisaconfig$b_mem_size_byte2; /* to get the true size, if byte1=0, size = 64M */ /* now we need the fill to leave space for the remaining 56 bytes of mem config data */ char eisaconfig$b_fill3a [56]; /* the following byte specifies the interrupt request information needed by the device */ /* each block is 2 bytes long, and there can be up to 7 blocks. Apparently some cards can */ /* have a function which needs several irq's. Again, the offsets for a single */ /* interrupt definition are defined here, to access multiple interrupt definitions, use the */ /* starlet macros $byteoffset, $bitposition, $fieldwidth, $extension and an index into the */ /* interrupt definition blocks. See the mem config block example above. */ __union { unsigned char eisaconfig$b_interr; __struct { unsigned eisaconfig$v_int_0_f : 4; unsigned eisaconfig$v_fill3 : 1; unsigned eisaconfig$v_int_edge_lvl : 1; unsigned eisaconfig$v_int_shared : 1; unsigned eisaconfig$v_int_last_entry : 1; } eisaconfig$r_interr_bits; } eisaconfig$r_interr_config_overlay; /* now leave the space for the remaining 13 potential blocks of IRQ info. */ char eisaconfig$b_fill3b [13]; /* the following byte specifies the dma channel information needed by the device */ /* each block is 2 bytes long, and there can be up to 4 blocks. Apparently some cards can */ /* have a function which needs several dma channels. Again, the offsets for a single */ /* block definition are defined here, to access multiple blocks, use the */ /* starlet macros $byteoffset, $bitposition, $fieldwidth, $extension and an index into the */ /* definition blocks. See the mem config block example above. */ __union { unsigned char eisaconfig$b_dma_byte0; __struct { unsigned eisaconfig$v_dma_last_entry : 1; unsigned eisaconfig$v_dma_shared : 1; unsigned eisaconfig$v_fill4 : 3; unsigned eisaconfig$v_dma_chan : 3; } eisaconfig$r_dma_byte0_bits; } eisaconfig$r_dma_chan_config_overl; __union { unsigned char eisaconfig$b_dma_byte1; __struct { unsigned eisaconfig$v_fill4a : 2; unsigned eisaconfig$v_dma_timing : 2; unsigned eisaconfig$v_dma_xfer_size : 2; unsigned eisaconfig$v_fill4 : 2; } eisaconfig$r_dma_byte1_bits; } eisaconfig$r_dma_chan_config1_over; char eisaconfig$b_fill6 [6]; /* the following block contains the necessary information specifying which IO ports */ /* a board has been assigned to use. Each entry consists of 3 bytes, and there can be */ /* as many as 20 entries, for a total size of 60 bytes. The first byte specifies if there */ /* are more entries to follow, and the number of ports-1 defined.(ie how many sequential bytes */ /* has the board been reserved) */ /* the second and third bytes specify the starting address. As per the above blocks, there are */ /* not 60 entries defined here. Instead a single entry is defined and the user needs to use the */ /* starlett macros $byteoffset, $bitposition, etc. and an index into the IO port config data to */ /* reference IO port block definitions 2-20. See mem config example above. */ __union { unsigned char eisaconfig$b_port_io_byte0; __struct { unsigned eisaconfig$v_port_io_last_entry : 1; unsigned eisaconfig$v_port_io_shared : 1; unsigned eisaconfig$v_fill5a : 1; unsigned eisaconfig$v_num_io_port_bytes : 5; } eisaconfig$r_port_io_byte0_bits; } eisaconfig$r_port_io_info_overlay; unsigned char eisaconfig$b_port_io_addr_l; unsigned char eisaconfig$b_port_io_addr_h; char eisaconfig$b_fill7 [57]; /* now leave space for the remaining port io blocks */ /* a major contribution of the ECU is it's ability to initialize board CSR with predefined */ /* information. This aspect of the ECU is utilized before boot, and the following information */ /* is not of importance to the VMS Bus Support code, so nothing is defined for it, space is simply */ /* reserved. */ char eisaconfig$b_init_data [60]; } EISACONFIGDEF; #if !defined(__VAXC) #define eisaconfig$b_pid_byte eisaconfig$r_pid0_overlay.eisaconfig$b_pid_byte #define eisaconfig$v_char_2_msb eisaconfig$r_pid0_overlay.eisaconfig$r_pid_byte0_bits.eisaconfig$v_char_2_msb #define eisaconfig$v_char_1 eisaconfig$r_pid0_overlay.eisaconfig$r_pid_byte0_bits.eisaconfig$v_char_1 #define eisaconfig$b_pid_byte1 eisaconfig$r_pid1_overlay.eisaconfig$b_pid_byte1 #define eisaconfig$v_char_3_msb eisaconfig$r_pid1_overlay.eisaconfig$r_pid_byte1_bits.eisaconfig$v_char_3_msb #define eisaconfig$v_char_2_lsb eisaconfig$r_pid1_overlay.eisaconfig$r_pid_byte1_bits.eisaconfig$v_char_2_lsb #define eisaconfig$b_pid_byte2 eisaconfig$r_pid2_overlay.eisaconfig$b_pid_byte2 #define eisaconfig$v_hex_2 eisaconfig$r_pid2_overlay.eisaconfig$r_pid_byte2_bits.eisaconfig$v_hex_2 #define eisaconfig$v_hex_1 eisaconfig$r_pid2_overlay.eisaconfig$r_pid_byte2_bits.eisaconfig$v_hex_1 #define eisaconfig$b_pid_byte3 eisaconfig$r_pid3_overlay.eisaconfig$b_pid_byte3 #define eisaconfig$v_hex_4 eisaconfig$r_pid3_overlay.eisaconfig$r_pid_byte3_bits.eisaconfig$v_hex_4 #define eisaconfig$v_hex_3 eisaconfig$r_pid3_overlay.eisaconfig$r_pid_byte3_bits.eisaconfig$v_hex_3 #define eisaconfig$b_slotid eisaconfig$r_slot_id_overlay.eisaconfig$b_slotid #define eisaconfig$v_cfg_rev eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_cfg_rev #define eisaconfig$v_slot_type eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_slot_type #define eisaconfig$v_read_id eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_read_id #define eisaconfig$v_dup_id eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_dup_id #define eisaconfig$b_config_err eisaconfig$r_config_err_overlay.eisaconfig$b_config_err #define eisaconfig$v_eisa_enable eisaconfig$r_config_err_overlay.eisaconfig$r_config_err_bits.eisaconfig$v_eisa_enable #define eisaconfig$v_iochkerr eisaconfig$r_config_err_overlay.eisaconfig$r_config_err_bits.eisaconfig$v_iochkerr #define eisaconfig$v_cfg_done eisaconfig$r_config_err_overlay.eisaconfig$r_config_err_bits.eisaconfig$v_cfg_done #define eisaconfig$b_func_info eisaconfig$r_func_info_overlay.eisaconfig$b_func_info #define eisaconfig$v_type_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_type_entry #define eisaconfig$v_mem_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_mem_entry #define eisaconfig$v_irq_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_irq_entry #define eisaconfig$v_dma_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_dma_entry #define eisaconfig$v_port_range_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_port_range_entry #define eisaconfig$v_port_init_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_port_init_entry #define eisaconfig$v_cfg_free_form eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_cfg_free_form #define eisaconfig$v_func_enb eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_func_enb #define eisaconfig$b_mem_config eisaconfig$r_mem_config_overlay.eisaconfig$b_mem_config #define eisaconfig$v_rom_ram eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_rom_ram #define eisaconfig$v_mem_cached eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_mem_cached #define eisaconfig$v_mem_type eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_mem_type #define eisaconfig$v_shared_mem eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_shared_mem #define eisaconfig$v_more_mem_entries eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_more_mem_entries #define eisaconfig$b_mem_data_size eisaconfig$r_mem_data_size_overlay.eisaconfig$b_mem_data_size #define eisaconfig$v_mem_access_size eisaconfig$r_mem_data_size_overlay.eisaconfig$r_mem_data_size_bits.eisaconfig$v_mem_access_size #define eisaconfig$v_mem_decode_size eisaconfig$r_mem_data_size_overlay.eisaconfig$r_mem_data_size_bits.eisaconfig$v_mem_decode_size #define eisaconfig$b_interr eisaconfig$r_interr_config_overlay.eisaconfig$b_interr #define eisaconfig$v_int_0_f eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_0_f #define eisaconfig$v_int_edge_lvl eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_edge_lvl #define eisaconfig$v_int_shared eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_shared #define eisaconfig$v_int_last_entry eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_last_entry #define eisaconfig$b_dma_byte0 eisaconfig$r_dma_chan_config_overl.eisaconfig$b_dma_byte0 #define eisaconfig$v_dma_last_entry eisaconfig$r_dma_chan_config_overl.eisaconfig$r_dma_byte0_bits.eisaconfig$v_dma_last_entry #define eisaconfig$v_dma_shared eisaconfig$r_dma_chan_config_overl.eisaconfig$r_dma_byte0_bits.eisaconfig$v_dma_shared #define eisaconfig$v_dma_chan eisaconfig$r_dma_chan_config_overl.eisaconfig$r_dma_byte0_bits.eisaconfig$v_dma_chan #define eisaconfig$b_dma_byte1 eisaconfig$r_dma_chan_config1_over.eisaconfig$b_dma_byte1 #define eisaconfig$v_dma_timing eisaconfig$r_dma_chan_config1_over.eisaconfig$r_dma_byte1_bits.eisaconfig$v_dma_timing #define eisaconfig$v_dma_xfer_size eisaconfig$r_dma_chan_config1_over.eisaconfig$r_dma_byte1_bits.eisaconfig$v_dma_xfer_size #define eisaconfig$b_port_io_byte0 eisaconfig$r_port_io_info_overlay.eisaconfig$b_port_io_byte0 #define eisaconfig$v_port_io_last_entry eisaconfig$r_port_io_info_overlay.eisaconfig$r_port_io_byte0_bits.eisaconfig$v_port_io_last\ _entry #define eisaconfig$v_port_io_shared eisaconfig$r_port_io_info_overlay.eisaconfig$r_port_io_byte0_bits.eisaconfig$v_port_io_shared #define eisaconfig$v_num_io_port_bytes eisaconfig$r_port_io_info_overlay.eisaconfig$r_port_io_byte0_bits.eisaconfig$v_num_io_port_b\ ytes #endif /* #if !defined(__VAXC) */ #define EISA_HW_ID_MASK_LO -1 #define EISA_HW_ID_MASK_HI -1 #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __EISABUSDEF_LOADED */