/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:15 by OpenVMS SDL EV3-3 */ /* Source: 03-MAY-1993 10:31:57 $1$DGA7274:[LIB_H.SRC]DMBDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $DMBDEF ***/ #ifndef __DMBDEF_LOADED #define __DMBDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*+ */ /* DMB32 (BICOMBO) specific register definitions */ /*- */ #define DMB$M_FORCE_FAIL 0x1 #define DMB$M_PROGRAM_RESET 0x2 #define DMB$M_PTE_VALID 0x4 #define DMB$M_SKIP_SELFTEST 0x8 #define DMB$M_MAINT_LEVEL1 0x10 #define DMB$M_MAINT_LEVEL2 0x20 #define DMB$M_SYNC 0x100 #define DMB$M_ASYNC 0x200 #define DMB$M_PRINT 0x400 #define DMB$M_DIAG_FAIL 0x800 #define DMB$M_X21_SUPPORT 0x1000 #define DMB$M_CABLE_KEY 0x2000 #define DMB$M_TURN_CONN 0x4000 #define DMB$M_MANF_CONN 0x8000 #define DMB$M_RX_I_E 0x100 #define DMB$M_TX_I_E 0x200 #define DMB$M_SYNC_I_E 0x800 #define DMB$M_PR_I_E 0x800 #define DMB$M_PR_DAVFU_READY 0x10000 #define DMB$M_PR_CONNECT_VERIFY 0x20000 #define DMB$M_PR_OFFLINE 0x40000 #define DMB$M_ASYNC_RESET 0x400 #define DMB$M_SYNC_RESET 0x400 #define DMB$M_PRINTER_RESET 0x400 #define DMB$M_PR_DMA_START 0x1 #define DMB$M_PR_DMA_PTE 0x2 #define DMB$M_PR_DMA_PHYS 0x4 #define DMB$M_PR_DMA_ABORT 0x100 #define DMB$M_PR_FORMAT 0x200 #define DMB$M_PR_TAB 0x1000000 #define DMB$M_PR_TRUNC 0x2000000 #define DMB$M_PR_AUTO_RETURN 0x4000000 #define DMB$M_PR_AUTO_FORM 0x8000000 #define DMB$M_PR_NON_PRINT 0x10000000 #define DMB$M_PR_DAVFU 0x20000000 #define DMB$M_PR_WRAP 0x40000000 #define DMB$M_PR_UPPER 0x80000000 #define DMB$M_TX1_DMA_START 0x1 #define DMB$M_TX1_DMA_PTE 0x2 #define DMB$M_TX1_DMA_PHYS 0x4 #define DMB$M_TX1_X21 0x8 #define DMB$M_TX1_PAR 0x10 #define DMB$M_TX1_DMA_ABORT 0x100 #define DMB$M_RX1_DMA_START 0x1 #define DMB$M_RX1_DMA_PTE 0x2 #define DMB$M_RX1_DMA_PHYS 0x4 #define DMB$M_RX1_X21 0x8 #define DMB$M_RX1_DMA_ABORT 0x100 #define DMB$M_RX_ENABLE 0x1 #define DMB$M_RX_MATCH_ENA 0x4 #define DMB$M_RX_PRIMARY 0x8 #define DMB$M_X21ENABLE 0x10 #define DMB$M_CLOCK_CONTROL 0x40 #define DMB$M_CODING_TYPE 0x80 #define DMB$M_BAUD_RATE 0xF00 #define DMB$M_LOOP 0x1000 #define DMB$M_V35_SELECT 0x2000 #define DMB$M_V10_SELECT 0x4000 #define DMB$M_MODEM_SUPPRESS 0x8000 #define DMB$M_LINE_RESET 0x80000000 #define DMB$M_SYNC_ML1 0x1 #define DMB$M_SYNC_DTR 0x2 #define DMB$M_SYNC_DRS 0x4 #define DMB$M_SYNC_ML2 0x8 #define DMB$M_SYNC_RTS 0x10 #define DMB$M_SPARE_MODEM 0xE0 #define DMB$M_SYNC_RXCLOCK 0x100 #define DMB$M_SYNC_TXCLOCK 0x200 #define DMB$M_SYNC_TI 0x400 #define DMB$M_SYNC_CTS 0x1000 #define DMB$M_SYNC_DCD 0x2000 #define DMB$M_SYNC_RI 0x4000 #define DMB$M_SYNC_DSR 0x8000 #define DMB$M_PROTOCOL 0x70000 #define DMB$C_PRO_DDCMP 0 #define DMB$C_PRO_SDLC 1 #define DMB$C_PRO_HDLC 2 #define DMB$C_PRO_BISYNC 3 #define DMB$C_PRO_GENBYTE 7 #define DMB$M_ERROR_TYPE 0x380000 #define DMB$C_ERR_CRC1 0 #define DMB$C_ERR_CRC0 1 #define DMB$C_ERR_LVE 2 #define DMB$C_ERR_CRC16 3 #define DMB$C_ERR_LRC0 4 #define DMB$C_ERR_LRCE 5 #define DMB$C_ERR_LVO 6 #define DMB$C_NOCON 7 #define DMB$M_RX_BPC 0x1C00000 #define DMB$M_TX_BPC 0xE000000 #define DMB$M_STRIP_SYNC 0x10000000 #define DMB$M_EBCDIC_CODE 0x20000000 #define DMB$M_IDLE_SYNC 0x40000000 #define DMB$M_MODEM_OVERRIDE 0x80000000 #define DMB$M_TX2_DMA_START 0x1 #define DMB$M_TX2_DMA_PTE 0x2 #define DMB$M_TX2_DMA_PHYS 0x4 #define DMB$M_TX2_X21 0x8 #define DMB$M_TX2_PAR 0x10 #define DMB$M_TX2_DMA_ABORT 0x100 #define DMB$M_RX2_DMA_START 0x1 #define DMB$M_RX2_DMA_PTE 0x2 #define DMB$M_RX2_DMA_PHYS 0x4 #define DMB$M_RX2_X21 0x8 #define DMB$M_RX2_DMA_ABORT 0x100 #define DMB$M_SYNC_CABLE 0xF000000 #define DMB$M_SYNC_LOOP 0x20000000 #define DMB$M_SYNC_VALID 0x40000000 #define DMB$M_SYNC_X21 0x80000000 #define DMB$M_PREEMPT_GO 0x8000 #define DMB$M_ML 0x1 #define DMB$M_DTR 0x2 #define DMB$M_DRS 0x4 #define DMB$M_RTS 0x10 #define DMB$M_TX_INT_DELAY 0x200 #define DMB$M_RX_ENA 0x400 #define DMB$M_BREAK 0x800 #define DMB$M_MAINT 0x3000 #define DMB$M_REPORT_MODEM 0x4000 #define DMB$M_DISCARD_FLOW 0x8000 #define DMB$M_CHAR_LENGTH 0x30000 #define DMB$M_PARITY_ENAB 0x40000 #define DMB$M_EVEN_PARITY 0x80000 #define DMB$M_STOP_CODE 0x100000 #define DMB$M_USE_CTS 0x200000 #define DMB$M_IAUTO_FLOW 0x400000 #define DMB$M_OAUTO_FLOW 0x800000 #define DMB$M_RX_SPEED 0xF000000 #define DMB$M_TX_SPEED 0xF0000000 #define DMB$M_TX_DMA_START 0x1 #define DMB$M_TX_DMA_PTE 0x2 #define DMB$M_TX_DMA_PHYS 0x4 #define DMB$M_TX_OUT_ABORT 0x100 #define DMB$M_ML2 0x400 #define DMB$M_CTS 0x1000 #define DMB$M_DCD 0x2000 #define DMB$M_RI 0x4000 #define DMB$M_DSR 0x8000 #define DMB$M_SNDOFF 0x800000 #define DMB$M_TX_ENA 0x80000000 #define DMB$M_TX_PREEMPT 0x100 #define DMB$M_TX_FIFO_DONE 0x200 #define DMB$M_TX_ACT 0x80000000 #define DMB$M_SYNC_MODEM 0x100 #define DMB$M_SYNC_TX_ACT 0x200 #define DMB$M_SYNC_SECOND_BUFFER 0x400 #define DMB$M_PARITY_ERR 0x1000 #define DMB$M_FRAME_ERR 0x2000 #define DMB$M_OVERRUN_ERR 0x4000 #define DMB$M_NON_CHAR 0x8000 #define DMB$M_DATA_VALID 0x80000000 #define DMB$C_NO_ERROR 0 #define DMB$C_DMA_ERROR 1 #define DMB$C_MSG_ERROR 2 #define DMB$C_LAST_CHAR_ERROR 3 #define DMB$C_BUFFER_ERROR 4 #define DMB$C_MODEM_ERROR 5 #define DMB$C_ABORT_ERROR 6 #define DMB$C_X21_ERROR 7 #define DMB$C_OFFLINE_ERROR 8 #define DMB$C_INTERNAL_ERROR 9 #define DMB$C_HEADER_CRC_ERROR 1 #define DMB$C_DATA_CRC_ERROR 2 #define DMB$C_LENGTH_ERROR 3 #define DMB$C_LENGTH_AND_CRC_ERROR 4 #define DMB$C_ABORT_CHARACTER_ERROR 5 #define DMB$C_INVALID_CHARACTER_ERROR 6 #define DMB$C_HOST_ABORT_ERROR 1 #define DMB$C_DMB_ABORT_ERROR 2 #define DMB$C_RX_OVERRUN_ERROR 1 #define DMB$C_TX_UNDERRUN_ERROR 2 #define DMB$S_DMBDEF 528 /* Old size name - synonym */ typedef struct _dmb { char dmbdef$$_fill_1 [256]; __union { unsigned int dmb$l_maint; /*Maintenance register */ __struct { unsigned dmb$v_force_fail : 1; /*Force failure */ unsigned dmb$v_program_reset : 1; /*Programmed reset */ unsigned dmb$v_pte_valid : 1; /*Page tables valid */ unsigned dmb$v_skip_selftest : 1; /*Skip self test */ unsigned dmb$v_maint_level1 : 1; /*Maintenance level 1 */ unsigned dmb$v_maint_level2 : 1; /*Maintenance level 2 */ unsigned dmbdef$$_fill_2 : 2; unsigned dmb$v_sync : 1; /*Sync lines present */ unsigned dmb$v_async : 1; /*Async lines present */ unsigned dmb$v_print : 1; /*Printer present */ unsigned dmb$v_diag_fail : 1; /*Diagnostic error */ unsigned dmb$v_x21_support : 1; /*X21 firmware support present */ unsigned dmb$v_cable_key : 1; /*Cable key signal present */ unsigned dmb$v_turn_conn : 1; /*stag. loopback conn. present */ unsigned dmb$v_manf_conn : 1; /*Mfg. loopback conn. present */ } dmb$r_maint_bits; } dmb$r_maint_overlay; /* */ /* The following 3 registers are the Control Status Registers (CSRs) for */ /* the Async, Sync, and Printer ports in that order. */ /* */ __union { unsigned int dmb$l_acsr; /*Async Control Status Register */ __struct { char dmb$b_async_ind_add; /*Indirect Addr. Register Ptr. */ unsigned dmb$v_rx_i_e : 1; /*Receive Interrupt Enable */ unsigned dmb$v_tx_i_e : 1; /*Transmit Interrupt Enable */ unsigned dmb$v_fill_0_ : 6; } dmb$r_acsr_bits; } dmb$r_acsr_overlay; __union { unsigned int dmb$l_scsr; /*Sync Control Status Register */ __struct { char dmb$b_sync_ind_add; /*Indirect Addr. Register Ptr. */ unsigned dmbdef$$_fill_4 : 3; unsigned dmb$v_sync_i_e : 1; /*Sync Interrupt Enable */ unsigned dmb$v_fill_1_ : 4; } dmb$r_scsr_bits; } dmb$r_scsr_overlay; __union { unsigned int dmb$l_pcsr; /*Printer Control Status Register */ __struct { unsigned dmbdef$$_fill_5 : 11; unsigned dmb$v_pr_i_e : 1; /*Printer Interrupt Enable */ unsigned dmbdef$$_fill_6 : 4; unsigned dmb$v_pr_davfu_ready : 1; /*DAVFU ready */ unsigned dmb$v_pr_connect_verify : 1; /*Connect verify */ unsigned dmb$v_pr_offline : 1; /*Line printer error */ unsigned dmb$v_fill_2_ : 5; } dmb$r_pcsr_bits; } dmb$r_pcsr_overlay; int dmb$l_fill_7; /*Unused */ /* */ /* Configuration of devices on DMB32. */ /* */ __union { unsigned int dmb$l_config; /*Device Configuration */ __struct { char dmb$b_async_lines; /*Number of async lines */ char dmb$b_sync_lines; /*Number of sync lines */ char dmb$b_printer_lines; /*Number of printer ports */ } dmb$r_config_fields; } dmb$r_config_overlay; /* */ /* The following 3 registers are the 2nd Control Status Registers for */ /* each of the ports on the DMB32 (Async, Sync, and Printer). */ /* */ __union { int dmb$l_acsr2; /*2ND Async Control Status Register */ __struct { unsigned dmbdef$$_fill_7 : 10; unsigned dmb$v_async_reset : 1; /*Async Port reset */ unsigned dmbdef$$_fill_8 : 5; char dmb$b_rx_timer; /*Rcv Interrupt delay timer */ } dmb$r_acsr2_bits; } dmb$r_acsr2_overlay; __union { int dmb$l_scsr2; /*2ND Sync Control Status Register */ __struct { unsigned dmbdef$$_fill_9 : 10; unsigned dmb$v_sync_reset : 1; /*Sync Port reset */ unsigned dmb$v_fill_3_ : 5; } dmb$r_scsr2_bits; } dmb$r_scsr2_overlay; __union { unsigned int dmb$l_pcsr2; /*2ND Printer Control Status Register */ __struct { unsigned dmbdef$$_fill_10 : 10; unsigned dmb$v_printer_reset : 1; /*Printer Port reset */ unsigned dmb$v_fill_4_ : 5; } dmb$r_pcsr2_bits; } dmb$r_pcsr2_overlay; int dmbdef$$_fill_11 [11]; unsigned int dmb$l_spte; /*SPTE system page table register */ unsigned int dmb$l_spts; /*System page table size register */ unsigned int dmb$l_gpte; /*Global page table register */ unsigned int dmb$l_gpts; /*Global page table size register */ /* */ /* The following 6 registers are specific to the printer port on the */ /* DMB32. */ /* */ __union { unsigned int dmb$l_pfix; /*Printer prefix/suffix control */ __struct { char dmb$b_prefix_count; /*Prefix count */ char dmb$b_prefix_char; /*Prefix character */ char dmb$b_suffix_count; /*Suffix count */ char dmb$b_suffix_char; /*Suffix character */ } dmb$r_pfix_fields; } dmb$r_pfix_overlay; void *dmb$l_pbufad; /*Printer Buffer Address */ __union { unsigned int dmb$l_pbufct; /*Printer Buffer count/offset */ __struct { short int dmb$w_pr_buff_off; /*printer buffer offset */ short int dmb$w_pr_buff_ct; /*transmit DMA char. count */ } dmb$r_pbufct_fields; } dmb$r_pbufct_overlay; __union { unsigned int dmb$l_pctrl; /*Printer Control Register */ __struct { unsigned dmb$v_pr_dma_start : 1; /*Start a DMA transfer */ unsigned dmb$v_pr_dma_pte : 1; /*PTE address */ unsigned dmb$v_pr_dma_phys : 1; /*Physical address */ unsigned dmbdef$$_fill_12 : 5; unsigned dmb$v_pr_dma_abort : 1; /*Abort a DMA transfer */ unsigned dmb$v_pr_format : 1; /*Format control */ unsigned dmbdef$$_fill_13 : 6; char dmb$b_pr_error; /*Error code */ unsigned dmb$v_pr_tab : 1; /*Tab expansion */ unsigned dmb$v_pr_trunc : 1; /*Truncation of Data */ unsigned dmb$v_pr_auto_return : 1; /*Auto CR insert */ unsigned dmb$v_pr_auto_form : 1; /*Auto FF to LF convert */ unsigned dmb$v_pr_non_print : 1; /*Non printing char. accept */ unsigned dmb$v_pr_davfu : 1; /*DAVFU */ unsigned dmb$v_pr_wrap : 1; /*Line Wrap */ unsigned dmb$v_pr_upper : 1; /*Convert to upper case */ } dmb$r_pctrl_bits; } dmb$r_pctrl_overlay; __union { unsigned int dmb$l_pcar; /*Printer Carriage Counter */ __struct { short int dmb$w_pr_line; /*Lines printed */ short int dmb$w_pr_char; /*Characters transmitted */ } dmb$r_pcar_fields; } dmb$r_pcar_overlay; __union { unsigned int dmb$l_psize; /*Printer page size */ __struct { short int dmb$w_pr_width; /*Line Width */ short int dmb$w_pr_page; /*Page size */ } dmb$r_psize_fields; } dmb$r_psize_overlay; int dmbdef$$_fill_14 [2]; /* */ /* The next 16 registers are specific to the SYNC port on the DMB32. */ /* */ void *dmb$l_tbuffad1; /*Transmit Buffer Address 1 */ __union { unsigned int dmb$l_tbuffct1; /*Transmit Buffer Count/offset 1 */ __struct { short int dmb$w_tx_buff_off1; /*Transmit buffer offset */ short int dmb$w_tx_char_ct1; /*Transmit DMA character count */ } dmb$r_tbuffct1_fields; } dmb$r_tbuffct1_overlay; void *dmb$l_rbuffad1; /*Receive Buffer Address 1 */ __union { unsigned int dmb$l_rbuffct1; /*Receive Buffer Count/offset 1 */ __struct { short int dmb$w_rx_buff_off1; /*Receive buffer offset */ short int dmb$w_rx_char_ct1; /*Receive DMA character count */ } dmb$r_rbuffct1_fields; } dmb$r_rbuffct1_overlay; __union { unsigned int dmb$l_tlnctrl1; /*Buffer 1 Transmit Control */ __struct { unsigned dmb$v_tx1_dma_start : 1; /*Start a DMA transfer */ unsigned dmb$v_tx1_dma_pte : 1; /*PTE address */ unsigned dmb$v_tx1_dma_phys : 1; /*Physical address */ unsigned dmb$v_tx1_x21 : 1; /*X.21 mode */ unsigned dmb$v_tx1_par : 1; /*Parameter change */ unsigned dmbdef$$_fill_15 : 3; unsigned dmb$v_tx1_dma_abort : 1; /*Transmitter DMA abort */ unsigned dmbdef$$_fill_16 : 15; char dmb$b_tx1_error; /*Transmitter Error bits */ } dmb$r_tlnctrl1_bits; } dmb$r_tlnctrl1_overlay; __union { unsigned int dmb$l_rlnctrl1; /*Buffer 1 Receive Control */ __struct { unsigned dmb$v_rx1_dma_start : 1; /*Start a DMA transfer */ unsigned dmb$v_rx1_dma_pte : 1; /*PTE address */ unsigned dmb$v_rx1_dma_phys : 1; /*Physical address */ unsigned dmb$v_rx1_x21 : 1; /*X.21 mode */ unsigned dmbdef$$_fill_17 : 4; unsigned dmb$v_rx1_dma_abort : 1; /*Receiver DMA abort */ unsigned dmbdef$$_fill_18 : 15; char dmb$b_rx1_error; /*Receiver error bits */ } dmb$r_rlnctrl1_bits; } dmb$r_rlnctrl1_overlay; __union { unsigned int dmb$l_lpr1; /*Sync line parameters 1 */ __struct { unsigned dmb$v_rx_enable : 1; /*Receiver Enable */ unsigned dmbdef$$_fill_19 : 1; unsigned dmb$v_rx_match_ena : 1; /*Receiver Match character enable */ unsigned dmb$v_rx_primary : 1; /*Primary-Secondary Station */ unsigned dmb$v_x21enable : 1; /*X21 Protocol Enable */ unsigned dmbdef$$_fill_20 : 1; unsigned dmb$v_clock_control : 1; /*Clock control bit */ unsigned dmb$v_coding_type : 1; /*Data coding type */ unsigned dmb$v_baud_rate : 4; /*Internal B.R. Generator speed */ unsigned dmb$v_loop : 1; /*Maintenance Loop back */ unsigned dmb$v_v35_select : 1; /*V.35 select */ unsigned dmb$v_v10_select : 1; /*V.10 select */ unsigned dmb$v_modem_suppress : 1; /*Supress modem change ints */ char dmb$b_number_sync; /*Number of sync characters */ unsigned dmbdef$$_fill_22 : 7; unsigned dmb$v_line_reset : 1; /*Line reset request */ } dmb$r_lpr1_bits; } dmb$r_lpr1_overlay; __union { unsigned int dmb$l_lpr2; /*Sync line parameters 2 */ __struct { unsigned dmb$v_sync_ml1 : 1; /*Modem loop output */ unsigned dmb$v_sync_dtr : 1; /*Data terminal ready output */ unsigned dmb$v_sync_drs : 1; /*Data rate select output */ unsigned dmb$v_sync_ml2 : 1; /*2nd modem loop output */ unsigned dmb$v_sync_rts : 1; /*Request to send output */ unsigned dmb$v_spare_modem : 3; /* */ unsigned dmb$v_sync_rxclock : 1; /*Receive clock running */ unsigned dmb$v_sync_txclock : 1; /*Transmit clock running */ unsigned dmb$v_sync_ti : 1; /*Test indicator */ unsigned dmbdef$$_fill_23 : 1; unsigned dmb$v_sync_cts : 1; /*Clear to send input */ unsigned dmb$v_sync_dcd : 1; /*Data carrier detect input */ unsigned dmb$v_sync_ri : 1; /*Ring indicator input */ unsigned dmb$v_sync_dsr : 1; /*Data set ready input */ unsigned dmb$v_protocol : 3; /*Protocol type */ unsigned dmb$v_error_type : 3; unsigned dmb$v_rx_bpc : 3; /*#of receive bits per char. */ unsigned dmb$v_tx_bpc : 3; /*# of transmit bits per char. */ unsigned dmb$v_strip_sync : 1; /*Strip Sync */ unsigned dmb$v_ebcdic_code : 1; /*Character code */ unsigned dmb$v_idle_sync : 1; /*Idle Sync */ unsigned dmb$v_modem_override : 1; /*Modem control override */ } dmb$r_lpr2_bits; } dmb$r_lpr2_overlay; void *dmb$l_tbuffad2; /*Transmit Buffer Address 2 */ __union { unsigned int dmb$l_tbuffct2; /*Transmit Buffer count/offset 1 */ __struct { short int dmb$w_tx_buff_off2; /*Transmit buffer offset */ short int dmb$w_tx_char_ct2; /*Transmit DMA character count */ } dmb$r_tbuffct2_fields; } dmb$r_tbuffct2_overlay; void *dmb$l_rbuffad2; /*Receive Buffer Address 2 */ __union { unsigned int dmb$l_rbuffct2; /*Receive Buffer count/offset 2 */ __struct { short int dmb$w_rx_buff_off2; /*Receive buffer offset */ short int dmb$w_rx_char_ct2; /*Receive DMA character count */ } dmb$r_rbuffct2_fields; } dmb$r_rbuffct2_overlay; __union { unsigned int dmb$l_tlnctrl2; /*Buffer 2 Transmit Control */ __struct { unsigned dmb$v_tx2_dma_start : 1; /*Start a DMA transfer */ unsigned dmb$v_tx2_dma_pte : 1; /*PTE address */ unsigned dmb$v_tx2_dma_phys : 1; /*Physical address */ unsigned dmb$v_tx2_x21 : 1; /*X.21 mode */ unsigned dmb$v_tx2_par : 1; /*Parameter change */ unsigned dmbdef$$_fill_24 : 3; unsigned dmb$v_tx2_dma_abort : 1; /*Transmitter DMA abort */ unsigned dmbdef$$_fill_25 : 15; char dmb$b_tx2_error; /*Transmitter error bits */ } dmb$r_tlnctrl2_bits; } dmb$r_tlnctrl2_overlay; __union { unsigned int dmb$l_rlnctrl2; /*Buffer 2 Receive control */ __struct { unsigned dmb$v_rx2_dma_start : 1; /*Start a DMA transfer */ unsigned dmb$v_rx2_dma_pte : 1; /*PTE address */ unsigned dmb$v_rx2_dma_phys : 1; /*Physical address */ unsigned dmb$v_rx2_x21 : 1; /*X.21 mode */ unsigned dmbdef$$_fill_26 : 4; unsigned dmb$v_rx2_dma_abort : 1; /*Receiver DMA abort */ unsigned dmbdef$$_fill_27 : 15; char dmb$b_rx2_error; /*Receiver error bits */ } dmb$r_rlnctrl2_bits; } dmb$r_rlnctrl2_overlay; __union { unsigned int dmb$l_lpr3; /*Sync Line parameters 3 */ __struct { char dmb$b_sync_char; /*Sync character */ char dmb$b_rx_match; /*Receive match character */ char dmb$b_address1; /*First address character */ char dmb$b_address2; /*Second address character */ } dmb$r_lpr3_fields; } dmb$r_lpr3_overlay; __union { unsigned int dmb$l_bufctrl; /*Sync Buffer Control Bits */ __struct { char dmb$b_tx_buff_prio; /*Transmitter Buf. Priority */ char dmb$b_rx_buff_prio; /*Receiver Buffer Priority */ char dmb$b_sync_test_input; /*Test inputs */ unsigned dmb$v_sync_cable : 4; /*Electrical Configuration */ unsigned dmbdef$$_fill_28 : 1; unsigned dmb$v_sync_loop : 1; /*Loopback present */ unsigned dmb$v_sync_valid : 1; /*Valid cable */ unsigned dmb$v_sync_x21 : 1; /*X.21 Mode */ } dmb$r_bufctrl_bits; } dmb$r_bufctrl_overlay; /* */ /* The next 10 registers are for the async port on the DMB32 */ /* */ __union { unsigned int dmb$l_preempt; /*Preempt Buffer */ __struct { char dmb$b_preempt_char; /*Character to Transmit */ unsigned dmbdef$$_fill_29 : 7; unsigned dmb$v_preempt_go : 1; /*Start Preempt */ } dmb$r_preempt_bits; } dmb$r_preempt_overlay; void *dmb$l_tbuffad; /*Transmit Buffer Address */ __union { unsigned int dmb$l_tbuffct; /*Transmit Buffer Count-Offset */ __struct { short int dmb$w_tx_buff_off; /*Transmit Buffer Offset */ short int dmb$w_tx_char_ct; /*Transmit Buffer Count */ } dmb$r_tbuffct_fields; } dmb$r_tbuffct_overlay; __union { unsigned int dmb$l_lpr; /*Line parameter register */ __struct { unsigned dmb$v_ml : 1; /*Modem Loop */ unsigned dmb$v_dtr : 1; /*Data Terminal Ready */ unsigned dmb$v_drs : 1; /*Data Rate Select */ unsigned dmbdef$$_fill_30 : 1; unsigned dmb$v_rts : 1; /*Request to Send */ unsigned dmbdef$$_fill_31 : 4; unsigned dmb$v_tx_int_delay : 1; /*Transmit Interrupt Control */ unsigned dmb$v_rx_ena : 1; /*Receiver Enable */ unsigned dmb$v_break : 1; /*Break control */ unsigned dmb$v_maint : 2; /*Maintenance Mode */ unsigned dmb$v_report_modem : 1; /*Report Modem changes */ unsigned dmb$v_discard_flow : 1; /*Discard flow contr. characters */ unsigned dmb$v_char_length : 2; /*character length */ unsigned dmb$v_parity_enab : 1; /*Parity enable */ unsigned dmb$v_even_parity : 1; /*Even parity */ unsigned dmb$v_stop_code : 1; /*Stop code */ unsigned dmb$v_use_cts : 1; /*CTS controls output */ unsigned dmb$v_iauto_flow : 1; /*Auto f.c. of incoming data */ unsigned dmb$v_oauto_flow : 1; /*Auto f.c. of outgoing data */ unsigned dmb$v_rx_speed : 4; /*Received data speed */ unsigned dmb$v_tx_speed : 4; /*Transmitted data rate */ } dmb$r_lpr_bits; } dmb$r_lpr_overlay; __union { unsigned int dmb$l_lnctrl; /*Line Control */ __struct { unsigned dmb$v_tx_dma_start : 1; /*Start a DMA transfer */ unsigned dmb$v_tx_dma_pte : 1; /*PTE address */ unsigned dmb$v_tx_dma_phys : 1; /*Physical address */ unsigned dmbdef$$_fill_32 : 5; unsigned dmb$v_tx_out_abort : 1; /*Transmitter output abort */ unsigned dmbdef$$_fill_33 : 7; char dmb$b_tx_error; /*Transmitter error bits */ unsigned dmbdef$$_fill_34 : 1; unsigned dmb$v_fill_5_ : 7; } dmb$r_lnctrl_bits; } dmb$r_lnctrl_overlay; __union { unsigned int dmb$l_lstat; /*Line status register */ __struct { unsigned dmbdef$$_fill_35 : 10; unsigned dmb$v_ml2 : 1; /*Spare modem control lead */ unsigned dmbdef$$_fill_36 : 1; unsigned dmb$v_cts : 1; /*Clear to send */ unsigned dmb$v_dcd : 1; /*Data carrier detected */ unsigned dmb$v_ri : 1; /*Ring indicator */ unsigned dmb$v_dsr : 1; /*Data set ready */ unsigned dmbdef$$_fill_37 : 7; unsigned dmb$v_sndoff : 1; /*Send XOFF */ unsigned dmbdef$$_fill_38 : 7; unsigned dmb$v_tx_ena : 1; /*Transmitter enable */ } dmb$r_lstat_bits; } dmb$r_lstat_overlay; __union { unsigned int dmb$l_flowc; /*Flow control characters */ __struct { char dmb$b_sent_xoff; /*Transmitted XOFF */ char dmb$b_sent_xon; /*Transmitted XON */ char dmb$b_received_xoff; /*Received XOFF */ char dmb$b_received_xon; /*Received XON */ } dmb$r_flowc_fields; } dmb$r_flowc_overlay; int dmbdef$$_fill_39 [10]; __union { unsigned int dmb$l_tbuf; /*Transmit completion fifo */ __struct { char dmb$b_tx_line; /*Transmit line number */ unsigned dmb$v_tx_preempt : 1; /*Preempt completed */ unsigned dmb$v_tx_fifo_done : 1; /*fifo empty */ unsigned dmbdef$$_fill_40 : 6; char dmb$b_tx_dma_error; /*Transmit error code */ unsigned dmbdef$$_fill_41 : 7; unsigned dmb$v_tx_act : 1; /*Transmitter action */ } dmb$r_tbuf_bits; } dmb$r_tbuf_overlay; __union { unsigned int dmb$l_sbuf; /*Sync line completion fifo */ __struct { char dmb$b_sync_line; /*Sync line number */ unsigned dmb$v_sync_modem : 1; /*Modem change */ unsigned dmb$v_sync_tx_act : 1; /*Sync Transmit complete */ unsigned dmb$v_sync_second_buffer : 1; /*buffer number */ unsigned dmb$v_sbuf_spare : 5; /* */ __union { /* */ char dmb$b_sync_modem_status; /*Sync line new modem status */ char dmb$b_sync_error; /*Sync line error code */ } dmb$r_sbuf_x; } dmb$r_sbuf_bits; } dmb$r_sbuf_overlay; __union { unsigned int dmb$l_rbuf; /*Async Receiver Buffer */ __struct { char dmb$b_rxchar; /*Received character */ unsigned dmbdef$$_fill_42 : 4; unsigned dmb$v_parity_err : 1; /*Parity error */ unsigned dmb$v_frame_err : 1; /*Framing error */ unsigned dmb$v_overrun_err : 1; /*Overrun error */ unsigned dmb$v_non_char : 1; /*non character data */ char dmb$b_rx_line; /*Receive line number */ unsigned dmbdef$$_fill_43 : 7; unsigned dmb$v_data_valid : 1; /*Data valid */ } dmb$r_rbuf_bits; } dmb$r_rbuf_overlay; } DMB; #if !defined(__VAXC) #define dmb$l_maint dmb$r_maint_overlay.dmb$l_maint #define dmb$v_force_fail dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_force_fail #define dmb$v_program_reset dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_program_reset #define dmb$v_pte_valid dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_pte_valid #define dmb$v_skip_selftest dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_skip_selftest #define dmb$v_maint_level1 dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_maint_level1 #define dmb$v_maint_level2 dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_maint_level2 #define dmb$v_sync dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_sync #define dmb$v_async dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_async #define dmb$v_print dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_print #define dmb$v_diag_fail dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_diag_fail #define dmb$v_x21_support dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_x21_support #define dmb$v_cable_key dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_cable_key #define dmb$v_turn_conn dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_turn_conn #define dmb$v_manf_conn dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_manf_conn #define dmb$l_acsr dmb$r_acsr_overlay.dmb$l_acsr #define dmb$b_async_ind_add dmb$r_acsr_overlay.dmb$r_acsr_bits.dmb$b_async_ind_add #define dmb$v_rx_i_e dmb$r_acsr_overlay.dmb$r_acsr_bits.dmb$v_rx_i_e #define dmb$v_tx_i_e dmb$r_acsr_overlay.dmb$r_acsr_bits.dmb$v_tx_i_e #define dmb$l_scsr dmb$r_scsr_overlay.dmb$l_scsr #define dmb$b_sync_ind_add dmb$r_scsr_overlay.dmb$r_scsr_bits.dmb$b_sync_ind_add #define dmb$v_sync_i_e dmb$r_scsr_overlay.dmb$r_scsr_bits.dmb$v_sync_i_e #define dmb$l_pcsr dmb$r_pcsr_overlay.dmb$l_pcsr #define dmb$v_pr_i_e dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_i_e #define dmb$v_pr_davfu_ready dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_davfu_ready #define dmb$v_pr_connect_verify dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_connect_verify #define dmb$v_pr_offline dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_offline #define dmb$l_config dmb$r_config_overlay.dmb$l_config #define dmb$b_async_lines dmb$r_config_overlay.dmb$r_config_fields.dmb$b_async_lines #define dmb$b_sync_lines dmb$r_config_overlay.dmb$r_config_fields.dmb$b_sync_lines #define dmb$b_printer_lines dmb$r_config_overlay.dmb$r_config_fields.dmb$b_printer_lines #define dmb$l_acsr2 dmb$r_acsr2_overlay.dmb$l_acsr2 #define dmb$v_async_reset dmb$r_acsr2_overlay.dmb$r_acsr2_bits.dmb$v_async_reset #define dmb$b_rx_timer dmb$r_acsr2_overlay.dmb$r_acsr2_bits.dmb$b_rx_timer #define dmb$l_scsr2 dmb$r_scsr2_overlay.dmb$l_scsr2 #define dmb$v_sync_reset dmb$r_scsr2_overlay.dmb$r_scsr2_bits.dmb$v_sync_reset #define dmb$l_pcsr2 dmb$r_pcsr2_overlay.dmb$l_pcsr2 #define dmb$v_printer_reset dmb$r_pcsr2_overlay.dmb$r_pcsr2_bits.dmb$v_printer_reset #define dmb$l_pfix dmb$r_pfix_overlay.dmb$l_pfix #define dmb$b_prefix_count dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_prefix_count #define dmb$b_prefix_char dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_prefix_char #define dmb$b_suffix_count dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_suffix_count #define dmb$b_suffix_char dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_suffix_char #define dmb$l_pbufct dmb$r_pbufct_overlay.dmb$l_pbufct #define dmb$w_pr_buff_off dmb$r_pbufct_overlay.dmb$r_pbufct_fields.dmb$w_pr_buff_off #define dmb$w_pr_buff_ct dmb$r_pbufct_overlay.dmb$r_pbufct_fields.dmb$w_pr_buff_ct #define dmb$l_pctrl dmb$r_pctrl_overlay.dmb$l_pctrl #define dmb$v_pr_dma_start dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_start #define dmb$v_pr_dma_pte dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_pte #define dmb$v_pr_dma_phys dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_phys #define dmb$v_pr_dma_abort dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_abort #define dmb$v_pr_format dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_format #define dmb$b_pr_error dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$b_pr_error #define dmb$v_pr_tab dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_tab #define dmb$v_pr_trunc dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_trunc #define dmb$v_pr_auto_return dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_auto_return #define dmb$v_pr_auto_form dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_auto_form #define dmb$v_pr_non_print dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_non_print #define dmb$v_pr_davfu dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_davfu #define dmb$v_pr_wrap dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_wrap #define dmb$v_pr_upper dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_upper #define dmb$l_pcar dmb$r_pcar_overlay.dmb$l_pcar #define dmb$w_pr_line dmb$r_pcar_overlay.dmb$r_pcar_fields.dmb$w_pr_line #define dmb$w_pr_char dmb$r_pcar_overlay.dmb$r_pcar_fields.dmb$w_pr_char #define dmb$l_psize dmb$r_psize_overlay.dmb$l_psize #define dmb$w_pr_width dmb$r_psize_overlay.dmb$r_psize_fields.dmb$w_pr_width #define dmb$w_pr_page dmb$r_psize_overlay.dmb$r_psize_fields.dmb$w_pr_page #define dmb$l_tbuffct1 dmb$r_tbuffct1_overlay.dmb$l_tbuffct1 #define dmb$w_tx_buff_off1 dmb$r_tbuffct1_overlay.dmb$r_tbuffct1_fields.dmb$w_tx_buff_off1 #define dmb$w_tx_char_ct1 dmb$r_tbuffct1_overlay.dmb$r_tbuffct1_fields.dmb$w_tx_char_ct1 #define dmb$l_rbuffct1 dmb$r_rbuffct1_overlay.dmb$l_rbuffct1 #define dmb$w_rx_buff_off1 dmb$r_rbuffct1_overlay.dmb$r_rbuffct1_fields.dmb$w_rx_buff_off1 #define dmb$w_rx_char_ct1 dmb$r_rbuffct1_overlay.dmb$r_rbuffct1_fields.dmb$w_rx_char_ct1 #define dmb$l_tlnctrl1 dmb$r_tlnctrl1_overlay.dmb$l_tlnctrl1 #define dmb$v_tx1_dma_start dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_start #define dmb$v_tx1_dma_pte dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_pte #define dmb$v_tx1_dma_phys dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_phys #define dmb$v_tx1_x21 dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_x21 #define dmb$v_tx1_par dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_par #define dmb$v_tx1_dma_abort dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_abort #define dmb$b_tx1_error dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$b_tx1_error #define dmb$l_rlnctrl1 dmb$r_rlnctrl1_overlay.dmb$l_rlnctrl1 #define dmb$v_rx1_dma_start dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_start #define dmb$v_rx1_dma_pte dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_pte #define dmb$v_rx1_dma_phys dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_phys #define dmb$v_rx1_x21 dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_x21 #define dmb$v_rx1_dma_abort dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_abort #define dmb$b_rx1_error dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$b_rx1_error #define dmb$l_lpr1 dmb$r_lpr1_overlay.dmb$l_lpr1 #define dmb$v_rx_enable dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_rx_enable #define dmb$v_rx_match_ena dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_rx_match_ena #define dmb$v_rx_primary dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_rx_primary #define dmb$v_x21enable dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_x21enable #define dmb$v_clock_control dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_clock_control #define dmb$v_coding_type dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_coding_type #define dmb$v_baud_rate dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_baud_rate #define dmb$v_loop dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_loop #define dmb$v_v35_select dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_v35_select #define dmb$v_v10_select dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_v10_select #define dmb$v_modem_suppress dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_modem_suppress #define dmb$b_number_sync dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$b_number_sync #define dmb$v_line_reset dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_line_reset #define dmb$l_lpr2 dmb$r_lpr2_overlay.dmb$l_lpr2 #define dmb$v_sync_ml1 dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_ml1 #define dmb$v_sync_dtr dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_dtr #define dmb$v_sync_drs dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_drs #define dmb$v_sync_ml2 dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_ml2 #define dmb$v_sync_rts dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_rts #define dmb$v_spare_modem dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_spare_modem #define dmb$v_sync_rxclock dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_rxclock #define dmb$v_sync_txclock dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_txclock #define dmb$v_sync_ti dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_ti #define dmb$v_sync_cts dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_cts #define dmb$v_sync_dcd dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_dcd #define dmb$v_sync_ri dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_ri #define dmb$v_sync_dsr dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_dsr #define dmb$v_protocol dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_protocol #define dmb$v_error_type dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_error_type #define dmb$v_rx_bpc dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_rx_bpc #define dmb$v_tx_bpc dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_tx_bpc #define dmb$v_strip_sync dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_strip_sync #define dmb$v_ebcdic_code dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_ebcdic_code #define dmb$v_idle_sync dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_idle_sync #define dmb$v_modem_override dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_modem_override #define dmb$l_tbuffct2 dmb$r_tbuffct2_overlay.dmb$l_tbuffct2 #define dmb$w_tx_buff_off2 dmb$r_tbuffct2_overlay.dmb$r_tbuffct2_fields.dmb$w_tx_buff_off2 #define dmb$w_tx_char_ct2 dmb$r_tbuffct2_overlay.dmb$r_tbuffct2_fields.dmb$w_tx_char_ct2 #define dmb$l_rbuffct2 dmb$r_rbuffct2_overlay.dmb$l_rbuffct2 #define dmb$w_rx_buff_off2 dmb$r_rbuffct2_overlay.dmb$r_rbuffct2_fields.dmb$w_rx_buff_off2 #define dmb$w_rx_char_ct2 dmb$r_rbuffct2_overlay.dmb$r_rbuffct2_fields.dmb$w_rx_char_ct2 #define dmb$l_tlnctrl2 dmb$r_tlnctrl2_overlay.dmb$l_tlnctrl2 #define dmb$v_tx2_dma_start dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_start #define dmb$v_tx2_dma_pte dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_pte #define dmb$v_tx2_dma_phys dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_phys #define dmb$v_tx2_x21 dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_x21 #define dmb$v_tx2_par dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_par #define dmb$v_tx2_dma_abort dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_abort #define dmb$b_tx2_error dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$b_tx2_error #define dmb$l_rlnctrl2 dmb$r_rlnctrl2_overlay.dmb$l_rlnctrl2 #define dmb$v_rx2_dma_start dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_start #define dmb$v_rx2_dma_pte dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_pte #define dmb$v_rx2_dma_phys dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_phys #define dmb$v_rx2_x21 dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_x21 #define dmb$v_rx2_dma_abort dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_abort #define dmb$b_rx2_error dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$b_rx2_error #define dmb$l_lpr3 dmb$r_lpr3_overlay.dmb$l_lpr3 #define dmb$b_sync_char dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_sync_char #define dmb$b_rx_match dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_rx_match #define dmb$b_address1 dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_address1 #define dmb$b_address2 dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_address2 #define dmb$l_bufctrl dmb$r_bufctrl_overlay.dmb$l_bufctrl #define dmb$b_tx_buff_prio dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$b_tx_buff_prio #define dmb$b_rx_buff_prio dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$b_rx_buff_prio #define dmb$b_sync_test_input dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$b_sync_test_input #define dmb$v_sync_cable dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_cable #define dmb$v_sync_loop dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_loop #define dmb$v_sync_valid dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_valid #define dmb$v_sync_x21 dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_x21 #define dmb$l_preempt dmb$r_preempt_overlay.dmb$l_preempt #define dmb$b_preempt_char dmb$r_preempt_overlay.dmb$r_preempt_bits.dmb$b_preempt_char #define dmb$v_preempt_go dmb$r_preempt_overlay.dmb$r_preempt_bits.dmb$v_preempt_go #define dmb$l_tbuffct dmb$r_tbuffct_overlay.dmb$l_tbuffct #define dmb$w_tx_buff_off dmb$r_tbuffct_overlay.dmb$r_tbuffct_fields.dmb$w_tx_buff_off #define dmb$w_tx_char_ct dmb$r_tbuffct_overlay.dmb$r_tbuffct_fields.dmb$w_tx_char_ct #define dmb$l_lpr dmb$r_lpr_overlay.dmb$l_lpr #define dmb$v_ml dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_ml #define dmb$v_dtr dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_dtr #define dmb$v_drs dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_drs #define dmb$v_rts dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_rts #define dmb$v_tx_int_delay dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_tx_int_delay #define dmb$v_rx_ena dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_rx_ena #define dmb$v_break dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_break #define dmb$v_maint dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_maint #define dmb$v_report_modem dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_report_modem #define dmb$v_discard_flow dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_discard_flow #define dmb$v_char_length dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_char_length #define dmb$v_parity_enab dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_parity_enab #define dmb$v_even_parity dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_even_parity #define dmb$v_stop_code dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_stop_code #define dmb$v_use_cts dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_use_cts #define dmb$v_iauto_flow dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_iauto_flow #define dmb$v_oauto_flow dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_oauto_flow #define dmb$v_rx_speed dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_rx_speed #define dmb$v_tx_speed dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_tx_speed #define dmb$l_lnctrl dmb$r_lnctrl_overlay.dmb$l_lnctrl #define dmb$v_tx_dma_start dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_dma_start #define dmb$v_tx_dma_pte dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_dma_pte #define dmb$v_tx_dma_phys dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_dma_phys #define dmb$v_tx_out_abort dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_out_abort #define dmb$b_tx_error dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$b_tx_error #define dmb$l_lstat dmb$r_lstat_overlay.dmb$l_lstat #define dmb$v_ml2 dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_ml2 #define dmb$v_cts dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_cts #define dmb$v_dcd dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_dcd #define dmb$v_ri dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_ri #define dmb$v_dsr dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_dsr #define dmb$v_sndoff dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_sndoff #define dmb$v_tx_ena dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_tx_ena #define dmb$l_flowc dmb$r_flowc_overlay.dmb$l_flowc #define dmb$b_sent_xoff dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_sent_xoff #define dmb$b_sent_xon dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_sent_xon #define dmb$b_received_xoff dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_received_xoff #define dmb$b_received_xon dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_received_xon #define dmb$l_tbuf dmb$r_tbuf_overlay.dmb$l_tbuf #define dmb$b_tx_line dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$b_tx_line #define dmb$v_tx_preempt dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$v_tx_preempt #define dmb$v_tx_fifo_done dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$v_tx_fifo_done #define dmb$b_tx_dma_error dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$b_tx_dma_error #define dmb$v_tx_act dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$v_tx_act #define dmb$l_sbuf dmb$r_sbuf_overlay.dmb$l_sbuf #define dmb$b_sync_line dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$b_sync_line #define dmb$v_sync_modem dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sync_modem #define dmb$v_sync_tx_act dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sync_tx_act #define dmb$v_sync_second_buffer dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sync_second_buffer #define dmb$v_sbuf_spare dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sbuf_spare #define dmb$r_sbuf_x dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$r_sbuf_x #define dmb$b_sync_modem_status dmb$r_sbuf_x.dmb$b_sync_modem_status #define dmb$b_sync_error dmb$r_sbuf_x.dmb$b_sync_error #define dmb$l_rbuf dmb$r_rbuf_overlay.dmb$l_rbuf #define dmb$b_rxchar dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$b_rxchar #define dmb$v_parity_err dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_parity_err #define dmb$v_frame_err dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_frame_err #define dmb$v_overrun_err dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_overrun_err #define dmb$v_non_char dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_non_char #define dmb$b_rx_line dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$b_rx_line #define dmb$v_data_valid dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_data_valid #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __DMBDEF_LOADED */