/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:27:04 by OpenVMS SDL EV3-3 */ /* Source: 21-JUL-1993 13:29:52 $1$DGA7274:[LIB_H.SRC]COREIODEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $COREIODEF ***/ #ifndef __COREIODEF_LOADED #define __COREIODEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define COREIO$M_LDP_DMA_PA_LO 0xFFFE0 #define COREIO$M_LDP_DMA_PA_HI 0xFFF00000 #define COREIO$M_SCOMM_TR_DMA_PA 0xFFFFFFE0 #define COREIO$M_SCOMM_RC_DMA_PA 0xFFFFFFE0 #define COREIO$M_PRINTER_TR_DMA_PA 0xFFFFFFE0 #define COREIO$M_PRINTER_RC_DMA_PA 0xFFFFFFE0 #define COREIO$M_ISDN_TR_DMA_PA 0xFFFFFFE0 #define COREIO$M_ISDN_TR_BUF_DMA_PA 0xFFFFFFE0 #define COREIO$M_ISDN_RC_DMA_PA 0xFFFFFFE0 #define COREIO$M_ISDN_RC_BUF_DMA_PA 0xFFFFFFE0 #define COREIO$M_SSR_GPO_0 0x1 #define COREIO$M_SSR_GPO_1 0x2 #define COREIO$M_SSR_GPO_2 0x4 #define COREIO$M_SSR_GPO_3 0x8 #define COREIO$M_SSR_GPO_4 0x10 #define COREIO$M_SSR_GPO_5 0x20 #define COREIO$M_SSR_GPO_6 0x40 #define COREIO$M_SSR_GPO_7 0x80 #define COREIO$M_SSR_GPO_8 0x100 #define COREIO$M_SSR_GPO_9 0x200 #define COREIO$M_SSR_GPO_10 0x400 #define COREIO$M_SSR_GPO_11 0x800 #define COREIO$M_SSR_GPO_12 0x1000 #define COREIO$M_SSR_GPO_13 0x2000 #define COREIO$M_SSR_GPO_14 0x4000 #define COREIO$M_SSR_GPO_15 0x8000 #define COREIO$M_SSR_LANCE_DMA_EN 0x10000 #define COREIO$M_SSR_SCSI_DMA_EN 0x20000 #define COREIO$M_SSR_SCSI_DMA_DIR 0x40000 #define COREIO$M_SSR_ISDN_RCV_EN 0x80000 #define COREIO$M_SSR_ISDN_TR_EN 0x100000 #define COREIO$M_SSR_FLOPPY_DMA_EN 0x200000 #define COREIO$M_SSR_FLOPPY_DMA_DIR 0x400000 #define COREIO$M_SSR_SCC1_RC_DMA_EN 0x10000000 #define COREIO$M_SSR_SCC1_TR_DMA_EN 0x20000000 #define COREIO$M_SSR_SCC0_RC_DMA_EN 0x40000000 #define COREIO$M_SSR_SCC0_TR_DMA_EN 0x80000000 #define COREIO$M_SSR_LEDS 0xFF #define COREIO$M_SSR_LANCE_RESET 0x100 #define COREIO$M_SSR_RTC_RESET 0x400 #define COREIO$M_SSR_SSC_RESET 0x800 #define COREIO$M_SSR_ISDN_RESET 0x1000 #define COREIO$M_SSR_10BASET_SEL 0x2000 #define COREIO$M_SSR_NI_LOOPBACK 0x4000 #define COREIO$M_SSR_TXDIS 0x8000 #define COREIO$M_SSR_ISDN_RC_DMA_EN 0x80000 #define COREIO$M_SSR_ISDN_TR_DMA_EN 0x100000 #define COREIO$M_SSR_PRINTER_RC_DMA_EN 0x10000000 #define COREIO$M_SSR_PRINTER_TR_DMA_EN 0x20000000 #define COREIO$M_SSR_COMM_RC_DMA_EN 0x40000000 #define COREIO$M_SSR_COMM_TR_DMA_EN 0x80000000 #define COREIO$M_SSR_IO_MASK 0xF #define COREIO$M_SSR_IO_MASK_EN 0x10 #define COREIO$M_SSR_FPE 0x80 #define COREIO$M_SSR_SMR0 0x1000000 #define COREIO$M_SSR_SMR1 0x2000000 #define COREIO$M_SSR_SMRA 0x4000000 #define COREIO$M_SSR_FAST_MODE 0x8000000 #define COREIO$M_SSR_KBD_RC_DMA_EN 0x10000000 #define COREIO$M_SSR_KBD_TR_DMA_EN 0x20000000 #define COREIO$C_SIR 544 /* A constant for C programmers - defines offset of SIR structure */ #define COREIO$M_SIR_GP_INT_0 0x1 #define COREIO$M_SIR_GP_INT_1 0x2 #define COREIO$M_SIR_GP_INT_2 0x4 #define COREIO$M_SIR_GP_INT_3 0x8 #define COREIO$M_SIR_GP_INT_4 0x10 #define COREIO$M_SIR_GP_INT_5 0x20 #define COREIO$M_SIR_GP_INT_6 0x40 #define COREIO$M_SIR_GP_INT_7 0x80 #define COREIO$M_SIR_GP_INT_8 0x100 #define COREIO$M_SIR_GP_INT_9 0x200 #define COREIO$M_SIR_GP_INT_10 0x400 #define COREIO$M_SIR_GP_INT_11 0x800 #define COREIO$M_SIR_GP_INT_12 0x1000 #define COREIO$M_SIR_GP_INT_13 0x2000 #define COREIO$M_SIR_GP_INT_14 0x4000 #define COREIO$M_SIR_GP_INT_15 0x8000 #define COREIO$M_SIR_LANCE_DMA_ER 0x10000 #define COREIO$M_SIR_SCSI_DMA_MRE 0x20000 #define COREIO$M_SIR_SCSI_DMA_OV 0x40000 #define COREIO$M_SIR_SCSI_DMA_PTR 0x80000 #define COREIO$M_SIR_ISDN_DMA_MRE 0x100000 #define COREIO$M_SIR_ISDN_DMA_RC_INTR 0x200000 #define COREIO$M_SIR_ISDN_DMA_TR_INTR 0x400000 #define COREIO$M_SIR_FLOPPY_DMA_INT 0x800000 #define COREIO$M_SIR_SCC1_DMA_OV 0x1000000 #define COREIO$M_SIR_SCC1_RCV_INT 0x2000000 #define COREIO$M_SIR_SCC1_TR_DMA_ME 0x4000000 #define COREIO$M_SIR_SCC1_TR_INT 0x8000000 #define COREIO$M_SIR_SCC0_DMA_OV 0x10000000 #define COREIO$M_SIR_SCC0_RCV_INT 0x20000000 #define COREIO$M_SIR_SCC0_TR_DMA_ME 0x40000000 #define COREIO$M_SIR_SCC0_TR_INT 0x80000000 #define COREIO$M_SIR_HALT0 0x1 #define COREIO$M_SIR_HALT1 0x2 #define COREIO$M_SIR_ALT_CONSOLE 0x8 #define COREIO$M_SIR_SCC0_SI 0x40 #define COREIO$M_SIR_SCC1_SI 0x80 #define COREIO$M_SIR_NI_INTR 0x100 #define COREIO$M_SIR_ISDN_INTR 0x2000 #define COREIO$M_SIR_LANCE_DMA_RE 0x10000 #define COREIO$M_SIR_PP_RC_DMA_OVR 0x1000000 #define COREIO$M_SIR_PP_RC_HP_INTR 0x2000000 #define COREIO$M_SIR_PP_TR_DMA_MRE 0x4000000 #define COREIO$M_SIR_PP_TR_PE_INTR 0x8000000 #define COREIO$M_SIR_COMM_RC_DMA_OVR 0x10000000 #define COREIO$M_SIR_COMM_RC_HP_INTR 0x20000000 #define COREIO$M_SIR_COMM_TR_DMA_MRE 0x40000000 #define COREIO$M_SIR_COMM_TR_PE_INTR 0x80000000 #define COREIO$M_SIR_TC_SLOT0 0x4 #define COREIO$M_SIR_TC_SLOT1 0x8 #define COREIO$M_SIR_SCC0_INT 0x40 #define COREIO$M_SIR_SCC1_INT 0x80 #define COREIO$M_SIR_LANCE_INT 0x100 #define COREIO$M_SIR_ISDN_INT 0x2000 #define COREIO$M_SIR_CONS_SEL 0x8000 #define COREIO$C_SIMR 576 /* A constant for C programmers - defines offset of SIMR structure */ #define COREIO$M_SIMR_GP_INT_0 0x1 #define COREIO$M_SIMR_GP_INT_1 0x2 #define COREIO$M_SIMR_GP_INT_2 0x4 #define COREIO$M_SIMR_GP_INT_3 0x8 #define COREIO$M_SIMR_GP_INT_4 0x10 #define COREIO$M_SIMR_GP_INT_5 0x20 #define COREIO$M_SIMR_GP_INT_6 0x40 #define COREIO$M_SIMR_GP_INT_7 0x80 #define COREIO$M_SIMR_GP_INT_8 0x100 #define COREIO$M_SIMR_GP_INT_9 0x200 #define COREIO$M_SIMR_GP_INT_10 0x400 #define COREIO$M_SIMR_GP_INT_11 0x800 #define COREIO$M_SIMR_GP_INT_12 0x1000 #define COREIO$M_SIMR_GP_INT_13 0x2000 #define COREIO$M_SIMR_GP_INT_14 0x4000 #define COREIO$M_SIMR_GP_INT_15 0x8000 #define COREIO$M_SIMR_LANCE_DMA_ER 0x10000 #define COREIO$M_SIMR_SCSI_DMA_MRE 0x20000 #define COREIO$M_SIMR_SCSI_DMA_OV 0x40000 #define COREIO$M_SIMR_SCSI_DMA_PTR 0x80000 #define COREIO$M_SIMR_ISDN_DMA_MRE 0x100000 #define COREIO$M_SIMR_ISDN_DMA_RC_INTR 0x200000 #define COREIO$M_SIMR_ISDN_DMA_TR_INTR 0x400000 #define COREIO$M_SIMR_FLOPPY_DMA_INT 0x800000 #define COREIO$M_SIMR_SCC1_DMA_OV 0x1000000 #define COREIO$M_SIMR_SCC1_RCV_INT 0x2000000 #define COREIO$M_SIMR_SCC1_TR_DMA_ME 0x4000000 #define COREIO$M_SIMR_SCC1_TR_INT 0x8000000 #define COREIO$M_SIMR_SCC0_DMA_OV 0x10000000 #define COREIO$M_SIMR_SCC0_RCV_INT 0x20000000 #define COREIO$M_SIMR_SCC0_TR_DMA_ME 0x40000000 #define COREIO$M_SIMR_SCC0_TR_INT 0x80000000 #define COREIO$M_SIMR_HALT0 0x1 #define COREIO$M_SIMR_HALT1 0x2 #define COREIO$M_SIMR_ALT_CONSOLE 0x8 #define COREIO$M_SIMR_SCC0_SI 0x40 #define COREIO$M_SIMR_SCC1_SI 0x80 #define COREIO$M_SIMR_NI_INTR 0x100 #define COREIO$M_SIMR_ISDN_INTR 0x2000 #define COREIO$M_SIMR_LANCE_DMA_RE 0x10000 #define COREIO$M_SIMR_PP_RC_DMA_OVR 0x1000000 #define COREIO$M_SIMR_PP_RC_HP_INTR 0x2000000 #define COREIO$M_SIMR_PP_TR_DMA_MRE 0x4000000 #define COREIO$M_SIMR_PP_TR_PE_INTR 0x8000000 #define COREIO$M_SIMR_COMM_RC_DMA_OVR 0x10000000 #define COREIO$M_SIMR_COMM_RC_HP_INTR 0x20000000 #define COREIO$M_SIMR_COMM_TR_DMA_MRE 0x40000000 #define COREIO$M_SIMR_COMM_TR_PE_INTR 0x80000000 #define COREIO$M_SIMR_TC_SLOT0 0x4 #define COREIO$M_SIMR_TC_SLOT1 0x8 #define COREIO$M_SIMR_SCC0_INT 0x40 #define COREIO$M_SIMR_SCC1_INT 0x80 #define COREIO$M_SIMR_LANCE_INT 0x100 #define COREIO$M_SIMR_ISDN_INT 0x2000 #define COREIO$M_SIMR_CONS_SEL 0x8000 #define COREIO$M_SADR_TC_ADDR 0x1FFFFE0 #define COREIO$M_ISDN_DATA_TR_DATA 0xFFFFFF #define COREIO$M_ISDN_DATA_RC_DATA 0xFFFFFF #define COREIO$M_LANCE_SLOT_CS 0xF #define COREIO$M_LANCE_SLOT_HW_ADDR 0x3F0 #define COREIO$M_SCC0_SLOT_CS 0xF #define COREIO$M_SCC0_SLOT_HW_ADDR 0x3F0 #define COREIO$M_SCC1_SLOT_CS 0xF #define COREIO$M_SCC1_SLOT_HW_ADDR 0x3F0 #define COREIO$C_ISDN_AUDIO 49152 /* A constant for C programmers - defines offset of ISDN CSR */ #define COREIO$Q_TC_NUMBER 1 /* High nibble of addr */ #define COREIO$Q_SLOT0_DENSE_BASE 0 /* base PA of TC slot 0 */ #define COREIO$Q_SLOT1_DENSE_BASE 536870912 /* base PA of TC slot 1 */ #define COREIO$Q_SLOT2_DENSE_BASE 1073741824 /* base PA of TC slot 2 */ #define COREIO$Q_SLOT3_DENSE_BASE 1610612736 /* base PA of TC slot 3 */ #define COREIO$Q_SLOT4_DENSE_BASE -2147483648 /* base PA of TC slot 4 */ #define COREIO$Q_SLOT5_DENSE_BASE -1610612736 /* base PA of TC slot 5 */ #define COREIO$Q_LANCE_RAP 1572872 /* PA of LANCE RAP reg */ #define COREIO$Q_LANCE_RDP_DENSE 786432 /* PA of LANCE RDP reg */ #define COREIO$Q_NI_ADR_ROM_DENSE 524288 /* PA of NI ADR ROM */ #define COREIO$Q_LDP_DENSE 262176 /* PA of LDP reg */ #define COREIO$Q_LANCE_SLOT 524992 /* PA of lance slot */ #define COREIO$Q_SSR 524800 /* SSR reg */ #define COREIO$Q_SIR 524832 /* SIR reg */ #define COREIO$Q_SIMR 524848 /* SIMR reg */ #define COREIO$S_COREIODEF 57344 /* Old COREIO size field for compatibility */ typedef struct _coreio { void *coreio$l_ioctl_csr; /* Core I/O base CSR address */ unsigned char coreio$b_fill560 [60]; __union { unsigned int coreio$l_ldp; /* Ethernet Lance DMA pointer */ __struct { unsigned coreio$v_ldp_fill1 : 5; unsigned coreio$v_ldp_dma_pa_lo : 15; unsigned coreio$v_ldp_dma_pa_hi : 12; } coreio$r_ldp_bits; } coreio$r_ldp_overlay; unsigned char coreio$b_fill570 [28]; __union { unsigned int coreio$l_scomm_tr; /* Serial comm transmit port 1 DMA pointer */ __struct { unsigned coreio$v_scomm_tr_fill1 : 5; unsigned coreio$v_scomm_tr_dma_pa : 27; } coreio$r_scomm_tr_bits; } coreio$r_scomm_tr_overlay; unsigned char coreio$b_fill580 [28]; __union { unsigned int coreio$l_scomm_rc; /* Serial comm receive port 1 DMA pointer */ __struct { unsigned coreio$v_scomm_rc_fill1 : 5; unsigned coreio$v_scomm_rc_dma_pa : 27; } coreio$r_scomm_rc_bits; } coreio$r_scomm_rc_overlay; unsigned char coreio$b_fill590 [28]; __union { unsigned int coreio$l_printer_tr; /* Printer transmit port DMA pointer */ __struct { unsigned coreio$v_printer_tr_fill1 : 5; unsigned coreio$v_printer_tr_dma_pa : 27; } coreio$r_printer_tr_bits; } coreio$r_printer_tr_overlay; unsigned char coreio$b_fill600 [28]; __union { unsigned int coreio$l_printer_rc; /* Printer receive port DMA pointer */ __struct { unsigned coreio$v_printer_rc_fill1 : 5; unsigned coreio$v_printer_rc_dma_pa : 27; } coreio$r_printer_rc_bits; } coreio$r_printer_rc_overlay; unsigned char coreio$b_fill610 [60]; __union { unsigned int coreio$l_isdn_tr; /* ISDN transmit DMA pointer */ __struct { unsigned coreio$v_isdn_tr_fill1 : 5; unsigned coreio$v_isdn_tr_dma_pa : 27; } coreio$r_isdn_tr_bits; } coreio$r_isdn_tr_overlay; unsigned char coreio$b_fill620 [28]; __union { unsigned int coreio$l_isdn_tr_buf; /* ISDN transmit DMA buffer pointer */ __struct { unsigned coreio$v_isdn_tr_buf_fill1 : 5; unsigned coreio$v_isdn_tr_buf_dma_pa : 27; } coreio$r_isdn_tr_buf_bits; } coreio$r_isdn_tr_buf_overlay; unsigned char coreio$b_fill630 [28]; __union { unsigned int coreio$l_isdn_rc; /* ISDN receive DMA pointer */ __struct { unsigned coreio$v_isdn_rc_fill1 : 5; unsigned coreio$v_isdn_rc_dma_pa : 27; } coreio$r_isdn_rc_bits; } coreio$r_isdn_rc_overlay; unsigned char coreio$b_fill640 [28]; __union { unsigned int coreio$l_isdn_rc_buf; /* ISDN receive DMA buffer pointer */ __struct { unsigned coreio$v_isdn_rc_buf_fill1 : 5; unsigned coreio$v_isdn_rc_buf_dma_pa : 27; } coreio$r_isdn_rc_buf_bits; } coreio$r_isdn_rc_buf_overlay; unsigned char coreio$b_fill650 [28]; unsigned int coreio$l_data0; /* System Data Buffer 0 */ unsigned char coreio$b_fill660 [28]; unsigned int coreio$l_data1; /* System Data Buffer 1 */ unsigned char coreio$b_fill670 [28]; unsigned int coreio$l_data2; /* System Data Buffer 2 */ unsigned char coreio$b_fill680 [28]; unsigned int coreio$l_data3; /* System Data Buffer 3 */ unsigned char coreio$b_fill690 [28]; __union { unsigned int coreio$l_ssr; /* System support register */ __struct { unsigned coreio$v_ssr_gpo_0 : 1; unsigned coreio$v_ssr_gpo_1 : 1; unsigned coreio$v_ssr_gpo_2 : 1; unsigned coreio$v_ssr_gpo_3 : 1; unsigned coreio$v_ssr_gpo_4 : 1; unsigned coreio$v_ssr_gpo_5 : 1; unsigned coreio$v_ssr_gpo_6 : 1; unsigned coreio$v_ssr_gpo_7 : 1; unsigned coreio$v_ssr_gpo_8 : 1; unsigned coreio$v_ssr_gpo_9 : 1; unsigned coreio$v_ssr_gpo_10 : 1; unsigned coreio$v_ssr_gpo_11 : 1; unsigned coreio$v_ssr_gpo_12 : 1; unsigned coreio$v_ssr_gpo_13 : 1; unsigned coreio$v_ssr_gpo_14 : 1; unsigned coreio$v_ssr_gpo_15 : 1; unsigned coreio$v_ssr_lance_dma_en : 1; unsigned coreio$v_ssr_scsi_dma_en : 1; unsigned coreio$v_ssr_scsi_dma_dir : 1; unsigned coreio$v_ssr_isdn_rcv_en : 1; unsigned coreio$v_ssr_isdn_tr_en : 1; unsigned coreio$v_ssr_floppy_dma_en : 1; unsigned coreio$v_ssr_floppy_dma_dir : 1; unsigned coreio$v_ssr_fill5 : 5; unsigned coreio$v_ssr_scc1_rc_dma_en : 1; unsigned coreio$v_ssr_scc1_tr_dma_en : 1; unsigned coreio$v_ssr_scc0_rc_dma_en : 1; unsigned coreio$v_ssr_scc0_tr_dma_en : 1; } coreio$r_ssr_bits; __struct { /* Flamingo specific bits */ unsigned coreio$v_ssr_leds : 8; unsigned coreio$v_ssr_lance_reset : 1; unsigned coreio$v_ssr_fill_04_1 : 1; unsigned coreio$v_ssr_rtc_reset : 1; unsigned coreio$v_ssr_ssc_reset : 1; unsigned coreio$v_ssr_isdn_reset : 1; unsigned coreio$v_ssr_10baset_sel : 1; unsigned coreio$v_ssr_ni_loopback : 1; unsigned coreio$v_ssr_txdis : 1; unsigned coreio$v_ssr_fill_04_3 : 3; unsigned coreio$v_ssr_isdn_rc_dma_en : 1; unsigned coreio$v_ssr_isdn_tr_dma_en : 1; unsigned coreio$v_ssr_fill_04_4 : 2; unsigned coreio$v_ssr_fill_04_5 : 5; unsigned coreio$v_ssr_printer_rc_dma_en : 1; unsigned coreio$v_ssr_printer_tr_dma_en : 1; unsigned coreio$v_ssr_comm_rc_dma_en : 1; unsigned coreio$v_ssr_comm_tr_dma_en : 1; } coreio$r_ssr_04_bits; __struct { /* Pelican specific bits */ unsigned coreio$v_ssr_io_mask : 4; unsigned coreio$v_ssr_io_mask_en : 1; unsigned coreio$v_ssr_sys_ok_led : 1; unsigned coreio$v_ssr_fill_07_1 : 1; unsigned coreio$v_ssr_fpe : 1; unsigned coreio$v_ssr_fill_07_3 : 16; unsigned coreio$v_ssr_smr0 : 1; unsigned coreio$v_ssr_smr1 : 1; unsigned coreio$v_ssr_smra : 1; unsigned coreio$v_ssr_fast_mode : 1; unsigned coreio$v_ssr_kbd_rc_dma_en : 1; unsigned coreio$v_ssr_kbd_tr_dma_en : 1; unsigned coreio$v_ssr_fill_07_4 : 2; } coreio$r_ssr_07_bits; } coreio$r_ssr_overlay; unsigned char coreio$b_fill700 [28]; __union { unsigned int coreio$l_sir; /* System interrupt register */ __struct { unsigned coreio$v_sir_gp_int_0 : 1; unsigned coreio$v_sir_gp_int_1 : 1; unsigned coreio$v_sir_gp_int_2 : 1; unsigned coreio$v_sir_gp_int_3 : 1; unsigned coreio$v_sir_gp_int_4 : 1; unsigned coreio$v_sir_gp_int_5 : 1; unsigned coreio$v_sir_gp_int_6 : 1; unsigned coreio$v_sir_gp_int_7 : 1; unsigned coreio$v_sir_gp_int_8 : 1; unsigned coreio$v_sir_gp_int_9 : 1; unsigned coreio$v_sir_gp_int_10 : 1; unsigned coreio$v_sir_gp_int_11 : 1; unsigned coreio$v_sir_gp_int_12 : 1; unsigned coreio$v_sir_gp_int_13 : 1; unsigned coreio$v_sir_gp_int_14 : 1; unsigned coreio$v_sir_gp_int_15 : 1; unsigned coreio$v_sir_lance_dma_er : 1; unsigned coreio$v_sir_scsi_dma_mre : 1; unsigned coreio$v_sir_scsi_dma_ov : 1; unsigned coreio$v_sir_scsi_dma_ptr : 1; unsigned coreio$v_sir_isdn_dma_mre : 1; unsigned coreio$v_sir_isdn_dma_rc_intr : 1; unsigned coreio$v_sir_isdn_dma_tr_intr : 1; unsigned coreio$v_sir_floppy_dma_int : 1; unsigned coreio$v_sir_scc1_dma_ov : 1; unsigned coreio$v_sir_scc1_rcv_int : 1; unsigned coreio$v_sir_scc1_tr_dma_me : 1; unsigned coreio$v_sir_scc1_tr_int : 1; unsigned coreio$v_sir_scc0_dma_ov : 1; unsigned coreio$v_sir_scc0_rcv_int : 1; unsigned coreio$v_sir_scc0_tr_dma_me : 1; unsigned coreio$v_sir_scc0_tr_int : 1; } coreio$r_sir_bits; __struct { /* Flamingo specific bits */ unsigned coreio$v_sir_halt0 : 1; unsigned coreio$v_sir_halt1 : 1; unsigned coreio$v_sir_fill_04_1 : 1; unsigned coreio$v_sir_alt_console : 1; unsigned coreio$v_sir_fill_04_2 : 2; unsigned coreio$v_sir_scc0_si : 1; unsigned coreio$v_sir_scc1_si : 1; unsigned coreio$v_sir_ni_intr : 1; unsigned coreio$v_sir_fill_04_3 : 4; unsigned coreio$v_sir_isdn_intr : 1; unsigned coreio$v_sir_fill_04_4 : 2; unsigned coreio$v_sir_lance_dma_re : 1; unsigned coreio$v_sir_fill_04_5 : 7; unsigned coreio$v_sir_pp_rc_dma_ovr : 1; unsigned coreio$v_sir_pp_rc_hp_intr : 1; unsigned coreio$v_sir_pp_tr_dma_mre : 1; unsigned coreio$v_sir_pp_tr_pe_intr : 1; unsigned coreio$v_sir_comm_rc_dma_ovr : 1; unsigned coreio$v_sir_comm_rc_hp_intr : 1; unsigned coreio$v_sir_comm_tr_dma_mre : 1; unsigned coreio$v_sir_comm_tr_pe_intr : 1; } coreio$r_sir_04_bits; __struct { /* Pelican specific bits */ unsigned coreio$v_sir_fill_07_1 : 2; unsigned coreio$v_sir_tc_slot0 : 1; unsigned coreio$v_sir_tc_slot1 : 1; unsigned coreio$v_sir_fill_07_1a : 2; unsigned coreio$v_sir_scc0_int : 1; unsigned coreio$v_sir_scc1_int : 1; unsigned coreio$v_sir_lance_int : 1; unsigned coreio$v_sir_fill_07_2 : 4; unsigned coreio$v_sir_isdn_int : 1; unsigned coreio$v_sir_fill_07_3 : 1; unsigned coreio$v_sir_cons_sel : 1; unsigned coreio$v_sir_fill_07_4 : 16; } coreio$r_sir_07__bits; } coreio$r_sir_overlay; unsigned char coreio$b_fill710 [28]; __union { unsigned int coreio$l_simr; /* System interrupt mask register */ __struct { unsigned coreio$v_simr_gp_int_0 : 1; unsigned coreio$v_simr_gp_int_1 : 1; unsigned coreio$v_simr_gp_int_2 : 1; unsigned coreio$v_simr_gp_int_3 : 1; unsigned coreio$v_simr_gp_int_4 : 1; unsigned coreio$v_simr_gp_int_5 : 1; unsigned coreio$v_simr_gp_int_6 : 1; unsigned coreio$v_simr_gp_int_7 : 1; unsigned coreio$v_simr_gp_int_8 : 1; unsigned coreio$v_simr_gp_int_9 : 1; unsigned coreio$v_simr_gp_int_10 : 1; unsigned coreio$v_simr_gp_int_11 : 1; unsigned coreio$v_simr_gp_int_12 : 1; unsigned coreio$v_simr_gp_int_13 : 1; unsigned coreio$v_simr_gp_int_14 : 1; unsigned coreio$v_simr_gp_int_15 : 1; unsigned coreio$v_simr_lance_dma_er : 1; unsigned coreio$v_simr_scsi_dma_mre : 1; unsigned coreio$v_simr_scsi_dma_ov : 1; unsigned coreio$v_simr_scsi_dma_ptr : 1; unsigned coreio$v_simr_isdn_dma_mre : 1; unsigned coreio$v_simr_isdn_dma_rc_intr : 1; unsigned coreio$v_simr_isdn_dma_tr_intr : 1; unsigned coreio$v_simr_floppy_dma_int : 1; unsigned coreio$v_simr_scc1_dma_ov : 1; unsigned coreio$v_simr_scc1_rcv_int : 1; unsigned coreio$v_simr_scc1_tr_dma_me : 1; unsigned coreio$v_simr_scc1_tr_int : 1; unsigned coreio$v_simr_scc0_dma_ov : 1; unsigned coreio$v_simr_scc0_rcv_int : 1; unsigned coreio$v_simr_scc0_tr_dma_me : 1; unsigned coreio$v_simr_scc0_tr_int : 1; } coreio$r_simr_bits; __struct { /* Flamingo specific bits */ unsigned coreio$v_simr_halt0 : 1; unsigned coreio$v_simr_halt1 : 1; unsigned coreio$v_simr_fill_04_1 : 1; unsigned coreio$v_simr_alt_console : 1; unsigned coreio$v_simr_fill_04_2 : 2; unsigned coreio$v_simr_scc0_si : 1; unsigned coreio$v_simr_scc1_si : 1; unsigned coreio$v_simr_ni_intr : 1; unsigned coreio$v_simr_fill_04_3 : 4; unsigned coreio$v_simr_isdn_intr : 1; unsigned coreio$v_simr_fill_04_4 : 2; unsigned coreio$v_simr_lance_dma_re : 1; unsigned coreio$v_simr_fill_04_5 : 7; unsigned coreio$v_simr_pp_rc_dma_ovr : 1; unsigned coreio$v_simr_pp_rc_hp_intr : 1; unsigned coreio$v_simr_pp_tr_dma_mre : 1; unsigned coreio$v_simr_pp_tr_pe_intr : 1; unsigned coreio$v_simr_comm_rc_dma_ovr : 1; unsigned coreio$v_simr_comm_rc_hp_intr : 1; unsigned coreio$v_simr_comm_tr_dma_mre : 1; unsigned coreio$v_simr_comm_tr_pe_intr : 1; } coreio$r_simr_04_bits; __struct { /* Pelican specific bits */ unsigned coreio$v_simr_fill_07_1 : 2; unsigned coreio$v_simr_tc_slot0 : 1; unsigned coreio$v_simr_tc_slot1 : 1; unsigned coreio$v_simr_fill_07_1a : 2; unsigned coreio$v_simr_scc0_int : 1; unsigned coreio$v_simr_scc1_int : 1; unsigned coreio$v_simr_lance_int : 1; unsigned coreio$v_simr_fill_07_2 : 4; unsigned coreio$v_simr_isdn_int : 1; unsigned coreio$v_simr_fill_07_3 : 1; unsigned coreio$v_simr_cons_sel : 1; unsigned coreio$v_simr_fill_07_4 : 16; } coreio$r_simr_07__bits; } coreio$r_simr_overlay; unsigned char coreio$b_fill720 [28]; __union { unsigned int coreio$l_sadr; /* System address register */ __struct { unsigned coreio$v_sadr_fill1 : 5; unsigned coreio$v_sadr_tc_addr : 20; unsigned coreio$v_sadr_fill2 : 7; } coreio$r_sadr_bits; } coreio$r_sadr_overlay; unsigned char coreio$b_fill730 [28]; __union { unsigned int coreio$l_isdn_data_tr; /* ISDN Data Transmit */ __struct { unsigned coreio$v_isdn_data_tr_data : 24; unsigned coreio$v_isdn_data_tr_fill : 8; } coreio$r_isdn_data_tr_bits; } coreio$r_isdn_data_tr_overlay; unsigned char coreio$b_fill740 [28]; __union { unsigned int coreio$l_isdn_data_rc; /* ISDN Data Receive */ __struct { unsigned coreio$v_isdn_data_rc_data : 24; unsigned coreio$v_isdn_data_rc_fill : 8; } coreio$r_isdn_data_rc_bits; } coreio$r_isdn_data_rc_overlay; unsigned char coreio$b_fill750 [28]; __union { unsigned int coreio$l_lance_slot; /* Lance slot register */ __struct { unsigned coreio$v_lance_slot_cs : 4; unsigned coreio$v_lance_slot_hw_addr : 6; unsigned coreio$v_lance_slot_fill : 22; } coreio$r_lance_slot_bits; } coreio$r_lance_slot_overlay; unsigned char coreio$b_fill760 [60]; __union { unsigned int coreio$l_scc0_slot; /* SCC0 slot register */ __struct { unsigned coreio$v_scc0_slot_cs : 4; unsigned coreio$v_scc0_slot_hw_addr : 6; unsigned coreio$v_scc0_slot_fill : 22; } coreio$r_scc0_slot_bits; } coreio$r_scc0_slot_overlay; unsigned char coreio$b_fill770 [28]; __union { unsigned int coreio$l_scc1_slot; /* SCC1 slot register */ __struct { unsigned coreio$v_scc1_slot_cs : 4; unsigned coreio$v_scc1_slot_hw_addr : 6; unsigned coreio$v_scc1_slot_fill : 22; } coreio$r_scc1_slot_bits; } coreio$r_scc1_slot_overlay; unsigned char coreio$b_fill780 [7388]; unsigned int coreio$l_ni_adr_rom; /* Ethernet address ROM */ unsigned char coreio$b_fill790 [8188]; unsigned int coreio$l_lance_rdp; /* Lance ethernet CSR */ unsigned char coreio$b_fill800 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_lance_rap; /* Lance ethernet CSR */ unsigned char coreio$b_fill810 [8180]; unsigned int coreio$l_scc0b_comm_rap; /* Comm Port 1 RAP */ unsigned char coreio$b_fill820 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_scc0b_comm_data; /* Comm Port 1 data */ unsigned char coreio$b_fill830 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_scc0a_mouse_rap; /* Mouse RAP */ unsigned char coreio$b_fill840 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_scc0a_mouse_data; /* Mouse port data register */ unsigned char coreio$b_fill850 [8164]; unsigned int coreio$l_scc1b_print_rap; /* Printer Port 2 RAP */ unsigned char coreio$b_fill860 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_scc1b_print_data; /* Printer Port 2 data */ unsigned char coreio$b_fill870 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_scc1a_key_rap; /* Keyboard RAP */ unsigned char coreio$b_fill880 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_scc1a_key_data; /* Keyboard port data register */ unsigned char coreio$b_fill890 [8164]; unsigned int coreio$l_rtc_sec; /* TOY clock CSR--seconds */ unsigned char coreio$b_fill900 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_alms; /* TOY clock CSR--seconds alarm */ unsigned char coreio$b_fill910 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_min; /* TOY clock CSR--minutes */ unsigned char coreio$b_fill920 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_almn; /* TOY clock CSR--minutes alarm */ unsigned char coreio$b_fill930 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_hour; /* TOY clock CSR--hours */ unsigned char coreio$b_fill940 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_almh; /* TOY clock CSR--hours alarm */ unsigned char coreio$b_fill950 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_dow; /* TOY clock CSR--day of week */ unsigned char coreio$b_fill960 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_day; /* TOY clock CSR--date of month */ unsigned char coreio$b_fill970 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_mon; /* TOY clock CSR--month */ unsigned char coreio$b_fill980 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_year; /* TOY clock CSR--year */ unsigned char coreio$b_fill990 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_rega; /* TOY clock CSR--register A */ unsigned char coreio$b_fill1000 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_regb; /* TOY clock CSR--register B */ unsigned char coreio$b_fill1010 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_regc; /* TOY clock CSR--register C */ unsigned char coreio$b_fill1020 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_regd; /* TOY clock CSR--register D */ unsigned char coreio$b_fill1030 [4]; /* Fill to allow sparse space byte mask */ unsigned int coreio$l_rtc_ram; /* TOY clock CSR--base of BBU RAM */ unsigned char coreio$b_fill1040 [8076]; unsigned int coreio$l_isdn_audio; /* ISDN audio chip CSR */ unsigned char coreio$b_fill1050 [8188]; } COREIO; #if !defined(__VAXC) #define coreio$l_ldp coreio$r_ldp_overlay.coreio$l_ldp #define coreio$v_ldp_dma_pa_lo coreio$r_ldp_overlay.coreio$r_ldp_bits.coreio$v_ldp_dma_pa_lo #define coreio$v_ldp_dma_pa_hi coreio$r_ldp_overlay.coreio$r_ldp_bits.coreio$v_ldp_dma_pa_hi #define coreio$l_scomm_tr coreio$r_scomm_tr_overlay.coreio$l_scomm_tr #define coreio$v_scomm_tr_dma_pa coreio$r_scomm_tr_overlay.coreio$r_scomm_tr_bits.coreio$v_scomm_tr_dma_pa #define coreio$l_scomm_rc coreio$r_scomm_rc_overlay.coreio$l_scomm_rc #define coreio$v_scomm_rc_dma_pa coreio$r_scomm_rc_overlay.coreio$r_scomm_rc_bits.coreio$v_scomm_rc_dma_pa #define coreio$l_printer_tr coreio$r_printer_tr_overlay.coreio$l_printer_tr #define coreio$v_printer_tr_dma_pa coreio$r_printer_tr_overlay.coreio$r_printer_tr_bits.coreio$v_printer_tr_dma_pa #define coreio$l_printer_rc coreio$r_printer_rc_overlay.coreio$l_printer_rc #define coreio$v_printer_rc_dma_pa coreio$r_printer_rc_overlay.coreio$r_printer_rc_bits.coreio$v_printer_rc_dma_pa #define coreio$l_isdn_tr coreio$r_isdn_tr_overlay.coreio$l_isdn_tr #define coreio$v_isdn_tr_dma_pa coreio$r_isdn_tr_overlay.coreio$r_isdn_tr_bits.coreio$v_isdn_tr_dma_pa #define coreio$l_isdn_tr_buf coreio$r_isdn_tr_buf_overlay.coreio$l_isdn_tr_buf #define coreio$v_isdn_tr_buf_dma_pa coreio$r_isdn_tr_buf_overlay.coreio$r_isdn_tr_buf_bits.coreio$v_isdn_tr_buf_dma_pa #define coreio$l_isdn_rc coreio$r_isdn_rc_overlay.coreio$l_isdn_rc #define coreio$v_isdn_rc_dma_pa coreio$r_isdn_rc_overlay.coreio$r_isdn_rc_bits.coreio$v_isdn_rc_dma_pa #define coreio$l_isdn_rc_buf coreio$r_isdn_rc_buf_overlay.coreio$l_isdn_rc_buf #define coreio$v_isdn_rc_buf_dma_pa coreio$r_isdn_rc_buf_overlay.coreio$r_isdn_rc_buf_bits.coreio$v_isdn_rc_buf_dma_pa #define coreio$l_ssr coreio$r_ssr_overlay.coreio$l_ssr #define coreio$v_ssr_gpo_0 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_0 #define coreio$v_ssr_gpo_1 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_1 #define coreio$v_ssr_gpo_2 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_2 #define coreio$v_ssr_gpo_3 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_3 #define coreio$v_ssr_gpo_4 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_4 #define coreio$v_ssr_gpo_5 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_5 #define coreio$v_ssr_gpo_6 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_6 #define coreio$v_ssr_gpo_7 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_7 #define coreio$v_ssr_gpo_8 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_8 #define coreio$v_ssr_gpo_9 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_9 #define coreio$v_ssr_gpo_10 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_10 #define coreio$v_ssr_gpo_11 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_11 #define coreio$v_ssr_gpo_12 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_12 #define coreio$v_ssr_gpo_13 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_13 #define coreio$v_ssr_gpo_14 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_14 #define coreio$v_ssr_gpo_15 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_15 #define coreio$v_ssr_lance_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_lance_dma_en #define coreio$v_ssr_scsi_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scsi_dma_en #define coreio$v_ssr_scsi_dma_dir coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scsi_dma_dir #define coreio$v_ssr_isdn_rcv_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_isdn_rcv_en #define coreio$v_ssr_isdn_tr_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_isdn_tr_en #define coreio$v_ssr_floppy_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_floppy_dma_en #define coreio$v_ssr_floppy_dma_dir coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_floppy_dma_dir #define coreio$v_ssr_scc1_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc1_rc_dma_en #define coreio$v_ssr_scc1_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc1_tr_dma_en #define coreio$v_ssr_scc0_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc0_rc_dma_en #define coreio$v_ssr_scc0_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc0_tr_dma_en #define coreio$v_ssr_leds coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_leds #define coreio$v_ssr_lance_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_lance_reset #define coreio$v_ssr_rtc_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_rtc_reset #define coreio$v_ssr_ssc_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_ssc_reset #define coreio$v_ssr_isdn_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_isdn_reset #define coreio$v_ssr_10baset_sel coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_10baset_sel #define coreio$v_ssr_ni_loopback coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_ni_loopback #define coreio$v_ssr_txdis coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_txdis #define coreio$v_ssr_isdn_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_isdn_rc_dma_en #define coreio$v_ssr_isdn_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_isdn_tr_dma_en #define coreio$v_ssr_printer_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_printer_rc_dma_en #define coreio$v_ssr_printer_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_printer_tr_dma_en #define coreio$v_ssr_comm_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_comm_rc_dma_en #define coreio$v_ssr_comm_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_comm_tr_dma_en #define coreio$v_ssr_io_mask coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_io_mask #define coreio$v_ssr_io_mask_en coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_io_mask_en #define coreio$v_ssr_fpe coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_fpe #define coreio$v_ssr_smr0 coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_smr0 #define coreio$v_ssr_smr1 coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_smr1 #define coreio$v_ssr_smra coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_smra #define coreio$v_ssr_fast_mode coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_fast_mode #define coreio$v_ssr_kbd_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_kbd_rc_dma_en #define coreio$v_ssr_kbd_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_kbd_tr_dma_en #define coreio$l_sir coreio$r_sir_overlay.coreio$l_sir #define coreio$v_sir_gp_int_0 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_0 #define coreio$v_sir_gp_int_1 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_1 #define coreio$v_sir_gp_int_2 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_2 #define coreio$v_sir_gp_int_3 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_3 #define coreio$v_sir_gp_int_4 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_4 #define coreio$v_sir_gp_int_5 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_5 #define coreio$v_sir_gp_int_6 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_6 #define coreio$v_sir_gp_int_7 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_7 #define coreio$v_sir_gp_int_8 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_8 #define coreio$v_sir_gp_int_9 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_9 #define coreio$v_sir_gp_int_10 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_10 #define coreio$v_sir_gp_int_11 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_11 #define coreio$v_sir_gp_int_12 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_12 #define coreio$v_sir_gp_int_13 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_13 #define coreio$v_sir_gp_int_14 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_14 #define coreio$v_sir_gp_int_15 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_15 #define coreio$v_sir_lance_dma_er coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_lance_dma_er #define coreio$v_sir_scsi_dma_mre coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scsi_dma_mre #define coreio$v_sir_scsi_dma_ov coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scsi_dma_ov #define coreio$v_sir_scsi_dma_ptr coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scsi_dma_ptr #define coreio$v_sir_isdn_dma_mre coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_isdn_dma_mre #define coreio$v_sir_isdn_dma_rc_intr coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_isdn_dma_rc_intr #define coreio$v_sir_isdn_dma_tr_intr coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_isdn_dma_tr_intr #define coreio$v_sir_floppy_dma_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_floppy_dma_int #define coreio$v_sir_scc1_dma_ov coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_dma_ov #define coreio$v_sir_scc1_rcv_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_rcv_int #define coreio$v_sir_scc1_tr_dma_me coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_tr_dma_me #define coreio$v_sir_scc1_tr_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_tr_int #define coreio$v_sir_scc0_dma_ov coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_dma_ov #define coreio$v_sir_scc0_rcv_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_rcv_int #define coreio$v_sir_scc0_tr_dma_me coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_tr_dma_me #define coreio$v_sir_scc0_tr_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_tr_int #define coreio$v_sir_halt0 coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_halt0 #define coreio$v_sir_halt1 coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_halt1 #define coreio$v_sir_alt_console coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_alt_console #define coreio$v_sir_scc0_si coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_scc0_si #define coreio$v_sir_scc1_si coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_scc1_si #define coreio$v_sir_ni_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_ni_intr #define coreio$v_sir_isdn_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_isdn_intr #define coreio$v_sir_lance_dma_re coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_lance_dma_re #define coreio$v_sir_pp_rc_dma_ovr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_rc_dma_ovr #define coreio$v_sir_pp_rc_hp_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_rc_hp_intr #define coreio$v_sir_pp_tr_dma_mre coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_tr_dma_mre #define coreio$v_sir_pp_tr_pe_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_tr_pe_intr #define coreio$v_sir_comm_rc_dma_ovr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_rc_dma_ovr #define coreio$v_sir_comm_rc_hp_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_rc_hp_intr #define coreio$v_sir_comm_tr_dma_mre coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_tr_dma_mre #define coreio$v_sir_comm_tr_pe_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_tr_pe_intr #define coreio$v_sir_tc_slot0 coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_tc_slot0 #define coreio$v_sir_tc_slot1 coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_tc_slot1 #define coreio$v_sir_scc0_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_scc0_int #define coreio$v_sir_scc1_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_scc1_int #define coreio$v_sir_lance_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_lance_int #define coreio$v_sir_isdn_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_isdn_int #define coreio$v_sir_cons_sel coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_cons_sel #define coreio$l_simr coreio$r_simr_overlay.coreio$l_simr #define coreio$v_simr_gp_int_0 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_0 #define coreio$v_simr_gp_int_1 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_1 #define coreio$v_simr_gp_int_2 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_2 #define coreio$v_simr_gp_int_3 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_3 #define coreio$v_simr_gp_int_4 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_4 #define coreio$v_simr_gp_int_5 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_5 #define coreio$v_simr_gp_int_6 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_6 #define coreio$v_simr_gp_int_7 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_7 #define coreio$v_simr_gp_int_8 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_8 #define coreio$v_simr_gp_int_9 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_9 #define coreio$v_simr_gp_int_10 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_10 #define coreio$v_simr_gp_int_11 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_11 #define coreio$v_simr_gp_int_12 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_12 #define coreio$v_simr_gp_int_13 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_13 #define coreio$v_simr_gp_int_14 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_14 #define coreio$v_simr_gp_int_15 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_15 #define coreio$v_simr_lance_dma_er coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_lance_dma_er #define coreio$v_simr_scsi_dma_mre coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scsi_dma_mre #define coreio$v_simr_scsi_dma_ov coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scsi_dma_ov #define coreio$v_simr_scsi_dma_ptr coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scsi_dma_ptr #define coreio$v_simr_isdn_dma_mre coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_isdn_dma_mre #define coreio$v_simr_isdn_dma_rc_intr coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_isdn_dma_rc_intr #define coreio$v_simr_isdn_dma_tr_intr coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_isdn_dma_tr_intr #define coreio$v_simr_floppy_dma_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_floppy_dma_int #define coreio$v_simr_scc1_dma_ov coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_dma_ov #define coreio$v_simr_scc1_rcv_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_rcv_int #define coreio$v_simr_scc1_tr_dma_me coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_tr_dma_me #define coreio$v_simr_scc1_tr_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_tr_int #define coreio$v_simr_scc0_dma_ov coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_dma_ov #define coreio$v_simr_scc0_rcv_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_rcv_int #define coreio$v_simr_scc0_tr_dma_me coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_tr_dma_me #define coreio$v_simr_scc0_tr_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_tr_int #define coreio$v_simr_halt0 coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_halt0 #define coreio$v_simr_halt1 coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_halt1 #define coreio$v_simr_alt_console coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_alt_console #define coreio$v_simr_scc0_si coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_scc0_si #define coreio$v_simr_scc1_si coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_scc1_si #define coreio$v_simr_ni_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_ni_intr #define coreio$v_simr_isdn_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_isdn_intr #define coreio$v_simr_lance_dma_re coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_lance_dma_re #define coreio$v_simr_pp_rc_dma_ovr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_rc_dma_ovr #define coreio$v_simr_pp_rc_hp_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_rc_hp_intr #define coreio$v_simr_pp_tr_dma_mre coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_tr_dma_mre #define coreio$v_simr_pp_tr_pe_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_tr_pe_intr #define coreio$v_simr_comm_rc_dma_ovr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_rc_dma_ovr #define coreio$v_simr_comm_rc_hp_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_rc_hp_intr #define coreio$v_simr_comm_tr_dma_mre coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_tr_dma_mre #define coreio$v_simr_comm_tr_pe_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_tr_pe_intr #define coreio$v_simr_tc_slot0 coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_tc_slot0 #define coreio$v_simr_tc_slot1 coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_tc_slot1 #define coreio$v_simr_scc0_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_scc0_int #define coreio$v_simr_scc1_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_scc1_int #define coreio$v_simr_lance_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_lance_int #define coreio$v_simr_isdn_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_isdn_int #define coreio$v_simr_cons_sel coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_cons_sel #define coreio$l_sadr coreio$r_sadr_overlay.coreio$l_sadr #define coreio$v_sadr_tc_addr coreio$r_sadr_overlay.coreio$r_sadr_bits.coreio$v_sadr_tc_addr #define coreio$l_isdn_data_tr coreio$r_isdn_data_tr_overlay.coreio$l_isdn_data_tr #define coreio$v_isdn_data_tr_data coreio$r_isdn_data_tr_overlay.coreio$r_isdn_data_tr_bits.coreio$v_isdn_data_tr_data #define coreio$l_isdn_data_rc coreio$r_isdn_data_rc_overlay.coreio$l_isdn_data_rc #define coreio$v_isdn_data_rc_data coreio$r_isdn_data_rc_overlay.coreio$r_isdn_data_rc_bits.coreio$v_isdn_data_rc_data #define coreio$l_lance_slot coreio$r_lance_slot_overlay.coreio$l_lance_slot #define coreio$v_lance_slot_cs coreio$r_lance_slot_overlay.coreio$r_lance_slot_bits.coreio$v_lance_slot_cs #define coreio$v_lance_slot_hw_addr coreio$r_lance_slot_overlay.coreio$r_lance_slot_bits.coreio$v_lance_slot_hw_addr #define coreio$l_scc0_slot coreio$r_scc0_slot_overlay.coreio$l_scc0_slot #define coreio$v_scc0_slot_cs coreio$r_scc0_slot_overlay.coreio$r_scc0_slot_bits.coreio$v_scc0_slot_cs #define coreio$v_scc0_slot_hw_addr coreio$r_scc0_slot_overlay.coreio$r_scc0_slot_bits.coreio$v_scc0_slot_hw_addr #define coreio$l_scc1_slot coreio$r_scc1_slot_overlay.coreio$l_scc1_slot #define coreio$v_scc1_slot_cs coreio$r_scc1_slot_overlay.coreio$r_scc1_slot_bits.coreio$v_scc1_slot_cs #define coreio$v_scc1_slot_hw_addr coreio$r_scc1_slot_overlay.coreio$r_scc1_slot_bits.coreio$v_scc1_slot_hw_addr #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __COREIODEF_LOADED */