/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:54 by OpenVMS SDL EV3-3 */ /* Source: 03-APR-1997 09:22:00 $1$DGA7274:[LIB_H.SRC]CIA_MCHKDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE CIA_MCHKDEF IDENT X-1A2 ***/ #ifndef __CIA_MCHKDEF_LOADED #define __CIA_MCHKDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mck { /* */ /* Define the field offsets for the machine check abort logout area */ /* */ #pragma __nomember_alignment __union { unsigned int mck$l_byte_count; /* Size of logout frame in bytes */ __union { __int64 mck$q_retry_str; __struct { unsigned mck$v_fill_1_1 : 32; unsigned mck$v_fill_1_2 : 30 /** WARNING: bitfield array has been reduced to a string **/ ; unsigned mck$v_second_error : 1; /* Second error occurred */ unsigned mck$v_retry : 1; /* Retry bit */ } mck$r_fill_1_; } mck$r_fill_0_; } mck$r_count_overlay; unsigned int mck$l_proc_offset; /* Offset to processor specific info */ unsigned int mck$l_system_offset; /* Offset to system specific info */ unsigned __int64 mck$q_mcheck_type; /* PAL-determined cause for mchk */ /* */ /* */ /* Processor specific segment of logout frame */ /* */ unsigned __int64 mck$q_shadow8; /* Shadow registers */ unsigned __int64 mck$q_shadow9; unsigned __int64 mck$q_shadow10; unsigned __int64 mck$q_shadow11; unsigned __int64 mck$q_shadow12; unsigned __int64 mck$q_shadow13; unsigned __int64 mck$q_shadow14; unsigned __int64 mck$q_shadow25; unsigned __int64 mck$q_paltemp0; /* PALTEMPs: 23 PAL temporary registers */ unsigned __int64 mck$q_paltemp1; unsigned __int64 mck$q_paltemp2; unsigned __int64 mck$q_paltemp3; unsigned __int64 mck$q_paltemp4; unsigned __int64 mck$q_paltemp5; unsigned __int64 mck$q_paltemp6; unsigned __int64 mck$q_paltemp7; unsigned __int64 mck$q_paltemp8; unsigned __int64 mck$q_paltemp9; unsigned __int64 mck$q_paltemp10; unsigned __int64 mck$q_paltemp11; unsigned __int64 mck$q_paltemp12; unsigned __int64 mck$q_paltemp13; unsigned __int64 mck$q_paltemp14; unsigned __int64 mck$q_paltemp15; unsigned __int64 mck$q_paltemp16; unsigned __int64 mck$q_paltemp17; unsigned __int64 mck$q_paltemp18; unsigned __int64 mck$q_paltemp19; unsigned __int64 mck$q_paltemp20; unsigned __int64 mck$q_paltemp21; unsigned __int64 mck$q_paltemp22; unsigned __int64 mck$q_paltemp23; unsigned __int64 mck$q_exc_address; /* Exception address register */ unsigned __int64 mck$q_exc_summ; /* Exception summary register */ unsigned __int64 mck$q_exc_mask; /* Exception mask register */ unsigned __int64 mck$q_pal_base; /* Contains the base address of Palcode */ unsigned __int64 mck$q_isr; /* Hardware Interrupt Enable Register */ unsigned __int64 mck$q_icsr; /* Hardware Interrupt Request Register */ unsigned __int64 mck$q_ic_perr_stat; /* Icache parity error status */ unsigned __int64 mck$q_dc_perr_stat; /* Dcache parity error status */ unsigned __int64 mck$q_proc_va; /* Processor mcheck VA */ unsigned __int64 mck$q_mm_stat; /* Info on memory management error or */ /* DTB miss */ unsigned __int64 mck$q_sc_addr; /* S-cache address register */ unsigned __int64 mck$q_sc_stat; /* S-cache status register */ unsigned __int64 mck$q_bc_tag_addr; /* B cache TAG register */ unsigned __int64 mck$q_ei_addr; /* */ unsigned __int64 mck$q_fill_syndrome; /* Contains syndromes for single bit */ /* errors */ unsigned __int64 mck$q_ei_stat; /* */ unsigned __int64 mck$q_ld_lock; /* */ /* */ unsigned __int64 mck$q_cpu_ei0; unsigned __int64 mck$q_cpu_ei1; unsigned __int64 mck$q_cia_err; unsigned __int64 mck$q_cia_err_stat; unsigned __int64 mck$q_cia_err_mask; unsigned __int64 mck$q_cia_syn; unsigned __int64 mck$q_mem_err0; unsigned __int64 mck$q_mem_err1; unsigned __int64 mck$q_pci_err0; unsigned __int64 mck$q_pci_err1; unsigned __int64 mck$q_nmi_info; } MCK; #if !defined(__VAXC) #define mck$l_byte_count mck$r_count_overlay.mck$l_byte_count #define mck$v_second_error mck$r_count_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$v_second_error #define mck$v_retry mck$r_count_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$v_retry #endif /* #if !defined(__VAXC) */ #define MCK$CIA_LOGOUT_SIZE 504 /* This portion of the sdl file describes each of the Alcor specific registers */ /* individually. They must be referenced as if from offset 0 */ /* Alcor specific segment of the logout frame */ /* */ /* CPU Error Information 0 - 0x8740008000 */ /* */ #define MCHECK$M_CPU_ERR0_ADDR 0xFFFFFFF0 union cpu_ei0 { __int64 mcheck$q_cpu_err0; __struct { unsigned mcheck$v_fillc0 : 4; unsigned mcheck$v_cpu_err0_addr : 28; /* Bad addr on EV5 interface error */ int mcheck$l_cpu_err0_fill; } mcheck$r_cpu_err0_bits; } ; #if !defined(__VAXC) #define mcheck$v_fillc0 mcheck$r_cpu_err0_bits.mcheck$v_fillc0 #define mcheck$v_cpu_err0_addr mcheck$r_cpu_err0_bits.mcheck$v_cpu_err0_addr #define mcheck$l_cpu_err0_fill mcheck$r_cpu_err0_bits.mcheck$l_cpu_err0_fill #endif /* #if !defined(__VAXC) */ /* */ /* CPU Error Information 1 - 0x8740008040 */ /* */ #define MCHECK$M_CPU_ERR1_3432 0x7 #define MCHECK$M_CPU_ERR1_39 0x80 #define MCHECK$M_CPU_ERR1_CMD 0xF00 #define MCHECK$M_CPU_ERR1_INT4_VALID 0xF000 #define MCHECK$M_CPU_ERR1_AC_PAR 0x200000 #define MCHECK$M_CPU_ERR1_FPE 0x40000000 #define MCHECK$M_CPU_ERR1_PE 0x80000000 union cpu_ei1 { __int64 mcheck$q_cpu_err1; __struct { unsigned mcheck$v_cpu_err1_3432 : 3; /* CPU addr <34:32> on error */ unsigned mcheck$v_filld0 : 4; unsigned mcheck$v_cpu_err1_39 : 1; /* CPU addr <39> on error */ unsigned mcheck$v_cpu_err1_cmd : 4; /* CPU command */ unsigned mcheck$v_cpu_err1_int4_valid : 4; /* INT4 valid bits */ unsigned mcheck$v_filld1 : 5; unsigned mcheck$v_cpu_err1_ac_par : 1; /* Parity bit from CPU Addr/cmd */ unsigned mcheck$v_filld2 : 8; unsigned mcheck$v_cpu_err1_fpe : 1; /*Copy of csr bit to force bad parity */ unsigned mcheck$v_cpu_err1_pe : 1; /*IF set, CPU detected PE. */ int mcheck$l_cpu_err1_fill; } mcheck$r_cpu_err1_bits; } ; #if !defined(__VAXC) #define mcheck$v_cpu_err1_3432 mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_3432 #define mcheck$v_filld0 mcheck$r_cpu_err1_bits.mcheck$v_filld0 #define mcheck$v_cpu_err1_39 mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_39 #define mcheck$v_cpu_err1_cmd mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_cmd #define mcheck$v_cpu_err1_int4_valid mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_int4_valid #define mcheck$v_filld1 mcheck$r_cpu_err1_bits.mcheck$v_filld1 #define mcheck$v_cpu_err1_ac_par mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_ac_par #define mcheck$v_filld2 mcheck$r_cpu_err1_bits.mcheck$v_filld2 #define mcheck$v_cpu_err1_fpe mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_fpe #define mcheck$v_cpu_err1_pe mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_pe #define mcheck$l_cpu_err1_fill mcheck$r_cpu_err1_bits.mcheck$l_cpu_err1_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA Error register - 0x8740008200 */ /* */ #define MCHECK$M_ERR_CORR_ECC 0x1 #define MCHECK$M_ERR_UNC_ECC 0x2 #define MCHECK$M_ERR_CPU_PE 0x4 #define MCHECK$M_ERR_MEM_NEM 0x8 #define MCHECK$M_ERR_PCI_SERR 0x10 #define MCHECK$M_ERR_PCI_PERR 0x20 #define MCHECK$M_ERR_PCI_ADR_PE 0x40 #define MCHECK$M_ERR_M_ABORT 0x80 #define MCHECK$M_ERR_T_ABORT 0x100 #define MCHECK$M_ERR_PA_PTE_INV 0x200 #define MCHECK$M_ERR_FROM_WRT_ERR 0x400 #define MCHECK$M_ERR_IOA_TIMEOUT 0x800 #define MCHECK$M_ERR_RESERVED_0 0xF000 #define MCHECK$M_ERR_LOST_CORR_ECC 0x10000 #define MCHECK$M_ERR_LOST_UNC_ECC 0x20000 #define MCHECK$M_ERR_LOST_CPU_PE 0x40000 #define MCHECK$M_ERR_LOST_MEM_NEM 0x80000 #define MCHECK$M_ERR_LOST_PCI_SERR 0x100000 #define MCHECK$M_ERR_LOST_PCI_PERR 0x200000 #define MCHECK$M_ERR_LOST_PCI_ADR_PE 0x400000 #define MCHECK$M_ERR_LOST_M_ABORT 0x800000 #define MCHECK$M_ERR_LOST_T_ABORT 0x1000000 #define MCHECK$M_ERR_LOST_PA_PTE_INV 0x2000000 #define MCHECK$M_ERR_LOST_FROM_WRT_ERR 0x4000000 #define MCHECK$M_ERR_LOST_IOA_TIMEOUT 0x8000000 #define MCHECK$M_ERR_RESERVED_1 0x70000000 #define MCHECK$M_ERR_VALID 0x80000000 union cia_err { __int64 mcheck$q_cia_err; __struct { unsigned mcheck$v_err_corr_ecc : 1; /* [0] */ unsigned mcheck$v_err_unc_ecc : 1; /* [1] */ unsigned mcheck$v_err_cpu_pe : 1; /* [2] */ unsigned mcheck$v_err_mem_nem : 1; /* [3] */ unsigned mcheck$v_err_pci_serr : 1; /* [4] */ unsigned mcheck$v_err_pci_perr : 1; /* [5] */ unsigned mcheck$v_err_pci_adr_pe : 1; /* [6] */ unsigned mcheck$v_err_m_abort : 1; /* [7] */ unsigned mcheck$v_err_t_abort : 1; /* [8] */ unsigned mcheck$v_err_pa_pte_inv : 1; /* [9] */ unsigned mcheck$v_err_from_wrt_err : 1; /* [10] */ unsigned mcheck$v_err_ioa_timeout : 1; /* [11] */ unsigned mcheck$v_err_reserved_0 : 4; /* [15:12] */ unsigned mcheck$v_err_lost_corr_ecc : 1; unsigned mcheck$v_err_lost_unc_ecc : 1; unsigned mcheck$v_err_lost_cpu_pe : 1; unsigned mcheck$v_err_lost_mem_nem : 1; unsigned mcheck$v_err_lost_pci_serr : 1; unsigned mcheck$v_err_lost_pci_perr : 1; unsigned mcheck$v_err_lost_pci_adr_pe : 1; unsigned mcheck$v_err_lost_m_abort : 1; unsigned mcheck$v_err_lost_t_abort : 1; unsigned mcheck$v_err_lost_pa_pte_inv : 1; unsigned mcheck$v_err_lost_from_wrt_err : 1; unsigned mcheck$v_err_lost_ioa_timeout : 1; unsigned mcheck$v_err_reserved_1 : 3; /* */ unsigned mcheck$v_err_valid : 1; int mcheck$l_cia_err_fill; } mcheck$r_cia_err_bits; } ; #if !defined(__VAXC) #define mcheck$v_err_corr_ecc mcheck$r_cia_err_bits.mcheck$v_err_corr_ecc #define mcheck$v_err_unc_ecc mcheck$r_cia_err_bits.mcheck$v_err_unc_ecc #define mcheck$v_err_cpu_pe mcheck$r_cia_err_bits.mcheck$v_err_cpu_pe #define mcheck$v_err_mem_nem mcheck$r_cia_err_bits.mcheck$v_err_mem_nem #define mcheck$v_err_pci_serr mcheck$r_cia_err_bits.mcheck$v_err_pci_serr #define mcheck$v_err_pci_perr mcheck$r_cia_err_bits.mcheck$v_err_pci_perr #define mcheck$v_err_pci_adr_pe mcheck$r_cia_err_bits.mcheck$v_err_pci_adr_pe #define mcheck$v_err_m_abort mcheck$r_cia_err_bits.mcheck$v_err_m_abort #define mcheck$v_err_t_abort mcheck$r_cia_err_bits.mcheck$v_err_t_abort #define mcheck$v_err_pa_pte_inv mcheck$r_cia_err_bits.mcheck$v_err_pa_pte_inv #define mcheck$v_err_from_wrt_err mcheck$r_cia_err_bits.mcheck$v_err_from_wrt_err #define mcheck$v_err_ioa_timeout mcheck$r_cia_err_bits.mcheck$v_err_ioa_timeout #define mcheck$v_err_reserved_0 mcheck$r_cia_err_bits.mcheck$v_err_reserved_0 #define mcheck$v_err_lost_corr_ecc mcheck$r_cia_err_bits.mcheck$v_err_lost_corr_ecc #define mcheck$v_err_lost_unc_ecc mcheck$r_cia_err_bits.mcheck$v_err_lost_unc_ecc #define mcheck$v_err_lost_cpu_pe mcheck$r_cia_err_bits.mcheck$v_err_lost_cpu_pe #define mcheck$v_err_lost_mem_nem mcheck$r_cia_err_bits.mcheck$v_err_lost_mem_nem #define mcheck$v_err_lost_pci_serr mcheck$r_cia_err_bits.mcheck$v_err_lost_pci_serr #define mcheck$v_err_lost_pci_perr mcheck$r_cia_err_bits.mcheck$v_err_lost_pci_perr #define mcheck$v_err_lost_pci_adr_pe mcheck$r_cia_err_bits.mcheck$v_err_lost_pci_adr_pe #define mcheck$v_err_lost_m_abort mcheck$r_cia_err_bits.mcheck$v_err_lost_m_abort #define mcheck$v_err_lost_t_abort mcheck$r_cia_err_bits.mcheck$v_err_lost_t_abort #define mcheck$v_err_lost_pa_pte_inv mcheck$r_cia_err_bits.mcheck$v_err_lost_pa_pte_inv #define mcheck$v_err_lost_from_wrt_err mcheck$r_cia_err_bits.mcheck$v_err_lost_from_wrt_err #define mcheck$v_err_lost_ioa_timeout mcheck$r_cia_err_bits.mcheck$v_err_lost_ioa_timeout #define mcheck$v_err_reserved_1 mcheck$r_cia_err_bits.mcheck$v_err_reserved_1 #define mcheck$v_err_valid mcheck$r_cia_err_bits.mcheck$v_err_valid #define mcheck$l_cia_err_fill mcheck$r_cia_err_bits.mcheck$l_cia_err_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA Error status register - 0x8740008240 */ /* */ #define DM_K_IDLE 0 #define DM_K_RESTART 4096 #define DM_K_IOW_64 8192 #define DM_K_IOW_32 12288 #define DM_K_R_4 16384 #define DM_K_NONE 20480 #define DM_K_DMA_RD 24576 #define DM_K_DMA_WR 28672 #define DM_K_GRU_WR 32768 #define DM_K_GRU_RD 36864 #define DM_K_CSR_RD 40960 #define DM_K_PCI_RD 45056 #define MCHECK$M_FILL1 0x1 #define MCHECK$M_STAT_MEM_SOURCE 0x2 #define MCHECK$M_STAT_IO_QUEUE 0x3C #define MCHECK$M_STAT_CPU_QUEUE 0x1C0 #define MCHECK$M_STAT_TLB_MISS 0x200 #define MCHECK$M_STAT_DM_STAT 0x3C00 #define MCHECK$M_STAT_PA_CPU_RES 0xC000 #define MCHECK$M_RESERVED_0 0x3FFF0000 union cia_error_stat { __int64 mcheck$q_cia_stat; __struct { unsigned mcheck$v_fill1 : 1; /* [2] */ unsigned mcheck$v_stat_mem_source : 1; /* [3] */ unsigned mcheck$v_stat_io_queue : 4; /* [7:4] */ unsigned mcheck$v_stat_cpu_queue : 3; /* [10:8] */ unsigned mcheck$v_stat_tlb_miss : 1; /* [11] */ unsigned mcheck$v_stat_dm_stat : 4; /* [15:12] */ unsigned mcheck$v_stat_pa_cpu_res : 2; /* [17:16] */ unsigned mcheck$v_reserved_0 : 14; /* [31:18] */ unsigned mcheck$v_fill_2_ : 2; int mcheck$l_cia_stat_fill; } mcheck$r_cia_stat_bits; } ; #if !defined(__VAXC) #define mcheck$v_fill1 mcheck$r_cia_stat_bits.mcheck$v_fill1 #define mcheck$v_stat_mem_source mcheck$r_cia_stat_bits.mcheck$v_stat_mem_source #define mcheck$v_stat_io_queue mcheck$r_cia_stat_bits.mcheck$v_stat_io_queue #define mcheck$v_stat_cpu_queue mcheck$r_cia_stat_bits.mcheck$v_stat_cpu_queue #define mcheck$v_stat_tlb_miss mcheck$r_cia_stat_bits.mcheck$v_stat_tlb_miss #define mcheck$v_stat_dm_stat mcheck$r_cia_stat_bits.mcheck$v_stat_dm_stat #define mcheck$v_stat_pa_cpu_res mcheck$r_cia_stat_bits.mcheck$v_stat_pa_cpu_res #define mcheck$v_reserved_0 mcheck$r_cia_stat_bits.mcheck$v_reserved_0 #define mcheck$l_cia_stat_fill mcheck$r_cia_stat_bits.mcheck$l_cia_stat_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA Error mask register - 0x8740008280 */ /* */ #define MCHECK$M_MASK_CORR_ECC_ERR 0x1 #define MCHECK$M_MASK_UNC_ECC_ERR 0x2 #define MCHECK$M_MASK_CPU_PE 0x4 #define MCHECK$M_MASK_MEM_NEM 0x8 #define MCHECK$M_MASK_PCI_SERR 0x10 #define MCHECK$M_MASK_PCI_PERR 0x20 #define MCHECK$M_MASK_PCI_ADR_PE 0x40 #define MCHECK$M_MASK_M_ABORT 0x80 #define MCHECK$M_MASK_T_ABORT 0x100 #define MCHECK$M_MASK_PA_PTE_INV 0x200 #define MCHECK$M_MASK_FROM_WRT_ERR 0x400 #define MCHECK$M_MASK_IOA_TIMEOUT 0x800 #define MCHECK$M_RESERVED_1 0xFFFFF000 union cia_error_mask { __int64 mcheck$q_cia_error_mask; __struct { unsigned mcheck$v_mask_corr_ecc_err : 1; /* [0] */ unsigned mcheck$v_mask_unc_ecc_err : 1; /* [1] */ unsigned mcheck$v_mask_cpu_pe : 1; /* [2] */ unsigned mcheck$v_mask_mem_nem : 1; /* [3] */ unsigned mcheck$v_mask_pci_serr : 1; /* [4] */ unsigned mcheck$v_mask_pci_perr : 1; /* [5] */ unsigned mcheck$v_mask_pci_adr_pe : 1; /* [6] */ unsigned mcheck$v_mask_m_abort : 1; /* [7] */ unsigned mcheck$v_mask_t_abort : 1; /* [8] */ unsigned mcheck$v_mask_pa_pte_inv : 1; /* [9] */ unsigned mcheck$v_mask_from_wrt_err : 1; /* [10] */ unsigned mcheck$v_mask_ioa_timeout : 1; /* [11] */ unsigned mcheck$v_reserved_1 : 20; /* [30:12] */ int mcheck$l_cia_mask_fill; } mcheck$r_cia_error_mask_bits; } ; #if !defined(__VAXC) #define mcheck$v_mask_corr_ecc_err mcheck$r_cia_error_mask_bits.mcheck$v_mask_corr_ecc_err #define mcheck$v_mask_unc_ecc_err mcheck$r_cia_error_mask_bits.mcheck$v_mask_unc_ecc_err #define mcheck$v_mask_cpu_pe mcheck$r_cia_error_mask_bits.mcheck$v_mask_cpu_pe #define mcheck$v_mask_mem_nem mcheck$r_cia_error_mask_bits.mcheck$v_mask_mem_nem #define mcheck$v_mask_pci_serr mcheck$r_cia_error_mask_bits.mcheck$v_mask_pci_serr #define mcheck$v_mask_pci_perr mcheck$r_cia_error_mask_bits.mcheck$v_mask_pci_perr #define mcheck$v_mask_pci_adr_pe mcheck$r_cia_error_mask_bits.mcheck$v_mask_pci_adr_pe #define mcheck$v_mask_m_abort mcheck$r_cia_error_mask_bits.mcheck$v_mask_m_abort #define mcheck$v_mask_t_abort mcheck$r_cia_error_mask_bits.mcheck$v_mask_t_abort #define mcheck$v_mask_pa_pte_inv mcheck$r_cia_error_mask_bits.mcheck$v_mask_pa_pte_inv #define mcheck$v_mask_from_wrt_err mcheck$r_cia_error_mask_bits.mcheck$v_mask_from_wrt_err #define mcheck$v_mask_ioa_timeout mcheck$r_cia_error_mask_bits.mcheck$v_mask_ioa_timeout #define mcheck$v_reserved_1 mcheck$r_cia_error_mask_bits.mcheck$v_reserved_1 #define mcheck$l_cia_mask_fill mcheck$r_cia_error_mask_bits.mcheck$l_cia_mask_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA Error Syndrome register - 0x8740008300 */ /* */ #define MCHECK$M_CIA_SYNDROME 0xFF #define MCHECK$M_CIA_SYND_UNUSED_0 0xFFFFFF00 union cia_syndrome { __int64 mcheck$q_cia_synd; __struct { unsigned mcheck$v_cia_syndrome : 8; unsigned mcheck$v_cia_synd_unused_0 : 24; int mcheck$l_cia_synd_fill; } mcheck$r_cia_synd_bits; } ; #if !defined(__VAXC) #define mcheck$v_cia_syndrome mcheck$r_cia_synd_bits.mcheck$v_cia_syndrome #define mcheck$v_cia_synd_unused_0 mcheck$r_cia_synd_bits.mcheck$v_cia_synd_unused_0 #define mcheck$l_cia_synd_fill mcheck$r_cia_synd_bits.mcheck$l_cia_synd_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA Memory Port status register 0 - 0x8740008400 */ /* */ #define MCHECK$M_MPSR0_ADDR_H 0xFFFFFFF0 union cia_mpsr0 { __int64 mcheck$q_cia_mpsr0; __struct { unsigned mcheck$v_unused_0 : 4; unsigned mcheck$v_mpsr0_addr_h : 28; int mcheck$l_mpsr0_fill; } mcheck$r_cia_mpsr0_bits; } ; #if !defined(__VAXC) #define mcheck$v_unused_0 mcheck$r_cia_mpsr0_bits.mcheck$v_unused_0 #define mcheck$v_mpsr0_addr_h mcheck$r_cia_mpsr0_bits.mcheck$v_mpsr0_addr_h #define mcheck$l_mpsr0_fill mcheck$r_cia_mpsr0_bits.mcheck$l_mpsr0_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA Memory Port status register 1 - 0x8740008440 */ /* */ #define MCHECK$M_MPSR1_ADDR_H 0x3 #define MCHECK$M_MPSR1_ADDR_39 0x80 #define MCHECK$M_MPSR1_CMD_H 0xF00 #define MCHECK$M_MPSR1_PORT_MASK 0xF000 #define MCHECK$M_MPSR1_SEQ_ST 0xF0000 #define MCHECK$M_MPSR1_PORT_SRC 0x100000 #define MCHECK$M_MPSR1_SET_SEL 0x1F000000 #define MCHECK$M_MPSR3_RESERVED_3 0xE0000000 union cia_mpsr1 { __int64 mcheck$q_cia_mpsr1; __struct { unsigned mcheck$v_mpsr1_addr_h : 2; /* [1:0] */ unsigned mcheck$v_mpsr1_reserved : 5; /* [6:2] */ unsigned mcheck$v_mpsr1_addr_39 : 1; /* [7] */ unsigned mcheck$v_mpsr1_cmd_h : 4; /* [11:8] */ unsigned mcheck$v_mpsr1_port_mask : 4; /* [15:12] */ unsigned mcheck$v_mpsr1_seq_st : 4; /* [19:16] */ unsigned mcheck$v_mpsr1_port_src : 1; /* [20] */ unsigned mcheck$v_mpsr2_reserved_2 : 3; /* [23:21] */ unsigned mcheck$v_mpsr1_set_sel : 5; /* [28:24] */ unsigned mcheck$v_mpsr3_reserved_3 : 3; /* [31:29] */ int mcheck$l_mpsr1_fill; } mcheck$r_cia_mpsr1_bits; } ; #if !defined(__VAXC) #define mcheck$v_mpsr1_addr_h mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_addr_h #define mcheck$v_mpsr1_reserved mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_reserved #define mcheck$v_mpsr1_addr_39 mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_addr_39 #define mcheck$v_mpsr1_cmd_h mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_cmd_h #define mcheck$v_mpsr1_port_mask mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_port_mask #define mcheck$v_mpsr1_seq_st mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_seq_st #define mcheck$v_mpsr1_port_src mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_port_src #define mcheck$v_mpsr2_reserved_2 mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr2_reserved_2 #define mcheck$v_mpsr1_set_sel mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_set_sel #define mcheck$v_mpsr3_reserved_3 mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr3_reserved_3 #define mcheck$l_mpsr1_fill mcheck$r_cia_mpsr1_bits.mcheck$l_mpsr1_fill #endif /* #if !defined(__VAXC) */ /* */ /* PCI Error register 0 - 0x8740008800 */ /* */ #define MCHECK$M_PCIE_CMD 0xF #define MCHECK$M_PCIE_LOCK_STATE 0x10 #define MCHECK$M_PCIE_DAC_CYCLE 0x20 #define MCHECK$M_PCIE_WINDOW 0xF00 #define MCHECK$M_PCIE_MSTR_STATE 0xF0000 #define MCHECK$M_PCIE_TRGT_STATE 0x700000 #define MCHECK$M_UNUSED_2 0xFF800000 union cia_pcie0 { __int64 mcheck$q_cia_pcie0; __struct { unsigned mcheck$v_pcie_cmd : 4; /* [3:0] */ unsigned mcheck$v_pcie_lock_state : 1; /* [4] */ unsigned mcheck$v_pcie_dac_cycle : 1; /* [5] */ unsigned mcheck$v_reserved : 2; /* [7:6] */ unsigned mcheck$v_pcie_window : 4; /* [11:8] */ unsigned mcheck$v_reserved_2 : 4; /* [15:12] */ unsigned mcheck$v_pcie_mstr_state : 4; /* [19:16] */ unsigned mcheck$v_pcie_trgt_state : 3; /* [22:20] */ unsigned mcheck$v_unused_2 : 9; /* [31:23] */ int mcheck$l_pcie0_fill; } mcheck$r_cia_pcie_bits; } ; #if !defined(__VAXC) #define mcheck$v_pcie_cmd mcheck$r_cia_pcie_bits.mcheck$v_pcie_cmd #define mcheck$v_pcie_lock_state mcheck$r_cia_pcie_bits.mcheck$v_pcie_lock_state #define mcheck$v_pcie_dac_cycle mcheck$r_cia_pcie_bits.mcheck$v_pcie_dac_cycle #define mcheck$v_reserved mcheck$r_cia_pcie_bits.mcheck$v_reserved #define mcheck$v_pcie_window mcheck$r_cia_pcie_bits.mcheck$v_pcie_window #define mcheck$v_reserved_2 mcheck$r_cia_pcie_bits.mcheck$v_reserved_2 #define mcheck$v_pcie_mstr_state mcheck$r_cia_pcie_bits.mcheck$v_pcie_mstr_state #define mcheck$v_pcie_trgt_state mcheck$r_cia_pcie_bits.mcheck$v_pcie_trgt_state #define mcheck$v_unused_2 mcheck$r_cia_pcie_bits.mcheck$v_unused_2 #define mcheck$l_pcie0_fill mcheck$r_cia_pcie_bits.mcheck$l_pcie0_fill #endif /* #if !defined(__VAXC) */ /* */ /* CIA PCI error register 1 - 0x8740008840 */ /* */ struct cia_pcie1 { int mcheck$l_pcie1_addr_h; int mcheck$l_pcie1_fill; } ; struct nmi_info { int mcheck$l_nmi_info_l; /* TBD */ int mcheck$l_nmi_info_h; } ; /* Processor detected error types */ #define MCK_PROC$K_TAG_PE 128 #define MCK_PROC$K_TAG_CTRL_PE 130 #define MCK_PROC$K_HARD_ERROR 132 #define MCK_PROC$K_PROC_CORR_ECC 134 #define MCK_PROC$K_PROC_UNCORR_ECC 136 #define MCK_PROC$K_OS_PAL_BUG 138 #define MCK_PROC$K_RESERVED2 140 #define MCK_PROC$K_RESERVED3 142 #define MCK_PROC$K_PAL_BUG 144 #define MCK_PROC$K_RESERVED4 146 #define MCK_PROC$K_RESERVED5 148 #define MCK_PROC$K_ICACHE_READ_RETRY 150 #define MCK_PROC$K_PROC_HARD_ERROR 152 /* System detected error types */ /* Hex */ #define MCK_SYS$K_SYS_CORR_ECC 513 /* 201 */ #define MCK_SYS$K_SYS_UNCORR_ECC 515 /* 203 */ #define MCK_SYS$K_CIA_PE 517 /* 205 */ #define MCK_SYS$K_NXM 519 /* 207 */ #define MCK_SYS$K_PCI_SERR 521 /* 209 */ #define MCK_SYS$K_PCI_D_PE 523 /* 20b */ #define MCK_SYS$K_PCI_A_PE 525 /* 20d */ #define MCK_SYS$K_PCI_MASTER_AB 527 /* 20f */ #define MCK_SYS$K_PCI_TARG_AB 529 /* 211 */ #define MCK_SYS$K_SG_INV_PTE 531 /* 213 */ #define MCK_SYS$K_FLASH_WR_ERR 533 /* 215 */ #define MCK_SYS$K_IOA_TIMEOUT 535 /* 217 */ #define MCK_SYS$K_IOCHK 537 /* 219 */ #define MCK_SYS$K_EISA_FS_TO 539 /* 21b */ #define MCK_SYS$K_EISA_BUS_TO 541 /* 21d */ #define MCK_SYS$K_EISA_SW_NMI 543 /* 21f */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __CIA_MCHKDEF_LOADED */