/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:53 by OpenVMS SDL EV3-3 */ /* Source: 23-JAN-1996 10:41:54 $1$DGA7274:[LIB_H.SRC]CIA_DEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $CIA_DEF ***/ #ifndef __CIA_DEF_LOADED #define __CIA_DEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define CIA$L_NODE_PA_H 135 /* High order word */ #define CIA$L_CIA_GENERAL_L 1073741824 #define CIA$L_CIA_MEMORY_L 1342177280 #define CIA$L_CIA_PCI_ADDR_L 1610612736 #define CIA$L_FLASH_AND_GRU_L -2147483648 #define CIA$L_PCI_REV_L 128 /*PCI revision */ #define CIA$L_PCI_LAT_L 192 /*PCI Latency */ #define CIA$L_CIA_CTRL_L 256 /*CIA COntrol */ #define CIA$L_HAE_MEM_L 1024 /*HAE memory */ #define CIA$L_HAE_IO_L 1088 /*HAE I/O */ #define CIA$L_HAE_CFG_L 1152 /*COnfig */ #define CIA$L_CIA_CACK_EN_L 1536 /*Ack control */ #define CIA$L_CIA_DIAG_L 8192 /*Diag control */ #define CIA$L_CIA_CHECK_L 12288 /*Diag check */ #define CIA$L_PERF_MON_L 16384 /*Perf monitor */ #define CIA$L_PERF_CNTR_L 16448 /*Perf control */ #define CIA$L_CPU_ERR0_L 32768 /*Cpu err info 0 */ #define CIA$L_CPU_ERR1_L 32832 /*Cpu err info 1 */ #define CIA$L_CIA_ERR_L 33280 /*CIA err */ #define CIA$L_CIA_STAT_L 33344 /*CIA status */ #define CIA$L_CIA_ERR_MSK_L 33408 /*CIA err mask */ #define CIA$L_CIA_SYN_L 33536 /*CIA syndrome */ #define CIA$L_CPU_MPSR0_L 33792 /*Memport stat0 */ #define CIA$L_CPU_MPSR1_L 33856 /*Memport stat1 */ #define CIA$L_PCI_ERR0_L 34816 /*PCI Err 0 */ #define CIA$L_PCI_ERR1_L 34880 /*PCI Err 1 */ #define CIA$L_PCI_ERR2_L 34944 /*PCI Err 1 */ #define CIA$L_MEM_CNFG_L 0 /*Memory config */ #define CIA$L_MEM_BA0_L 1536 /*Mem base addr0 */ #define CIA$L_MEM_BA2_L 1664 /*Mem base addr2 */ #define CIA$L_MEM_BA4_L 1792 /*Mem base addr4 */ #define CIA$L_MEM_BA6_L 1920 /*Mem base addr6 */ #define CIA$L_MEM_BA8_L 2048 /*Mem base addr8 */ #define CIA$L_MEM_BAA_L 2176 /*Mem base addrA */ #define CIA$L_MEM_BAC_L 2304 /*Mem base addrC */ #define CIA$L_MEM_BAE_L 2432 /*Mem base addrE */ #define CIA$L_MEM_TMG0_L 2816 /*Mem timing 0 */ #define CIA$L_MEM_TMG1_L 2880 /*Mem timing 1 */ #define CIA$L_MEM_TMG2_L 2944 /*Mem timing 2 */ #define CIA$L_PCI_TBIA_L 256 /*SG TB inval */ #define CIA$L_PCI_W0_BASE_L 1024 /*Window base0 */ #define CIA$L_PCI_W0_MASK_L 1088 /*Window mask0 */ #define CIA$L_PCI_T0_BASE_L 1152 /*Trans base0 */ #define CIA$L_PCI_W1_BASE_L 1280 /*Window base1 */ #define CIA$L_PCI_W1_MASK_L 1344 /*Window mask1 */ #define CIA$L_PCI_T1_BASE_L 1408 /*Trans base1 */ #define CIA$L_PCI_W2_BASE_L 1536 /*Window base2 */ #define CIA$L_PCI_W2_MASK_L 1600 /*Window mask2 */ #define CIA$L_PCI_T2_BASE_L 1664 /*Trans base2 */ #define CIA$L_PCI_W3_BASE_L 1792 /*Window base3 */ #define CIA$L_PCI_W3_MASK_L 1856 /*Window mask3 */ #define CIA$L_PCI_T3_BASE_L 1920 /*Trans base3 */ #define CIA$L_PCI_DAC_BASE_L 1984 /*DAC Base */ #define CIA$L_PCI_LTB_TAG0_L 2048 /*Lock TB tag0 */ #define CIA$L_PCI_LTB_TAG1_L 2112 /*Lock TB tag1 */ #define CIA$L_PCI_LTB_TAG2_L 2176 /*Lock TB tag2 */ #define CIA$L_PCI_LTB_TAG3_L 2240 /*Lock TB tag3 */ #define CIA$L_PCI_TB_TAG0_L 2304 /* TB tag0 */ #define CIA$L_PCI_TB_TAG1_L 2368 /* TB tag1 */ #define CIA$L_PCI_TB_TAG2_L 2432 /* TB tag2 */ #define CIA$L_PCI_TB_TAG3_L 2496 /* TB tag3 */ #define CIA$L_PCI_TB0_PAGE0_L 4096 /* TB0 page0 */ #define CIA$L_PCI_TB0_PAGE1_L 4160 /* TB0 page1 */ #define CIA$L_PCI_TB0_PAGE2_L 4224 /* TB0 page2 */ #define CIA$L_PCI_TB0_PAGE3_L 4288 /* TB0 page3 */ #define CIA$L_PCI_TB1_PAGE0_L 4352 /* TB1 page0 */ #define CIA$L_PCI_TB1_PAGE1_L 4416 /* TB1 page1 */ #define CIA$L_PCI_TB1_PAGE2_L 4480 /* TB1 page2 */ #define CIA$L_PCI_TB1_PAGE3_L 4544 /* TB1 page3 */ #define CIA$L_PCI_TB2_PAGE0_L 4608 /* TB2 page0 */ #define CIA$L_PCI_TB2_PAGE1_L 4672 /* TB2 page1 */ #define CIA$L_PCI_TB2_PAGE2_L 4736 /* TB2 page2 */ #define CIA$L_PCI_TB2_PAGE3_L 4800 /* TB2 page3 */ #define CIA$L_PCI_TB3_PAGE0_L 4864 /* TB3 page0 */ #define CIA$L_PCI_TB3_PAGE1_L 4928 /* TB3 page1 */ #define CIA$L_PCI_TB3_PAGE2_L 4992 /* TB3 page2 */ #define CIA$L_PCI_TB3_PAGE3_L 5056 /* TB3 page3 */ #define CIA$L_PCI_TB4_PAGE0_L 5120 /* TB4 page0 */ #define CIA$L_PCI_TB4_PAGE1_L 5184 /* TB4 page1 */ #define CIA$L_PCI_TB4_PAGE2_L 5248 /* TB4 page2 */ #define CIA$L_PCI_TB4_PAGE3_L 5312 /* TB4 page3 */ #define CIA$L_PCI_TB5_PAGE0_L 5376 /* TB5 page0 */ #define CIA$L_PCI_TB5_PAGE1_L 5440 /* TB5 page1 */ #define CIA$L_PCI_TB5_PAGE2_L 5504 /* TB5 page2 */ #define CIA$L_PCI_TB5_PAGE3_L 5568 /* TB5 page3 */ #define CIA$L_PCI_TB6_PAGE0_L 5632 /* TB6 page0 */ #define CIA$L_PCI_TB6_PAGE1_L 5696 /* TB6 page1 */ #define CIA$L_PCI_TB6_PAGE2_L 5760 /* TB6 page2 */ #define CIA$L_PCI_TB6_PAGE3_L 5824 /* TB6 page3 */ #define CIA$L_PCI_TB7_PAGE0_L 5888 /* TB7 page0 */ #define CIA$L_PCI_TB7_PAGE1_L 5952 /* TB7 page1 */ #define CIA$L_PCI_TB7_PAGE2_L 6016 /* TB7 page2 */ #define CIA$L_PCI_TB7_PAGE3_L 6080 /* TB7 page3 */ #define CIA$M_CIA_CTRL_PCI_EN 0x1 #define CIA$M_CIA_CTRL_PCI_LOCK_EN 0x2 #define CIA$M_CIA_CTRL_PCI_LOOP_EN 0x4 #define CIA$M_CIA_CTRL_FST_BB_EN 0x8 #define CIA$M_CIA_CTRL_MST_EN 0x10 #define CIA$M_CIA_CTRL_MEM_EN 0x20 #define CIA$M_CIA_CTRL_REQ64_EN 0x40 #define CIA$M_CIA_CTRL_ACK64_EN 0x80 #define CIA$M_CIA_CTRL_ADDR_PE_EN 0x100 #define CIA$M_CIA_CTRL_PERR_EN 0x200 #define CIA$M_CIA_CTRL_FILL_ERR_EN 0x400 #define CIA$M_CIA_CTRL_ECC_CHK_EN 0x1000 #define CIA$M_CIA_CTRL_CACK_EN_PE 0x2000 #define CIA$M_CIA_CTRL_CON_IDLE_BC 0x4000 #define CIA$M_CIA_CTRL_CSR_IOA_BYP 0x8000 #define CIA$M_CIA_CTRL_IO_FLUSH_REQ 0x10000 #define CIA$M_CIA_CTRL_CPU_FLUSH_REQ 0x20000 #define CIA$M_CIA_CTRL_ARB_EV5_EN 0x40000 #define CIA$M_CIA_CTRL_EN_ARB_LINK 0x80000 #define CIA$M_CIA_CTRL_RD_TYP 0x300000 #define CIA$M_CIA_CTRL_RL_TYP 0x3000000 #define CIA$M_CIA_CTRL_RM_TYP 0x30000000 #define CIA$M_CIA_CNFG_PCI_WIDTH 0x100 #define CIA$M_CIA_CNFG_IOD_WIDTH 0x10000 #define CIA$M_HAE_MEM_REG_3 0xFC #define CIA$M_HAE_MEM_REG_2 0xF800 #define CIA$M_HAE_MEM_REG_1 0xE0000000 #define CIA$M_HAE_IO 0xFE000000 #define CIA$M_FROM_EN 0x1 #define CIA$M_USE_CHECK 0x2 #define CIA$M_FPE_PCI 0x30000000 #define CIA$M_FPE_TO_EV5 0x80000000 #define CIA$M_CPU_ERR0_ADDR 0xFFFFFFF0 #define CIA$M_CPU_ERR1_3432 0x7 #define CIA$M_CPU_ERR1_39 0x80 #define CIA$M_CPU_ERR1_CMD 0xF00 #define CIA$M_CPU_ERR1_INT4_VALID 0xF000 #define CIA$M_CPU_ERR1_AC_PAR 0x200000 #define CIA$M_CPU_ERR1_FPE 0x40000000 #define CIA$M_CPU_ERR1_PE 0x80000000 #define CIA$M_ERR_CORR_ECC 0x1 #define CIA$M_ERR_UNC_ECC 0x2 #define CIA$M_ERR_CPU_PE 0x4 #define CIA$M_ERR_MEM_NEM 0x8 #define CIA$M_ERR_PCI_SERR 0x10 #define CIA$M_ERR_PCI_PERR 0x20 #define CIA$M_ERR_PCI_ADR_PE 0x40 #define CIA$M_ERR_M_ABORT 0x80 #define CIA$M_ERR_T_ABORT 0x100 #define CIA$M_ERR_PA_PTE_INV 0x200 #define CIA$M_ERR_FROM_WRT_ERR 0x400 #define CIA$M_ERR_IOA_TIMEOUT 0x800 #define CIA$M_ERR_LOST_CORR_ECC 0x10000 #define CIA$M_ERR_LOST_UNC_ECC 0x20000 #define CIA$M_ERR_LOST_CPU_PE 0x40000 #define CIA$M_ERR_LOST_MEM_NEM 0x80000 #define CIA$M_ERR_LOST_PCI_SERR 0x100000 #define CIA$M_ERR_LOST_PCI_PERR 0x200000 #define CIA$M_ERR_LOST_PCI_ADR_PE 0x400000 #define CIA$M_ERR_LOST_M_ABORT 0x800000 #define CIA$M_ERR_LOST_T_ABORT 0x1000000 #define CIA$M_ERR_LOST_PA_PTE_INV 0x2000000 #define CIA$M_ERR_LOST_FROM_WRT_ERR 0x4000000 #define CIA$M_ERR_LOST_IOA_TIMEOUT 0x8000000 #define CIA$M_ERR_VALID 0x80000000 #define DM_K_IDLE 0 #define DM_K_RESTART 4096 #define DM_K_IOW_64 8192 #define DM_K_IOW_32 12288 #define DM_K_R_4 16384 #define DM_K_NONE 20480 #define DM_K_DMA_RD 24576 #define DM_K_DMA_WR 28672 #define DM_K_GRU_WR 32768 #define DM_K_GRU_RD 36864 #define DM_K_CSR_RD 40960 #define DM_K_PCI_RD 45056 #define CIA$M_STAT_PCI_STATUS 0x3 #define CIA$M_STAT_MEM_SOURCE 0x8 #define CIA$M_STAT_IO_QUEUE 0xF0 #define CIA$M_STAT_CPU_QUEUE 0x700 #define CIA$M_STAT_TLB_MISS 0x800 #define CIA$M_STAT_DM_STAT 0xF000 #define CIA$M_STAT_PA_CPU_RES 0x30000 #define CIA$M_MASK_CORR_ECC_ERR 0x1 #define CIA$M_MASK_UNC_ECC_ERR 0x2 #define CIA$M_MASK_CPU_PE 0x4 #define CIA$M_MASK_MEM_NEM 0x8 #define CIA$M_MASK_PCI_SERR 0x10 #define CIA$M_MASK_PCI_PERR 0x20 #define CIA$M_MASK_PCI_ADR_PE 0x40 #define CIA$M_MASK_M_ABORT 0x80 #define CIA$M_MASK_T_ABORT 0x100 #define CIA$M_MASK_PA_PTE_INV 0x200 #define CIA$M_MASK_FROM_WRT_ERR 0x400 #define CIA$M_MASK_IOA_TIMEOUT 0x800 #define CIA$M_CIA_SYNDROME 0xFF #define CIA$M_MPSR0_ADDR_H 0xFFFFFFF0 #define CIA$M_MPSR1_ADDR_H 0x3 #define CIA$M_MPSR1_ADDR_39 0x80 #define CIA$M_MPSR1_CMD_H 0xF00 #define CIA$M_MPSR1_PORT_MASK 0xF000 #define CIA$M_MPSR1_SEQ_ST 0xF0000 #define CIA$M_MPSR1_PORT_SRC 0x100000 #define CIA$M_MPSR1_SET_SEL 0x1F000000 #define CIA$M_PCIE_CMD 0xF #define CIA$M_PCIE_LOCK_STATE 0x10 #define CIA$M_PCIE_DAC_CYCLE 0x20 #define CIA$M_PCIE_WINDOW 0xF00 #define CIA$M_PCIE_MSTR_STATE 0xF0000 #define CIA$M_PCIE_TRGT_STATE 0x700000 #define CIA$M_MCR_MEM_SIZE 0x1 #define CIA$M_MCR_CACHE_SIZE 0x70 #define CIA$M_MCR_REF_RATE 0x3FF00 #define CIA$M_MCR_REF_BURST 0xC0000 #define CIA$M_MCR_TMG_R0 0x300000 #define CIA$M_MCR_LONG_CBR_CAS 0x400000 #define CIA$M_MCR_DLY_IDLE_BC 0xC000000 #define CIA$M_MCR_EARLY_IDLE_BC 0x20000000 #define CIA$M_MBA0_S0_VALID 0x1 #define CIA$M_MBA0_ROW_TYPE 0x6 #define CIA$M_MBA0_MASK 0x1F0 #define CIA$M_MBA0_S1_VALID 0x8000 #define CIA$M_MBA0_PATTERN 0x3FF0000 #define CIA$M_MBA0_TIMING 0x30000000 #define CIA$M_MBA0_RESERVED_5 0xC0000000 #define CIA$M_MBA2_S0_VALID 0x1 #define CIA$M_MBA2_ROW_TYPE 0x6 #define CIA$M_MBA2_MASK 0x1F0 #define CIA$M_MBA2_S1_VALID 0x8000 #define CIA$M_MBA2_PATTERN 0x3FF0000 #define CIA$M_MBA2_TIMING 0x30000000 #define CIA$M_MBA4_S0_VALID 0x1 #define CIA$M_MBA4_ROW_TYPE 0x6 #define CIA$M_MBA4_MASK 0x1F0 #define CIA$M_MBA4_S1_VALID 0x8000 #define CIA$M_MBA4_PATTERN 0x3FF0000 #define CIA$M_MBA4_TIMING 0x30000000 #define CIA$M_MBA6_S0_VALID 0x1 #define CIA$M_MBA6_ROW_TYPE 0x6 #define CIA$M_MBA6_MASK 0x1F0 #define CIA$M_MBA6_S1_VALID 0x8000 #define CIA$M_MBA6_PATTERN 0x3FF0000 #define CIA$M_MBA6_TIMING 0x30000000 #define CIA$M_MBA8_S0_VALID 0x1 #define CIA$M_MBA8_ROW_TYPE 0x6 #define CIA$M_MBA8_MASK 0x1F0 #define CIA$M_MBA8_S1_VALID 0x8000 #define CIA$M_MBA8_PATTERN 0x3FF0000 #define CIA$M_MBA8_TIMING 0x30000000 #define CIA$M_MBAA_S0_VALID 0x1 #define CIA$M_MBAA_ROW_TYPE 0x6 #define CIA$M_MBAA_MASK 0x1F0 #define CIA$M_MBAA_S1_VALID 0x8000 #define CIA$M_MBAA_PATTERN 0x3FF0000 #define CIA$M_MBAA_TIMING 0x30000000 #define CIA$M_MBAC_S0_VALID 0x1 #define CIA$M_MBAC_ROW_TYPE 0x6 #define CIA$M_MBAC_MASK 0x1F0 #define CIA$M_MBAC_S1_VALID 0x8000 #define CIA$M_MBAC_PATTERN 0x3FF0000 #define CIA$M_MBAC_TIMING 0x30000000 #define CIA$M_MBAE_S0_VALID 0x1 #define CIA$M_MBAE_ROW_TYPE 0x6 #define CIA$M_MBAE_MASK 0x1F0 #define CIA$M_MBAE_S1_VALID 0x8000 #define CIA$M_MBAE_PATTERN 0x3FF0000 #define CIA$M_MBAE_TIMING 0x30000000 #define CIA$M_TMG0_R1 0x3 #define CIA$M_TMG0_R2 0xC #define CIA$M_TMG0_R3 0x30 #define CIA$M_TMG0_R4 0xC0 #define CIA$M_TMG0_R5 0x300 #define CIA$M_TMG0_R6 0xC00 #define CIA$M_TMG0_W1 0x7000 #define CIA$M_TMG0_W4 0x38000 #define CIA$M_TMG0_PRE 0x40000 #define CIA$M_TMG0_V3 0x180000 #define CIA$M_TMG0_V4 0x600000 #define CIA$M_TMG0_V5 0x3000000 #define CIA$M_TMG0_V6 0xC000000 #define CIA$M_TMG0_RV 0x30000000 #define CIA$M_TMG0_RD_DLY 0xC0000000 #define CIA$M_TMG1_R1 0x3 #define CIA$M_TMG1_R2 0xC #define CIA$M_TMG1_R3 0x30 #define CIA$M_TMG1_R4 0xC0 #define CIA$M_TMG1_R5 0x300 #define CIA$M_TMG1_R6 0xC00 #define CIA$M_TMG1_W1 0x7000 #define CIA$M_TMG1_W4 0x38000 #define CIA$M_TMG1_PRE 0x40000 #define CIA$M_TMG1_V3 0x180000 #define CIA$M_TMG1_V4 0x600000 #define CIA$M_TMG1_V5 0x3000000 #define CIA$M_TMG1_V6 0xC000000 #define CIA$M_TMG1_RV 0x30000000 #define CIA$M_TMG1_RD_DLY 0xC0000000 #define CIA$M_TMG2_R1 0x3 #define CIA$M_TMG2_R2 0xC #define CIA$M_TMG2_R3 0x30 #define CIA$M_TMG2_R4 0xC0 #define CIA$M_TMG2_R5 0x300 #define CIA$M_TMG2_R6 0xC00 #define CIA$M_TMG2_W1 0x7000 #define CIA$M_TMG2_W4 0x38000 #define CIA$M_TMG2_PRE 0x40000 #define CIA$M_TMG2_V3 0x180000 #define CIA$M_TMG2_V4 0x600000 #define CIA$M_TMG2_V5 0x3000000 #define CIA$M_TMG2_V6 0xC000000 #define CIA$M_TMG2_RV 0x30000000 #define CIA$M_TMG2_RD_DLY 0xC0000000 #define CIA$M_TBIA_CSR_WR_DATA 0x3 #define CIA$M_WBASE0_W_EN 0x1 #define CIA$M_WBASE0_SG_EN 0x2 #define CIA$M_WBASE0_MEMCS_EN 0x4 #define CIA$M_WBASE0_DAC_EN 0x8 #define CIA$M_WBASE0_BASE 0xFFF00000 #define CIA$M_WMASK0_MASK 0xFFF00000 #define CIA$M_TBASE0_BASE 0xFFFFFF00 #define CIA$M_WBASE1_W_EN 0x1 #define CIA$M_WBASE1_SG_EN 0x2 #define CIA$M_WBASE1_MEMCS_EN 0x4 #define CIA$M_WBASE1_DAC_EN 0x8 #define CIA$M_WBASE1_BASE 0xFFF00000 #define CIA$M_WMASK1_MASK 0xFFF00000 #define CIA$M_TBASE1_BASE 0xFFFFFF00 #define CIA$M_WBASE2_W_EN 0x1 #define CIA$M_WBASE2_SG_EN 0x2 #define CIA$M_WBASE2_MEMCS_EN 0x4 #define CIA$M_WBASE2_DAC_EN 0x8 #define CIA$M_WBASE2_BASE 0xFFF00000 #define CIA$M_WMASK2_MASK 0xFFF00000 #define CIA$M_TBASE2_BASE 0xFFFFFF00 #define CIA$M_WBASE3_W_EN 0x1 #define CIA$M_WBASE3_SG_EN 0x2 #define CIA$M_WBASE3_MEMCS_EN 0x4 #define CIA$M_WBASE3_DAC_EN 0x8 #define CIA$M_WBASE3_BASE 0xFFF00000 #define CIA$M_WMASK3_MASK 0xFFF00000 #define CIA$M_TBASE3_BASE 0xFFFFFF00 #define CIA$M_DAC_BASE 0xFF #define CIA$M_LTB0_VALID 0x1 #define CIA$M_LTB0_LOCKED 0x2 #define CIA$M_LTB0_DAC 0x4 #define CIA$M_LTB0_TAG 0xFFFF8000 #define CIA$M_LTB1_VALID 0x1 #define CIA$M_LTB1_LOCKED 0x2 #define CIA$M_LTB1_DAC 0x4 #define CIA$M_LTB1_TAG 0xFFFF8000 #define CIA$M_LTB2_VALID 0x1 #define CIA$M_LTB2_LOCKED 0x2 #define CIA$M_LTB2_DAC 0x4 #define CIA$M_LTB2_TAG 0xFFFF8000 #define CIA$M_LTB3_VALID 0x1 #define CIA$M_LTB3_LOCKED 0x2 #define CIA$M_LTB3_DAC 0x4 #define CIA$M_LTB3_TAG 0xFFFF8000 #define CIA$M_TB0_VALID 0x1 #define CIA$M_TB0_DAC 0x4 #define CIA$M_TB0_TAG 0xFFFF8000 #define CIA$M_TB1_VALID 0x1 #define CIA$M_TB1_DAC 0x4 #define CIA$M_TB1_TAG 0xFFFF8000 #define CIA$M_TB2_VALID 0x1 #define CIA$M_TB2_DAC 0x4 #define CIA$M_TB2_TAG 0xFFFF8000 #define CIA$M_TB3_VALID 0x1 #define CIA$M_TB3_DAC 0x4 #define CIA$M_TB3_TAG 0xFFFF8000 #define CIA$M_TB0_PAGE0_VALID 0x1 #define CIA$M_TB0_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB0_PAGE1_VALID 0x1 #define CIA$M_TB0_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB0_PAGE2_VALID 0x1 #define CIA$M_TB0_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB0_PAGE3_VALID 0x1 #define CIA$M_TB0_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB1_PAGE0_VALID 0x1 #define CIA$M_TB1_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB1_PAGE1_VALID 0x1 #define CIA$M_TB1_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB1_PAGE2_VALID 0x1 #define CIA$M_TB1_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB1_PAGE3_VALID 0x1 #define CIA$M_TB1_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB2_PAGE0_VALID 0x1 #define CIA$M_TB2_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB2_PAGE1_VALID 0x1 #define CIA$M_TB2_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB2_PAGE2_VALID 0x1 #define CIA$M_TB2_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB2_PAGE3_VALID 0x1 #define CIA$M_TB2_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB3_PAGE0_VALID 0x1 #define CIA$M_TB3_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB3_PAGE1_VALID 0x1 #define CIA$M_TB3_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB3_PAGE2_VALID 0x1 #define CIA$M_TB3_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB3_PAGE3_VALID 0x1 #define CIA$M_TB3_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB4_PAGE0_VALID 0x1 #define CIA$M_TB4_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB4_PAGE1_VALID 0x1 #define CIA$M_TB4_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB4_PAGE2_VALID 0x1 #define CIA$M_TB4_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB4_PAGE3_VALID 0x1 #define CIA$M_TB4_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB5_PAGE0_VALID 0x1 #define CIA$M_TB5_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB5_PAGE1_VALID 0x1 #define CIA$M_TB5_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB5_PAGE2_VALID 0x1 #define CIA$M_TB5_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB5_PAGE3_VALID 0x1 #define CIA$M_TB5_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB6_PAGE0_VALID 0x1 #define CIA$M_TB6_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB6_PAGE1_VALID 0x1 #define CIA$M_TB6_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB6_PAGE2_VALID 0x1 #define CIA$M_TB6_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB6_PAGE3_VALID 0x1 #define CIA$M_TB6_PAGE3_ADDR 0x3FFFFE #define CIA$M_TB7_PAGE0_VALID 0x1 #define CIA$M_TB7_PAGE0_ADDR 0x3FFFFE #define CIA$M_TB7_PAGE1_VALID 0x1 #define CIA$M_TB7_PAGE1_ADDR 0x3FFFFE #define CIA$M_TB7_PAGE2_VALID 0x1 #define CIA$M_TB7_PAGE2_ADDR 0x3FFFFE #define CIA$M_TB7_PAGE3_VALID 0x1 #define CIA$M_TB7_PAGE3_ADDR 0x3FFFFE #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _cia { /* CIA ASIC revision 8740000080 */ #pragma __nomember_alignment unsigned char cia$b_fill00 [128]; __union { int cia$l_pci_cia_rev; __struct { char cia$b_cia_rev; /* CIA revision */ unsigned cia$v_fill01 : 24; } cia$r_rev_bits; } cia$r_pci_cia_revision; unsigned char cia$b_fill02 [60]; /* PCI master latency timeout 87400000C0 */ __union { int cia$l_pci_lat; __struct { char cia$b_fill10; char cia$b_pci_latency; /* CIA revision */ unsigned cia$v_fill11 : 16; } cia$r_latency_bits; } cia$r_pci_latency; unsigned char cia$b_fill20 [60]; /* CIA Control register 8740000100 */ __union { int cia$l_cia_ctl; __struct { unsigned cia$v_cia_ctrl_pci_en : 1; /*CIA disable/enable resets to PCI */ unsigned cia$v_cia_ctrl_pci_lock_en : 1; /*CIA locks from PCI enable */ unsigned cia$v_cia_ctrl_pci_loop_en : 1; /*CIA loopback enable */ unsigned cia$v_cia_ctrl_fst_bb_en : 1; /*CIA fast back-to-back enable */ unsigned cia$v_cia_ctrl_mst_en : 1; /*CIA is a PCI master enable */ unsigned cia$v_cia_ctrl_mem_en : 1; /*CIA is a PCI target enable */ unsigned cia$v_cia_ctrl_req64_en : 1; /*CIA will request 64bit PCI txactions */ unsigned cia$v_cia_ctrl_ack64_en : 1; /*CIA will accept 64bit PCI txactions */ unsigned cia$v_cia_ctrl_addr_pe_en : 1; /*CIA will check address parity enable */ unsigned cia$v_cia_ctrl_perr_en : 1; /*CIA will check PCI data enable */ unsigned cia$v_cia_ctrl_fill_err_en : 1; /*CIA will assert fill_err enable */ unsigned cia$v_fill20 : 1; unsigned cia$v_cia_ctrl_ecc_chk_en : 1; /*CIA checks IOD data enable */ unsigned cia$v_cia_ctrl_cack_en_pe : 1; /*CIA checks c/a parity on CACK */ unsigned cia$v_cia_ctrl_con_idle_bc : 1; /*CIA generated contig. IDLE_BC */ unsigned cia$v_cia_ctrl_csr_ioa_byp : 1; /*CIA bypasses I/O addr queue */ unsigned cia$v_cia_ctrl_io_flush_req : 1; /*Controls response to PCI FLUSH_REQ */ unsigned cia$v_cia_ctrl_cpu_flush_req : 1; /*Controls response to PCI FLUSH_REQ */ unsigned cia$v_cia_ctrl_arb_ev5_en : 1; /*Enable bypass path ev5 to mem/io */ unsigned cia$v_cia_ctrl_en_arb_link : 1; unsigned cia$v_cia_ctrl_rd_typ : 2; /*Control prefetch algorithm RD */ unsigned cia$v_fill21 : 2; unsigned cia$v_cia_ctrl_rl_typ : 2; /*Control prefetch algorithm RL */ unsigned cia$v_fill22 : 2; unsigned cia$v_cia_ctrl_rm_typ : 2; /*Control prefetch algorithm RM */ unsigned cia$v_fill23 : 2; } cia$r_cia_control_bits; } cia$r_cia_control; unsigned char cia$b_fill30 [252]; /* CIA Config => Size information of the two busses 8740000200 */ __union { int cia$l_cia_config; __struct { char cia$b_fill30a; unsigned cia$v_cia_cnfg_pci_width : 1; /* Bit is set -> 64bit PCI */ unsigned cia$v_fill31 : 7; unsigned cia$v_cia_cnfg_iod_width : 1; /* Bit is set -> 64bit IOD */ unsigned cia$v_fill32 : 15; } cia$r_cia_config_bits; } cia$r_cia_config_overlay; unsigned char cia$b_fill40 [508]; /* HAE MEM => Extends sparse space addr to full 32 bits 8740000400 */ __union { int cia$l_hae_mem; __struct { unsigned cia$v_fill40a : 2; unsigned cia$v_hae_mem_reg_3 : 6; /* High order sparse bits */ unsigned cia$v_fill41 : 3; unsigned cia$v_hae_mem_reg_2 : 5; /* High order sparse bits */ unsigned cia$v_fill42 : 13; unsigned cia$v_hae_mem_reg_1 : 3; /* High order sparse bits */ } cia$r_hae_mem_bits; } cia$r_hae_mem_overlay; unsigned char cia$b_fill50 [60]; /* HAE IO => Extends sparse space addr to full 32 bits 8740000440 */ __union { int cia$l_hae_io; __struct { unsigned cia$v_fill51 : 25; unsigned cia$v_hae_io : 7; /* High order sparse bits */ } cia$r_hae_io_bits; } cia$r_hae_io_overlay; unsigned char cia$b_fill60 [60]; /* CFG => Low two address bits during access to PCI COnfig space 8740000480 */ __union { int cia$l_cfg; __struct { unsigned cia$v_cfg_bits : 2; /* Low order bits of config space ref */ unsigned cia$v_fill61 : 29; unsigned cia$v_fill_0_ : 1; } cia$r_cgf_bits_overlay; } cia$r_cfg_overlay; unsigned char cia$b_fill70 [380]; /* CACK_EN Enable CIA's response to EV5 commands 840000600 */ __union { int cia$l_cack_en; __struct { unsigned cia$v_cack_en_bits : 4; /* Control CIA's response to EV5 */ unsigned cia$v_fill71 : 28; } cia$r_cack_en_bits; } cia$r_cack_en_overlay; unsigned char cia$b_fill80 [6652]; /* CIA_DIAG Diagnostic control enable 840002000 */ __union { int cia$l_cia_diag; __struct { unsigned cia$v_from_en : 1; /* FROM write enable */ unsigned cia$v_use_check : 1; /* USed with DIA_CHECK for ECC testing */ unsigned cia$v_fill81 : 26; unsigned cia$v_fpe_pci : 2; /* Force bad parity on PCI */ unsigned cia$v_fill82 : 1; unsigned cia$v_fpe_to_ev5 : 1; /* Force parity error */ } cia$r_cia_diag_bits; } cia$r_cia_diag_overlay; unsigned char cia$b_fill90 [4092]; /* DIAG_CHECK Diagnostic used to write a known ECC pattern 840003000 */ __union { int cia$l_diag_check; __struct { char cia$b_diag_check_ecc; /* ECC to be used */ unsigned cia$v_fill91 : 24; } cia$r_diag_check_bits; } cia$r_diag_check_overlay; unsigned char cia$b_fill100 [4092]; /* Perf Monitor counts 8740004000 */ __union { int cia$l_perf_monitor; } cia$r_perf_monitor_overlay; unsigned char cia$b_fill110 [60]; /* Perf Monitor control 8740004040 */ __union { int cia$l_perf_control; } cia$r_perf_control_overlay; unsigned char cia$b_fill120 [16316]; /* CPU Error reigster 0 8740008000 */ __union { int cia$l_cpu_err0; __struct { unsigned cia$v_fillc0 : 4; unsigned cia$v_cpu_err0_addr : 28; /* Bad addr on EV5 interface error */ } cia$r_cpu_err0_bits; } cia$r_cpu_err0_overlay; unsigned char cia$b_fill130 [60]; /* CPU error register 1 8740008040 */ __union { int cia$l_cpu_err1; __struct { unsigned cia$v_cpu_err1_3432 : 3; /* CPU addr <34:32> on error */ unsigned cia$v_filld0 : 4; unsigned cia$v_cpu_err1_39 : 1; /* CPU addr <39> on error */ unsigned cia$v_cpu_err1_cmd : 4; /* CPU command */ unsigned cia$v_cpu_err1_int4_valid : 4; /* INT4 valid bits */ unsigned cia$v_filld1 : 5; unsigned cia$v_cpu_err1_ac_par : 1; /* Parity bit from CPU Addr/cmd */ unsigned cia$v_filld2 : 8; unsigned cia$v_cpu_err1_fpe : 1; /*Copy of csr bit to force bad parity */ unsigned cia$v_cpu_err1_pe : 1; /*IF set, CPU detected PE. */ } cia$r_cpu_err1_bits; } cia$r_cpu_err1_overlay; unsigned char cia$b_fill140 [444]; /* CIA Error reigster 8740008200 */ __union { int cia$l_cia_err; __struct { unsigned cia$v_err_corr_ecc : 1; /* [0] */ unsigned cia$v_err_unc_ecc : 1; /* [1] */ unsigned cia$v_err_cpu_pe : 1; /* [2] */ unsigned cia$v_err_mem_nem : 1; /* [3] */ unsigned cia$v_err_pci_serr : 1; /* [4] */ unsigned cia$v_err_pci_perr : 1; /* [5] */ unsigned cia$v_err_pci_adr_pe : 1; /* [6] */ unsigned cia$v_err_m_abort : 1; /* [7] */ unsigned cia$v_err_t_abort : 1; /* [8] */ unsigned cia$v_err_pa_pte_inv : 1; /* [9] */ unsigned cia$v_err_from_wrt_err : 1; /* [10] */ unsigned cia$v_err_ioa_timeout : 1; /* [11] */ unsigned cia$v_err_ioa_reserved_0 : 4; /* [15:12] */ unsigned cia$v_err_lost_corr_ecc : 1; unsigned cia$v_err_lost_unc_ecc : 1; unsigned cia$v_err_lost_cpu_pe : 1; unsigned cia$v_err_lost_mem_nem : 1; unsigned cia$v_err_lost_pci_serr : 1; unsigned cia$v_err_lost_pci_perr : 1; unsigned cia$v_err_lost_pci_adr_pe : 1; unsigned cia$v_err_lost_m_abort : 1; unsigned cia$v_err_lost_t_abort : 1; unsigned cia$v_err_lost_pa_pte_inv : 1; unsigned cia$v_err_lost_from_wrt_err : 1; unsigned cia$v_err_lost_ioa_timeout : 1; unsigned cia$v_err_lost_reserved_1 : 3; /* */ unsigned cia$v_err_valid : 1; } cia$r_cia_err_bits; } cia$r_cia_err_overlay; unsigned char cia$b_fill150 [60]; /* */ /* CIA Error status register - 0x8740008240 */ /* */ __union { int cia$l_cia_stat; __struct { unsigned cia$v_stat_pci_status : 2; /* [1:0] */ unsigned cia$v_stat_fill1 : 1; /* [2] */ unsigned cia$v_stat_mem_source : 1; /* [3] */ unsigned cia$v_stat_io_queue : 4; /* [7:4] */ unsigned cia$v_stat_cpu_queue : 3; /* [10:8] */ unsigned cia$v_stat_tlb_miss : 1; /* [11] */ unsigned cia$v_stat_dm_stat : 4; /* [15:12] */ unsigned cia$v_stat_pa_cpu_res : 2; /* [17:16] */ unsigned cia$v_stat_reserved_0 : 14; /* [31:18] */ } cia$r_cia_stat_bits; } cia$r_cia_stat_overlay; unsigned char cia$b_fill160 [60]; /* */ /* */ /* CIA Error mask register - 0x8740008280 */ /* */ __union { int cia$l_cia_error_mask; __struct { unsigned cia$v_mask_corr_ecc_err : 1; /* [0] */ unsigned cia$v_mask_unc_ecc_err : 1; /* [1] */ unsigned cia$v_mask_cpu_pe : 1; /* [2] */ unsigned cia$v_mask_mem_nem : 1; /* [3] */ unsigned cia$v_mask_pci_serr : 1; /* [4] */ unsigned cia$v_mask_pci_perr : 1; /* [5] */ unsigned cia$v_mask_pci_adr_pe : 1; /* [6] */ unsigned cia$v_mask_m_abort : 1; /* [7] */ unsigned cia$v_mask_t_abort : 1; /* [8] */ unsigned cia$v_mask_pa_pte_inv : 1; /* [9] */ unsigned cia$v_mask_from_wrt_err : 1; /* [10] */ unsigned cia$v_mask_ioa_timeout : 1; /* [11] */ unsigned cia$v_mask_reserved_1 : 20; /* [30:12] */ } cia$r_cia_error_mask_bits; } cia$r_cia_error_mask_overlay; unsigned char cia$b_fill170 [124]; /* */ /* CIA Error Syndrome register - 0x8740008300 */ /* */ __union { int cia$l_cia_synd; __struct { unsigned cia$v_cia_syndrome : 8; unsigned cia$v_fill : 24; } cia$r_cia_synd_bits; } cia$r_cia_syndrome; unsigned char cia$b_fill180 [252]; /* */ /* CIA Memory Port status register 0 - 0x8740008400 */ /* */ __union { int cia$l_cia_mpsr0; __struct { unsigned cia$v_unused_0 : 4; unsigned cia$v_mpsr0_addr_h : 28; } cia$r_cia_mpsr0_bits; } cia$r_cia_mpsr0_overlay; unsigned char cia$b_fill190 [60]; /* */ /* CIA Memory Port status register 1 - 0x8740008440 */ /* */ __union { int cia$l_cia_mpsr1; __struct { unsigned cia$v_mpsr1_addr_h : 2; /* [1:0] */ unsigned cia$v_mpsr1_reserved : 5; /* [6:2] */ unsigned cia$v_mpsr1_addr_39 : 1; /* [7] */ unsigned cia$v_mpsr1_cmd_h : 4; /* [11:8] */ unsigned cia$v_mpsr1_port_mask : 4; /* [15:12] */ unsigned cia$v_mpsr1_seq_st : 4; /* [19:16] */ unsigned cia$v_mpsr1_port_src : 1; /* [20] */ unsigned cia$v_mpsr1_reserved_2 : 3; /* [23:21] */ unsigned cia$v_mpsr1_set_sel : 5; /* [28:24] */ unsigned cia$v_mpsr1_reserved_3 : 3; /* [31:29] */ } cia$r_cia_mpsr1_bits; } cia$r_cia_mpsr1_overlay; unsigned char cia$b_fill200 [956]; /* */ /* PCI Error register 0 - 0x8740008800 */ /* */ __union { int cia$l_cia_pcie0; __struct { unsigned cia$v_pcie_cmd : 4; /* [3:0] */ unsigned cia$v_pcie_lock_state : 1; /* [4] */ unsigned cia$v_pcie_dac_cycle : 1; /* [5] */ unsigned cia$v_pcie_reserved : 2; /* [7:6] */ unsigned cia$v_pcie_window : 4; /* [11:8] */ unsigned cia$v_pcie_reserved_2 : 4; /* [15:12] */ unsigned cia$v_pcie_mstr_state : 4; /* [19:16] */ unsigned cia$v_pcie_trgt_state : 3; /* [22:20] */ unsigned cia$v_pcie_unused_2 : 9; /* [31:23] */ } cia$r_cia_pcie_bits; } cia$r_cia_pcie0_overlay; unsigned char cia$b_fill210 [60]; /* */ /* CIA PCI error register 1 - 0x8740008840 */ /* */ __union { int cia$l_pcie1_mem_addr_h; } cia$r_cia_pcie1_overlay; unsigned char cia$b_fill220 [6076]; /* */ /* Memory Configuration Register - 0x8750000000 */ /* */ __union { int cia$l_mem_mcr; __struct { unsigned cia$v_mcr_mem_size : 1; /* */ unsigned cia$v_mcr_reserved : 3; /* */ unsigned cia$v_mcr_cache_size : 3; /* */ unsigned cia$v_mcr_reserved_2 : 1; /* */ unsigned cia$v_mcr_ref_rate : 10; /* */ unsigned cia$v_mcr_ref_burst : 2; /* */ unsigned cia$v_mcr_tmg_r0 : 2; /* */ unsigned cia$v_mcr_long_cbr_cas : 1; /* */ unsigned cia$v_mcr_reserved_3 : 3; /* */ unsigned cia$v_mcr_dly_idle_bc : 2; /* */ unsigned cia$v_mcr_unused_4 : 1; /* */ unsigned cia$v_mcr_early_idle_bc : 1; /* */ unsigned cia$v_mcr_unused_5 : 2; /* */ } cia$r_mem_mcr_bits; } cia$r_mem_mcr_overlay; unsigned char cia$b_fill230 [1532]; /* */ /* Memory Base Address 0 Register - 0x8750000600 */ /* */ __union { int cia$l_mem_mba0; __struct { unsigned cia$v_mba0_s0_valid : 1; /* */ unsigned cia$v_mba0_row_type : 2; /* */ unsigned cia$v_mba0_reserved : 1; /* */ unsigned cia$v_mba0_mask : 5; /* */ unsigned cia$v_mba0_reserved_2 : 6; /* */ unsigned cia$v_mba0_s1_valid : 1; /* */ unsigned cia$v_mba0_pattern : 10; /* */ unsigned cia$v_mba0_reserved_3 : 2; /* */ unsigned cia$v_mba0_timing : 2; /* */ unsigned cia$v_mba0_reserved_5 : 2; /* */ } cia$r_mem_mba0_bits; } cia$r_mem_mba0_overlay; unsigned char cia$b_fill240 [124]; /* */ /* Memory Base Address 2 Register - 0x8750000680 */ /* */ __union { int cia$l_mem_mba2; __struct { unsigned cia$v_mba2_s0_valid : 1; /* */ unsigned cia$v_mba2_row_type : 2; /* */ unsigned cia$v_mba2_reserved : 1; /* */ unsigned cia$v_mba2_mask : 5; /* */ unsigned cia$v_mba2_reserved_2 : 6; /* */ unsigned cia$v_mba2_s1_valid : 1; /* */ unsigned cia$v_mba2_pattern : 10; /* */ unsigned cia$v_mba2_reserved_3 : 2; /* */ unsigned cia$v_mba2_timing : 2; /* */ unsigned cia$v_mba2_reserved_5 : 2; /* */ } cia$r_mem_mba2_bits; } cia$r_mem_mba2_overlay; unsigned char cia$b_fill250 [124]; /* */ /* Memory Base Address 4 Register - 0x8750000700 */ /* */ __union { int cia$l_mem_mba4; __struct { unsigned cia$v_mba4_s0_valid : 1; /* */ unsigned cia$v_mba4_row_type : 2; /* */ unsigned cia$v_mba4_reserved : 1; /* */ unsigned cia$v_mba4_mask : 5; /* */ unsigned cia$v_mba4_reserved_2 : 6; /* */ unsigned cia$v_mba4_s1_valid : 1; /* */ unsigned cia$v_mba4_pattern : 10; /* */ unsigned cia$v_mba4_reserved_3 : 2; /* */ unsigned cia$v_mba4_timing : 2; /* */ unsigned cia$v_mba4_reserved_5 : 2; /* */ } cia$r_mem_mba4_bits; } cia$r_mem_mba4_overlay; unsigned char cia$b_fill260 [124]; /* */ /* Memory Base Address 6 Register - 0x8750000780 */ /* */ __union { int cia$l_mem_mba6; __struct { unsigned cia$v_mba6_s0_valid : 1; /* */ unsigned cia$v_mba6_row_type : 2; /* */ unsigned cia$v_mba6_reserved : 1; /* */ unsigned cia$v_mba6_mask : 5; /* */ unsigned cia$v_mba6_reserved_2 : 6; /* */ unsigned cia$v_mba6_s1_valid : 1; /* */ unsigned cia$v_mba6_pattern : 10; /* */ unsigned cia$v_mba6_reserved_3 : 2; /* */ unsigned cia$v_mba6_timing : 2; /* */ unsigned cia$v_mba6_reserved_5 : 2; /* */ } cia$r_mem_mba6_bits; } cia$r_mem_mba6_overlay; unsigned char cia$b_fill270 [124]; /* */ /* Memory Base Address 8 Register - 0x8750000800 */ /* */ __union { int cia$l_mem_mba8; __struct { unsigned cia$v_mba8_s0_valid : 1; /* */ unsigned cia$v_mba8_row_type : 2; /* */ unsigned cia$v_mba8_reserved : 1; /* */ unsigned cia$v_mba8_mask : 5; /* */ unsigned cia$v_mba8_reserved_2 : 6; /* */ unsigned cia$v_mba8_s1_valid : 1; /* */ unsigned cia$v_mba8_pattern : 10; /* */ unsigned cia$v_mba8_reserved_3 : 2; /* */ unsigned cia$v_mba8_timing : 2; /* */ unsigned cia$v_mba8_reserved_5 : 2; /* */ } cia$r_mem_mba8_bits; } cia$r_mem_mba8_overlay; unsigned char cia$b_fill280 [124]; /* */ /* Memory Base Address 10 Register - 0x8750000880 */ /* */ __union { int cia$l_mem_mbaa; __struct { unsigned cia$v_mbaa_s0_valid : 1; /* */ unsigned cia$v_mbaa_row_type : 2; /* */ unsigned cia$v_mbaa_reserved : 1; /* */ unsigned cia$v_mbaa_mask : 5; /* */ unsigned cia$v_mbaa_reserved_2 : 6; /* */ unsigned cia$v_mbaa_s1_valid : 1; /* */ unsigned cia$v_mbaa_pattern : 10; /* */ unsigned cia$v_mbaa_reserved_3 : 2; /* */ unsigned cia$v_mbaa_timing : 2; /* */ unsigned cia$v_mbaa_reserved_5 : 2; /* */ } cia$r_mem_mbaa_bits; } cia$r_mem_mbaa_overlay; unsigned char cia$b_fill290 [124]; /* */ /* Memory Base Address C Register - 0x8750000900 */ /* */ __union { int cia$l_mem_mbac; __struct { unsigned cia$v_mbac_s0_valid : 1; /* */ unsigned cia$v_mbac_row_type : 2; /* */ unsigned cia$v_mbac_reserved : 1; /* */ unsigned cia$v_mbac_mask : 5; /* */ unsigned cia$v_mbac_reserved_2 : 6; /* */ unsigned cia$v_mbac_s1_valid : 1; /* */ unsigned cia$v_mbac_pattern : 10; /* */ unsigned cia$v_mbac_reserved_3 : 2; /* */ unsigned cia$v_mbac_timing : 2; /* */ unsigned cia$v_mbac_reserved_5 : 2; /* */ } cia$r_mem_mbac_bits; } cia$r_mem_mbac_overlay; unsigned char cia$b_fill300 [124]; /* */ /* Memory Base Address E Register - 0x8750000980 */ /* */ __union { int cia$l_mem_mbae; __struct { unsigned cia$v_mbae_s0_valid : 1; /* */ unsigned cia$v_mbae_row_type : 2; /* */ unsigned cia$v_mbae_reserved : 1; /* */ unsigned cia$v_mbae_mask : 5; /* */ unsigned cia$v_mbae_reserved_2 : 6; /* */ unsigned cia$v_mbae_s1_valid : 1; /* */ unsigned cia$v_mbae_pattern : 10; /* */ unsigned cia$v_mbae_reserved_3 : 2; /* */ unsigned cia$v_mbae_timing : 2; /* */ unsigned cia$v_mbae_reserved_5 : 2; /* */ } cia$r_mem_mbae_bits; } cia$r_mem_mbae_overlay; unsigned char cia$b_fill310 [380]; /* */ /* Memory Timing Register 0 - 0x8750000B00 */ /* */ __union { int cia$l_mem_tmg0; __struct { unsigned cia$v_tmg0_r1 : 2; /* */ unsigned cia$v_tmg0_r2 : 2; /* */ unsigned cia$v_tmg0_r3 : 2; /* */ unsigned cia$v_tmg0_r4 : 2; /* */ unsigned cia$v_tmg0_r5 : 2; /* */ unsigned cia$v_tmg0_r6 : 2; /* */ unsigned cia$v_tmg0_w1 : 3; /* */ unsigned cia$v_tmg0_w4 : 3; /* */ unsigned cia$v_tmg0_pre : 1; /* */ unsigned cia$v_tmg0_v3 : 2; /* */ unsigned cia$v_tmg0_v4 : 2; /* */ unsigned cia$v_tmg0_reserved : 1; /* */ unsigned cia$v_tmg0_v5 : 2; /* */ unsigned cia$v_tmg0_v6 : 2; /* */ unsigned cia$v_tmg0_rv : 2; /* */ unsigned cia$v_tmg0_rd_dly : 2; /* */ } cia$r_mem_tmg0_bits; } cia$r_mem_tmg0_overlay; unsigned char cia$b_fill320 [60]; /* */ /* Memory Timing Register 1 - 0x8750000B40 */ /* */ __union { int cia$l_mem_tmg1; __struct { unsigned cia$v_tmg1_r1 : 2; /* */ unsigned cia$v_tmg1_r2 : 2; /* */ unsigned cia$v_tmg1_r3 : 2; /* */ unsigned cia$v_tmg1_r4 : 2; /* */ unsigned cia$v_tmg1_r5 : 2; /* */ unsigned cia$v_tmg1_r6 : 2; /* */ unsigned cia$v_tmg1_w1 : 3; /* */ unsigned cia$v_tmg1_w4 : 3; /* */ unsigned cia$v_tmg1_pre : 1; /* */ unsigned cia$v_tmg1_v3 : 2; /* */ unsigned cia$v_tmg1_v4 : 2; /* */ unsigned cia$v_tmg1_reserved : 1; /* */ unsigned cia$v_tmg1_v5 : 2; /* */ unsigned cia$v_tmg1_v6 : 2; /* */ unsigned cia$v_tmg1_rv : 2; /* */ unsigned cia$v_tmg1_rd_dly : 2; /* */ } cia$r_mem_tmg1_bits; } cia$r_mem_tmg1_overlay; unsigned char cia$b_fill330 [60]; /* */ /* Memory Timing Register 2 - 0x8750000B80 */ /* */ __union { int cia$l_mem_tmg2; __struct { unsigned cia$v_tmg2_r1 : 2; /* */ unsigned cia$v_tmg2_r2 : 2; /* */ unsigned cia$v_tmg2_r3 : 2; /* */ unsigned cia$v_tmg2_r4 : 2; /* */ unsigned cia$v_tmg2_r5 : 2; /* */ unsigned cia$v_tmg2_r6 : 2; /* */ unsigned cia$v_tmg2_w1 : 3; /* */ unsigned cia$v_tmg2_w4 : 3; /* */ unsigned cia$v_tmg2_pre : 1; /* */ unsigned cia$v_tmg2_v3 : 2; /* */ unsigned cia$v_tmg2_v4 : 2; /* */ unsigned cia$v_tmg2_reserved : 1; /* */ unsigned cia$v_tmg2_v5 : 2; /* */ unsigned cia$v_tmg2_v6 : 2; /* */ unsigned cia$v_tmg2_rv : 2; /* */ unsigned cia$v_tmg2_rd_dly : 2; /* */ } cia$r_mem_tmg2_bits; } cia$r_mem_tmg2_overlay; unsigned char cia$b_fill340 [5244]; /* */ /* PCI Scatter/Gather TBIA - 0x8760000100 */ /* */ unsigned char cia$b_fill345 [256]; __union { int cia$l_pci_tbia; __struct { unsigned cia$v_tbia_csr_wr_data : 2; /* */ unsigned cia$v_tbia_reserved : 30; /* */ } cia$r_pci_tbia_bits; } cia$r_pci_tbia_overlay; unsigned char cia$b_fill350 [764]; /* */ /* PCI Window Base 0 - 0x8760000400 */ /* */ __union { int cia$l_pci_wbase0; __struct { unsigned cia$v_wbase0_w_en : 1; /* */ unsigned cia$v_wbase0_sg_en : 1; /* enable scatter/gather */ unsigned cia$v_wbase0_memcs_en : 1; /* enable MEMCS */ unsigned cia$v_wbase0_dac_en : 1; /* enable 64BIT PCI */ unsigned cia$v_wbase0_reserved : 16; /* */ unsigned cia$v_wbase0_base : 12; } cia$r_pci_wbase0_bits; } cia$r_pci_wbase0_overlay; unsigned char cia$b_fill360 [60]; /* */ /* PCI Window Mask 0 - 0x8760000440 */ /* */ __union { int cia$l_pci_wmask0; __struct { unsigned cia$v_wmask0_reserved : 20; /* */ unsigned cia$v_wmask0_mask : 12; } cia$r_pci_wmask0_bits; } cia$r_pci_wmask0_overlay; unsigned char cia$b_fill370 [60]; /* */ /* PCI Window Translated Base 0 - 0x8760000480 */ /* */ __union { int cia$l_pci_tbase0; __struct { unsigned cia$v_tbase0_reserved : 8; /* */ unsigned cia$v_tbase0_base : 24; } cia$r_pci_tbase0_bits; } cia$r_pci_tbase0_overlay; unsigned char cia$b_fill380 [124]; /****** */ /* */ /* PCI Window Base 1 - 0x8760000500 */ /* */ __union { int cia$l_pci_wbase1; __struct { unsigned cia$v_wbase1_w_en : 1; /* */ unsigned cia$v_wbase1_sg_en : 1; /* enable scatter/gather */ unsigned cia$v_wbase1_memcs_en : 1; /* enable MEMCS */ unsigned cia$v_wbase1_dac_en : 1; /* enable 64BIT PCI */ unsigned cia$v_wbase1_reserved : 16; /* */ unsigned cia$v_wbase1_base : 12; } cia$r_pci_wbase1_bits; } cia$r_pci_wbase1_overlay; unsigned char cia$b_fill390 [60]; /* */ /* PCI Window Mask 1 - 0x8760000540 */ /* */ __union { int cia$l_pci_wmask1; __struct { unsigned cia$v_wmask1_reserved : 20; /* */ unsigned cia$v_wmask1_mask : 12; } cia$r_pci_wmask1_bits; } cia$r_pci_wmask1_overlay; unsigned char cia$b_fill400 [60]; /* */ /* PCI Window Translated Base 1 - 0x8760000580 */ /* */ __union { int cia$l_pci_tbase1; __struct { unsigned cia$v_tbase1_reserved : 8; /* */ unsigned cia$v_tbase1_base : 24; } cia$r_pci_tbase1_bits; } cia$r_pci_tbase1_overlay; unsigned char cia$b_fill410 [124]; /* */ /* PCI Window Base 2 - 0x8760000600 */ /* */ __union { int cia$l_pci_wbase2; __struct { unsigned cia$v_wbase2_w_en : 1; /* */ unsigned cia$v_wbase2_sg_en : 1; /* enable scatter/gather */ unsigned cia$v_wbase2_memcs_en : 1; /* enable MEMCS */ unsigned cia$v_wbase2_dac_en : 1; /* enable 64BIT PCI */ unsigned cia$v_wbase2_reserved : 16; /* */ unsigned cia$v_wbase2_base : 12; } cia$r_pci_wbase2_bits; } cia$r_pci_wbase2_overlay; unsigned char cia$b_fill420 [60]; /* */ /* PCI Window Mask 2 - 0x8760000640 */ /* */ __union { int cia$l_pci_wmask2; __struct { unsigned cia$v_wmask2_reserved : 20; /* */ unsigned cia$v_wmask2_mask : 12; } cia$r_pci_wmask2_bits; } cia$r_pci_wmask2_overlay; unsigned char cia$b_fill430 [60]; /* */ /* PCI Window Translated Base 2 - 0x8760000680 */ /* */ __union { int cia$l_pci_tbase2; __struct { unsigned cia$v_tbase2_reserved : 8; /* */ unsigned cia$v_tbase2_base : 24; } cia$r_pci_tbase2_bits; } cia$r_pci_tbase2_overlay; unsigned char cia$b_fill440 [124]; /* */ /* PCI Window Base 3 - 0x8760000700 */ /* */ __union { int cia$l_pci_wbase3; __struct { unsigned cia$v_wbase3_w_en : 1; /* */ unsigned cia$v_wbase3_sg_en : 1; /* enable scatter/gather */ unsigned cia$v_wbase3_memcs_en : 1; /* enable MEMCS */ unsigned cia$v_wbase3_dac_en : 1; /* enable 64BIT PCI */ unsigned cia$v_wbase3_reserved : 16; /* */ unsigned cia$v_wbase3_base : 12; } cia$r_pci_wbase3_bits; } cia$r_pci_wbase3_overlay; unsigned char cia$b_fill450 [60]; /* */ /* PCI Window Mask 3 - 0x8760000740 */ /* */ __union { int cia$l_pci_wmask3; __struct { unsigned cia$v_wmask3_reserved : 20; /* */ unsigned cia$v_wmask3_mask : 12; } cia$r_pci_wmask3_bits; } cia$r_pci_wmask3_overlay; unsigned char cia$b_fill460 [60]; /* */ /* PCI Window Translated Base 3 - 0x8760000780 */ /* */ __union { int cia$l_pci_tbase3; __struct { unsigned cia$v_tbase3_reserved : 8; /* */ unsigned cia$v_tbase3_base : 24; } cia$r_pci_tbase3_bits; } cia$r_pci_tbase3_overlay; unsigned char cia$b_fill470 [60]; /* */ /* PCI DAC Base Register - 0x87600007C0 */ /* */ __union { int cia$l_pci_dac; __struct { unsigned cia$v_dac_base : 8; unsigned cia$v_dac_reserved : 24; /* */ } cia$r_pci_dac_bits; } cia$r_pci_dac_overlay; unsigned char cia$b_fill480 [60]; /* */ /* PCI Lockable TB Tag 0- 0x8760000800 */ /* */ __union { int cia$l_pci_ltb0; __struct { unsigned cia$v_ltb0_valid : 1; /* */ unsigned cia$v_ltb0_locked : 1; /* enable scatter/gather */ unsigned cia$v_ltb0_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_ltb0_reserved : 12; /* */ unsigned cia$v_ltb0_tag : 17; } cia$r_pci_ltb0_bits; } cia$r_pci_ltb0_overlay; unsigned char cia$b_fill490 [60]; /* */ /* PCI Lockable TB Tag 1- 0x8760000840 */ /* */ __union { int cia$l_pci_ltb1; __struct { unsigned cia$v_ltb1_valid : 1; /* */ unsigned cia$v_ltb1_locked : 1; /* enable scatter/gather */ unsigned cia$v_ltb1_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_ltb1_reserved : 12; /* */ unsigned cia$v_ltb1_tag : 17; } cia$r_pci_ltb1_bits; } cia$r_pci_ltb1_overlay; unsigned char cia$b_fill500 [60]; /* */ /* PCI Lockable TB Tag 2- 0x8760000880 */ /* */ __union { int cia$l_pci_ltb2; __struct { unsigned cia$v_ltb2_valid : 1; /* */ unsigned cia$v_ltb2_locked : 1; /* enable scatter/gather */ unsigned cia$v_ltb2_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_ltb2_reserved : 12; /* */ unsigned cia$v_ltb2_tag : 17; } cia$r_pci_ltb2_bits; } cia$r_pci_ltb2_overlay; unsigned char cia$b_fill510 [60]; /* */ /* PCI Lockable TB Tag 3- 0x87600008C0 */ /* */ __union { int cia$l_pci_ltb3; __struct { unsigned cia$v_ltb3_valid : 1; /* */ unsigned cia$v_ltb3_locked : 1; /* enable scatter/gather */ unsigned cia$v_ltb3_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_ltb3_reserved : 12; /* */ unsigned cia$v_ltb3_tag : 17; } cia$r_pci_ltb3_bits; } cia$r_pci_ltb3_overlay; unsigned char cia$b_fill520 [60]; /* */ /* PCI TB Tag 0- 0x8760000900 */ /* */ __union { int cia$l_pci_tb0; __struct { unsigned cia$v_tb0_valid : 1; /* */ unsigned cia$v_reserved : 1; /* */ unsigned cia$v_tb0_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_tb0_reserved2 : 12; /* */ unsigned cia$v_tb0_tag : 17; } cia$r_pci_tb0_bits; } cia$r_pci_tb0_overlay; unsigned char cia$b_fill530 [60]; /* */ /* PCI TB Tag 1 - 0x8760000940 */ /* */ __union { int cia$l_pci_tb1; __struct { unsigned cia$v_tb1_valid : 1; /* */ unsigned cia$v_tb1_reserved : 1; /* */ unsigned cia$v_tb1_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_tb1_reserved2 : 12; /* */ unsigned cia$v_tb1_tag : 17; } cia$r_pci_tb1_bits; } cia$r_pci_tb1_overlay; unsigned char cia$b_fill540 [60]; /* */ /* PCI TB Tag 2 - 0x8760000980 */ /* */ __union { int cia$l_pci_tb2; __struct { unsigned cia$v_tb2_valid : 1; /* */ unsigned cia$v_tb2_reserved : 1; /* */ unsigned cia$v_tb2_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_tb2_reserved2 : 12; /* */ unsigned cia$v_tb2_tag : 17; } cia$r_pci_tb2_bits; } cia$r_pci_tb2_overlay; unsigned char cia$b_fill550 [60]; /* */ /* PCI TB Tag 3- 0x87600009C0 */ /* */ __union { int cia$l_pci_tb3; __struct { unsigned cia$v_tb3_valid : 1; /* */ unsigned cia$v_tb3_reserved : 1; /* */ unsigned cia$v_tb3_dac : 1; /* enable 64BIT PCI */ unsigned cia$v_tb3_reserved2 : 12; /* */ unsigned cia$v_tb3_tag : 17; } cia$r_pci_tb3_bits; } cia$r_pci_tb3_overlay; unsigned char cia$b_fill560 [1596]; /* */ /* PCI TB0 Page 0- 0x8760001000 */ /* */ __union { int cia$l_pci_tb0_page0; __struct { unsigned cia$v_tb0_page0_valid : 1; /* */ unsigned cia$v_tb0_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb0_page0_bits; } cia$r_pci_tb0_page0_overlay; unsigned char cia$b_fill570 [60]; /* */ /* PCI TB0 Page 1 - 0x8760001040 */ /* */ __union { int cia$l_pci_tb0_page1; __struct { unsigned cia$v_tb0_page1_valid : 1; /* */ unsigned cia$v_tb0_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb0_page1_bits; } cia$r_pci_tb0_page1_overlay; unsigned char cia$b_fill580 [60]; /* */ /* PCI TB0 Page 2 - 0x8760001080 */ /* */ __union { int cia$l_pci_tb0_page2; __struct { unsigned cia$v_tb0_page2_valid : 1; /* */ unsigned cia$v_tb0_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb0_page2_bits; } cia$r_pci_tb0_page2_overlay; unsigned char cia$b_fill590 [60]; /* */ /* PCI TB0 Page 3- 0x87600010C0 */ /* */ __union { int cia$l_pci_tb0_page3; __struct { unsigned cia$v_tb0_page3_valid : 1; /* */ unsigned cia$v_tb0_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb0_page3_bits; } cia$r_pci_tb0_page3_overlay; unsigned char cia$b_fill600 [60]; /* */ /* PCI TB1 Page 0- 0x8760001100 */ /* */ __union { int cia$l_pci_tb1_page0; __struct { unsigned cia$v_tb1_page0_valid : 1; /* */ unsigned cia$v_tb1_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb1_page0_bits; } cia$r_pci_tb1_page0_overlay; unsigned char cia$b_fill610 [60]; /* */ /* PCI TB1 Page 1 - 0x8760001140 */ /* */ __union { int cia$l_pci_tb1_page1; __struct { unsigned cia$v_tb1_page1_valid : 1; /* */ unsigned cia$v_tb1_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb1_page1_bits; } cia$r_pci_tb1_page1_overlay; unsigned char cia$b_fill620 [60]; /* */ /* PCI TB1 Page 2 - 0x8760001180 */ /* */ __union { int cia$l_pci_tb1_page2; __struct { unsigned cia$v_tb1_page2_valid : 1; /* */ unsigned cia$v_tb1_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb1_page2_bits; } cia$r_pci_tb1_page2_overlay; unsigned char cia$b_fill630 [60]; /* */ /* PCI TB1 Page 3- 0x87600011C0 */ /* */ __union { int cia$l_pci_tb1_page3; __struct { unsigned cia$v_tb1_page3_valid : 1; /* */ unsigned cia$v_tb1_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb1_page3_bits; } cia$r_pci_tb1_page3_overlay; unsigned char cia$b_fill640 [60]; /* */ /* PCI TB2 Page 0- 0x8760001200 */ /* */ __union { int cia$l_pci_tb2_page0; __struct { unsigned cia$v_tb2_page0_valid : 1; /* */ unsigned cia$v_tb2_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb2_page0_bits; } cia$r_pci_tb2_page0_overlay; unsigned char cia$b_fill650 [60]; /* */ /* PCI TB2 Page 1 - 0x8760001240 */ /* */ __union { int cia$l_pci_tb2_page1; __struct { unsigned cia$v_tb2_page1_valid : 1; /* */ unsigned cia$v_tb2_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb2_page1_bits; } cia$r_pci_tb2_page1_overlay; unsigned char cia$b_fill660 [60]; /* */ /* PCI TB2 Page 2 - 0x8760001280 */ /* */ __union { int cia$l_pci_tb2_page2; __struct { unsigned cia$v_tb2_page2_valid : 1; /* */ unsigned cia$v_tb2_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb2_page2_bits; } cia$r_pci_tb2_page2_overlay; unsigned char cia$b_fill670 [60]; /* */ /* PCI TB2 Page 3- 0x87600012C0 */ /* */ __union { int cia$l_pci_tb2_page3; __struct { unsigned cia$v_tb2_page3_valid : 1; /* */ unsigned cia$v_tb2_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb2_page3_bits; } cia$r_pci_tb2_page3_overlay; unsigned char cia$b_fill680 [60]; /* */ /* PCI TB3 Page 0- 0x8760001300 */ /* */ __union { int cia$l_pci_tb3_page0; __struct { unsigned cia$v_tb3_page0_valid : 1; /* */ unsigned cia$v_tb3_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb3_page0_bits; } cia$r_pci_tb3_page0_overlay; unsigned char cia$b_fill690 [60]; /* */ /* PCI TB3 Page 1 - 0x8760001340 */ /* */ __union { int cia$l_pci_tb3_page1; __struct { unsigned cia$v_tb3_page1_valid : 1; /* */ unsigned cia$v_tb3_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb3_page1_bits; } cia$r_pci_tb3_page1_overlay; unsigned char cia$b_fill700 [60]; /* */ /* PCI TB3 Page 2 - 0x8760001380 */ /* */ __union { int cia$l_pci_tb3_page2; __struct { unsigned cia$v_tb3_page2_valid : 1; /* */ unsigned cia$v_tb3_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb3_page2_bits; } cia$r_pci_tb3_page2_overlay; unsigned char cia$b_fill710 [60]; /* */ /* PCI TB3 Page 3- 0x87600013C0 */ /* */ __union { int cia$l_pci_tb3_page3; __struct { unsigned cia$v_tb3_page3_valid : 1; /* */ unsigned cia$v_tb3_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb3_page3_bits; } cia$r_pci_tb3_page3_overlay; unsigned char cia$b_fill720 [60]; /* */ /* PCI TB4 Page 0- 0x8760001400 */ /* */ __union { int cia$l_pci_tb4_page0; __struct { unsigned cia$v_tb4_page0_valid : 1; /* */ unsigned cia$v_tb4_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb4_page0_bits; } cia$r_pci_tb4_page0_overlay; unsigned char cia$b_fill730 [60]; /* */ /* PCI TB4 Page 1 - 0x8760001440 */ /* */ __union { int cia$l_pci_tb4_page1; __struct { unsigned cia$v_tb4_page1_valid : 1; /* */ unsigned cia$v_tb4_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb4_page1_bits; } cia$r_pci_tb4_page1_overlay; unsigned char cia$b_fill740 [60]; /* */ /* PCI TB4 Page 2 - 0x8760001480 */ /* */ __union { int cia$l_pci_tb4_page2; __struct { unsigned cia$v_tb4_page2_valid : 1; /* */ unsigned cia$v_tb4_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb4_page2_bits; } cia$r_pci_tb4_page2_overlay; unsigned char cia$b_fill750 [60]; /* */ /* PCI TB4 Page 3- 0x87600014C0 */ /* */ __union { int cia$l_pci_tb4_page3; __struct { unsigned cia$v_tb4_page3_valid : 1; /* */ unsigned cia$v_tb4_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb4_page3_bits; } cia$r_pci_tb4_page3_overlay; unsigned char cia$b_fill760 [60]; /* */ /* PCI TB5 Page 0- 0x8760001500 */ /* */ __union { int cia$l_pci_tb5_page0; __struct { unsigned cia$v_tb5_page0_valid : 1; /* */ unsigned cia$v_tb5_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb5_page0_bits; } cia$r_pci_tb5_page0_overlay; unsigned char cia$b_fill770 [60]; /* */ /* PCI TB5 Page 1 - 0x8760001540 */ /* */ __union { int cia$l_pci_tb5_page1; __struct { unsigned cia$v_tb5_page1_valid : 1; /* */ unsigned cia$v_tb5_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb5_page1_bits; } cia$r_pci_tb5_page1_overlay; unsigned char cia$b_fill780 [60]; /* */ /* PCI TB5 Page 2 - 0x8760001580 */ /* */ __union { int cia$l_pci_tb5_page2; __struct { unsigned cia$v_tb5_page2_valid : 1; /* */ unsigned cia$v_tb5_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb5_page2_bits; } cia$r_pci_tb5_page2_overlay; unsigned char cia$b_fill790 [60]; /* */ /* PCI TB5 Page 3- 0x87600015C0 */ /* */ __union { int cia$l_pci_tb5_page3; __struct { unsigned cia$v_tb5_page3_valid : 1; /* */ unsigned cia$v_tb5_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb5_page3_bits; } cia$r_pci_tb5_page3_overlay; unsigned char cia$b_fill800 [60]; /* */ /* PCI TB6 Page 0- 0x8760001600 */ /* */ __union { int cia$l_pci_tb6_page0; __struct { unsigned cia$v_tb6_page0_valid : 1; /* */ unsigned cia$v_tb6_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb6_page0_bits; } cia$r_pci_tb6_page0_overlay; unsigned char cia$b_fill810 [60]; /* */ /* PCI TB6 Page 1 - 0x8760001640 */ /* */ __union { int cia$l_pci_tb6_page1; __struct { unsigned cia$v_tb6_page1_valid : 1; /* */ unsigned cia$v_tb6_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb6_page1_bits; } cia$r_pci_tb6_page1_overlay; unsigned char cia$b_fill820 [60]; /* */ /* PCI TB6 Page 2 - 0x8760001680 */ /* */ __union { int cia$l_pci_tb6_page2; __struct { unsigned cia$v_tb6_page2_valid : 1; /* */ unsigned cia$v_tb6_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb6_page2_bits; } cia$r_pci_tb6_page2_overlay; unsigned char cia$b_fill830 [60]; /* */ /* PCI TB6 Page 3- 0x87600016C0 */ /* */ __union { int cia$l_pci_tb6_page3; __struct { unsigned cia$v_tb6_page3_valid : 1; /* */ unsigned cia$v_tb6_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb6_page3_bits; } cia$r_pci_tb6_page3_overlay; unsigned char cia$b_fill840 [60]; /* */ /* PCI TB7 Page 0- 0x8760001700 */ /* */ __union { int cia$l_pci_tb7_page0; __struct { unsigned cia$v_tb7_page0_valid : 1; /* */ unsigned cia$v_tb7_page0_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb7_page0_bits; } cia$r_pci_tb7_page0_overlay; unsigned char cia$b_fill850 [60]; /* */ /* PCI TB7 Page 1 - 0x8760001740 */ /* */ __union { int cia$l_pci_tb7_page1; __struct { unsigned cia$v_tb7_page1_valid : 1; /* */ unsigned cia$v_tb7_page1_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb7_page1_bits; } cia$r_pci_tb7_page1_overlay; unsigned char cia$b_fill860 [60]; /* */ /* PCI TB7 Page 2 - 0x8760001780 */ /* */ __union { int cia$l_pci_tb7_page2; __struct { unsigned cia$v_tb7_page2_valid : 1; /* */ unsigned cia$v_tb7_page2_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb7_page2_bits; } cia$r_pci_tb7_page2_overlay; unsigned char cia$b_fill870 [60]; /* */ /* PCI TB7 Page 3- 0x87600017C0 */ /* */ __union { int cia$l_pci_tb7_page3; __struct { unsigned cia$v_tb7_page3_valid : 1; /* */ unsigned cia$v_tb7_page3_addr : 21; unsigned cia$v_fill : 10; /* */ } cia$r_pci_tb7_page3_bits; } cia$r_pci_tb7_page3_overlay; unsigned char cia$b_fill880 [2108]; } CIA; #if !defined(__VAXC) #define cia$l_pci_cia_rev cia$r_pci_cia_revision.cia$l_pci_cia_rev #define cia$b_cia_rev cia$r_pci_cia_revision.cia$r_rev_bits.cia$b_cia_rev #define cia$l_pci_lat cia$r_pci_latency.cia$l_pci_lat #define cia$b_pci_latency cia$r_pci_latency.cia$r_latency_bits.cia$b_pci_latency #define cia$l_cia_ctl cia$r_cia_control.cia$l_cia_ctl #define cia$v_cia_ctrl_pci_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_pci_en #define cia$v_cia_ctrl_pci_lock_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_pci_lock_en #define cia$v_cia_ctrl_pci_loop_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_pci_loop_en #define cia$v_cia_ctrl_fst_bb_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_fst_bb_en #define cia$v_cia_ctrl_mst_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_mst_en #define cia$v_cia_ctrl_mem_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_mem_en #define cia$v_cia_ctrl_req64_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_req64_en #define cia$v_cia_ctrl_ack64_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_ack64_en #define cia$v_cia_ctrl_addr_pe_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_addr_pe_en #define cia$v_cia_ctrl_perr_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_perr_en #define cia$v_cia_ctrl_fill_err_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_fill_err_en #define cia$v_cia_ctrl_ecc_chk_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_ecc_chk_en #define cia$v_cia_ctrl_cack_en_pe cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_cack_en_pe #define cia$v_cia_ctrl_con_idle_bc cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_con_idle_bc #define cia$v_cia_ctrl_csr_ioa_byp cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_csr_ioa_byp #define cia$v_cia_ctrl_io_flush_req cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_io_flush_req #define cia$v_cia_ctrl_cpu_flush_req cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_cpu_flush_req #define cia$v_cia_ctrl_arb_ev5_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_arb_ev5_en #define cia$v_cia_ctrl_en_arb_link cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_en_arb_link #define cia$v_cia_ctrl_rd_typ cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_rd_typ #define cia$v_cia_ctrl_rl_typ cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_rl_typ #define cia$v_cia_ctrl_rm_typ cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_rm_typ #define cia$l_cia_config cia$r_cia_config_overlay.cia$l_cia_config #define cia$v_cia_cnfg_pci_width cia$r_cia_config_overlay.cia$r_cia_config_bits.cia$v_cia_cnfg_pci_width #define cia$v_cia_cnfg_iod_width cia$r_cia_config_overlay.cia$r_cia_config_bits.cia$v_cia_cnfg_iod_width #define cia$l_hae_mem cia$r_hae_mem_overlay.cia$l_hae_mem #define cia$v_hae_mem_reg_3 cia$r_hae_mem_overlay.cia$r_hae_mem_bits.cia$v_hae_mem_reg_3 #define cia$v_hae_mem_reg_2 cia$r_hae_mem_overlay.cia$r_hae_mem_bits.cia$v_hae_mem_reg_2 #define cia$v_hae_mem_reg_1 cia$r_hae_mem_overlay.cia$r_hae_mem_bits.cia$v_hae_mem_reg_1 #define cia$l_hae_io cia$r_hae_io_overlay.cia$l_hae_io #define cia$v_hae_io cia$r_hae_io_overlay.cia$r_hae_io_bits.cia$v_hae_io #define cia$l_cfg cia$r_cfg_overlay.cia$l_cfg #define cia$v_cfg_bits cia$r_cfg_overlay.cia$r_cgf_bits_overlay.cia$v_cfg_bits #define cia$l_cack_en cia$r_cack_en_overlay.cia$l_cack_en #define cia$v_cack_en_bits cia$r_cack_en_overlay.cia$r_cack_en_bits.cia$v_cack_en_bits #define cia$l_cia_diag cia$r_cia_diag_overlay.cia$l_cia_diag #define cia$v_from_en cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_from_en #define cia$v_use_check cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_use_check #define cia$v_fpe_pci cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_fpe_pci #define cia$v_fpe_to_ev5 cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_fpe_to_ev5 #define cia$l_diag_check cia$r_diag_check_overlay.cia$l_diag_check #define cia$b_diag_check_ecc cia$r_diag_check_overlay.cia$r_diag_check_bits.cia$b_diag_check_ecc #define cia$l_perf_monitor cia$r_perf_monitor_overlay.cia$l_perf_monitor #define cia$l_perf_control cia$r_perf_control_overlay.cia$l_perf_control #define cia$l_cpu_err0 cia$r_cpu_err0_overlay.cia$l_cpu_err0 #define cia$v_cpu_err0_addr cia$r_cpu_err0_overlay.cia$r_cpu_err0_bits.cia$v_cpu_err0_addr #define cia$l_cpu_err1 cia$r_cpu_err1_overlay.cia$l_cpu_err1 #define cia$v_cpu_err1_3432 cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_3432 #define cia$v_cpu_err1_39 cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_39 #define cia$v_cpu_err1_cmd cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_cmd #define cia$v_cpu_err1_int4_valid cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_int4_valid #define cia$v_cpu_err1_ac_par cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_ac_par #define cia$v_cpu_err1_fpe cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_fpe #define cia$v_cpu_err1_pe cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_pe #define cia$l_cia_err cia$r_cia_err_overlay.cia$l_cia_err #define cia$v_err_corr_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_corr_ecc #define cia$v_err_unc_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_unc_ecc #define cia$v_err_cpu_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_cpu_pe #define cia$v_err_mem_nem cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_mem_nem #define cia$v_err_pci_serr cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pci_serr #define cia$v_err_pci_perr cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pci_perr #define cia$v_err_pci_adr_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pci_adr_pe #define cia$v_err_m_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_m_abort #define cia$v_err_t_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_t_abort #define cia$v_err_pa_pte_inv cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pa_pte_inv #define cia$v_err_from_wrt_err cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_from_wrt_err #define cia$v_err_ioa_timeout cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_ioa_timeout #define cia$v_err_lost_corr_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_corr_ecc #define cia$v_err_lost_unc_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_unc_ecc #define cia$v_err_lost_cpu_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_cpu_pe #define cia$v_err_lost_mem_nem cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_mem_nem #define cia$v_err_lost_pci_serr cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_pci_serr #define cia$v_err_lost_pci_perr cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_pci_perr #define cia$v_err_lost_pci_adr_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_pci_adr_pe #define cia$v_err_lost_m_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_m_abort #define cia$v_err_lost_t_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_t_abort #define cia$v_err_lost_pa_pte_inv cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_pa_pte_inv #define cia$v_err_lost_from_wrt_err cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_from_wrt_err #define cia$v_err_lost_ioa_timeout cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_ioa_timeout #define cia$v_err_valid cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_valid #define cia$l_cia_stat cia$r_cia_stat_overlay.cia$l_cia_stat #define cia$v_stat_pci_status cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_pci_status #define cia$v_stat_mem_source cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_mem_source #define cia$v_stat_io_queue cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_io_queue #define cia$v_stat_cpu_queue cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_cpu_queue #define cia$v_stat_tlb_miss cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_tlb_miss #define cia$v_stat_dm_stat cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_dm_stat #define cia$v_stat_pa_cpu_res cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_pa_cpu_res #define cia$l_cia_error_mask cia$r_cia_error_mask_overlay.cia$l_cia_error_mask #define cia$v_mask_corr_ecc_err cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_corr_ecc_err #define cia$v_mask_unc_ecc_err cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_unc_ecc_err #define cia$v_mask_cpu_pe cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_cpu_pe #define cia$v_mask_mem_nem cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_mem_nem #define cia$v_mask_pci_serr cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pci_serr #define cia$v_mask_pci_perr cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pci_perr #define cia$v_mask_pci_adr_pe cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pci_adr_pe #define cia$v_mask_m_abort cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_m_abort #define cia$v_mask_t_abort cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_t_abort #define cia$v_mask_pa_pte_inv cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pa_pte_inv #define cia$v_mask_from_wrt_err cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_from_wrt_err #define cia$v_mask_ioa_timeout cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_ioa_timeout #define cia$l_cia_synd cia$r_cia_syndrome.cia$l_cia_synd #define cia$r_cia_synd_bits cia$r_cia_syndrome.cia$r_cia_synd_bits #define cia$v_cia_syndrome cia$r_cia_synd_bits.cia$v_cia_syndrome #define cia$l_cia_mpsr0 cia$r_cia_mpsr0_overlay.cia$l_cia_mpsr0 #define cia$v_mpsr0_addr_h cia$r_cia_mpsr0_overlay.cia$r_cia_mpsr0_bits.cia$v_mpsr0_addr_h #define cia$l_cia_mpsr1 cia$r_cia_mpsr1_overlay.cia$l_cia_mpsr1 #define cia$v_mpsr1_addr_h cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_addr_h #define cia$v_mpsr1_addr_39 cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_addr_39 #define cia$v_mpsr1_cmd_h cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_cmd_h #define cia$v_mpsr1_port_mask cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_port_mask #define cia$v_mpsr1_seq_st cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_seq_st #define cia$v_mpsr1_port_src cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_port_src #define cia$v_mpsr1_set_sel cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_set_sel #define cia$l_cia_pcie0 cia$r_cia_pcie0_overlay.cia$l_cia_pcie0 #define cia$v_pcie_cmd cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_cmd #define cia$v_pcie_lock_state cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_lock_state #define cia$v_pcie_dac_cycle cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_dac_cycle #define cia$v_pcie_window cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_window #define cia$v_pcie_mstr_state cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_mstr_state #define cia$v_pcie_trgt_state cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_trgt_state #define cia$l_pcie1_mem_addr_h cia$r_cia_pcie1_overlay.cia$l_pcie1_mem_addr_h #define cia$l_mem_mcr cia$r_mem_mcr_overlay.cia$l_mem_mcr #define cia$v_mcr_mem_size cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_mem_size #define cia$v_mcr_cache_size cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_cache_size #define cia$v_mcr_ref_rate cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_ref_rate #define cia$v_mcr_ref_burst cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_ref_burst #define cia$v_mcr_tmg_r0 cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_tmg_r0 #define cia$v_mcr_long_cbr_cas cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_long_cbr_cas #define cia$v_mcr_dly_idle_bc cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_dly_idle_bc #define cia$v_mcr_early_idle_bc cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_early_idle_bc #define cia$l_mem_mba0 cia$r_mem_mba0_overlay.cia$l_mem_mba0 #define cia$v_mba0_s0_valid cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_s0_valid #define cia$v_mba0_row_type cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_row_type #define cia$v_mba0_mask cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_mask #define cia$v_mba0_s1_valid cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_s1_valid #define cia$v_mba0_pattern cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_pattern #define cia$v_mba0_timing cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_timing #define cia$l_mem_mba2 cia$r_mem_mba2_overlay.cia$l_mem_mba2 #define cia$v_mba2_s0_valid cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_s0_valid #define cia$v_mba2_row_type cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_row_type #define cia$v_mba2_mask cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_mask #define cia$v_mba2_s1_valid cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_s1_valid #define cia$v_mba2_pattern cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_pattern #define cia$v_mba2_timing cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_timing #define cia$l_mem_mba4 cia$r_mem_mba4_overlay.cia$l_mem_mba4 #define cia$v_mba4_s0_valid cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_s0_valid #define cia$v_mba4_row_type cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_row_type #define cia$v_mba4_mask cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_mask #define cia$v_mba4_s1_valid cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_s1_valid #define cia$v_mba4_pattern cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_pattern #define cia$v_mba4_timing cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_timing #define cia$l_mem_mba6 cia$r_mem_mba6_overlay.cia$l_mem_mba6 #define cia$v_mba6_s0_valid cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_s0_valid #define cia$v_mba6_row_type cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_row_type #define cia$v_mba6_mask cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_mask #define cia$v_mba6_s1_valid cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_s1_valid #define cia$v_mba6_pattern cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_pattern #define cia$v_mba6_timing cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_timing #define cia$l_mem_mba8 cia$r_mem_mba8_overlay.cia$l_mem_mba8 #define cia$v_mba8_s0_valid cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_s0_valid #define cia$v_mba8_row_type cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_row_type #define cia$v_mba8_mask cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_mask #define cia$v_mba8_s1_valid cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_s1_valid #define cia$v_mba8_pattern cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_pattern #define cia$v_mba8_timing cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_timing #define cia$l_mem_mbaa cia$r_mem_mbaa_overlay.cia$l_mem_mbaa #define cia$v_mbaa_s0_valid cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_s0_valid #define cia$v_mbaa_row_type cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_row_type #define cia$v_mbaa_mask cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_mask #define cia$v_mbaa_s1_valid cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_s1_valid #define cia$v_mbaa_pattern cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_pattern #define cia$v_mbaa_timing cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_timing #define cia$l_mem_mbac cia$r_mem_mbac_overlay.cia$l_mem_mbac #define cia$v_mbac_s0_valid cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_s0_valid #define cia$v_mbac_row_type cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_row_type #define cia$v_mbac_mask cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_mask #define cia$v_mbac_s1_valid cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_s1_valid #define cia$v_mbac_pattern cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_pattern #define cia$v_mbac_timing cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_timing #define cia$l_mem_mbae cia$r_mem_mbae_overlay.cia$l_mem_mbae #define cia$v_mbae_s0_valid cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_s0_valid #define cia$v_mbae_row_type cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_row_type #define cia$v_mbae_mask cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_mask #define cia$v_mbae_s1_valid cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_s1_valid #define cia$v_mbae_pattern cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_pattern #define cia$v_mbae_reserved_3 cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_reserved_3 #define cia$v_mbae_timing cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_timing #define cia$l_mem_tmg0 cia$r_mem_tmg0_overlay.cia$l_mem_tmg0 #define cia$v_tmg0_r1 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r1 #define cia$v_tmg0_r2 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r2 #define cia$v_tmg0_r3 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r3 #define cia$v_tmg0_r4 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r4 #define cia$v_tmg0_r5 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r5 #define cia$v_tmg0_r6 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r6 #define cia$v_tmg0_w1 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_w1 #define cia$v_tmg0_w4 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_w4 #define cia$v_tmg0_pre cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_pre #define cia$v_tmg0_v3 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v3 #define cia$v_tmg0_v4 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v4 #define cia$v_tmg0_v5 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v5 #define cia$v_tmg0_v6 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v6 #define cia$v_tmg0_rv cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_rv #define cia$v_tmg0_rd_dly cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_rd_dly #define cia$l_mem_tmg1 cia$r_mem_tmg1_overlay.cia$l_mem_tmg1 #define cia$v_tmg1_r1 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r1 #define cia$v_tmg1_r2 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r2 #define cia$v_tmg1_r3 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r3 #define cia$v_tmg1_r4 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r4 #define cia$v_tmg1_r5 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r5 #define cia$v_tmg1_r6 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r6 #define cia$v_tmg1_w1 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_w1 #define cia$v_tmg1_w4 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_w4 #define cia$v_tmg1_pre cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_pre #define cia$v_tmg1_v3 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v3 #define cia$v_tmg1_v4 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v4 #define cia$v_tmg1_v5 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v5 #define cia$v_tmg1_v6 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v6 #define cia$v_tmg1_rv cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_rv #define cia$v_tmg1_rd_dly cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_rd_dly #define cia$l_mem_tmg2 cia$r_mem_tmg2_overlay.cia$l_mem_tmg2 #define cia$v_tmg2_r1 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r1 #define cia$v_tmg2_r2 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r2 #define cia$v_tmg2_r3 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r3 #define cia$v_tmg2_r4 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r4 #define cia$v_tmg2_r5 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r5 #define cia$v_tmg2_r6 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r6 #define cia$v_tmg2_w1 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_w1 #define cia$v_tmg2_w4 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_w4 #define cia$v_tmg2_pre cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_pre #define cia$v_tmg2_v3 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v3 #define cia$v_tmg2_v4 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v4 #define cia$v_tmg2_v5 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v5 #define cia$v_tmg2_v6 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v6 #define cia$v_tmg2_rv cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_rv #define cia$v_tmg2_rd_dly cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_rd_dly #define cia$l_pci_tbia cia$r_pci_tbia_overlay.cia$l_pci_tbia #define cia$v_tbia_csr_wr_data cia$r_pci_tbia_overlay.cia$r_pci_tbia_bits.cia$v_tbia_csr_wr_data #define cia$l_pci_wbase0 cia$r_pci_wbase0_overlay.cia$l_pci_wbase0 #define cia$v_wbase0_w_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_w_en #define cia$v_wbase0_sg_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_sg_en #define cia$v_wbase0_memcs_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_memcs_en #define cia$v_wbase0_dac_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_dac_en #define cia$v_wbase0_base cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_base #define cia$l_pci_wmask0 cia$r_pci_wmask0_overlay.cia$l_pci_wmask0 #define cia$v_wmask0_mask cia$r_pci_wmask0_overlay.cia$r_pci_wmask0_bits.cia$v_wmask0_mask #define cia$l_pci_tbase0 cia$r_pci_tbase0_overlay.cia$l_pci_tbase0 #define cia$v_tbase0_base cia$r_pci_tbase0_overlay.cia$r_pci_tbase0_bits.cia$v_tbase0_base #define cia$l_pci_wbase1 cia$r_pci_wbase1_overlay.cia$l_pci_wbase1 #define cia$v_wbase1_w_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_w_en #define cia$v_wbase1_sg_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_sg_en #define cia$v_wbase1_memcs_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_memcs_en #define cia$v_wbase1_dac_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_dac_en #define cia$v_wbase1_base cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_base #define cia$l_pci_wmask1 cia$r_pci_wmask1_overlay.cia$l_pci_wmask1 #define cia$v_wmask1_mask cia$r_pci_wmask1_overlay.cia$r_pci_wmask1_bits.cia$v_wmask1_mask #define cia$l_pci_tbase1 cia$r_pci_tbase1_overlay.cia$l_pci_tbase1 #define cia$v_tbase1_base cia$r_pci_tbase1_overlay.cia$r_pci_tbase1_bits.cia$v_tbase1_base #define cia$l_pci_wbase2 cia$r_pci_wbase2_overlay.cia$l_pci_wbase2 #define cia$v_wbase2_w_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_w_en #define cia$v_wbase2_sg_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_sg_en #define cia$v_wbase2_memcs_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_memcs_en #define cia$v_wbase2_dac_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_dac_en #define cia$v_wbase2_base cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_base #define cia$l_pci_wmask2 cia$r_pci_wmask2_overlay.cia$l_pci_wmask2 #define cia$v_wmask2_mask cia$r_pci_wmask2_overlay.cia$r_pci_wmask2_bits.cia$v_wmask2_mask #define cia$l_pci_tbase2 cia$r_pci_tbase2_overlay.cia$l_pci_tbase2 #define cia$v_tbase2_base cia$r_pci_tbase2_overlay.cia$r_pci_tbase2_bits.cia$v_tbase2_base #define cia$l_pci_wbase3 cia$r_pci_wbase3_overlay.cia$l_pci_wbase3 #define cia$v_wbase3_w_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_w_en #define cia$v_wbase3_sg_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_sg_en #define cia$v_wbase3_memcs_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_memcs_en #define cia$v_wbase3_dac_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_dac_en #define cia$v_wbase3_base cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_base #define cia$l_pci_wmask3 cia$r_pci_wmask3_overlay.cia$l_pci_wmask3 #define cia$v_wmask3_mask cia$r_pci_wmask3_overlay.cia$r_pci_wmask3_bits.cia$v_wmask3_mask #define cia$l_pci_tbase3 cia$r_pci_tbase3_overlay.cia$l_pci_tbase3 #define cia$v_tbase3_base cia$r_pci_tbase3_overlay.cia$r_pci_tbase3_bits.cia$v_tbase3_base #define cia$l_pci_dac cia$r_pci_dac_overlay.cia$l_pci_dac #define cia$v_dac_base cia$r_pci_dac_overlay.cia$r_pci_dac_bits.cia$v_dac_base #define cia$l_pci_ltb0 cia$r_pci_ltb0_overlay.cia$l_pci_ltb0 #define cia$v_ltb0_valid cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_valid #define cia$v_ltb0_locked cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_locked #define cia$v_ltb0_dac cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_dac #define cia$v_ltb0_tag cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_tag #define cia$l_pci_ltb1 cia$r_pci_ltb1_overlay.cia$l_pci_ltb1 #define cia$v_ltb1_valid cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_valid #define cia$v_ltb1_locked cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_locked #define cia$v_ltb1_dac cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_dac #define cia$v_ltb1_tag cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_tag #define cia$l_pci_ltb2 cia$r_pci_ltb2_overlay.cia$l_pci_ltb2 #define cia$v_ltb2_valid cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_valid #define cia$v_ltb2_locked cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_locked #define cia$v_ltb2_dac cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_dac #define cia$v_ltb2_tag cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_tag #define cia$l_pci_ltb3 cia$r_pci_ltb3_overlay.cia$l_pci_ltb3 #define cia$v_ltb3_valid cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_valid #define cia$v_ltb3_locked cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_locked #define cia$v_ltb3_dac cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_dac #define cia$v_ltb3_tag cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_tag #define cia$l_pci_tb0 cia$r_pci_tb0_overlay.cia$l_pci_tb0 #define cia$v_tb0_valid cia$r_pci_tb0_overlay.cia$r_pci_tb0_bits.cia$v_tb0_valid #define cia$v_tb0_dac cia$r_pci_tb0_overlay.cia$r_pci_tb0_bits.cia$v_tb0_dac #define cia$v_tb0_tag cia$r_pci_tb0_overlay.cia$r_pci_tb0_bits.cia$v_tb0_tag #define cia$l_pci_tb1 cia$r_pci_tb1_overlay.cia$l_pci_tb1 #define cia$v_tb1_valid cia$r_pci_tb1_overlay.cia$r_pci_tb1_bits.cia$v_tb1_valid #define cia$v_tb1_dac cia$r_pci_tb1_overlay.cia$r_pci_tb1_bits.cia$v_tb1_dac #define cia$v_tb1_tag cia$r_pci_tb1_overlay.cia$r_pci_tb1_bits.cia$v_tb1_tag #define cia$l_pci_tb2 cia$r_pci_tb2_overlay.cia$l_pci_tb2 #define cia$v_tb2_valid cia$r_pci_tb2_overlay.cia$r_pci_tb2_bits.cia$v_tb2_valid #define cia$v_tb2_dac cia$r_pci_tb2_overlay.cia$r_pci_tb2_bits.cia$v_tb2_dac #define cia$v_tb2_tag cia$r_pci_tb2_overlay.cia$r_pci_tb2_bits.cia$v_tb2_tag #define cia$l_pci_tb3 cia$r_pci_tb3_overlay.cia$l_pci_tb3 #define cia$v_tb3_valid cia$r_pci_tb3_overlay.cia$r_pci_tb3_bits.cia$v_tb3_valid #define cia$v_tb3_dac cia$r_pci_tb3_overlay.cia$r_pci_tb3_bits.cia$v_tb3_dac #define cia$v_tb3_tag cia$r_pci_tb3_overlay.cia$r_pci_tb3_bits.cia$v_tb3_tag #define cia$l_pci_tb0_page0 cia$r_pci_tb0_page0_overlay.cia$l_pci_tb0_page0 #define cia$v_tb0_page0_valid cia$r_pci_tb0_page0_overlay.cia$r_pci_tb0_page0_bits.cia$v_tb0_page0_valid #define cia$v_tb0_page0_addr cia$r_pci_tb0_page0_overlay.cia$r_pci_tb0_page0_bits.cia$v_tb0_page0_addr #define cia$l_pci_tb0_page1 cia$r_pci_tb0_page1_overlay.cia$l_pci_tb0_page1 #define cia$v_tb0_page1_valid cia$r_pci_tb0_page1_overlay.cia$r_pci_tb0_page1_bits.cia$v_tb0_page1_valid #define cia$v_tb0_page1_addr cia$r_pci_tb0_page1_overlay.cia$r_pci_tb0_page1_bits.cia$v_tb0_page1_addr #define cia$l_pci_tb0_page2 cia$r_pci_tb0_page2_overlay.cia$l_pci_tb0_page2 #define cia$v_tb0_page2_valid cia$r_pci_tb0_page2_overlay.cia$r_pci_tb0_page2_bits.cia$v_tb0_page2_valid #define cia$v_tb0_page2_addr cia$r_pci_tb0_page2_overlay.cia$r_pci_tb0_page2_bits.cia$v_tb0_page2_addr #define cia$l_pci_tb0_page3 cia$r_pci_tb0_page3_overlay.cia$l_pci_tb0_page3 #define cia$v_tb0_page3_valid cia$r_pci_tb0_page3_overlay.cia$r_pci_tb0_page3_bits.cia$v_tb0_page3_valid #define cia$v_tb0_page3_addr cia$r_pci_tb0_page3_overlay.cia$r_pci_tb0_page3_bits.cia$v_tb0_page3_addr #define cia$l_pci_tb1_page0 cia$r_pci_tb1_page0_overlay.cia$l_pci_tb1_page0 #define cia$v_tb1_page0_valid cia$r_pci_tb1_page0_overlay.cia$r_pci_tb1_page0_bits.cia$v_tb1_page0_valid #define cia$v_tb1_page0_addr cia$r_pci_tb1_page0_overlay.cia$r_pci_tb1_page0_bits.cia$v_tb1_page0_addr #define cia$l_pci_tb1_page1 cia$r_pci_tb1_page1_overlay.cia$l_pci_tb1_page1 #define cia$v_tb1_page1_valid cia$r_pci_tb1_page1_overlay.cia$r_pci_tb1_page1_bits.cia$v_tb1_page1_valid #define cia$v_tb1_page1_addr cia$r_pci_tb1_page1_overlay.cia$r_pci_tb1_page1_bits.cia$v_tb1_page1_addr #define cia$l_pci_tb1_page2 cia$r_pci_tb1_page2_overlay.cia$l_pci_tb1_page2 #define cia$v_tb1_page2_valid cia$r_pci_tb1_page2_overlay.cia$r_pci_tb1_page2_bits.cia$v_tb1_page2_valid #define cia$v_tb1_page2_addr cia$r_pci_tb1_page2_overlay.cia$r_pci_tb1_page2_bits.cia$v_tb1_page2_addr #define cia$l_pci_tb1_page3 cia$r_pci_tb1_page3_overlay.cia$l_pci_tb1_page3 #define cia$v_tb1_page3_valid cia$r_pci_tb1_page3_overlay.cia$r_pci_tb1_page3_bits.cia$v_tb1_page3_valid #define cia$v_tb1_page3_addr cia$r_pci_tb1_page3_overlay.cia$r_pci_tb1_page3_bits.cia$v_tb1_page3_addr #define cia$l_pci_tb2_page0 cia$r_pci_tb2_page0_overlay.cia$l_pci_tb2_page0 #define cia$v_tb2_page0_valid cia$r_pci_tb2_page0_overlay.cia$r_pci_tb2_page0_bits.cia$v_tb2_page0_valid #define cia$v_tb2_page0_addr cia$r_pci_tb2_page0_overlay.cia$r_pci_tb2_page0_bits.cia$v_tb2_page0_addr #define cia$l_pci_tb2_page1 cia$r_pci_tb2_page1_overlay.cia$l_pci_tb2_page1 #define cia$v_tb2_page1_valid cia$r_pci_tb2_page1_overlay.cia$r_pci_tb2_page1_bits.cia$v_tb2_page1_valid #define cia$v_tb2_page1_addr cia$r_pci_tb2_page1_overlay.cia$r_pci_tb2_page1_bits.cia$v_tb2_page1_addr #define cia$l_pci_tb2_page2 cia$r_pci_tb2_page2_overlay.cia$l_pci_tb2_page2 #define cia$v_tb2_page2_valid cia$r_pci_tb2_page2_overlay.cia$r_pci_tb2_page2_bits.cia$v_tb2_page2_valid #define cia$v_tb2_page2_addr cia$r_pci_tb2_page2_overlay.cia$r_pci_tb2_page2_bits.cia$v_tb2_page2_addr #define cia$l_pci_tb2_page3 cia$r_pci_tb2_page3_overlay.cia$l_pci_tb2_page3 #define cia$v_tb2_page3_valid cia$r_pci_tb2_page3_overlay.cia$r_pci_tb2_page3_bits.cia$v_tb2_page3_valid #define cia$v_tb2_page3_addr cia$r_pci_tb2_page3_overlay.cia$r_pci_tb2_page3_bits.cia$v_tb2_page3_addr #define cia$l_pci_tb3_page0 cia$r_pci_tb3_page0_overlay.cia$l_pci_tb3_page0 #define cia$v_tb3_page0_valid cia$r_pci_tb3_page0_overlay.cia$r_pci_tb3_page0_bits.cia$v_tb3_page0_valid #define cia$v_tb3_page0_addr cia$r_pci_tb3_page0_overlay.cia$r_pci_tb3_page0_bits.cia$v_tb3_page0_addr #define cia$l_pci_tb3_page1 cia$r_pci_tb3_page1_overlay.cia$l_pci_tb3_page1 #define cia$v_tb3_page1_valid cia$r_pci_tb3_page1_overlay.cia$r_pci_tb3_page1_bits.cia$v_tb3_page1_valid #define cia$v_tb3_page1_addr cia$r_pci_tb3_page1_overlay.cia$r_pci_tb3_page1_bits.cia$v_tb3_page1_addr #define cia$l_pci_tb3_page2 cia$r_pci_tb3_page2_overlay.cia$l_pci_tb3_page2 #define cia$v_tb3_page2_valid cia$r_pci_tb3_page2_overlay.cia$r_pci_tb3_page2_bits.cia$v_tb3_page2_valid #define cia$v_tb3_page2_addr cia$r_pci_tb3_page2_overlay.cia$r_pci_tb3_page2_bits.cia$v_tb3_page2_addr #define cia$l_pci_tb3_page3 cia$r_pci_tb3_page3_overlay.cia$l_pci_tb3_page3 #define cia$v_tb3_page3_valid cia$r_pci_tb3_page3_overlay.cia$r_pci_tb3_page3_bits.cia$v_tb3_page3_valid #define cia$v_tb3_page3_addr cia$r_pci_tb3_page3_overlay.cia$r_pci_tb3_page3_bits.cia$v_tb3_page3_addr #define cia$l_pci_tb4_page0 cia$r_pci_tb4_page0_overlay.cia$l_pci_tb4_page0 #define cia$v_tb4_page0_valid cia$r_pci_tb4_page0_overlay.cia$r_pci_tb4_page0_bits.cia$v_tb4_page0_valid #define cia$v_tb4_page0_addr cia$r_pci_tb4_page0_overlay.cia$r_pci_tb4_page0_bits.cia$v_tb4_page0_addr #define cia$l_pci_tb4_page1 cia$r_pci_tb4_page1_overlay.cia$l_pci_tb4_page1 #define cia$v_tb4_page1_valid cia$r_pci_tb4_page1_overlay.cia$r_pci_tb4_page1_bits.cia$v_tb4_page1_valid #define cia$v_tb4_page1_addr cia$r_pci_tb4_page1_overlay.cia$r_pci_tb4_page1_bits.cia$v_tb4_page1_addr #define cia$l_pci_tb4_page2 cia$r_pci_tb4_page2_overlay.cia$l_pci_tb4_page2 #define cia$v_tb4_page2_valid cia$r_pci_tb4_page2_overlay.cia$r_pci_tb4_page2_bits.cia$v_tb4_page2_valid #define cia$v_tb4_page2_addr cia$r_pci_tb4_page2_overlay.cia$r_pci_tb4_page2_bits.cia$v_tb4_page2_addr #define cia$l_pci_tb4_page3 cia$r_pci_tb4_page3_overlay.cia$l_pci_tb4_page3 #define cia$v_tb4_page3_valid cia$r_pci_tb4_page3_overlay.cia$r_pci_tb4_page3_bits.cia$v_tb4_page3_valid #define cia$v_tb4_page3_addr cia$r_pci_tb4_page3_overlay.cia$r_pci_tb4_page3_bits.cia$v_tb4_page3_addr #define cia$l_pci_tb5_page0 cia$r_pci_tb5_page0_overlay.cia$l_pci_tb5_page0 #define cia$v_tb5_page0_valid cia$r_pci_tb5_page0_overlay.cia$r_pci_tb5_page0_bits.cia$v_tb5_page0_valid #define cia$v_tb5_page0_addr cia$r_pci_tb5_page0_overlay.cia$r_pci_tb5_page0_bits.cia$v_tb5_page0_addr #define cia$l_pci_tb5_page1 cia$r_pci_tb5_page1_overlay.cia$l_pci_tb5_page1 #define cia$v_tb5_page1_valid cia$r_pci_tb5_page1_overlay.cia$r_pci_tb5_page1_bits.cia$v_tb5_page1_valid #define cia$v_tb5_page1_addr cia$r_pci_tb5_page1_overlay.cia$r_pci_tb5_page1_bits.cia$v_tb5_page1_addr #define cia$l_pci_tb5_page2 cia$r_pci_tb5_page2_overlay.cia$l_pci_tb5_page2 #define cia$v_tb5_page2_valid cia$r_pci_tb5_page2_overlay.cia$r_pci_tb5_page2_bits.cia$v_tb5_page2_valid #define cia$v_tb5_page2_addr cia$r_pci_tb5_page2_overlay.cia$r_pci_tb5_page2_bits.cia$v_tb5_page2_addr #define cia$l_pci_tb5_page3 cia$r_pci_tb5_page3_overlay.cia$l_pci_tb5_page3 #define cia$v_tb5_page3_valid cia$r_pci_tb5_page3_overlay.cia$r_pci_tb5_page3_bits.cia$v_tb5_page3_valid #define cia$v_tb5_page3_addr cia$r_pci_tb5_page3_overlay.cia$r_pci_tb5_page3_bits.cia$v_tb5_page3_addr #define cia$l_pci_tb6_page0 cia$r_pci_tb6_page0_overlay.cia$l_pci_tb6_page0 #define cia$v_tb6_page0_valid cia$r_pci_tb6_page0_overlay.cia$r_pci_tb6_page0_bits.cia$v_tb6_page0_valid #define cia$v_tb6_page0_addr cia$r_pci_tb6_page0_overlay.cia$r_pci_tb6_page0_bits.cia$v_tb6_page0_addr #define cia$l_pci_tb6_page1 cia$r_pci_tb6_page1_overlay.cia$l_pci_tb6_page1 #define cia$v_tb6_page1_valid cia$r_pci_tb6_page1_overlay.cia$r_pci_tb6_page1_bits.cia$v_tb6_page1_valid #define cia$v_tb6_page1_addr cia$r_pci_tb6_page1_overlay.cia$r_pci_tb6_page1_bits.cia$v_tb6_page1_addr #define cia$l_pci_tb6_page2 cia$r_pci_tb6_page2_overlay.cia$l_pci_tb6_page2 #define cia$v_tb6_page2_valid cia$r_pci_tb6_page2_overlay.cia$r_pci_tb6_page2_bits.cia$v_tb6_page2_valid #define cia$v_tb6_page2_addr cia$r_pci_tb6_page2_overlay.cia$r_pci_tb6_page2_bits.cia$v_tb6_page2_addr #define cia$l_pci_tb6_page3 cia$r_pci_tb6_page3_overlay.cia$l_pci_tb6_page3 #define cia$v_tb6_page3_valid cia$r_pci_tb6_page3_overlay.cia$r_pci_tb6_page3_bits.cia$v_tb6_page3_valid #define cia$v_tb6_page3_addr cia$r_pci_tb6_page3_overlay.cia$r_pci_tb6_page3_bits.cia$v_tb6_page3_addr #define cia$l_pci_tb7_page0 cia$r_pci_tb7_page0_overlay.cia$l_pci_tb7_page0 #define cia$v_tb7_page0_valid cia$r_pci_tb7_page0_overlay.cia$r_pci_tb7_page0_bits.cia$v_tb7_page0_valid #define cia$v_tb7_page0_addr cia$r_pci_tb7_page0_overlay.cia$r_pci_tb7_page0_bits.cia$v_tb7_page0_addr #define cia$l_pci_tb7_page1 cia$r_pci_tb7_page1_overlay.cia$l_pci_tb7_page1 #define cia$v_tb7_page1_valid cia$r_pci_tb7_page1_overlay.cia$r_pci_tb7_page1_bits.cia$v_tb7_page1_valid #define cia$v_tb7_page1_addr cia$r_pci_tb7_page1_overlay.cia$r_pci_tb7_page1_bits.cia$v_tb7_page1_addr #define cia$l_pci_tb7_page2 cia$r_pci_tb7_page2_overlay.cia$l_pci_tb7_page2 #define cia$v_tb7_page2_valid cia$r_pci_tb7_page2_overlay.cia$r_pci_tb7_page2_bits.cia$v_tb7_page2_valid #define cia$v_tb7_page2_addr cia$r_pci_tb7_page2_overlay.cia$r_pci_tb7_page2_bits.cia$v_tb7_page2_addr #define cia$l_pci_tb7_page3 cia$r_pci_tb7_page3_overlay.cia$l_pci_tb7_page3 #define cia$v_tb7_page3_valid cia$r_pci_tb7_page3_overlay.cia$r_pci_tb7_page3_bits.cia$v_tb7_page3_valid #define cia$v_tb7_page3_addr cia$r_pci_tb7_page3_overlay.cia$r_pci_tb7_page3_bits.cia$v_tb7_page3_addr #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __CIA_DEF_LOADED */