/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:37:40 by OpenVMS SDL EV3-3 */ /* Source: 14-DEC-2006 17:37:48 $1$DGA7274:[LIB_H.SRC]BUSARRAYDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $BUSARRAYDEF ***/ #ifndef __BUSARRAYDEF_LOADED #define __BUSARRAYDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #include #include /*+ */ /* Bus Array -- each node on a bus has an entry in the Bus Array for that bus. */ /* */ /* A Bus Array is pointed to by a field in the ADP. A Bus Array consists */ /* of a header and a number of entries (one for each node on the bus or one */ /* for each channel on an adapter). */ /* Each entry contains info on the node, such as hardware id, base CSR */ /* address, a pointer to a data structure, and node number. */ /* */ /*- */ /* Define Bus Array Entry */ /* ================================================================ */ /* BUSARRAYENTRY */ /* ================================================================ */ /* Characterizes hardware connected to the bus adapter represented */ /* by the ADP. The Bus Array is comprised of a number of these */ /* BUSARRAYENTRYs, one for each node on the bus. */ /* */ #define BUSARRAY$M_NO_RECONNECT 0x1 #define BUSARRAY$M_MSI 0x2 #define BUSARRAY$M_INVALID_BAE 0x4 #define BUSARRAY$M_SPAREBIT03 0x8 #define BUSARRAY$M_MULTI 0x10 #define BUSARRAY$M_CHANNEL 0x20 #define BUSARRAY$M_PCI_BRIDGE 0x40 #define BUSARRAY$M_NO_DRIVER 0x80 #define BUSARRAY$M_INT_ENABLED 0x100 #ifdef __cplusplus /* Define structure prototypes */ struct _crb; struct _adp; struct _bax; #endif /* #ifdef __cplusplus */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _busarrayentry { __union { #pragma __nomember_alignment unsigned __int64 busarray$q_hw_id; /* Hardware ID. */ __struct { unsigned short int busarray$w_pci_vend_id; /* Vendor ID */ unsigned short int busarray$w_pci_dev_id; /* Device ID */ unsigned short int busarray$w_pci_subvend_id; /* Subsytem Vendor ID */ unsigned short int busarray$w_pci_subsys_id; /* Subsystem (Device) ID */ } busarray$r_pci_hw_word_fields; __struct { unsigned int busarray$l_pci_dev_vend_id; /* Device & Vendor ID */ unsigned int busarray$l_pci_subsys_vend_id; /* Subsystem Vendor & subsys ID */ } busarray$r_pci_hw_lword_fields; } busarray$r_hw_id_overlay; unsigned __int64 busarray$q_csr; /* Base CSR address */ __union { /* Node or channel number */ __int64 busarray$q_node_number; __struct { __union { int busarray$l_node_number_l; int busarray$l_node_number; } busarray$r_nn_low_long_overlay; int busarray$l_node_number_h; } busarray$r_nn_long_struct; } busarray$r_nn_overlay; __union { unsigned int busarray$l_flags; /* Flags */ __struct { unsigned busarray$v_no_reconnect : 1; unsigned busarray$v_msi : 1; /* PCI 2.2 & PCIX message signaled interrupts. */ unsigned busarray$v_invalid_bae : 1; /* Invalid BAE - ignore. */ unsigned busarray$v_sparebit03 : 1; /* A named bit for future needs. */ unsigned busarray$v_multi : 1; /* multi-function or multi-channel device */ unsigned busarray$v_channel : 1; /* This BUSARRAYENTRY is a channel */ unsigned busarray$v_pci_bridge : 1; /* PCI-PCI Bridge device */ unsigned busarray$v_no_driver : 1; /* No entry in SYS$CONFIG.DAT */ unsigned busarray$v_int_enabled : 1; unsigned busarray$v_fill_0_ : 7; } busarray$r_flag_bits; } busarray$r_flags_overlay; struct _crb *busarray$ps_crb; /* Pointer to Channel Request Block */ struct _adp *busarray$ps_adp; /* Pointer to subordinate ADP */ __union { unsigned int busarray$l_autoconfig; /* Reserved for Autoconfigure */ void *busarray$ps_autoconfig; /* Reserved for Autoconfigure */ } busarray$r_autoconfig_overlay; __union { unsigned int busarray$l_ctrlltr; unsigned char busarray$b_ctrlltr; } busarray$r_ctrlltr_overlay; /* Make sure the following quadword stays aligned properly */ char busarray$b_fill_1_ [4]; #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif __union { #pragma __nomember_alignment unsigned __int64 busarray$q_bus_specific; __struct { __union { unsigned int busarray$l_bus_specific_l; void *busarray$ps_bus_specific_l; unsigned int busarray$l_int_vec; /* Offset into SCB or vector table */ unsigned int busarray$l_sys_irq; /* System IRQ (4*SYS_IRQ = vector table offset) */ unsigned int busarray$l_scb_offset; /* Offset into the SCB */ } busarray$r_bus_specific_l_overlay; __union { unsigned int busarray$l_bus_specific_h; void *busarray$ps_bus_specific_h; unsigned int busarray$l_bus_specific_1; void *busarray$ps_bus_specific_1; } busarray$r_bus_specific_h_overlay; } busarray$r_bus_specific_fields; } busarray$r_bus_specific_overlay; __union { /* Quadword aligns the structure */ unsigned int busarray$l_bus_specific_2; void *busarray$ps_bus_specific_2; struct _bax *busarray$ps_bax; } busarray$r_bus_specific_2_overlay; char busarray$b_fill_2_ [4]; #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif __union { #pragma __nomember_alignment CBB busarray$r_cbb_cpu_affinity; /* Embedded CBB block */ __struct { /* Compatability offset cells */ __int64 busarray$q_cbb_fill_1 [6]; __union { unsigned int busarray$l_cpu_affinity; /* Identifies CPU the device is interrupting on */ unsigned __int64 busarray$q_cpu_affinity; /* Identifies CPU the device is interrupting on */ } busarray$r_cbb_cpu_affinity_data_o; } busarray$r_cbb_cpu_affinity_compat; } busarray$r_cbb_cpu_affinity_overla; } BUSARRAYENTRY; #if !defined(__VAXC) #define busarray$q_hw_id busarray$r_hw_id_overlay.busarray$q_hw_id #define busarray$w_pci_vend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_vend_id #define busarray$w_pci_dev_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_dev_id #define busarray$w_pci_subvend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_subvend_id #define busarray$w_pci_subsys_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_subsys_id #define busarray$l_pci_dev_vend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_lword_fields.busarray$l_pci_dev_vend_id #define busarray$l_pci_subsys_vend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_lword_fields.busarray$l_pci_subsys_vend_id #define busarray$q_node_number busarray$r_nn_overlay.busarray$q_node_number #define busarray$l_node_number_l busarray$r_nn_overlay.busarray$r_nn_long_struct.busarray$r_nn_low_long_overlay.busarray$l_node_num\ ber_l #define busarray$l_node_number busarray$r_nn_overlay.busarray$r_nn_long_struct.busarray$r_nn_low_long_overlay.busarray$l_node_number #define busarray$l_node_number_h busarray$r_nn_overlay.busarray$r_nn_long_struct.busarray$l_node_number_h #define busarray$l_flags busarray$r_flags_overlay.busarray$l_flags #define busarray$v_no_reconnect busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_no_reconnect #define busarray$v_msi busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_msi #define busarray$v_invalid_bae busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_invalid_bae #define busarray$v_sparebit03 busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_sparebit03 #define busarray$v_multi busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_multi #define busarray$v_channel busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_channel #define busarray$v_pci_bridge busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_pci_bridge #define busarray$v_no_driver busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_no_driver #define busarray$v_int_enabled busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_int_enabled #define busarray$l_autoconfig busarray$r_autoconfig_overlay.busarray$l_autoconfig #define busarray$ps_autoconfig busarray$r_autoconfig_overlay.busarray$ps_autoconfig #define busarray$l_ctrlltr busarray$r_ctrlltr_overlay.busarray$l_ctrlltr #define busarray$b_ctrlltr busarray$r_ctrlltr_overlay.busarray$b_ctrlltr #define busarray$q_bus_specific busarray$r_bus_specific_overlay.busarray$q_bus_specific #define busarray$l_bus_specific_l busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.\ busarray$l_bus_specific_l #define busarray$ps_bus_specific_l busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay\ .busarray$ps_bus_specific_l #define busarray$l_int_vec busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.busarra\ y$l_int_vec #define busarray$l_sys_irq busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.busarra\ y$l_sys_irq #define busarray$l_scb_offset busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.busa\ rray$l_scb_offset #define busarray$l_bus_specific_h busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay.\ busarray$l_bus_specific_h #define busarray$ps_bus_specific_h busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay\ .busarray$ps_bus_specific_h #define busarray$l_bus_specific_1 busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay.\ busarray$l_bus_specific_1 #define busarray$ps_bus_specific_1 busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay\ .busarray$ps_bus_specific_1 #define busarray$l_bus_specific_2 busarray$r_bus_specific_2_overlay.busarray$l_bus_specific_2 #define busarray$ps_bus_specific_2 busarray$r_bus_specific_2_overlay.busarray$ps_bus_specific_2 #define busarray$ps_bax busarray$r_bus_specific_2_overlay.busarray$ps_bax #define busarray$r_cbb_cpu_affinity busarray$r_cbb_cpu_affinity_overla.busarray$r_cbb_cpu_affinity #define busarray$l_cpu_affinity busarray$r_cbb_cpu_affinity_overla.busarray$r_cbb_cpu_affinity_compat.busarray$r_cbb_cpu_affinity_d\ ata_o.busarray$l_cpu_affinity #define busarray$q_cpu_affinity busarray$r_cbb_cpu_affinity_overla.busarray$r_cbb_cpu_affinity_compat.busarray$r_cbb_cpu_affinity_d\ ata_o.busarray$q_cpu_affinity #endif /* #if !defined(__VAXC) */ #define BUSARRAYENTRY$K_LENGTH 120 /* ================================================================ */ /* BUSARRAY_HEADER */ /* ================================================================ */ /* Descriptor for the Bus Array hanging off the ADP. */ /* */ #define BUSARRAYHEADER$K_LENGTH 24 /* Keep length before ENTRY_LIST, which has no real */ /* length */ #define BUSARRAY$S_BUSARRAYHEADER 24 /* Old size name */ #ifdef __cplusplus /* Define structure prototypes */ struct _adp; #endif /* #ifdef __cplusplus */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _busarray_header { #pragma __nomember_alignment struct _adp *busarray$ps_parent_adp; /* Point back to ADP */ unsigned int busarray$l_fill1; /* */ unsigned short int busarray$w_size; /* Structure size in bytes */ unsigned char busarray$b_type; /* Structure type */ unsigned char busarray$b_subtype; /* Structure subtype */ unsigned int busarray$l_bus_type; /* Bus Type code */ unsigned int busarray$l_bus_node_cnt; /* Number of entries in Bus Array */ unsigned int busarray$l_fill2; /* Fill to quadword boundary */ __union { __int64 busarray$q_entry_list [1]; /* Bus Array entries start */ /* at entry_list */ BUSARRAYENTRY busarray$r_bus_array_entry; /* First bus array in the list */ } busarray$r_bae_overlay; } BUSARRAY_HEADER; #if !defined(__VAXC) #define busarray$q_entry_list busarray$r_bae_overlay.busarray$q_entry_list #define busarray$r_bus_array_entry busarray$r_bae_overlay.busarray$r_bus_array_entry #endif /* #if !defined(__VAXC) */ /* ================================================================ */ /* BAX - BUSARRAYENTRY EXTENSION */ /* ================================================================ */ /* This structure is the BusArray eXtension and provides more */ /* detail for the characterization of the hardware represented */ /* by the BUSARRAYENTRY. */ /* */ #define BAX$K_LENGTH 112 #ifdef __cplusplus /* Define structure prototypes */ struct _adp; struct _vec_list; struct _mvi_data; #endif /* #ifdef __cplusplus */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _bax { /* */ /* */ /* The following field points back to the ADP on which this BAX */ /* resides. */ /* */ #pragma __nomember_alignment struct _adp *bax$ps_parent_adp; /* Mother ADP */ /* */ /* */ /* This field points back to the BUSARRAYENTRY that "owns" this BAX */ /* instance. */ /* */ struct _busarrayentry *bax$ps_parent_bae; /* */ /* */ /*-------------------------------------------------------------- */ /* General Data */ /*-------------------------------------------------------------- */ /* */ unsigned int bax$l_channel; /* Channel number */ struct _vec_list *bax$ps_vec_list; /* Interrupt Vectors List see IOCDEF */ unsigned int bax$l_int_mech; /* Interrupt delivery mechanism */ /* */ /* */ /*-------------------------------------------------------------- */ /* Descriptor for Bus-specific data buffer. */ /*-------------------------------------------------------------- */ /* For PCI busses, this is a snapshot of the Config Header. */ /* */ char bax$b_fill_3_ [4]; #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif __struct { #pragma __nomember_alignment __union { __int64 bax$q_bus_data_area [4]; __struct { unsigned int bax$l_bus_data_size; unsigned int bax$l_bus_data_type; void *bax$ps_bus_data; } bax$r_bus_data_descriptor; } bax$r_bus_data_overlay; } bax$r_bus_data; /* */ /* */ /*-------------------------------------------------------------- */ /* Interrupt Routine Pointers */ /*-------------------------------------------------------------- */ /* Since PCI-X, it has been possible for devices on the same bus */ /* to use different interrupt technologies. These fields provide */ /* long (64-bit) and short (32-bit) pointers to the device-specific */ /* Interrupt Init, Enable, Disable, and Redirection routines. These */ /* fields are initialized with the appropriate routine pointer when */ /* the interrupt technology is determined (IOSAPIC, MSI, MSI-X...), */ /* during device configuration. The IRQ init and node_function */ /* routines will call through these pointers to the correct routine */ /* for the device. */ /* */ void *bax$ps_msiabs; int (*bax$ps_init_interrupt)(); int (*bax$ps_enable_interrupt)(); int (*bax$ps_disable_interrupt)(); int (*bax$ps_redirect_interrupt)(); /* */ /* */ /*-------------------------------------------------------------- */ /* Multiple Vector Interrupt Routines and Data */ /*-------------------------------------------------------------- */ struct _mvi_data *bax$ps_mvi_data; int (*bax$ps_mvi_request_vectors)(); int (*bax$ps_mvi_map_vector)(); int (*bax$ps_mvi_dispatch_vte)(); /* MSIX only */ int (*bax$ps_mvi_dispatch_unique)(); int (*bax$ps_mvi_dispatch_vector)(); int (*bax$ps_mvi_mask_vector)(); int (*bax$ps_mvi_unmask_vector)(); int (*bax$ps_mvi_pending_vector)(); /* */ /* */ /* Fill to quadword boundary */ /* */ } BAX; #if !defined(__VAXC) #define bax$q_bus_data_area bax$r_bus_data.bax$r_bus_data_overlay.bax$q_bus_data_area #define bax$l_bus_data_size bax$r_bus_data.bax$r_bus_data_overlay.bax$r_bus_data_descriptor.bax$l_bus_data_size #define bax$l_bus_data_type bax$r_bus_data.bax$r_bus_data_overlay.bax$r_bus_data_descriptor.bax$l_bus_data_type #define bax$ps_bus_data bax$r_bus_data.bax$r_bus_data_overlay.bax$r_bus_data_descriptor.bax$ps_bus_data #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __BUSARRAYDEF_LOADED */