/**/ /***************************************************************************/ /** **/ /** © Copyright 2010, Hewlett-Packard Development Company, L.P. **/ /** **/ /** Confidential computer software. Valid license from HP and/or **/ /** its subsidiaries required for possession, use, or copying. **/ /** **/ /** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, **/ /** Computer Software Documentation, and Technical Data for Commercial **/ /** Items are licensed to the U.S. Government under vendor's standard **/ /** commercial license. **/ /** **/ /** Neither HP nor any of its subsidiaries shall be liable for technical **/ /** or editorial errors or omissions contained herein. The information **/ /** in this document is provided "as is" without warranty of any kind and **/ /** is subject to change without notice. The warranties for HP products **/ /** are set forth in the express limited warranty statements accompanying **/ /** such products. Nothing herein should be construed as constituting an **/ /** additional warranty. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 30-Mar-2010 17:26:19 by OpenVMS SDL EV3-3 */ /* Source: 14-OCT-1994 16:13:32 $1$DGA7274:[LIB_H.SRC]APECSDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $APECSDEF ***/ #ifndef __APECSDEF_LOADED #define __APECSDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define APECS$Q_D21071CA_BASE -2147483648 #define APECS$Q_D21071CA_BASE_H 1 #define APECS$Q_D21071DA_BASE -1610612736 #define APECS$Q_D21071DA_BASE_H 1 #define APECS$Q_PCI_SCS -1342177280 #define APECS$Q_PCI_SCS_H 1 #define APECS$Q_PCI_SPARSE_IO -1073741824 #define APECS$Q_PCI_SPARSE_IO_H 1 #define APECS$Q_PCI_CONFIG -536870912 #define APECS$Q_PCI_CONFIG_H 1 #define APECS$Q_PCI_SPARSE_MEM 0 #define APECS$Q_PCI_SPARSE_MEM_H 2 #define APECS$Q_PCI_DENSE_MEM 0 #define APECS$Q_PCI_DENSE_MEM_H 3 #define APECS_PCI_NODE_COUNT 13 #define APECS$K_MEMORY_BANKS 9 #define APECS$M_TBASE1_32_10 0xFFFFFE00 #define APECS$M_TBASE2_32_10 0xFFFFFE00 #define APECS$M_PCIBASE1_SG_EN 0x40000 #define APECS$M_PCIBASE1_WEN 0x80000 #define APECS$M_PCIBASE2_SG_EN 0x40000 #define APECS$M_PCIBASE2_WEN 0x80000 #define APECS$M_PCIMASK1_31_20 0xFFF00000 #define APECS$M_PCIMASK2_31_20 0xFFF00000 #define APECS$M_HAXR1_PCI_31_27 0xF8000000 #define APECS$M_HAXR2_PCI_1_0 0x3 #define APECS$M_HAXR2_PCI_31_24 0xFF000000 #define APECS$M_PMLC 0xFF #define APECS$K_LENGTH 16384 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _apecs { #pragma __nomember_alignment __union { int apecs$l_gcsr; __struct { unsigned apecs$v_gcsr_fill1 : 32; } apecs$r_gcsr_fields; } apecs$r_gcsr; char apecs$b_fill10 [2044]; __struct { __struct { short int apecs$w_base_csr; short int apecs$w_fill_base [15]; } apecs$r_bankset_base [9]; char apecs$b_fill_base_array [224]; } apecs$r_bankset_bases; __struct { __struct { __union { short int apecs$w_config_csr; __struct { unsigned apecs$v_valid : 1; unsigned apecs$v_fill_0_ : 7; } apecs$r_bits; } apecs$r_bankset_config_reg; short int apecs$w_fill_config [15]; } apecs$r_bankset_config [9]; char apecs$b_fill_config_array [224]; } apecs$r_bankset_configs; __struct { __struct { short int apecs$w_timing_a_csr; short int apecs$w_fill_timing_a [15]; } apecs$r_bankset_timing_a [9]; char apecs$b_fill_timing_a_array [224]; } apecs$r_bankset_timing_as; __struct { __struct { short int apecs$w_timing_b_csr; short int apecs$w_fill_timing_b [15]; } apecs$r_bankset_timing_b [9]; char apecs$b_fill_timing_b_array [224]; } apecs$r_bankset_timing_bs; char apecs$b_fill20 [4096]; __union { int apecs$l_dcsr; __struct { unsigned apecs$v_dcsr_fill1 : 32; } apecs$r_dcsr_fields; } apecs$r_dcsr; char apecs$b_fill30 [28]; __union { int apecs$l_pear; __struct { unsigned apecs$v_pear_fill1 : 32; } apecs$r_pear_fields; } apecs$r_pear; char apecs$b_fill40 [28]; __union { int apecs$l_sear; __struct { unsigned apecs$v_sear_fill1 : 32; } apecs$r_sear_fields; } apecs$r_sear; char apecs$b_fill50 [28]; __union { int apecs$l_dr1; __struct { unsigned apecs$v_dr1_fill1 : 32; } apecs$r_dr1_fields; } apecs$r_dr1; char apecs$b_fill60 [28]; __union { int apecs$l_dr2; __struct { unsigned apecs$v_dr2_fill1 : 32; } apecs$r_dr2_fields; } apecs$r_dr2; char apecs$b_fill70 [28]; __union { int apecs$l_dr3; __struct { unsigned apecs$v_dr3_fill1 : 32; } apecs$r_dr3_fields; } apecs$r_dr3; char apecs$b_fill80 [28]; __union { int apecs$l_tbase1; __struct { unsigned apecs$v_tbase1_fill1 : 9; unsigned apecs$v_tbase1_32_10 : 23; } apecs$r_tbase1_fields; } apecs$r_tbase1; char apecs$b_fill90 [28]; __union { int apecs$l_tbase2; __struct { unsigned apecs$v_tbase2_fill1 : 9; unsigned apecs$v_tbase2_32_10 : 23; } apecs$r_tbase2_fields; } apecs$r_tbase2; char apecs$b_filla0 [28]; __union { int apecs$l_pcibase1; __struct { unsigned apecs$v_pcibase1_fill1 : 18; unsigned apecs$v_pcibase1_sg_en : 1; unsigned apecs$v_pcibase1_wen : 1; unsigned apecs$v_pcibase1_31_20 : 12; } apecs$r_pcibase1_fields; } apecs$r_pcibase1; char apecs$b_fillb0 [28]; __union { int apecs$l_pcibase2; __struct { unsigned apecs$v_pcibase2_fill1 : 18; unsigned apecs$v_pcibase2_sg_en : 1; unsigned apecs$v_pcibase2_wen : 1; unsigned apecs$v_pcibase2_31_20 : 12; } apecs$r_pcibase2_fields; } apecs$r_pcibase2; char apecs$b_fillc0 [28]; __union { int apecs$l_pcimask1; __struct { unsigned apecs$v_pcimask1_fill1 : 20; unsigned apecs$v_pcimask1_31_20 : 12; } apecs$r_pcimask1_fields; } apecs$r_pcimask1; char apecs$b_filld0 [28]; __union { int apecs$l_pcimask2; __struct { unsigned apecs$v_pcimask2_fill1 : 20; unsigned apecs$v_pcimask2_31_20 : 12; } apecs$r_pcimask2_fields; } apecs$r_pcimask2; char apecs$b_fille0 [28]; __union { int apecs$l_haxr0; __struct { unsigned apecs$v_haxr0_fill1 : 32; } apecs$r_haxr0_fields; } apecs$r_haxr0; char apecs$b_fillf0 [28]; __union { int apecs$l_haxr1; __struct { unsigned apecs$v_haxr1_fill1 : 27; unsigned apecs$v_haxr1_pci_31_27 : 5; } apecs$r_haxr1_fields; } apecs$r_haxr1; char apecs$b_fill100 [28]; __union { int apecs$l_haxr2; __struct { unsigned apecs$v_haxr2_pci_1_0 : 2; unsigned apecs$v_haxr2_fill1 : 22; unsigned apecs$v_haxr2_pci_31_24 : 8; } apecs$r_haxr2_fields; } apecs$r_haxr2; char apecs$b_fill110 [28]; __union { int apecs$l_pmlt; __struct { unsigned apecs$v_pmlc : 8; unsigned apecs$v_pmlt_fill1 : 24; } apecs$r_pmlt_fields; } apecs$r_pmlt; char apecs$b_fill120 [28]; __union { int apecs$l_tlb_tag0; __struct { unsigned apecs$v_tlb_tag0_fill1 : 32; } apecs$r_tlb_tag0_fields; } apecs$r_tlb_tag0; char apecs$b_fill130 [28]; __union { int apecs$l_tlb_tag1; __struct { unsigned apecs$v_tlb_tag1_fill1 : 32; } apecs$r_tlb_tag1_fields; } apecs$r_tlb_tag1; char apecs$b_fill140 [28]; __union { int apecs$l_tlb_tag2; __struct { unsigned apecs$v_tlb_tag2_fill1 : 32; } apecs$r_tlb_tag2_fields; } apecs$r_tlb_tag2; char apecs$b_fill150 [28]; __union { int apecs$l_tlb_tag3; __struct { unsigned apecs$v_tlb_tag3_fill1 : 32; } apecs$r_tlb_tag3_fields; } apecs$r_tlb_tag3; char apecs$b_fill160 [28]; __union { int apecs$l_tlb_tag4; __struct { unsigned apecs$v_tlb_tag4_fill1 : 32; } apecs$r_tlb_tag4_fields; } apecs$r_tlb_tag4; char apecs$b_fill170 [28]; __union { int apecs$l_tlb_tag5; __struct { unsigned apecs$v_tlb_tag5_fill1 : 32; } apecs$r_tlb_tag5_fields; } apecs$r_tlb_tag5; char apecs$b_fill180 [28]; __union { int apecs$l_tlb_tag6; __struct { unsigned apecs$v_tlb_tag6_fill1 : 32; } apecs$r_tlb_tag6_fields; } apecs$r_tlb_tag6; char apecs$b_fill190 [28]; __union { int apecs$l_tlb_tag7; __struct { unsigned apecs$v_tlb_tag7_fill1 : 32; } apecs$r_tlb_tag7_fields; } apecs$r_tlb_tag7; char apecs$b_fill1a0 [28]; __union { int apecs$l_tlb_data0; __struct { unsigned apecs$v_tlb_data0_fill1 : 32; } apecs$r_tlb_data0_fields; } apecs$r_tlb_data0; char apecs$b_fill1b0 [28]; __union { int apecs$l_tlb_data1; __struct { unsigned apecs$v_tlb_data1_fill1 : 32; } apecs$r_tlb_data1_fields; } apecs$r_tlb_data1; char apecs$b_fill1c0 [28]; __union { int apecs$l_tlb_data2; __struct { unsigned apecs$v_tlb_data2_fill1 : 32; } apecs$r_tlb_data2_fields; } apecs$r_tlb_data2; char apecs$b_fill1d0 [28]; __union { int apecs$l_tlb_data3; __struct { unsigned apecs$v_tlb_data3_fill1 : 32; } apecs$r_tlb_data3_fields; } apecs$r_tlb_data3; char apecs$b_fill1e0 [28]; __union { int apecs$l_tlb_data4; __struct { unsigned apecs$v_tlb_data4_fill1 : 32; } apecs$r_tlb_data4_fields; } apecs$r_tlb_data4; char apecs$b_fill1f0 [28]; __union { int apecs$l_tlb_data5; __struct { unsigned apecs$v_tlb_data5_fill1 : 32; } apecs$r_tlb_data5_fields; } apecs$r_tlb_data5; char apecs$b_fill200 [28]; __union { int apecs$l_tlb_data6; __struct { unsigned apecs$v_tlb_data6_fill1 : 32; } apecs$r_tlb_data6_fields; } apecs$r_tlb_data6; char apecs$b_fill210 [28]; __union { int apecs$l_tlb_data7; __struct { unsigned apecs$v_tlb_data7_fill1 : 32; } apecs$r_tlb_data7_fields; } apecs$r_tlb_data7; char apecs$b_fill220 [28]; __union { int apecs$l_tbia; __struct { unsigned apecs$v_tbia_fill1 : 32; } apecs$r_tbia_fields; } apecs$r_tbia; char apecs$b_fill230 [7164]; } APECS; #if !defined(__VAXC) #define apecs$l_gcsr apecs$r_gcsr.apecs$l_gcsr #define apecs$r_bankset_base apecs$r_bankset_bases.apecs$r_bankset_base #define apecs$w_base_csr apecs$w_base_csr #define apecs$w_fill_base apecs$w_fill_base #define apecs$b_fill_base_array apecs$r_bankset_bases.apecs$b_fill_base_array #define apecs$r_bankset_config apecs$r_bankset_configs.apecs$r_bankset_config #define apecs$r_bankset_config_reg apecs$r_bankset_config_reg #define apecs$w_config_csr apecs$r_bankset_config_reg.apecs$w_config_csr #define apecs$r_bits apecs$r_bankset_config_reg.apecs$r_bits #define apecs$v_valid apecs$r_bits.apecs$v_valid #define apecs$r_bankset_timing_a apecs$r_bankset_timing_as.apecs$r_bankset_timing_a #define apecs$w_timing_a_csr apecs$w_timing_a_csr #define apecs$r_bankset_timing_b apecs$r_bankset_timing_bs.apecs$r_bankset_timing_b #define apecs$w_timing_b_csr apecs$w_timing_b_csr #define apecs$l_dcsr apecs$r_dcsr.apecs$l_dcsr #define apecs$l_pear apecs$r_pear.apecs$l_pear #define apecs$l_sear apecs$r_sear.apecs$l_sear #define apecs$l_dr1 apecs$r_dr1.apecs$l_dr1 #define apecs$l_dr2 apecs$r_dr2.apecs$l_dr2 #define apecs$l_dr3 apecs$r_dr3.apecs$l_dr3 #define apecs$l_tbase1 apecs$r_tbase1.apecs$l_tbase1 #define apecs$v_tbase1_32_10 apecs$r_tbase1.apecs$r_tbase1_fields.apecs$v_tbase1_32_10 #define apecs$l_tbase2 apecs$r_tbase2.apecs$l_tbase2 #define apecs$v_tbase2_32_10 apecs$r_tbase2.apecs$r_tbase2_fields.apecs$v_tbase2_32_10 #define apecs$l_pcibase1 apecs$r_pcibase1.apecs$l_pcibase1 #define apecs$v_pcibase1_sg_en apecs$r_pcibase1.apecs$r_pcibase1_fields.apecs$v_pcibase1_sg_en #define apecs$v_pcibase1_wen apecs$r_pcibase1.apecs$r_pcibase1_fields.apecs$v_pcibase1_wen #define apecs$l_pcibase2 apecs$r_pcibase2.apecs$l_pcibase2 #define apecs$v_pcibase2_sg_en apecs$r_pcibase2.apecs$r_pcibase2_fields.apecs$v_pcibase2_sg_en #define apecs$v_pcibase2_wen apecs$r_pcibase2.apecs$r_pcibase2_fields.apecs$v_pcibase2_wen #define apecs$l_pcimask1 apecs$r_pcimask1.apecs$l_pcimask1 #define apecs$v_pcimask1_31_20 apecs$r_pcimask1.apecs$r_pcimask1_fields.apecs$v_pcimask1_31_20 #define apecs$l_pcimask2 apecs$r_pcimask2.apecs$l_pcimask2 #define apecs$v_pcimask2_31_20 apecs$r_pcimask2.apecs$r_pcimask2_fields.apecs$v_pcimask2_31_20 #define apecs$l_haxr0 apecs$r_haxr0.apecs$l_haxr0 #define apecs$l_haxr1 apecs$r_haxr1.apecs$l_haxr1 #define apecs$v_haxr1_pci_31_27 apecs$r_haxr1.apecs$r_haxr1_fields.apecs$v_haxr1_pci_31_27 #define apecs$l_haxr2 apecs$r_haxr2.apecs$l_haxr2 #define apecs$v_haxr2_pci_1_0 apecs$r_haxr2.apecs$r_haxr2_fields.apecs$v_haxr2_pci_1_0 #define apecs$v_haxr2_pci_31_24 apecs$r_haxr2.apecs$r_haxr2_fields.apecs$v_haxr2_pci_31_24 #define apecs$l_pmlt apecs$r_pmlt.apecs$l_pmlt #define apecs$v_pmlc apecs$r_pmlt.apecs$r_pmlt_fields.apecs$v_pmlc #define apecs$l_tlb_tag0 apecs$r_tlb_tag0.apecs$l_tlb_tag0 #define apecs$l_tlb_tag1 apecs$r_tlb_tag1.apecs$l_tlb_tag1 #define apecs$l_tlb_tag2 apecs$r_tlb_tag2.apecs$l_tlb_tag2 #define apecs$l_tlb_tag3 apecs$r_tlb_tag3.apecs$l_tlb_tag3 #define apecs$l_tlb_tag4 apecs$r_tlb_tag4.apecs$l_tlb_tag4 #define apecs$l_tlb_tag5 apecs$r_tlb_tag5.apecs$l_tlb_tag5 #define apecs$l_tlb_tag6 apecs$r_tlb_tag6.apecs$l_tlb_tag6 #define apecs$l_tlb_tag7 apecs$r_tlb_tag7.apecs$l_tlb_tag7 #define apecs$l_tlb_data0 apecs$r_tlb_data0.apecs$l_tlb_data0 #define apecs$l_tlb_data1 apecs$r_tlb_data1.apecs$l_tlb_data1 #define apecs$l_tlb_data2 apecs$r_tlb_data2.apecs$l_tlb_data2 #define apecs$l_tlb_data3 apecs$r_tlb_data3.apecs$l_tlb_data3 #define apecs$l_tlb_data4 apecs$r_tlb_data4.apecs$l_tlb_data4 #define apecs$l_tlb_data5 apecs$r_tlb_data5.apecs$l_tlb_data5 #define apecs$l_tlb_data6 apecs$r_tlb_data6.apecs$l_tlb_data6 #define apecs$l_tlb_data7 apecs$r_tlb_data7.apecs$l_tlb_data7 #define apecs$l_tbia apecs$r_tbia.apecs$l_tbia #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __APECSDEF_LOADED */