! *** PREDECLARED TYPES
     
      %IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN
         RECORD BASIC$QUADWORD
            LONG FILL ( 2 )
         END RECORD
         %LET %BASIC$QUADWORD_DECLARED = 1
      %END %IF
     
      %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN
         RECORD BASIC$OCTAWORD
            LONG FILL ( 4 )
         END RECORD
         %LET %BASIC$OCTAWORD_DECLARED = 1
      %END %IF
     
      %IF %DECLARED ( %BASIC$HFLOAT_AXP_DECLARED ) = 0 %THEN
         RECORD BASIC$HFLOAT_AXP
            LONG FILL ( 4 )
         END RECORD
         %LET %BASIC$HFLOAT_AXP_DECLARED = 1
      %END %IF
     
      %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN
         RECORD BASIC$F_FLOATING_COMPLEX
            SINGLE REAL_PART
            SINGLE IMAGINARY_PART
         END RECORD
         %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1
      %END %IF
     
      %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN
         RECORD BASIC$D_FLOATING_COMPLEX
            DOUBLE REAL_PART
            DOUBLE IMAGINARY_PART
         END RECORD
         %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1
      %END %IF
     
      %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN
         RECORD BASIC$G_FLOATING_COMPLEX
            GFLOAT REAL_PART
            GFLOAT IMAGINARY_PART
         END RECORD
         %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1
      %END %IF
     
      %IF %DECLARED ( %BASIC$H_FLOAT_AXP_CMPLX_DCL ) = 0 %THEN
         RECORD BASIC$H_FLOATING_COMPLEX_AXP
            BASIC$HFLOAT_AXP REAL_PART
            BASIC$HFLOAT_AXP IMAGINARY_PART
         END RECORD
         %LET %BASIC$H_FLOAT_AXP_CMPLX_DCL = 1
      %END %IF
    
    
    ! +
    !   PROCESSOR REGISTER DEFINITIONS
    ! 
    ! 	The following IPR symbols are provided for the convenience
    ! 	of common Macro-32 code using the VAX MFPR/MTPR instructions
    ! 	to operate against IPRs that exist in both architectures
    ! 	architectures. Even Alpha-specific Macro-32 code would benefit
    ! 	since the compiler can calculate register live-ness around the
    ! 	VAX MFPR/MTPR instructions.
    ! 
    ! 	The assigned values for the PR$_ipr symbols match the VAX
    ! 	IPR numbers themselves wherever possible. VAX IPR numbers that
    ! 	are extremely unlikely ever to be encountered are otherwise used.
    ! 	The compiler uses the VAX values to validate the invocation of
    ! 	MTPR/MFPR instructions.
    ! -
      DECLARE LONG CONSTANT PR$_ESP = 1     !  Executive Stack Pointer
      DECLARE LONG CONSTANT PR$_SSP = 2     !  Supervisor Stack Pointer
      DECLARE LONG CONSTANT PR$_USP = 3     !  User Stack Pointer
      DECLARE LONG CONSTANT PR$_ASN = 6     !  Address Space Number
      DECLARE LONG CONSTANT PR$_ASTEN = 48  !  AST Enabled Register (MFPR only)
      DECLARE LONG CONSTANT PR$_ASTSR = 49  !  AST Summary Register (MFPR only)
      DECLARE LONG CONSTANT PR$_DATFX = 23  !  Data Alignment Trap Fixup in PALcode Enable
      DECLARE LONG CONSTANT PR$_IPIR = 22   !  Interprocess Interrupt Request
      DECLARE LONG CONSTANT PR$_IPL = 18    !  Interrupt Priority Level
      DECLARE LONG CONSTANT PR$_MCES = 38   !  Machine Check Error Summary
      DECLARE LONG CONSTANT PR$_PCBB = 16   !  Privileged Context Block Base
      DECLARE LONG CONSTANT PR$_PME = 61    !  Performance Monitor Enable
      DECLARE LONG CONSTANT PR$_PRBR = 15   !  Processor Base Register
      DECLARE LONG CONSTANT PR$_SCBB = 17   !  System Control Block Base
      DECLARE LONG CONSTANT PR$_SIRR = 20   !  Software Interrupt Request
      DECLARE LONG CONSTANT PR$_SISR = 21   !  Software Interrupt Summary
      DECLARE LONG CONSTANT PR$_TBIA = 57   !  Translation Buffer Invalidate All
      DECLARE LONG CONSTANT PR$_TBIAP = 50  !  Translation Buffer Invalidate All Process
      DECLARE LONG CONSTANT PR$_TBIS = 58   !  Translation Buffer Invalidate Single - 32 bit VA
      DECLARE LONG CONSTANT PR$_TBIS_64 = 60  !  Translation Buffer Invalidate Single - 64 bit VA
      DECLARE LONG CONSTANT PR$_TBISD = 59  !  Translation Buffer Invalidate Single - 64 bit VA - D-stream only
      DECLARE LONG CONSTANT PR$_TBISI = 47  !  Translation Buffer Invalidate Single - 64 bit VA - I-stream only
      DECLARE LONG CONSTANT PR$_VPTB = 12   !  Virtual Page Table Base Register
    ! +
    !   PROCESSOR REGISTER FIELD DEFINITIONS
    ! -
      DECLARE LONG CONSTANT PR$_SID_TYP780 = 1  !  VAX 11/780 
      DECLARE LONG CONSTANT PR$_SID_TYP750 = 2  !  VAX 11/750 
      DECLARE LONG CONSTANT PR$_SID_TYP730 = 3  !  VAX 11/730 
      DECLARE LONG CONSTANT PR$_SID_TYP790 = 4  !  VAX 11/790
      DECLARE LONG CONSTANT PR$_SID_TYP8SS = 5  !  Scorpio for now
      DECLARE LONG CONSTANT PR$_SID_TYP8NN = 6  !  Nautilus for now
      DECLARE LONG CONSTANT PR$_SID_TYPUV1 = 7  !  MicroVAX I 
      DECLARE LONG CONSTANT PR$_SID_TYPUV2 = 8  !  MicroVAX II 
      DECLARE LONG CONSTANT PR$_SID_TYP410 = 8  !  VAXstar
      DECLARE LONG CONSTANT PR$_SID_TYP009 = 9  !  Virtual VAX
      DECLARE LONG CONSTANT PR$_SID_TYP420 = 10  !  PVAX
      DECLARE LONG CONSTANT PR$_SID_TYP520 = 10  !  Cirrus I
      DECLARE LONG CONSTANT PR$_SID_TYP650 = 10  !  Mayfair
      DECLARE LONG CONSTANT PR$_SID_TYP9CC = 10  !  Calypso/XCP
      DECLARE LONG CONSTANT PR$_SID_TYP9CI = 10
      DECLARE LONG CONSTANT PR$_SID_TYP60 = 10  !  Firefox
      DECLARE LONG CONSTANT PR$_SID_TYP670 = 11  !  KA670 (Pele)
      DECLARE LONG CONSTANT PR$_SID_TYP9RR = 11  !  XRP
      DECLARE LONG CONSTANT PR$_SID_TYP43 = 11  !  KA43 (RigelMAX)
      DECLARE LONG CONSTANT PR$_SID_TYP9AQ = 14  !  Aquarius
      DECLARE LONG CONSTANT PR$_SID_TYP8PS = 17  !  Polarstar
      DECLARE LONG CONSTANT PR$_SID_TYP1202 = 18  !  Mariah/XMP
      DECLARE LONG CONSTANT PR$_SID_TYP46 = 18  !  PV-Mariah
      DECLARE LONG CONSTANT PR$_SID_TYP600 = 19
      DECLARE LONG CONSTANT PR$_SID_TYP690 = 19
      DECLARE LONG CONSTANT PR$_SID_TYP700 = 19
      DECLARE LONG CONSTANT PR$_SID_TYP1302 = 19
      DECLARE LONG CONSTANT PR$_SID_TYP49 = 19
      DECLARE LONG CONSTANT PR$_SID_TYP1303 = 19
      DECLARE LONG CONSTANT PR$_SID_TYP660 = 20  !  KA660 (Spitfire)
      DECLARE LONG CONSTANT PR$_SID_TYP440 = 20  !  PVAX2
      DECLARE LONG CONSTANT PR$_SID_TYP4A = 20  !  PCVAX
      DECLARE LONG CONSTANT PR$_SID_TYP550 = 20  !  Cirrus II
      DECLARE LONG CONSTANT PR$_SID_TYP1701 = 23  !  Laser/Neon
      DECLARE LONG CONSTANT PR$_SID_TYPMAX = 23  !  MAX LEGAL CPU TYPE 
      DECLARE LONG CONSTANT PR$_SID_TYP_NOTAVAX = 128  !  Not a VAX (i.e. Alpha or some such)
    ! Chip CPU types
      DECLARE LONG CONSTANT PR$_SID_TYPUV = 8  !  MicroVAX chip
    ! MicroVAX chip CPU Subtypes
      DECLARE LONG CONSTANT PR$_XSID_UV_UV = 0  !  Generic MicroVAX (unused subtype)
      DECLARE LONG CONSTANT PR$_XSID_UV_UV2 = 1  !  MicroVAX II
      DECLARE LONG CONSTANT PR$_XSID_UV_410 = 4  !  VAXstar
      DECLARE LONG CONSTANT PR$_SID_TYPCV = 10  !  CVAX chip
    ! CVAX chip CPU Subtypes
      DECLARE LONG CONSTANT PR$_XSID_CV_CV = 0  !  Generic CVAX (unused subtype)
      DECLARE LONG CONSTANT PR$_XSID_CV_650 = 1  !  Mayfair
      DECLARE LONG CONSTANT PR$_XSID_CV_9CC = 2  !  Calypso/XCP
      DECLARE LONG CONSTANT PR$_XSID_CV_60 = 3  !  Firefox
      DECLARE LONG CONSTANT PR$_XSID_CV_420 = 4  !  PVAX
      DECLARE LONG CONSTANT PR$_XSID_CV_9CI = 5
      DECLARE LONG CONSTANT PR$_XSID_CV_520 = 7  !  CIRRUS I
      DECLARE LONG CONSTANT PR$_SID_TYPRV = 11  !  Rigel chip
    !  Rigel chip CPU Subtypes
      DECLARE LONG CONSTANT PR$_XSID_RV_RV = 0  !  Generic Rigel (unused subtype)
      DECLARE LONG CONSTANT PR$_XSID_RV_670 = 1  !  KA670 (Pele)
      DECLARE LONG CONSTANT PR$_XSID_RV_9RR = 2  !  Calypso/XRP
      DECLARE LONG CONSTANT PR$_XSID_RV_43 = 4  !  KA43 (RigelMAX)
      DECLARE LONG CONSTANT PR$_SID_TYPV12 = 18  !  Mariah chip set
    !  Mariah chip CPU Subtypes
      DECLARE LONG CONSTANT PR$_XSID_V12_V12 = 0  !  Generic Mariah (unused subtype)
      DECLARE LONG CONSTANT PR$_XSID_V12_1202 = 2  !  MARIAH/XMP
      DECLARE LONG CONSTANT PR$_XSID_V12_46 = 4  !  PVAX- mariah subtype
      DECLARE LONG CONSTANT PR$_SID_TYPV13 = 19
      DECLARE LONG CONSTANT PR$_XSID_V13_V13 = 0
      DECLARE LONG CONSTANT PR$_XSID_V13_690 = 1
      DECLARE LONG CONSTANT PR$_XSID_V13_1302 = 2
      DECLARE LONG CONSTANT PR$_XSID_V13_1303 = 3
      DECLARE LONG CONSTANT PR$_XSID_V13_49 = 4
      DECLARE LONG CONSTANT PR$_XSID_V13_700 = 5
      DECLARE LONG CONSTANT PR$_XSID_V13_600 = 6
      DECLARE LONG CONSTANT PR$_SID_TYPV14 = 20  !  SOC Chip SID
    !  SOC chip CPU subtypes
      DECLARE LONG CONSTANT PR$_XSID_V14_V14 = 0  !  unused subtype
      DECLARE LONG CONSTANT PR$_XSID_V14_660 = 1  !  KA660 (Spitfire)
      DECLARE LONG CONSTANT PR$_XSID_V14_440 = 4  !  PVAX2 subtype
      DECLARE LONG CONSTANT PR$_XSID_V14_4A = 5  !  PCVAX subtype
      DECLARE LONG CONSTANT PR$_XSID_V14_550 = 7  !  CIRRUS II
      DECLARE LONG CONSTANT PR$_SID_TYPV17 = 23  !  NVAX+ Chip SID
    !  NVAX+ chip CPU subtypes
      DECLARE LONG CONSTANT PR$_XSID_V17_V17 = 0  !  unused subtype
      DECLARE LONG CONSTANT PR$_XSID_V17_1701 = 1  !  Laser/Neon
    ! Nautilus CPU Subtypes
      DECLARE LONG CONSTANT PR$_XSID_N8800 = 0  !  VAX 8800
      DECLARE LONG CONSTANT PR$_XSID_N8700 = 1  !  VAX 8700
      DECLARE LONG CONSTANT PR$_XSID_N2 = 2  !  Undefined Nautilus CPU
      DECLARE LONG CONSTANT PR$_XSID_N3 = 3  !  Undefined Nautilus CPU
      DECLARE LONG CONSTANT PR$_XSID_N4 = 4  !  Undefined Nautilus CPU
      DECLARE LONG CONSTANT PR$_XSID_N5 = 5  !  Undefined Nautilus CPU
      DECLARE LONG CONSTANT PR$_XSID_N8550 = 6  !  VAX 8550
      DECLARE LONG CONSTANT PR$_XSID_N8500 = 7  !  VAX 8500
      DECLARE LONG CONSTANT PR$_XSID_N8NNN = -1  !  Unknown Nautilus CPU
    ! -------------------------------------------------------------------
      DECLARE LONG CONSTANT PR$M_ASTEN = x'0000000F'
      DECLARE LONG CONSTANT PR$M_ASTEN_KEN = x'00000001'
      DECLARE LONG CONSTANT PR$M_ASTEN_EEN = x'00000002'
      DECLARE LONG CONSTANT PR$M_ASTEN_SEN = x'00000004'
      DECLARE LONG CONSTANT PR$M_ASTEN_UEN = x'00000008'
      DECLARE LONG CONSTANT PR$M_ASTEN_DSBL_ALL = 0  !  Disable all ASTs
      DECLARE LONG CONSTANT PR$M_ASTEN_ENBL_ALL = 255  !  Enable all ASTs
      DECLARE LONG CONSTANT PR$M_ASTEN_ENBL_K = 17  !  Enable kernel ASTs
      DECLARE LONG CONSTANT PR$M_ASTEN_ENBL_E = 34  !  Enable executive ASTs
      DECLARE LONG CONSTANT PR$M_ASTEN_ENBL_S = 68  !  Enable supervisor ASTs
      DECLARE LONG CONSTANT PR$M_ASTEN_ENBL_U = 136  !  Enable user ASTs
      DECLARE LONG CONSTANT PR$M_ASTEN_PRSRV_ALL = 15  !  Preserve all enable/disable states
      DECLARE LONG CONSTANT PR$M_ASTEN_PRSRV_K = 1  !  Preserve kernel enable/disable
      DECLARE LONG CONSTANT PR$M_ASTEN_PRSRV_E = 2  !  Preserve executive enable/disable
      DECLARE LONG CONSTANT PR$M_ASTEN_PRSRV_S = 4  !  Preserve supervisor enable/disable
      DECLARE LONG CONSTANT PR$M_ASTEN_PRSRV_U = 8  !  Preserve user enable/disable
    ! -------------------------------------------------------------------
      DECLARE LONG CONSTANT PR$M_ASTSR = x'0000000F'
      DECLARE LONG CONSTANT PR$M_ASTSR_KPD = x'00000001'
      DECLARE LONG CONSTANT PR$M_ASTSR_EPD = x'00000002'
      DECLARE LONG CONSTANT PR$M_ASTSR_SPD = x'00000004'
      DECLARE LONG CONSTANT PR$M_ASTSR_UPD = x'00000008'
      DECLARE LONG CONSTANT PR$M_ASTSR_CLR_ALL = 0  !  Clear pending ASTs
      DECLARE LONG CONSTANT PR$M_ASTSR_SET_ALL = 255  !  Set all ASTs pending
      DECLARE LONG CONSTANT PR$M_ASTSR_SET_K = 17  !  Set kernel AST pending
      DECLARE LONG CONSTANT PR$M_ASTSR_SET_E = 34  !  Set executive AST pending
      DECLARE LONG CONSTANT PR$M_ASTSR_SET_S = 68  !  Set supervisor AST pending
      DECLARE LONG CONSTANT PR$M_ASTSR_SET_U = 136  !  Set user AST pending
      DECLARE LONG CONSTANT PR$M_ASTSR_PRSRV_ALL = 15  !  Preserve all pending bits
      DECLARE LONG CONSTANT PR$M_ASTSR_PRSRV_K = 1  !  Preserve kernel pending
      DECLARE LONG CONSTANT PR$M_ASTSR_PRSRV_E = 2  !  Preserve executive pending
      DECLARE LONG CONSTANT PR$M_ASTSR_PRSRV_S = 4  !  Preserve supervisor pending
      DECLARE LONG CONSTANT PR$M_ASTSR_PRSRV_U = 8  !  Preserve user pending
    ! -------------------------------------------------------------------
      DECLARE LONG CONSTANT PR$M_FEN_FEN = x'00000001'
      DECLARE LONG CONSTANT PR$M_DATFX_DATFX = x'00000001'
      DECLARE LONG CONSTANT PR$M_IPL_IPL = x'0000001F'
      DECLARE LONG CONSTANT PR$M_MCES_MCK = x'00000001'
      DECLARE LONG CONSTANT PR$M_MCES_SCE = x'00000002'
      DECLARE LONG CONSTANT PR$M_MCES_PCE = x'00000004'
      DECLARE LONG CONSTANT PR$M_MCES_DPC = x'00000008'
      DECLARE LONG CONSTANT PR$M_MCES_DSC = x'00000010'
      DECLARE LONG CONSTANT PR$V_PCBB_PA = 0  !  HWPCB Physical Address
      DECLARE LONG CONSTANT PR$S_PCBB_PA = 48  !  HWPCB Physical Address
    ! -------------------------------------------------------------------
      DECLARE LONG CONSTANT PR$M_PS_SW = x'00000003'
      DECLARE LONG CONSTANT PR$M_PS_PRVMOD = x'00000003'
      DECLARE LONG CONSTANT PR$M_PS_SYSSTATE = x'00000004'
      DECLARE LONG CONSTANT PR$M_PS_CURMOD = x'00000018'
      DECLARE LONG CONSTANT PR$M_PS_VMM = x'00000080'
      DECLARE LONG CONSTANT PR$M_PS_IPL = x'00001F00'
      DECLARE LONG CONSTANT PR$M_PS_SP_ALIGN = x'00000000'
      DECLARE LONG CONSTANT PR$M_PS_MBZ_62 = x'00000000'
      DECLARE LONG CONSTANT PR$M_PS_MBZ_63 = x'00000000'
      DECLARE LONG CONSTANT PR$V_PS_MAX_PS_REG_BIT = 13
    ! 
      DECLARE LONG CONSTANT PR$C_PS_KERNEL = 0  !  Kernel Mode
      DECLARE LONG CONSTANT PR$C_PS_EXEC = 1  !  Executive Mode
      DECLARE LONG CONSTANT PR$C_PS_SUPER = 2  !  Supervisor Mode
      DECLARE LONG CONSTANT PR$C_PS_USER = 3  !  User Mode
    ! -------------------------------------------------------------------
      DECLARE LONG CONSTANT PR$M_PTBR_PFN = x'FFFFFFFF'
      DECLARE LONG CONSTANT PR$M_SCBB_PFN = x'FFFFFFFF'
      DECLARE LONG CONSTANT PR$M_SIRR_LVL = x'0000000F'
      DECLARE LONG CONSTANT PR$M_SISR_SUMMARY = x'0000FFFF'
      DECLARE LONG CONSTANT PR$M_SISR_RAZ = x'00000001'
      DECLARE LONG CONSTANT PR$M_SISR_IR1 = x'00000002'
      DECLARE LONG CONSTANT PR$M_SISR_IR2 = x'00000004'
      DECLARE LONG CONSTANT PR$M_SISR_IR3 = x'00000008'
      DECLARE LONG CONSTANT PR$M_SISR_IR4 = x'00000010'
      DECLARE LONG CONSTANT PR$M_SISR_IR5 = x'00000020'
      DECLARE LONG CONSTANT PR$M_SISR_IR6 = x'00000040'
      DECLARE LONG CONSTANT PR$M_SISR_IR7 = x'00000080'
      DECLARE LONG CONSTANT PR$M_SISR_IR8 = x'00000100'
      DECLARE LONG CONSTANT PR$M_SISR_IR9 = x'00000200'
      DECLARE LONG CONSTANT PR$M_SISR_IR10 = x'00000400'
      DECLARE LONG CONSTANT PR$M_SISR_IR11 = x'00000800'
      DECLARE LONG CONSTANT PR$M_SISR_IR12 = x'00001000'
      DECLARE LONG CONSTANT PR$M_SISR_IR13 = x'00002000'
      DECLARE LONG CONSTANT PR$M_SISR_IR14 = x'00004000'
      DECLARE LONG CONSTANT PR$M_SISR_IR15 = x'00008000'
      DECLARE LONG CONSTANT PR$M_TBCHK_VA_PRESENT = x'00000001'
      DECLARE LONG CONSTANT PR$M_IEEE_DNOD = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_DNZ = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_INVD = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_DZED = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_OVFD = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_INV = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_DZE = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_OVF = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_UNF = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_INE = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_IOV = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_UNDZ = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_UNFD = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_INED = x'00000000'
      DECLARE LONG CONSTANT PR$M_IEEE_SUMMARY = x'00000000'
      DECLARE LONG CONSTANT PR$S_PRDEF = 8
      record PRDEF
         variant
            case
               BASIC$QUADWORD PR$Q_QUAD_ACCESS  !  Access to register as a quadword
            case
               LONG PR$L_LONG_ACCESS ( 1 to 2 )  !  Access to register as a quadword
            case
               group PR$R_PRDEF_BITS
                   !  SERIAL NUMBER FIELD 
                   !  PLANT ID 
                   !  ECO LEVEL 
                   !  CPU TYPE CODE 
                  LONG SID_SN_bits   ! COMMENT ADDED BY SDL - SID_SN_bits contains bits SID_SN through SID_TYPE
               end group PR$R_PRDEF_BITS
            case
               group PR$R_PRDEF_XBITS
                   !  CPU-SPECIFIC XSID BITS
                   !  CPU SUBTYPE CODE 
                  LONG FILL_XSID_BITS_bits   ! COMMENT ADDED BY SDL - FILL_XSID_BITS_bits contains bits FILL_XSID_BITS through  &
 ! XSID_TYPE
               end group PR$R_PRDEF_XBITS
    !  SYSTEM ID REGISTER CPU TYPES 
    !  Number assignments are
    !  based upon the jumpers
    !  read by the console from
    !  the MPS backplane
    !  ASTEN - AST Enabled Register
    ! 
    !  NOTE WELL: These bit symbols are to be used only when interfacing to the
    ! 	ASTEN internal processor register. They are NOT to be used when
    ! 	interfacing to the copy of ASTEN which is stored in the Hardware
    ! 	Privileged Context Block (HWPCB). See the HWPCB-specific symbols
    ! 	for how to refer to the ASTEN field in the HWPCB.
    ! 
            case
               group PR$R_ASTEN_DEF
                  variant
                  case
                      !  Enabled AST mask
                     BYTE ASTEN_bits   ! COMMENT ADDED BY SDL - ASTEN_bits contains bits ASTEN through ASTEN
                  case
                     group PR$R_ASTEN_BITS
                         !  Kernel AST Enabled
                         !  Executive AST Enabled
                         !  Supervisor AST Enabled
                         !  User AST Enabled
                        BYTE ASTEN_KEN_bits   ! COMMENT ADDED BY SDL - ASTEN_KEN_bits contains bits ASTEN_KEN through FILL_68_
                     end group PR$R_ASTEN_BITS
                  end variant
               end group PR$R_ASTEN_DEF
    !  ASTSR - AST Summary Register
    ! 
    !  NOTE WELL: These bit symbols are to be used only when interfacing to the
    ! 	ASTSR internal processor register. They are NOT to be used when
    ! 	interfacing to the copy of ASTSR which is stored in the Hardware
    ! 	Privileged Context Block (HWPCB). See the HWPCB-specific symbols
    ! 	for how to refer to the ASTSR field in the HWPCB.
    ! 
            case
               group PR$R_ASTSR_DEF
                  variant
                  case
                      !  AST pending summary mask
                     BYTE ASTSR_bits   ! COMMENT ADDED BY SDL - ASTSR_bits contains bits ASTSR through ASTSR
                  case
                     group PR$R_ASTSR_BITS
                         !  Kernel AST Pending
                         !  Executive AST Pending
                         !  Supervisor AST Pending
                         !  User AST Pending
                        BYTE ASTSR_KPD_bits   ! COMMENT ADDED BY SDL - ASTSR_KPD_bits contains bits ASTSR_KPD through FILL_69_
                     end group PR$R_ASTSR_BITS
                  end variant
               end group PR$R_ASTSR_DEF
    !  FEN - Floating Point Enable
    ! 
    !  NOTE WELL: These bit symbols are to be used only when interfacing to the
    ! 	FEN internal processor register. They are NOT to be used when
    ! 	interfacing to the copy of FEN which is stored in the Hardware
    ! 	Privileged Context Block (HWPCB). See the HWPCB-specific symbols
    ! 	for how to refer to the FEN field in the HWPCB.
    ! 
            case
                !  Floating point enabled = 1
    ! -------------------------------------------------------------------
    !  DATFX - Data Alignment Trap Fixup
    ! 
                !  Data Alignment Trap Fixup
    ! -------------------------------------------------------------------
    !  IPL - Interrupt Priority Level
    ! 
                !  Interrupt Priority Level
    ! -------------------------------------------------------------------
    !  MCES - Machine Check Error Summary Register
    ! 
               BYTE FEN_FEN_bits   ! COMMENT ADDED BY SDL - FEN_FEN_bits contains bits FEN_FEN through IPL_IPL
            case
               group PR$R_MCES_OVERLAY
                   !  Machine Check (W1C)
                   !  System Correctable Error (W1C)
                   !  Processor Correctable Error (W1C)
                   !  Disable Processor Correctable Error report
                   !  Disable System Correctable Error report
                  BYTE MCES_MCK_bits   ! COMMENT ADDED BY SDL - MCES_MCK_bits contains bits MCES_MCK through FILL_70_
               end group PR$R_MCES_OVERLAY
    ! -------------------------------------------------------------------
    !  PCBB - Privileged Context Block Base
    ! 
    !  PS - Processor Status
    ! 
    !  The PS is not an IPR in the sense that it isn't read/written using
    !  the MxPR operators. However, the bitfields of the PS are defined
    !  here since this is the repository for bitfields of architected IPRs,
    !  hence it's convenient to define them here.
    ! 
    !  Although the 'software' field of the PS is not privileged state and
    !  may be used by users as they see fit in User mode, VMS imposes a
    !  privileged interpretation on the bits when used in any of the three
    !  inner processor modes (Kernel, Executive, Supervisor). There are
    !  consequences of this:
    ! 
    ! 	1) Should User mode code be using the software field bits, it
    ! 		must be assumed that the User mode setting of these
    ! 		bits are entirely ignored by inner mode software.
    ! 
    ! 	2) VMS reserves the right to redefine its privileged (inner
    ! 		mode) interpretation of these bits at any time.
    ! 
            case
               group PR$R_PS_SWDEF_BITS
                   !  Software Bits
                  BYTE PS_SW_bits   ! COMMENT ADDED BY SDL - PS_SW_bits contains bits PS_SW through FILL_71_
               end group PR$R_PS_SWDEF_BITS
            case
               group PR$R_PSDEF_BITS
                   !  Previous Processor Mode
                   !  System State Indicator
                   !  Current Processor Mode
                   !  Virtual Machine Monitor
                   !  Interrupt Priority Level
                   !  Stack Pointer Alignment
                   !  Reserved bit above SP alignment
                   !  Reserved bit above SP alignment
                  BYTE PS_PRVMOD_bits ( 8 )   ! COMMENT ADDED BY SDL - PS_PRVMOD_bits contains bits PS_PRVMOD through PS_MBZ_63
               end group PR$R_PSDEF_BITS
    ! 
    !   Maximum bit number used in the PS register
    ! 
    !  MODE SYMBOL DEFINITIONS
    ! 
    !  PTBR - Page Table Base Register
    ! 
            case
                !  PFN of current L1PT
    ! -------------------------------------------------------------------
    !  SCBB - System Control Block Base
    ! 
                !  PFN of SCB
    ! -------------------------------------------------------------------
    !  SIRR - Software Interrupt Request Register
    ! 
                !  Software Interrupt Request Level
    ! -------------------------------------------------------------------
    !  SISR - Software Interrupt Summary Register
    ! 
               BYTE PTBR_PFN_bits ( 8 )   ! COMMENT ADDED BY SDL - PTBR_PFN_bits contains bits PTBR_PFN through SIRR_LVL
            case
               group PR$R_SISR_FIELDS
                  variant
                  case
                      !  Sofware Interrupt Summary
                     WORD SISR_SUMMARY_bits   ! COMMENT ADDED BY SDL - SISR_SUMMARY_bits contains bits SISR_SUMMARY through  &
 ! SISR_SUMMARY
                  case
                     group PR$R_SISR_BITS
                         !  Read As Zero
                         !  Softint 1 pending
                         !  Softint 2 pending
                         !  Softint 3 pending
                         !  Softint 4 pending
                         !  Softint 5 pending
                         !  Softint 6 pending
                         !  Softint 7 pending
                         !  Softint 8 pending
                         !  Softint 9 pending
                         !  Softint 10 pending
                         !  Softint 11 pending
                         !  Softint 12 pending
                         !  Softint 13 pending
                         !  Softint 14 pending
                         !  Softint 15 pending
                        WORD SISR_RAZ_bits   ! COMMENT ADDED BY SDL - SISR_RAZ_bits contains bits SISR_RAZ through SISR_IR15
                     end group PR$R_SISR_BITS
                  end variant
               end group PR$R_SISR_FIELDS
    ! -------------------------------------------------------------------
    !  TBCHK - Translation Buffer Check
    ! 
    !  This IPR may always be referenced with MFPR without causing an error
    !  to occur (unlike VAX), but the feature provided by TBCHK may or may
    !  not be implemented. If not, then <TBCHK_NO_TBCHK>=1 and <TBCHK_VA_PRESENT>
    !  should be ignored. If TBCHK's function IS implemented, then
    !  <TBCHK_NO_TBCHK>=0 and <TBCHK_VA_PRESENT> returns the desired data.
    ! 
            case
               group PR$R_TBCHK_BITS
                   !  VA in TB = 1
                   !  Not implemented = 1
                  BYTE TBCHK_VA_PRESENT_bits ( 8 )   ! COMMENT ADDED BY SDL - TBCHK_VA_PRESENT_bits contains bits TBCHK_VA_PRESENT  
&
 ! through TBCHK_NO_TBCHK
               end group PR$R_TBCHK_BITS
    ! -------------------------------------------------------------------
    !  FPCR - Floating Point Control Register
    ! 
    !  NOTE WELL: These bit symbols are to be used only when interfacing to the
    ! 	hardware FPCR internal processor register. They are NOT to be used when
    ! 	interfacing to the software floating point control register pointed to
    !  	by CTL$GQ_IEEE_FP_CONTROL/PKTA$Q_IEEE_FP_CONTROL.
    ! 
    ! 	The hardware FPCR should only be manipulated via the system service, 
    ! 	SYS$IEEE_FP_CONTROL, rather than directly.
    ! 
            case
               group PR$R_FPCR_BITS
                   !  Denormal operand exception disable
                   !  Denormal operands to 0.0
                   !  Invalid operation disable
                   !  Division by zero disable
                   !  Overflow disable
                   !  Invalid operation.
                   !  Division by zero occured.
                   !  Overflow occured.
                   !  Underflow occured.
                   !  Inexact result occured.
                   !  Integer overflow occured
                   !  Dynamic Rounding mode
                   !  Underflow to zero
                   !  Underflow disable
                   !  Inexact disable
                   !  Bitwise OR of FPCR exception bits
                  BYTE FPCR_fill_1_bits ( 8 )   ! COMMENT ADDED BY SDL - FPCR_fill_1_bits contains bits FPCR_fill_1 through  &
 ! IEEE_SUMMARY
               end group PR$R_FPCR_BITS
         end variant
      end record PRDEF